FAGD1654348BA [ROCHESTER]
CLOCK RECOVERY CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-48;
| 型号： | FAGD1654348BA |
| 厂家： | 
Rochester Electronics |
| 描述： | CLOCK RECOVERY CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-48 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总10页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 Gbit/s
Clock and Data
Recovery Circuit
GD16543
an Intel company
Preliminary
General Description
Features
l
The GD16543 is a high performance
monolithic integrated Clock and Data Re-
covery (CDR) device applicable for opti-
cal communication systems including:
The device meets all ITU-T jitter require-
ments when used with the recommended
loop filter (jitter tolerance, -transfer and
-generation).
Clock and Data Recovery covering
2.3 Gbit/s to 2.7 Gbit/s.
l
SDH STM-16, SONET OC-48
compatible.
u
SDH STM-16
SONET OC-48
u
The integrated 1:4 demultiplexer with dif-
ferential ECL outputs ensures a simple
and universal interface to the system
CMOS ASICs.
l
Differential Data inputs with 20 mV
sensitivity.
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase to the incoming data-stream.
l
Differential ECL Data and Clock
outputs.
The 622 MHz output clock is maintained
within 500 ppm tolerance even in ab-
sence of data.
The electrical input sensitivity is better
than 20 mV. Optical receivers with sensi-
tivity better than -34 dBm have been ob-
tained without optical pre-amplifiers.
l
Acquisition time: < 500 ms
l
The GD16543 is available in a 40 lead
ceramic LCC and in a 48 lead 7x7 mm
TQFP power enhanced plastic package.
Few external passive components
needed.
l
50 W Loop-Through data inputs for
higher sensitivity.
l
Single supply operation.
l
Power dissipation: 1 W.
Limiter
DOUT0
DOUN0
SIPO
l
Available in:
–
D
Bang
Bang
SIPI
SINI
DOUT1
DOUN1
CK
a 48 lead 7x7 mm TQFP plastic
package
a 40 lead ceramic LCC.
De-
MUX
Phase
Detector
DOUT2
DOUN2
DO
U
–
SINO
D
DOUT3
DOUN3
R
V
CKOUT
CKOUN
U
D
REFXI
Phase
Frequency
Detector
Applications
REFXO
VDD
Change
Pump
l
Clock and Data Recovery for optical
communication systems including:
VCO
VEE
VDDA
VEEA
–
–
SDH STM-16
SONET OC-48
Lock
SEL1
SEL2
Detect
RES
LOCK
CHPO
VCTL
Data Sheet Rev.: 07
Functional Details
The main application of the GD16543 is
as a receiver for:
Bang-Bang Phase Detector
The negligible penalty paid is a static
phase error on the sampling time in the
decision gate. However, due to the na-
ture of the phase detector the error will
be small (few degrees), forcing the loop
to be at one edge of the error-function
shaped transfer characteristic of the de-
tector.
u
SDH STM-16
SONET OC-48 optical communica-
tion systems.
The Bang-Bang phase detector is used
in CDR mode as a true digital type de-
tector, producing a binary output. It sam-
ples the incoming data twice each bit
period: once in the transition of the (pre-
vious) bit period and once in the middle
of the bit period. When a transition
occurs between 2 consecutive bits - the
value of the sample in the transition be-
tween the bits will show whether the
VCO clock leads or lags the data. Hence
the PLL is controlled by the bit transition
point, thereby ensuring that data is sam-
pled in the middle of the eye, once the
system is in CDR mode. The external
loop filter components control the chara-
cteristics of the PLL.
u
It integrates:
u
a Voltage Controlled Oscillator (VCO)
a Lock Detect Circuit
u
u
a Frequency Detector (PFD)
a Bang-Bang Phase Detector
u
Inputs
into a Phase Locked Loop (PLL) - based
clock and data recovery circuit followed
by a 1:4 demultiplexer with differential
ECL data and clock outputs.
The input amplifier (pin SIPI / SINI) is de-
signed as a limiting amplifier with a sen-
sitivity better than 20 mV (differential).
The inputs may be either AC or DC cou-
pled. In both cases input termination is
made through pins SIPO / SINO. If the
inputs are AC coupled the amplifier fea-
tures an internal offset cancelling DC
feedback. Notice that the offset cancella-
tion will only work when the input is dif-
ferential and AC-coupled as shown in the
Figures at page 3.
VCO
The VCO is a low noise LC-type differen-
tial oscillator with a tuning range from 2.2
to 2.7 GHz. Tuning is done by applying a
voltage to the VCTL pin.
The binary output of either the PFD or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is fed to a charge pump capable of
sinking or sourcing current or tristating.
The output of the charge pump is filtered
through the loop filter and controls the
tune-voltage of the VCO.
Lock Detect Circuit
The lock detect circuit continuously moni-
tors the difference between the reference
clock and the divided VCO clock. If the
reference clock and the divided VCO fre-
quency differs by more than 500 ppm (or
2000 ppm, selectable), it switches the
PFD into the PLL in order to pull the VCO
back inside the lock-in range. This mode
is called the acquisition mode.
Following the CDR block the data is 1:4
demultiplexed and output together with a
622 MHz clock. The data and clock out-
puts are differential ECL outputs that
should be terminated via 50 W to -2 V.
As a result of the continuous monitoring
lock-detect circuit the VCO frequency
never deviates more than 500 ppm
(2000 ppm) from the reference clock be-
fore the PLL is considered to be ’Out of
Lock’. Hence the acquisition time is pre-
dictable and short and the output clock
CKOUT is always kept within the
Package
The GD16543 is provided in either a
48 lead power enhanced TQFP or in a
40 pin Multi Layer Ceramic package with
internal 50 W transmission lines.
The PFD is used to ensure predictable
lock up conditions for the GD16543 by
locking the VCO to an external reference
clock source. It is only used during acqui-
sition and pulls the VCO into the lock
range where the Bang-Bang phase de-
tector is capable of acquiring lock. The
PFD is made with digital set/reset cells
giving it a true phase and frequency
characteristic.
500 ppm (2000 ppm) limits, ensuring
safe clocking of down stream circuitry.
The LOCK Signal
The status of the lock-detection circuit is
given by the LOCK signal. In CDR mode
LOCK is steady high. In acquisition mode
LOCK is alternating indicating the con-
tinuous shifts between the Bang-Bang
Detector (high) and the PFD (low).
Once the VCO is inside the lock-range
the lock-detection circuit switches the
Bang-Bang phase detector into the PLL
in order to lock to the data signal. This
mode is called CDR mode.
The LOCK output may be used to gener-
ate Loss Of Signal (LOS). The time for
LOCK to assert is predictable and short,
equal to the time to go into lock, but the
time for LOCK to de-assert must be con-
sidered. When the line is down (i.e. no in-
formation received) the optical receiver
circuit may produce random noise. It is
possible that this random noise will keep
the GD16543 within the 500 ppm
(2000 ppm) range of the line frequency,
hence LOCK will remain asserted for a
non-deterministic time. This may be pre-
vented by injecting a small current at the
loop filter node, which actively pulls the
PLL out of the lock range when the out-
put of the phase detector acts randomly.
For the purpose of stand alone applica-
tions the GD16543 has been equipped
with a crystal oscillator for a series reso-
nance, fundamental mode crystal. A
crystal for use at 2.488 GHz is also avail-
able. When not used with a crystal, the
REFXI input can be used as a standard
ECL input.
The reference clock input, REFXI, to the
PFD is at 1/64 of the data rate.
Data Sheet Rev.: 07
GD16543
Page 2 of 9
SIPI
From LINE
8k
REFXI
SIPO
SINO
SINI
50R
50R
+
50R
VTH = -1.3V
VTT
VTT
26dB
REFXO
-
8k
From LINE
Figure 1. DC Coupled Input (Ignoring internal offset com-
pensation)
Figure 4. External Reference Clock
SIPI
0V
From LINE
8k
68k
10pF
REFXI
SIPO
50R
+
300k
-5V
26dB
38.88MHz
10pF
SINO
SINI
REFXO
50R
-
8k
3k3
-5V
From LINE
Figure 2. AC Coupled Input (Using internal offset compen-
sation)
Figure 5. Crystal Oscillator
CHPO
33R 2.2mF
VCTL
Figure 3. Loop Filter
Data Sheet Rev.: 07
GD16543
Page 3 of 9
Pin List
Mnemonic:
SIPI, SIPO
SINI, SINO
Pin No.:
40 LCC 48 TQFP
Pin Type:
Anl. IN
Description:
22, 21
6, 7
Loop-through terminated serial positive differential input.
May be used as ECL compatible input.
24, 25
5, 4
Anl. IN
Loop-through terminated serial negative differential input.
May be used as ECL compatible input.
DOUT0, DOUN0
DOUT1, DOUN1
DOUT2, DOUN2
DOUT3, DOUN3
11, 10
9, 8
19,18
17,16
19, 20
21, 22
10, 11
12, 13
ECL OUT
Re-timed differential data outputs. DOUT0 is the first bit received.
Regenerated differential output clock, 622 MHz.
CKOUT, CKOUN
REFXI
14, 13
35
16, 17
38
ECL OUT
ECL IN
38.88 MHz Reference clock input or X-tal input for Phase/ Freq.
detect and Lock-detect.
REFXO
36
37
ECL OUT
ECL IN
38.88 MHz Reference clock output.
SEL1, SEL2
38, 39
34, 33
Single ended inputs, PLL set-up of Internal/ External switch mode
and LOCK:
SEL1 SEL2
0
0
1
1
0
1
0
1
Auto lock, 500 ppm.
Auto Lock, 2000 ppm.
Manual, Phase/Freq. Detector, 500 ppm.
Manual, Phase Detector, 2000 ppm.
LOCK
RES
4
2
26
29
ECL OUT
ECL IN
Single ended CDR Lock alarm output. When low, the divided
VCO freq. deviates more than 500/2000 ppm from REFXI.
Global reset when high. For test purposes only. Connect to VEE
for normal operation.
VCTL
CHPO
VDD
29
33
45
41
Anl. IN
Anl. OUT
PWR
VCO control voltage input.
Charge pump current output.
0 V power for core and ECL I/O.
1, 3, 6, 3, 9, 15,
12, 23
18, 24,
25, 27,
31, 32,
36, 40,
48
VEE
5, 7, 15, 1, 2, 8,
PWR
-5 V power for core and ECL I/O.
20, 26,
27, 30,
34, 37,
40
14, 23,
28, 30,
35, 39,
42, 47
VDDA
VEEA
NC
28
43, 46
44
PWR
PWR
NC
0 V power for VCO.
-5 V power for VCO.
Not Connected
31, 32
Heat sink
Connected to VDD
Data Sheet Rev.: 07
GD16543
Page 4 of 9
Pin Outline
6
7
35
34
33
32
31
30
29
28
27
26
VDD
VEE
REFXI
VEE
8
DOUN1
DOUT1
DOUN0
DOUT0
VDD
CHPO
NC
9
10
11
12
13
14
15
NC
VEE
VCTL
VDDA
VEE
CKOUN
CKOUT
VEE
VEE
Figure 6. 40 Lead LCC, Top View
1
36
VEE
VDD
VEE
SEL1
SEL2
VDD
VDD
VEE
RES
VEE
VDD
LOCK
VDD
2
35
34
33
32
31
30
29
28
27
26
25
VEE
3
VDD
4
SINO
5
SINI
6
SIPI
7
SIPO
8
VEE
9
VDD
10
DOUT2
11
DOUN2
12
DOUT3
Figure 7. 48 Lead TQFP, Top View
Data Sheet Rev.: 07
GD16543
Page 5 of 9
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in the table are referred to VDD.
All currents in the table are defined positive out of the pin.
Symbol:
VEE, VEEA
V0 MAX
I0 MAX, ECL
I0 MAX, CHPO
VI MAX
II MAX
Characteristic:
Supply voltage
Output voltage
Output current
Conditions:
MIN.:
-6
TYP.:
MAX.:
0
UNIT.:
V
VEE - 0.5
0.5
30
V
mA
mA
V
Output current
1
Input voltage
VEE - 0.5
-1.0
0.5
1.0
125
150
Input current
mA
°C
T0
Operating temperature
Storage temperature
Junction
-55
TS
-65
°C
DC Characteristics
TCASE = 0 °C to 85 °C, VEE = -5.0 V
All voltages in the table are referred to VDD.
All input signal and power currents in the table are defined positive into the pin.
All output signal currents are defined positive out of the pin.
Symbol:
VEE
Characteristic:
Conditions:
MIN.:
TYP.:
-5.0
180
20
MAX.:
UNIT.:
V
Supply voltage
-5.40
-4.5
IEE
Supply current
Note 1
Note 2
Note 6
mA
mV
mV
V
VI SINX/SIPX
Data input sensitivity, differential/single-ended
25
500
-1
VI MAX SINX/SIPX Maximum input voltage swing, differential
VICM SINX/SIPX
VIH ECL
Data common mode
ECL input high voltage
ECL input low voltage
ECL input high current
ECL input low current
VCO control voltage
ECL output high voltage
ECL output low voltage
CHPO source current
CHPO sink current
-2
-1.3
Note 1
Note 1
-1.1
VEE
0
V
VIL ECL
-1.5
100
100
-1
V
IIH ECL
mA
mA
V
IIL ECL
V1 VCTL
VOH ECL
VOL ECL
IOH CHPO
IOL CHPO
IVCTL <30 mA
Note 3, 4
Note 3, 4
Note 5
VEE
-1.0
VTT
-0.5
-1.6
V
V
400
400
mA
mA
Note 5
Note 1: VEE = -5.0 V
Note 2: AC-coupled, p-p voltage for differential coupling, BER 10 –12. Data eye diagram in accordance with ITU G.957,
223 - 1 PRBS, terminated via loop through 50 W.
Note 3: VTT = -2.0 V 5 %
Note 4: RL = 50 W to VTT
Note 5: Output terminated to -2.5 V during test.
Note 6: AC coupled input, p-p voltage.
Data Sheet Rev.: 07
GD16543
Page 6 of 9
AC Characteristics
TCASE = 0 °C to 85 °C, VEE = -5.0 V
DOUT
CKOUT
Td
Symbol:
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
UNIT.:
J TOL
Jitter tolerance
2 Hz < f < 100 kHz
1 MHz < f < 5 MHz
1.5
>2
UI 16, p-p
Note 2
Note 1. See Figure 8.
0.15
>0.35
J TRF
Jitter transfer
12 kHz < f < 2 MHz
0.08
0.1
dB
Note 1. See Figure 9.
J OUT
Output clock intrinsic jitter
Note 1
5 kHz < f < 1 MHz
0.125
0.05
UI 4, p-p
UI 4, p-p
Note 2
1 MHz < f < 20 MHz
TA
Acquisition time
223 – 1 PRBS
50
500
ms
LCID
Consecutive identical bits
# of bits with
no transition
400
1000
bits
DC
Input data / REFXI frequency deviation
REFXI clock duty cycle
Note 3
-200
40
200
60
ppm
%
CDUTY, REFXI
FVCO
Vthr = -1.3 V
VCO centre frequency
2.5
GHz
%
CDUTY, CKOUT
Output clock duty cycle
Vthr = -1.3 V,
45
55
50 W to -2.0 V
TRISE, ECL
TFALL, ECL
TD, DOUXX
ECL output rise time
ECL output fall time
20 - 80%,
350
350
275
700
700
ps
ps
ps
50 W to -2.0 V
80 - 20%,
50 W to -2.0 V
Data output from CKOUT
See figure above
Note 1: Jitter parameters acquired at VEE = 5.0 V ±5 %, R = 33 W, and C = 2.2 mF. When shifting the VEE range and tolerance,
R and C values should be changed to accommodate changed loop gain parameters.
Note 2: 1 UI 16, p-p = 402 ps. 1 UI 4, p-p = 1.608 ns.
Note 3: Maximum allowable deviation between reference clock and divided VCO clock when locked to data.
UI
UI
ITU-T Specs.
ITU-T Specs.
1.5
0.1
0.0
20dB/dec.
0.35
0.15
F
F
Figure 8. Jitter Tolerance, Typical
Figure 9. Jitter Transfer, Transfer
Data Sheet Rev.: 07
GD16543
Page 7 of 9
Package Outline
0.105" +- 0.011
0.100" +- 0.02
0.040" +- 0.006
Pin 1
Max 0.008"
0.680" +- 0.006
Bottom View
Top View
0.015" +- 0.003"
0.020"
Side View
0.480" +- 0.006
Note 1: Leads are hot dip soldered before cutting
Note 2: Coplanarity of leads > 0.008"
Figure 10. 40 Lead LCC, Leaded (All Dimensions are in inch)
Figure 11. 48 Lead TQFP, Power Enchanced (All Dimensions are in mm)
Data Sheet Rev.: 07
GD16543
Page 8 of 9
External References
ITU-T G.825 (03/93) Control of Jitter and Wander within digital networks based on SDH
ITU-T G.957 (07/95) Optical interfaces for equip. and systems relating to SDH
ITU-T G.958 (11/94) Digital line systems based on SDH for use on optical fibre cables
Device Marking
GD16543
<Mask ID> <Lot ID>
<WW YY>
Figure 12. Device Marking, (Top - 48 pin and Bottom - 40 pin)
Ordering Information
To order, please specify as shown below:
Product Name:
Intel Order Number:
Package Type:
Case Temperature Range:
GD16543-40AC
GD16543-40AB
GD16543-48BA
40 lead Ceramic LCC
0..85 °C
40 lead Ceramic LCC, leaded 0..85 °C
48 lead TQFP, EDQUAD 0..85 °C
FAGD1654348BA
MM#: 836065
GD16543, Data Sheet Rev.: 07 - Date: 30 July 2001
an Intel company
Mileparken 22, DK-2740 Skovlunde
Denmark
Phone : +45 7010 1062
Distributor:
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
Fax : +45 7010 1063
E-mail : sales@giga.dk
Web site : http://www.intel.com/ixa
Copyright © 2001 GIGA ApS
An Intel company
All rights reserved
Please check our Internet web site
for latest version of this data sheet.
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