MTB16N25E [ROCHESTER]
16A, 250V, 0.25ohm, N-CHANNEL, Si, POWER, MOSFET, CASE 418B-02, D2PAK-3;
| 型号： | MTB16N25E |
| 厂家： | 
Rochester Electronics |
| 描述： | 16A, 250V, 0.25ohm, N-CHANNEL, Si, POWER, MOSFET, CASE 418B-02, D2PAK-3 |
| 文件： | 总12页 (文件大小：958K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTB16N25E
Designer’s™ Data Sheet
TMOS E−FET.™
High Energy Power FET
D2PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
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TMOS POWER FET
16 AMPERES, 250 VOLTS
2
The D PAK package has the capability of housing a larger die than
any existing surface mount package which allows it to be used in
applications that require the use of surface mount components with
R
DS(on) = 0.25 OHM
higher power and lower R
capabilities. This advanced TMOS
DS(on)
E−FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain−to−source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
CASE 418B−02, Style 2
2
D PAK
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
D
• Diode is Characterized for Use in Bridge Circuits
• I
and V
Specified at Elevated Temperature
DSS
DS(on)
G
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13−inch/800 Unit Tape & Reel, Add −T4
Suffix to Part Number
®
S
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
August, 2006 − Rev. 1
MTB16N25E/D
MTB16N25E
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
250
Unit
Vdc
Vdc
Drain−Source Voltage
V
DSS
DGR
Drain−Gate Voltage (R = 1.0 MΩ)
V
V
250
GS
Gate−Source Voltage — Continuous
V
GS
± 20
± 40
Vdc
Vpk
Gate−Source Voltage — Non−Repetitive (t ≤ 10 ms)
p
GSM
Drain Current — Continuous
Drain Current — Continuous @ T = 100°C
Drain Current — Single Pulse (t ≤ 10 μs)
I
I
16
10
56
Adc
D
C
D
I
Apk
p
DM
Total Power Dissipation @ T = 25°C
Derate above 25°C
P
D
125
1.0
2.5
Watts
W/°C
Watts
C
Total Power Dissipation @ T = 25°C, when mounted with the minimum recommended pad size
A
Operating and Storage Temperature Range
T , T
− 55 to 150
°C
J
stg
Single Pulse Drain−to−Source Avalanche Energy — Starting T = 25°C
E
AS
384
mJ
J
(V = 80 Vdc, V = 10 Vdc, I = 16 Apk, L = 3.0 mH, R = 25 Ω )
DD
GS
L
G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
R
R
R
1.0
62.5
50
°C/W
θ
JC
JA
JA
θ
θ
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
L
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
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MTB16N25E
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
V
(BR)DSS
(V = 0 Vdc, I = 250 μAdc)
Temperature Coefficient (Positive)
250
—
—
333
—
—
Vdc
mV/°C
GS
D
Zero Gate Voltage Drain Current
I
μAdc
DSS
(V = 250 Vdc, V = 0 Vdc)
—
—
—
—
10
100
DS
GS
(V = 250 Vdc, V = 0 Vdc, T = 125°C)
DS
GS
J
Gate−Body Leakage Current (V = ± 20 Vdc, V = 0)
I
—
—
100
nAdc
GS
DS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
V
GS(th)
(V = V , I = 250 μAdc)
Temperature Coefficient (Negative)
2.0
—
3.0
7.0
4.0
—
Vdc
mV/°C
DS
GS
D
Static Drain−Source On−Resistance (V = 10 Vdc, I = 8.0 Adc)
R
V
—
0.17
0.25
Ohm
Vdc
GS
D
DS(on)
Drain−Source On−Voltage (V = 10 Vdc)
GS
DS(on)
(I = 16 Adc)
(I = 8.0 Adc, T = 125°C)
D
—
—
3.6
—
4.8
4.2
D
J
Forward Transconductance (V = 15 Vdc, I = 8.0 Adc)
g
FS
3.0
7.0
—
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
1558
281
2180
390
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
130
260
rss
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
t
—
—
—
—
—
—
—
—
15
64
30
130
110
90
ns
d(on)
(V = 125 Vdc, I = 16 Adc,
DD
D
Rise Time
t
r
V
GS
= 10 Vdc,
Turn−Off Delay Time
Fall Time
t
56
d(off)
R
= 9.1 Ω)
G
t
f
44
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
53.4
9.3
27.5
17.1
70
nC
—
(V = 200 Vdc, I = 16 Adc,
DS
D
V
GS
= 10 Vdc)
—
—
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (1)
V
Vdc
ns
SD
(I = 16 Adc, V = 0 Vdc)
S
GS
—
—
0.915
1.39
1.5
—
(I = 16 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
(See Figure 14)
t
—
—
—
—
234
170
—
—
—
—
rr
t
a
(I = 16 Adc, V = 0 Vdc,
S
GS
dI /dt = 100 A/μs)
S
t
64
b
Reverse Recovery Stored Charge
Q
2.165
μC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
—
—
4.5
7.5
—
—
nH
nH
D
Internal Source Inductance
L
S
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
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MTB16N25E
TYPICAL ELECTRICAL CHARACTERISTICS
32
24
16
32
V
GS
= 10 V
T = 25°C
J
V
DS
≥ 10 V
8 V
7 V
24
16
25°C
6 V
100°C
8
0
8
0
5 V
T = −55°C
J
0
1
2
3
4
5
6
7
8
2
3
4
5
6
7
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.26
0.22
0.18
0.14
0.1
0.6
0.5
0.4
0.3
V
GS
= 10 V
T = 25°C
J
V
GS
= 10 V
T = 100°C
J
15 V
25°C
0.2
0.1
0
−55°C
0
5
10
15
20
25
30
35
0
8
16
24
32
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
Figure 4. On−Resistance versus Drain Current
and Temperature
and Gate Voltage
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
0
V
GS
= 0 V
V
GS
I = 8 A
= 10 V
T = 125°C
D
J
100°C
25°C
1
−50
−25
0
25
50
75
100
125
150
0
50
V
100
150
200
250
3
T , JUNCTION TEMPERATURE (°C)
J
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−To−Source Leakage
Temperature
Current versus Voltage
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MTB16N25E
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
the on−state when calculating td(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP
tf = Q2 x RG/VGSP
where
)
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP
)
5000
4000
V
GS
= 0 V
V
DS
= 0 V
T = 25°C
J
C
iss
3000
2000
C
iss
C
rss
1000
0
C
oss
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTB16N25E
12
9
1000
200
150
100
QT
V
DD
I = 16 A
= 250 V
D
V
GS
V
GS
= 10 V
T = 25°C
J
100
t
r
Q1
Q2
t
f
t
t
d(off)
6
3
0
d(on)
10
1
I = 16 A
D
T = 25°C
J
50
0
Q3
10
V
DS
1
10
R , GATE RESISTANCE (OHMS)
1
0
20
30
40
50
60
Q , TOTAL CHARGE (nC)
T
G
Figure 8. Gate−To−Source and Drain−To−Source
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
16
V
GS
= 0 V
T = 25°C
J
12
8
4
0
0.5
0.55 0.6
0.65 0.7
0.75 0.8
0.85 0.9 0.95
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
A Power MOSFET designated E−FET can be safely used
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
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MTB16N25E
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
SAFE OPERATING AREA
100
10
1
400
V
= 20 V
SINGLE PULSE
GS
I = 16 A
D
10ꢀμs
T = 25°C
C
300
200
100
0
100ꢀμs
1ꢀms
10ꢀms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1.0
10
100
1000
25
50
75
100
125
1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
(pk)
R
θ
(t) = r(t) R
θ
JC
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
0.01
1
t
2
T
− T = P
C
R (t)
θ
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
SINGLE PULSE
1 2
0.01
0.00001
0.0001
0.001
0.01
0.1
1.0
10
t, TIME (s)
Figure 13. Thermal Response
3
R
= 50°C/W
θ
JA
Board material = 0.065 mil FR−4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 9 450 mils x 350 mils
2.5
2.0
1.5
1
di/dt
I
S
t
rr
t
a
t
b
TIME
0.5
0.25 I
t
p
S
0
25
50
75
100
125
15
I
S
T , AMBIENT TEMPERATURE (°C)
A
Figure 14. Diode Reverse Recovery Waveform
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Figure 15. D2PAK Power Derating Curve
7
MTB16N25E
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.08
2.032
0.24
0.42
10.66
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of RθJA versus drain pad area is shown in
Figure 16.
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet, PD can be calculated as follows:
70
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
T = 25°C
A
60
2.5 Watts
TJ(max) − TA
PD =
50
Rθ
JA
3.5 Watts
40
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.
5 Watts
30
20
0
2
4
6
8
10
12
14
16
150°C − 25°C
A, AREA (SQUARE INCHES)
= 2.5 Watts
PD =
50°C/W
Figure 16. Thermal Resistance versus Drain Pad
Area for the D2PAK Package (Typical)
The 50°C/W for the D2PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad™. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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MTB16N25E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 17 shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
SOLDER PASTE
OPENINGS
STENCIL
Figure 17. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
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MTB16N25E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177−189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend
to heat first. The components on the board are then heated
by conduction. The circuit board, because it has a large
surface area, absorbs the thermal energy more efficiently,
then distributes this energy to the components. Because of
this effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a
figure for belt speed. Taken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 18 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good
starting point. Factors that can affect the profile include the
type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 1
PREHEAT
ZONE 1
ꢁRAMP"
STEP 2
VENT
STEP 3
HEATING
STEP 4
HEATING
STEP 5
HEATING
STEP 6
VENT
STEP 7
COOLING
ꢁSOAK" ZONES 2 & 5
ꢁRAMP"
ZONES 3 & 6 ZONES 4 & 7
ꢁSOAK" ꢁSPIKE"
170°C
205° TO 219°C
PEAK AT
SOLDER JOINT
200°C
150°C
100°C
50°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 18. Typical Solder Heating Profile
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MTB16N25E
PACKAGE DIMENSIONS
CASE 418B−02
ISSUE B
C
E
V
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
MILLIMETERS
STYLE 2:
PIN 1. GATE
A
MIN
8.64
9.65
4.06
0.51
1.14
MAX
9.65
10.29
4.83
0.89
1.40
S
A
B
C
D
E
G
H
J
0.340
0.380
0.160
0.020
0.045
0.380
0.405
0.190
0.035
0.055
2. DRAIN
3. SOURCE
4. DRAIN
1
2
3
−T−
SEATING
PLANE
K
0.100 BSC
2.54 BSC
0.080
0.018
0.090
0.575
0.045
0.110
0.025
0.110
0.625
0.055
2.03
0.46
2.79
0.64
J
G
K
S
V
2.29
14.60
1.14
2.79
15.88
1.40
H
D 3 PL
M
0.13 (0.005)
T
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