BU1521GVW-E2_技术文档

BU1521GVW

Video Accessory IC Series

For portable image equipment

Upscaler IC

No.09069EAT02

BU1521GVW

●

Description

BU1521GVW upscales and interpolates images when upconverting to the HDTV (Maximum 1080P) format from the usual SDTV

(NTSC/PAL) format.

High quality IP change・up scale management is realized by the frame memory less operate.

It is the LSI which is the most suitable for the compact system of the mobile.

●

Features

1）Input format

480i or 576i(ITUR BT656) YCbCr 4:2:2(ITUR BT601) 8bit Digital Interface

2）Output Format

480i or 576i(ITUR BT656) YCbCr 4:2:2 8bit Digital Interface

480p or 576p(SMPTE 293・ITUR BT1358) YCbCr 4:2:2 16bit Digital Interface

1080/59.94i(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface

1080/50i(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface

1080/59.94p(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface

1080/50p(SMPTE 274) YCbCr 4:2:2 16bit Digital Interface

3）IP conversion function

Conversion function from interlace to progressive

4）Upscale function

Horizontal direction: 720 pixels pass-through or upscaling to 1920 pixels

Vertical direction: up scaling to 480, 576, 540, and 1080 pixels

5）Filter function

5 × 5 filtering function over input data

Filter coefficient is programmable with registers

6）Register access

Register read/write through the SPI interface

Burst write/read support

7）Built-in PLL

Input frequency 27MHz

Output frequency 74.25MHz,74.175824MHz,148.5MHz,148.351648MHz

8）Power-down mode and through-mode support

Power-down mode can be controlled through STBY pin or register setting.

Through-mode can be selected by register setting.

9）Supply voltage

VDD(core voltage )1.15V～1.25V、AVDD(PLL)=2.7V~3.3V、

VDDIO1(SDTV input)=1.7V～3.6V、VDDIO2(control)=2.7V～3.3V、

VDDIO3(HDTV output)=1.7V～1.9V

10）Package

63 pin, BGA package (SBGA063W060, Size = 6 mm × 6 mm, 0.65 mm pitch)

●

Aplications

Digital Video Camera、Digital still camera , Video game, a portable DVD

www.rohm.com

2009.05 - Rev.A

1/15

Technical Note

BU1521GVW

●

Absolute Maximum Rating

Table. 1 Absolute maximum rating

Parameter

Symbol

VDDIO1

VDDIO2

VDDIO3

AVDD

VDD

Rating

-0.3～+4.2

Unit

Supplyvoltage1 (SD input)

Supplyvoltage2 (Control)

Supplyvoltage3 (HD output)

Supply voltage 4 (PLL)

Supply voltage 5 (CORE)

Input voltage 1

V

-0.3～+4.2

V

-0.3～+4.2

V

-0.3～+1.68

V

VIN1

-0.3～VDDIO1+0.3

-0.3～VDDIO2+0.3

-0.3～VDDIO3+0.3

-25～+125

V

Input voltage 2

VIN2

V

Input voltage 3

VIN3

V

Storage temperature range

Tstg

ºC

mW

Power dissipation

PD

330*1, 1200*2

*1 IC only. In the case exceeding 25°C, 3.3 mW should be reduced at the rating 1C.

*2 When packaging a glass epoxy board of 114.3 × 76.2 × 1.6 mm. In the case exceeding 25°C, 12 mW should be reduced at t

he rating 1C.

* Has not been designed to withstand radiation.

* Operation is not guaranteed.

●

Operating Conditions

Table. 2 Operating conditions

Parameter

Symbol

VDDIO1

VDDIO2

VDDIO3

AVDD

Min

1.7

2.7

1.7

2.7

1.15

-25

Typ

3.3

3.0

1.8

3.0

1.2

-

Max

3.6

3.3

1.9

3.3

1.25

85

Unit

V

Supplyvoltage1 (SD input)

Supplyvoltage2 (Control)

Supplyvoltage3 (HD output)

Supplyvoltage4 (PLL)

V

Supplyvoltage5 (CORE)

Operating temperature range

VDD

V

Topr

℃

●

Electrical Characteristics (DC Characteristics)

Table. 3 Electric characteristics

Specification

Unit

Parameter

Operational current (CORE)

Operational current (IO)

Operational current (CORE)

Operational current (IO)

Symbol

IDD1

IDD2

IDD3

IDD4

Conditions

MIN

-

TYP

150

MAX

200

mA When operated with HDCLK = 148.5 MHz

When operated with HDCLK = 148.5 MHz and

-

40

15

10

80

20

mA

external capacitor of 5pF

mA When operated with DCLK = 27 MHz

When operated with HDCLK = 27 MHz and

mA

external capacitor of 5pF

Static current

IDDst

IIH

-

-10

-

800

10

μA In standby mode

μA VIH=VDDIO1/2

μA VIL=GND

Input “H” current

Input “L” current

IIL

-10

10

VDDIO1

*0.8

VDDIO1

+0.3

Input “H” voltage 1

Input “L” voltage 1

Input “H” voltage 2

VIH1

VIL1

VIH2

-

V

Ordinary input (Including input mode of I/O pin)

Hysteresis input

VDDIO1

*0.2

-0.3

VDDIO1

*0.85

VDDIO1

+0.3

VDDIO1

*0.15

-

Input “L” voltage 2

VIL2

-0.3

-

V

Hysteresis input

Hysteresis voltage range 2

Output “H” voltage 1

Output “L” voltage 1

Output “H” voltage 2

Output “L” voltage 2

Vhys2

VOH1

VOL1

VOH2

VOL2

-

VDDIO2

-0.4

0.75

-

VDDIO2

0.4

IOH1=-1.0mA(DC)

IOL1=1.0mA(DC)

IOH1=-1.0mA(DC)

IOL1=1.0mA(DC)

SDOUT

0.0

SDOUT

VDDIO3

-0.2

VDDIO3

0.2

HD output pin

0.0

(When not otherwise specified, under the conditions of VDD = 1.20 V, VDDIO1 = 3.3 V, VDDIO3 = 1.8 V, VDDIO2 =AVDD = 3.0 V, AVSS = GND = 0.0 V, and Ta = 25C)

www.rohm.com

2009.05 - Rev.A

2/15

Technical Note

BU1521GVW

●

Electrical Characteristics (AC Characteristics)

1. 3-wire serial interface timing

SCSB

t_word

t_Wt

SCLK

0

1

5

6

7

0

1

5

6

7

t_wcs

SCSB

SCLK

SDIN

t_css

t_wsclk

t_csh

t_sds

t_sdh

t_sdo

SDOUT

Fig. 1 3-wire serial interface format

Table. 4 3-wire serial interface format

Symbol

Description

MIN

200

1

TYP

MAX

Unit

ns

t_wsclk

t_wcs

t_css

t_sds

t_csh

t_sdh

t_sdo

t_word

t_wt

SCLK clock cycle

SCSB access interval

SCSB setup time

SDIN setup time

-

μs

ns

200

30

1

-

ns

SCSB holding time

SDIN holding time

-

μs

ns

30

-

Time from trailing of the clock to the establishment of SDOUT

1 word write time

60

-

ns

2.5

1

μs

1 word write interval

-

www.rohm.com

2009.05 - Rev.A

3/15

Technical Note

BU1521GVW

2. Image Data Input Timing

ｔCIP

ｔCIL

ｔCIH

CLKIN

DI0-15

ｔDIS ｔDIH

Fig. 2 Image Data Input Timing

Table. 5 Image Data Input Timing

Symbol

Description

MIN

TYP MAX

Unit

ns

%

t_CIP

d_CKI

t_DIS

t_DIH

CLKIN Clock cycle

-

45

2

37.03

-

55

-

CLKIN clock duty (tCIL/tCIP or tCIH/tCIP)

Data setup time from the CLKIN rise

Data holding time from the CLKIN rise

50

-

ns

3

-

3. Image Data Output Timing

ｔCOP

ｔCOL

ｔCOH

CLKOUT

DO0-15

ｔDOD

Fig. 3 Image Data Output Timing

Table. 6 Image Data Output Timing

Symbol

Description

MIN

TYP MAX

Unit

ns

%

t_COP

d_CKO

t_DOD

t_JIT

CLKOUT Clock cycle

6.734

-

55

CLKOUT clock duty (tCOL/tCOP or tCOH/tCOP) *

45

1

Time from the rise of CLKOUT to the establishment of DO0-15

12

ns

Time from the rise of CLKOUT to the establishment of DO0-15

1

5.734

2

Output jitter of CLKOUT (1 us cycle)

-

* When PLLis used. When 27 MHz is output, the input clock duty is 50%.

www.rohm.com

2009.05 - Rev.A

4/15

Technical Note

BU1521GVW

●

Pin configuration diagram (Bottom View)

Fig. 4 Pin configuration diagram of BU1521GVW (Bottom view).

H

16

GND

19

DI15

21

DI1

24

SCSB

25

SDIN

28

STBY

30

DO1

32

GND

G

F

14

17

20

23

26

29

33

35

DI13

DI11

DI2

SCLK

SDOUT

CLKOUT

DO0

DO2

12

DI10

13

DI7

15

GND

22

RESETB

27

VDDIO2

31

VDD

36

DO4

37

DO3

E

D

C

B

A

9

10

11

18

34

38

39

40

DI14

DI0

GND

VDD

VDDIO3

GND

DO6

DO5

8

DI9

7

DI12

6

2

50

GND

43

VDD

42

DO8

41

DO7

VDDIO1

AVDD

4

DI5

63

GND

59

AVSS

54

VDDIO3

47

GND

45

DO10

44

DO9

3

DI6

1

DI3

61

DI8

58

GND

55

TEST0

52

DO14

49

DO12

46

DO11

60

CLKIN

62

DI4

64

GND

57

TEST2

56

TEST1

53

DO15

51

DO13

48

GND

1

2

3

4

5

6

7

8

Fig. 4 BU1521GVW Pin configuration diagram(Bottom View)

www.rohm.com

2009.05 - Rev.A

5/15

Technical Note

BU1521GVW

●

Pin Function

PIN No. Ball No. PIN Name In/Out

Table. 7 BU1521GVW terminal function(1)

Init

--

Function Description

3rd bit of SD input data

Power Source for PLL

6th bit of SD input data

5th bit of SD input data

--

I/O Type

B

I/O System

VDDIO1

--

1

B2

D4

B1

C2

--

DI3

AVDD

DI6

In

--

2

--

3

In

--

B

VDDIO1

--

4

DI5

In

--

B

5

N.C *1

VDDIO1

DI12

--

6

D3

D2

D1

E1

E2

E3

F1

F2

G1

F3

H1

G2

E4

H2

G3

H3

F4

G4

H4

H5

G5

F5

H6

G6

H7

F6

H8

G7

E5

G8

F7

F8

E6

E7

E8

D8

--

Data input IO voltage (Typical 3.3 V)

12th bit of SD input data

9th bit of SD input data

14th bit of SD input data

0th bit of SD input data

GND

--

7

In

--

B

VDDIO1

--

8

DI9

In

--

B

9

DI14

In

--

B

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

DI0

In

--

B

GND

DI10

--

In

--

10th bit of SD input data

7th bit of SD input data

13th bit of SD input data

GND

B

VDDIO1

--

DI7

In

--

B

DI13

In

--

B

GND

DI11

--

GND

--

In

--

11th bit of SD input data

Core power supply (1.2 V)

15th bit of SD input data

2nd bit of SD input data

1st bit of SD input data

Reset pin (low active)

3-wire serial I/F clock

3-wire serial I/F chip select

3-wire serial I/F data input

3-wire serial I/F data output

Control signal IO voltage (typically 3.3 V)

IC stand-by control

B

VDDIO1

--

VDD

--

DI15

In

--

B

VDDIO1

VDDIO2

--

DI2

In

--

B

DI1

In

--

B

RESETB

SCLK

SCSB

SDIN

SDOUT

VDDIO2

STBY

CLKOUT

DO1

In

--

B*2

C*3

--

In

--

In

--

In

--

Out

--

Low

--

In

--

A

VDDIO2

VDDIO3

--

Out

--

Low

PD

--

HD clock output

D

1st bit of HD output pin

Core power supply (1.2 V)

GND

C

VDD

--

GND

DO0

--

Out

--

PD

--

0th bit of HD output pin

Data output IO voltage (typically 1.8 V)

2nd bit of HD output pin

4th bit of HD output pin

3rd bit of HD output pin

GND

C

VDDIO3

--

VDDIO3

DO2

--

Out

--

PD

--

C

VDDIO3

--

DO4

C

DO3

C

GND

DO6

--

Out

PD

6th bit of HD output pin

5th bit of HD output pin

7th bit of HD output pin

C

VDDIO3

DO5

C

DO7

C

www.rohm.com

2009.05 - Rev.A

6/15

Technical Note

BU1521GVW

Table. 8 BU1521GVW terminal function(2)

PIN No. Ball No. PIN Name In/Out

Init

PD

--

Function Description

8th bit of HD output pin

Core power supply (1.2 V)

9th bit of HD output pin

10th bit of HD output pin

11th bit of HD output pin

GND

I/O Type

I/O System

VDDIO3

--

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D7

D6

C8

C7

B8

C6

A8

B7

D5

A7

B6

A6

C5

B5

A5

A4

B4

C4

A3

B3

A2

C3

A1

DO8

VDD

Out

--

C

--

C

--

C

--

C

--

A

--

B

--

DO9

Out

--

PD

--

VDDIO3

--

DO10

DO11

GND

--

GND

--

DO12

GND

Out

--

PD

--

12th bit of HD output pin

GND

VDDIO3

--

DO13

DO14

DO15

VDDIO3

TEST0

TEST1

TEST2

GND

Out

--

PD

--

13th bit of HD output pin

14th bit of HD output pin

15th bit of HD output pin

Data output IO voltage (Typical 1.8 V)

Test pin 0 (Connect to GND)

Test pin 1 (Connect to GND)

Test pin 2 (Connect to GND)

GND

VDDIO3

--

In

--

VDDIO3

--

In

--

In

--

AVSS

CLKIN

DI8

--

GND for PLL

--

In

--

SD clock input (27 MHz)

8th bit of SD input data

4th bit of SD input data

GND

VDDIO1

--

In

--

DI4

In

--

GND

--

GND

--

GND

--

Init column indicates pin status when released from reset. Low: L output

PD: Pull-down

*1: No balls

*2: Input suspend function is fixed to OFF by an internal signal

*3: No pull-down function

●

Block Diagram

DIN[15:0]

Output

controller

Filter(5x5)

Interpolator

Upscaler

DOUT[15:0]

CLKOUT

Memory CTL

CLKIN

(27MHz)

PLL

Line memory

SPI I/F

Line memory

STBY

RESETB

Register Array

SCLK,SCSB,SDIN,SDOUT

Fig. 5 BU1521GVW Block diagram

www.rohm.com

2009.05 - Rev.A

7/15

Technical Note

BU1521GVW

●

Functions Discpriction

1. Input format

The following is the input format for BU1521GVW

480i or 576i(ITUR BT656) YCbCr 4:2:2 8bit(ITUR BT601) Digital Interface

Table. 9 Input format

Size including

Data

Pixel

Active

Format

Standard

bit width

clock (MHz)

blank (HxV)

858x525

Size (HxV)

480/59.94i

576/50i

8

27

720x(244/243)

720x(288/288)

ITUR BT656-4

864x625

SYS2 register (0 × 12) setting allows applying whether Y data and CbCr data to be assigned to lower DI [7:0] or upper DI [15:8].

2. Output format

480(I),576(I)

CLKIN[27MHz]

EAV

SAV

EAV

SAV

Input Data

(DI7-DI0)

Blanking

480(I)=276Clocks

576(I)=288Clocks

720Pixels(Y=720,Cb/Cr=360)

[1440Clocks]

Clock/Line

480(I)=1716Clock

576(I)=1728Clock

The following is the output format for BU1521GVW:

480i or 576i(ITUR BT656) YCbCr 4:2:2 8bit (ITUR BT601)Digital Interface

480p or 576p(ITUR BT1358) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface

1080/59.94i(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface

1080/50i(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface

1080/59.94p(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface

1080/50p(SMPTE 274) YCbCr 4:2:2 16bit(ITUR BT601) Digital Interface

Table. 10 Output format

Pixel

Blanking

Data

Clock

Frequency

(MHz)

27

Active Image

Size (HxV)

Format

Size including

Line (HxV)

Standard

bit width

480/59.94i

576/50i

8

858x525

864x625

720x(244/243)

720x(288/288)

720x483

ITUR BT656-4

8

27

480/59.94p

576/50p

16

27

858x525

ITUR BT1358

SMPTE 293M

864x625

720x576

1080/59.94i

1080/50i

74.25/1.001

74.25

2200x1125

2640x1125

2200x1125

2640x1125

1920x1080

SMPTE 274

1080/59.94p

1080/50p

148.5/1.001

148.5

www.rohm.com

2009.05 - Rev.A

8/15

Technical Note

BU1521GVW

3. IP conversion, upscale function

BU1521GVW upscales and interpolates images when upconverting to output format.

Supported image data I/O conversion is shown in Table. 11 .

Only input size of 720 or upscale to 1920 are supported for the horizontal direction.

The edge of the upscaled image can be enhanced (3 levels) by changing the UPC_SEL register.

When upscaling the 480i input, upscaling is applied to 240 lines among the overall effective lines

Table. 11 Image data I/O conversion table

Output (HD)

Input (SD)

480/

59.94i

○

480/

59.94p

○※

--

576/

50i

--

576/

50p

--

1080/

59.94i

○

1080/

50i

--

1080/

59.94p

○

1080/

50p

--

480/59.94i

576/50i

--

○

--

○

--

○

* Immediately after reset and when standby mode is set, 480i becomes 480p.

4. Filter fiunction

BU1521GVW can apply 5 taps of filtering both horizontally and vertically.

5 taps of filter tap coefficients can be set independently on horizontal and vertical directions using filter coefficient registers (0x14–0x1B).

5 x 5 Filter tap coefficients = Horizontal filter tap coefficients x Vertical filter tap coefficients.

The values of the horizontal and vertical filter taps must be set to make the sum of the coefficients 64.

The initial value makes the filter invalid.

[Horizontal filter tap coefficients]

1

2

3

4

5

TH1

TH2

TH3

TH4

TH5

/64

[Vertical filter tap coefficients]

1

2

3

4

5

TV1

TV2

TV3

TV4

TV5

/64

[5 × 5 filter tap coefficients]

列番号

行番号

1

2

3

4

5

1

2

3

4

5

TH1*TV1

TH1*TV2

TH1*TV3

TH1*TV4

TH1*TV5

TH2*TV1

TH2*TV2

TH2*TV3

TH2*TV4

TH2*TV5

TH3*TV1

TH3*TV2

TH3*TV3

TH3*TV4

TH3*TV5

TH4*TV1

TH4*TV2

TH4*TV3

TH4*TV4

TH4*TV5

TH5*TV1

TH5*TV2

TH5*TV3

TH5*TV4

TH5*TV5 /4096

Fig. 6 5 × 5 filter tap coefficients

www.rohm.com

2009.05 - Rev.A

9/15

Technical Note

BU1521GVW

5. Register access

Registers are accessed by 3 wire serial interfaces (SCSB, SCLK, SDIN, SDOUT).

Burst write/read is supported; therefore, consecutive writing is possible.



Regular write sequence

The address 8 bits and data 8 bits should be written in this order.

Both address and data have MSB first.

SCSB

SCLK

0

1

5

6

7

0

1

5

6

7

SDIN

Address 8bit (MSB First)

WriteData 8bit (MSB First)

7

0 7

Fig. 7 Regular write sequence

0



Regular read sequence

For reading, the address of the register to be read out should be written in the SADR register (0 × 70), then SRDAT register (0 × 80) should be read

out. Both address and data have MSB first.

SCSB

SCLK

0

1

5

6

7

0

1

5

6

7

0x80 (MSB First)

SDIN

7

0

ReadData 8bit (MSB First)

SDOUT

7

0

Fig. 8 Regular read sequence

6. PLL

BU1521GVW has an integrated PLL to generate and output the clock for HD format from the 27 MHz pixel clock.

The PLL output frequency is selected and output is executed according to the output format only, by setting the output format to the register.

The input frequency is 27 MHz and the output frequency can be 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz, or 148.5/1.001 MHz.

With 480i/576i output format, the 27 MHz input clock is output without going through the PLL.

www.rohm.com

2009.05 - Rev.A

10/15

Technical Note

BU1521GVW

●

Typical application circuit

The typical application circuit of BU1521GVW is shown in Fig. 9 It does not guarantee

+1.8V

AVSS

GND

CLKIN

0.1uF

DI[15:0]

GND

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

+3.0V

DI3

GND

DO11

DO10

DO9

AVDD

DI6

GND

0.1uF

GND

DI5

+1.2V

+3.3V

N.C

VDDIO1

DI12

DI9

VDD

0.1uF

GND

0.1uF

GND

DO8

DO7

BU1521GVW

DI14

DO5

¹⁰DI0

DO6

¹¹GND

¹²DI10

¹³DI7

GND

DO3

GND

DO4

+1.8V

¹⁴DI13

¹⁵GND

¹⁶GND

DO2

VDDIO3

DO0

0.1uF

GND

DO[15:0]

CLKOUT

+1.2V

+3.3V

+1.2V

0.1uF

GND

0.1uF

GND

0.1uF

GND

RESETB

SCLK

SCSB

SDIN

SDOUT

STBY

Note 1) Adjust the output damping resistance for CLKOUT and DO [15:0] with the line load.

Note 2) When the STBY pin is unused, pull it down with a 10 k resistor.

Fig. 9 BU1521GVW typical application circuit

www.rohm.com

2009.05 - Rev.A

11/15

Technical Note

BU1521GVW

●

I/O pin equivalent circuit diagram

Fig. 10 An I/O pin equivalent circuit diagram.

Type

The equivalent circuit structure

Type

The equivalent circuit structure

Internal signal

VDDIO

To internal

A

B

GND

Internal signal

GND

Input pin with Pull ｰ Down

Input pin with hysteresis and suspend

VDDIO

Internal signal

C

D

Internal signal

GND

Internal signal

GND

Output pin with a built-in pull ｰ down

Output pin

Fig. 10 BU1521GVW I/O pin equivalent circuit diagram

www.rohm.com

2009.05 - Rev.A

12/15

Technical Note

BU1521GVW

●

Not for uses

Absolute Maximum Ratings

(1)

An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down

devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the

absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.

Operating conditions

(2)

(3)

(4)

These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics

are guaranteed under the conditions of each parameter.

Reverse connection of power supply connector

The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the

reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal.

Power supply line

Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.

In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level

of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital

noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to

design the patterns in a similar manner.

Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time,

in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem

including the occurrence of capacity dropout at a low temperature, thus determining the constant.

GND voltage

(5)

(6)

Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to

be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.

Short circuit between terminals and erroneous mounting

In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the

ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply

or the GND terminal, the ICs can break down.

(7)

(8)

Operation in strong electromagnetic field

Be noted that using ICs in the strong electromagnetic field can malfunction them.

Inspection with set PCB

On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure

to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection

process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn

OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the

assembly process and pay thorough attention to the transportation and the storage of the set PCB.

Input terminals

(9)

In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can

cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough

attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any

parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC.

In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within

the guaranteed value of electrical characteristics.

(10)

(11)

Ground wiring pattern

If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the

small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and

voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause

fluctuations in the GND wiring pattern of external parts as well.

External capacitor

In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the

nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.

www.rohm.com

2009.05 - Rev.A

13/15

Technical Note

BU1521GVW

●

External Dimensional Drawing and Mark Drawing

U1521GVW

Top View

Lot.No.

Bottom View

Fig. 11 BU1521GVW Package external view (SBGA063W060)

www.rohm.com

2009.05 - Rev.A

14/15

Technical Note

BU1521GVW

● Ordering part number

B

U

1

5

2

1

G

V W

E

2

ROHM

Part No.

Package

Packaging and forming specification

E2: Embossed tape and reel

model name

GVW: SBGA

SBGA063W060

Tape

Embossed carrier tape(with dry pack)

Quantity

2000pcs

E2

Direction

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand.)

1234

Direction of feed

※When you order , please order in times the amount of package quantity.

1Pin

Reel

(Unit:mm)

www.rohm.com

2009.05 - Rev.A

15/15

Notice

N o t e s

No copying or reproduction of this document, in part or in whole, is permitted without the

consent of ROHM Co.,Ltd.

The content speciﬁed herein is subject to change for improvement without notice.

The content speciﬁed herein is for the purpose of introducing ROHM's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the speciﬁcations,

which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein

illustrate the standard usage and operations of the Products. The peripheral conditions must

be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information speciﬁed in this document.

However, should you incur any damage arising from any inaccuracy or misprint of such

information, ROHM shall bear no responsibility for such damage.

The technical information speciﬁed herein is intended only to show the typical functions of and

examples of application circuits for the Products. ROHM does not grant you, explicitly or

implicitly, any license to use or exercise intellectual property or other rights held by ROHM and

other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the

use of such technical information.

The Products speciﬁed in this document are intended to be used with general-use electronic

equipment or devices (such as audio visual equipment, ofﬁce-automation equipment, commu-

nication devices, electronic appliances and amusement devices).

The Products speciﬁed in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard

against the possibility of physical injury, ﬁre or any other damage caused in the event of the

failure of any Product, such as derating, redundancy, ﬁre control and fail-safe designs. ROHM

shall bear no responsibility whatsoever for your use of any Product outside of the prescribed

scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or

system which requires an extremely high level of reliability the failure or malfunction of which

may result in a direct threat to human life or create a risk of human injury (such as a medical

instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,

fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of

any of the Products for the above special purposes. If a Product is intended to be used for any

such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology speciﬁed herein that may

be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to

obtain a license or permit under the Law.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact us.

ROHM Customer Support System

http://www.rohm.com/contact/

www.rohm.com

R0039

A


型号：	BU1521GVW-E2
厂家：	ROHM
描述：	Consumer Circuit, PBGA63 商用集成电路
文件：	总16页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BU1521GVW-E2 [ROHM]

相关型号：

BU1523KV

BU1523KV-E2

BU1561GV

BU1563GV

BU1570KN

BU1570KN-E2

BU1570KN_09

BU1571KN

BU1571KN-E2

BU1571KN_10

BU1572GUW

BU1573KV