ML5233 [ROHM]
过充电和过放电电压检测充放电过电流检测高温检测短路电流检测内置FET驱动器多级连接;
| 型号： | ML5233 |
| 厂家： | 
ROHM |
| 描述： | 过充电和过放电电压检测充放电过电流检测高温检测短路电流检测内置FET驱动器多级连接 驱动 驱动器 |
| 文件： | 总34页 (文件大小：1487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL5233-04
1 December, 2020
ML5233
4- to 10-Series Cell Li-ion Rechargeable Battery Protection IC
■ General Description
The ML5233 is a protection IC for the 4- to 10-cell Li-ion rechargeable battery pack. It detects individual cell
overvoltage/undervoltage and the pack overcurrent/over-temperature, and then automatically turns on or turns
off the external charge/discharge NMOS-FETs accordingly. Also the ML5233 can be cascaded to handle battery
packs with more than 10 cells.
■ Features
• 4 to 10 cell high-precision overvoltage and undervoltage detection function
Voltage monitoring function for individual cells
Overvoltage detection threshold
Undervoltage detection threshold
4.25 V,
2.7 V,
Detection accuracy: ±15 mV (max)
Detection accuracy: ±50 mV (max)
• Overcurrent detection function
Discharge overcurrent detection threshold
Charge overcurrent detection threshold
150 mV, Detection accuracy: ±10 mV (max)
-40 mV, Detection accuracy: ±15 mV (max)
• Short circuit detection function
Short circuit detection threshold
300 mV, Detection accuracy: ±15 mV (max)
Detection delays adjustable using an external capacitor
• Temperature detection function
: With external NTC (10 k, B=3435) and 4.7 k resistor
Discharge inhibition temperature: 75 °C or higher
Charge inhibition temperature : 55 °C or higher
• External charge/discharge FET control: NMOS-FET gate driver built-in
External shut down command is accepted on the /CFOFF and /DFOFF pins
In a cascade configuration external circuits can be minimized with the power-up control pin VRSO
• Cell number selectable from predefined 4 values using the CS0 and CS1 pins
Product code 001 supports 7, 8, 9 or 10-cell connectivity
Cell numbers and other parameters can be redefined and supplied as an individual product code
• Low current consumption
Normal operation state : 25 µA (typ.),
60 µA (max)
Power-down state
: 0.1 µA (typ.), 1 µA (max)
• Supply voltage
: +5 V to +60 V
• Operating temperature
• Package
: -40°C to +85°C
: 32-pin LQFP
Note) This product is not intended for automotive use and for any equipment, device, or system that requires a
specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace
machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether
your application corresponds to such special purposes, please contact your local ROHM sales
representative in advance.
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FEDL5233-04
ML5233
■ Block Diagram
VDD
VREG
VNTC
TSNS
Voltage
Regulator
V10
Thermistor
Driver
V9
V8
V7
Voltage
Clamp
Temperature
Detector
Clock
Generator
V6
Reference
Voltage
Generator
CS0
V5
V4
Control
Logic
&
CS1
CAS
Delay
Timer
PULLD
Cell Voltage
Detector
V3
TEST
V2
V1
Cell Voltage
Monitor
VRSO
VRSI
Charger/Load
Detector
V0
/DFOFF
/CFOFF
FET
Driver
Current
Detector
GND
C_FET
D_FET
CDLY
ISENSE
■ Pin Configuration (top view)
VDD
V10
V9
V8
V7
V6
V5
V4
1
24 PULLD
23 CDLY
22 GND
21 TEST
20 VRSO
19 VRSI
18 N.C.
2
3
4
5
6
7
8
17 C_FET
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FEDL5233-04
ML5233
■ Pin Description
Pin
Pin No.
I/O
Description
Power supply input pin.
Connect an external CR filter for noise rejection.
1
VDD
—
Battery cell 10 high voltage input pin.
2
3
4
5
6
V10
V9
V8
V7
V6
I
I
I
I
I
Battery cell 10 low voltage input and Battery cell 9 high voltage input pin.
Battery cell 9 low voltage input and Battery cell 8 high voltage input pin.
Battery cell 8 low voltage input and Battery cell 7 high voltage input pin.
Battery cell 7 low voltage input and Battery cell 6 high voltage input pin.
Battery cell 6 low voltage input and Battery cell 5 high voltage input pin.
Should be connected to GND for the 4 cell series connected battery pack application.
Battery cell 5 low voltage input and Battery cell 4 high voltage input pin.
Should be connected to GND for the 4 to 5 cell series connected battery pack application.
Battery cell 4 low voltage input and Battery cell 3 high voltage input pin.
Should be connected to GND for the 4 to 6 cell series connected battery pack application.
Battery cell 3 low voltage input and Battery cell 2 high voltage input pin.
Should be connected to GND for the 4 to 7 cell series connected battery pack application.
Battery cell 2 low voltage input and Battery cell 1 high voltage input pin.
Should be connected to GND for the 4 to 8 cell series connected battery pack application.
Battery cell 1 low voltage input pin.
Should be connected to GND for the 4 to 9 cell series connected battery pack application.
Ground pins.
Current sense resistor input pin. Connect a resistor of the resistance value corresponding to
the detecting current between this pin and the GND pin. Should be tied to GND if not used.
Discharge FET control signal output pin. Should be tied to the gate pin of the external NMOS
FET.
Charge FET control signal output pin. Should be tied to the gate pin of the external NMOS
FET.
7
8
V5
V4
V3
V2
V1
V0
I
I
I
I
I
9
10
11
12
I
—
I
13, 22 GND
15
16
17
19
ISENSE
D_FET
C_FET
VRSI
O
O
Negative terminal of the load/charger input pin. Load or charger presence is decided by this
input level.
IO
Power-up signal output pin in cascade connection. Should be tied to the next upper VRSI pin.
LSI test input pin. Should be fixed to GND.
20
21
23
VRSO
TEST
CDLY
O
I
Short current detection delay time setting pin. Should be tied to GND through a capacitor.
IO
External pull-down control signal output for load removal detection. Should be tied to the gate
of the external pull-down control NMOS-FET when cascaded.
24
PULLD
O
Cascade mode selection input. Should be fixed to the VREG level when cascaded.
25
26
27
CAS
CS1
CS0
I
I
I
Pins to specify battery cell number. Either the VREG or the GND level should be applied.
Input pin for high temperature charge/discharge inhibition detection. Connect a thermistor
between this pin and GND. Should be tied to the VNTC pin if not used.
Thermistor power supply. Should be connected to TSNS through a 4.7 k resistor.
Should be pulled down with a 100 kΩ resistor if not used.
Built-in 4.3 V regulator output pin. Should be tied to GND through a 1 F capacitor. Do not
use this pin as power supply for an external circuit.
28
29
30
TSNS
VNTC
VREG
I
O
O
OFF control command input pin for the charge FET. The "L" level input forces Hi-Z on the
C_FET output. Should be tied to the next upper C_FET pin through an external resistor when
cascaded.
31
/CFOFF
I
OFF control command input pin for the discharge FET. The "L" level input forces "L" on the
D_FET output. Should be tied to the next upper D_FET pin through an external resistor when
cascaded.
32
/DFOFF
N.C.
I
No connect. Leave them electrically unconnected.
14, 18
—
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FEDL5233-04
ML5233
■ Absolute Maximum Ratings
GND=0V, Ta=25°C
Item
Symbol
VDD
Condition
Applied to VDD pin
Rating
Unit
Supply voltage
-0.3 to +86.5
-0.3 to VDD+0.3
V
V
V
VIN1
Applied to V0 to V10 pins
Applied to VRSI pin
VIN2
VDD-86.5 to VDD+0.3
Applied to /CFOFF and /DFOFF
pins
VIN3
VIN4
-0.3 to +86.5
V
V
Input voltage
Applied to CS0, CS1, CAS, TSNS,
CDLY, and ISENSE pins
-0.3 to VREG+0.3
VIN5
Applied to TEST pin
-0.3 to VDD+0.3
-0.3 to VDD+0.3
VDD-86.5 to VDD+0.3
-0.3 to +6.5
V
V
V
V
V
VOUT1
VOUT2
VOUT3
VOUT4
Applied to D_FET and VRSO pins
Applied to C_FET pin
Output voltage
Applied to VREG pin
Applied to VNTC and PULLD pins
-0.3 to VREG+0.3
Power
dissipation
PD
IOS
—
1.0
10
W
mA
°C
Short-circuit
output current
Applied to VREG, VNTC, PULLD,
C_FET, D_FET, and VRSO pins
Storage
temperature
TSTG
—
-55 to +150
■ Recommended Operating Conditions
(GND= 0 V)
Item
Symbol
VDD
Condition
Applied to VDD pin
—
Range
5 to 60
Unit
V
Supply voltage
Operational temperature
TOP
-40 to +85
°C
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ML5233
■ Electrical Characteristics
⚫ DC Characteristics
VDD=5 V to 60 V, GND=0 V, Ta=-40 to +85°C
Item
Symbol
VIH1
VIL1
Condition
—
Min.
Typ.
—
Max.
VREG
0.2×VREG
2
Unit
V
Digital "H" input voltage (Note 1)
Digital "L" input voltage (Note 1)
Digital "H" input current (Note 1)
Digital "L" input current (Note 1)
0.8×VREG
—
0
—
V
IIH1
VIH = VREG
VIL = GND
Average current in
normal operation
mode
—
–2
—
µA
µA
IIL1
—
—
Cell monitoring pin
Input current (Note 2)
IINVC
–0.1
0.1
3
µA
Cell monitoring pin
Input leakage current (Note 2)
IILVC
Power-down mode
—
—
2
µA
V
IOH=-10 µA
VDD =18 V to 60 V
IOL = 100 µA
FET "H" output voltage (Note 3)
VOH1
10
14
18
FET "L" output voltage (Note 4)
C_FET output leakage current
/CFOFF and /DFOFF pins
"H" input voltage
VOL1
ILCF
—
—
—
0.2
5
V
VCFET= 0 V to VDD
–5
µA
VIH2
VIL2
IIH2
—
VDD-0.1
—
—
—
—
VDD+18
VDD-1.5
2
V
V
/CFOFF and /DFOFF pins
"L" input voltage
—
0
/CFOFF and /DFOFF pins
"H" input current
VIH2=VDD
VIL2=0 V
—
–2
µA
µA
/CFOFF and /DFOFF pins
"L" input current
IIL2
—
PULLD pin "H" output voltage
PULLD pin "L" output voltage
CDLY pin "L" output voltage
VOH2
VOL2
VOL3
IOH = -100 µA
IOL = 100 µA
VREG-0.4
—
—
—
VREG
0.1
V
V
V
—
—
IOL = 100 µA
0.4
At short current
detection
CDLY pin pull-up resistor
VREG pin output voltage
VNTC pin output voltage
RPUC
VREG
VNTC
44
3.8
2.2
63
4.3
2.4
82
4.8
2.6
k
V
With load current 1
mA or less
With 14.7 kΩ
V
resistor connection
VNTC=0 V to 3.5 V
VTSNS=0 V to 3.5 V
VNTC pin output leakage current
TSNS pin input leakage current
ISENSE pin input leakage
current
ILNTC
IILTS
–2
–2
—
—
2
2
µA
µA
IILIS
VISENSE=0 V to 3.5 V
–2
—
2
µA
TEST pin pull-down resistance
RPDT
—
50
100
200
k
Note 1: Applied to CS0, CS1, and CAS pins.
Note 2: Applied to V0 to V10 pins.
Note 3: Applied to C_FET and D_FET pins.
Note 4: Applied to D_FET pin.
Note 5: Applied to C_FET pin.
⚫ Supply Current Characteristics
VDD= 5 to 60 V, GND=0 V, Ta=-40 to +85°C
Item
Symbol
IDD
Condition
Min.
Typ.
Max.
Unit
Current consumption in
normal operation
No output load
—
25
60
µA
Current consumption
in power-down mode
IDDS
No output load
—
0.1
1.0
µA
5/34
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ML5233
⚫ Detection/Release Threshold Characteristics (Ta = 25 °C)
VDD=36 V, GND=0 V, Ta=+25°C
Item
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
Overvoltage detection
threshold
—
4.235
4.25
4.265
V
Overvoltage release
threshold
VOVR
VUV
—
—
—
—
—
—
3.95
2.65
2.95
140
-55
4.00
2.70
3.00
150
-40
4.05
2.75
3.05
160
-25
V
V
Undervoltage detection
threshold
Undervoltage release
threshold
VUVR
VOCU
VOCO
VSHRT
V
Discharge overcurrent
detection threshold
Charge overcurrent
detection threshold
Short circuit
mV
mV
mV
285
300
315
detection threshold
High temperature
charge inhibition
detection threshold
High temperature
charge inhibition
release threshold
High temperature
discharge inhibition
detection threshold
High temperature
discharge inhibition
release threshold
VCHD
VCHR
VDHD
VDHR
—
—
—
—
0.99
1.16
670
800
1.02
1.21
700
850
1.05
1.26
730
900
V
V
mV
mV
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ML5233
⚫ Detection/Release Threshold Characteristics (Ta = 0 to 60 °C)
VDD=36 V, GND=0 V, Ta=0 to 60°C
Item
Symbol
VOV
Condition
Min.
Typ.
Max.
Unit
Overvoltage detection
threshold
—
4.225
4.25
4.275
V
Overvoltage release
threshold
VOVR
VUV
—
—
—
—
—
—
3.93
2.6
4.00
2.7
4.07
2.8
V
V
Undervoltage detection
threshold
Undervoltage release
threshold
VUVR
VOCU
VOCO
VSHRT
2.9
3.0
3.1
V
Discharge overcurrent
detection threshold
Charge overcurrent
detection threshold
Short circuit
135
-65
270
150
-40
300
165
-15
330
mV
mV
mV
detection threshold
High temperature
charge inhibition
detection threshold
High temperature
charge inhibition
release threshold
High temperature
discharge inhibition
detection threshold
High temperature
discharge inhibition
release threshold
VREG drop detection
threshold
VCHD
VCHR
VDHD
VDHR
—
—
—
—
0.97
1.14
650
780
1.02
1.21
700
850
1.07
1.28
750
920
V
V
mV
mV
VUREG
VRREG
—
—
3.0
3.4
3.4
3.8
3.8
4.2
V
V
VREG drop release
threshold
7/34
FEDL5233-04
ML5233
⚫ Charger Detection / Removal and Load Removal Threshold Characteristics (Ta=25 °C)
VDD=36 V, GND=0 V, Ta=+25°C
Item
Symbol
VPC
Condition
Wake-up from
power-down mode
In charge overcurrent state
CAS pin = "L"
Min.
Typ.
Max.
Unit
Charger detection
VRSI threshold
VDDX0.4
VDDX0.5
VDDX0.6
V
VPLU1
0.1
0.2
0.3
V
Charger removal
VRSI threshold
In charge overcurrent state
CAS pin = "H"
VPLU2
VPLD
VRL
0.3
VDDX0.7
2.2
0.4
VDDX0.75
2.4
0.5
VDDX0.8
2.6
V
V
V
Power-down mode
In discharge overcurrent
state
Load removal
VRSI threshold
⚫ Charger Detection / Removal and Load Removal Threshold Characteristics
(Ta=0 to 60 °C)
VDD=36 V, GND=0 V, Ta=0 to 60°C
Item
Symbol
VPC
Condition
Wake-up from power-down
mode
Min.
Typ.
Max.
Unit
Charger detection
VRSI threshold
VDDX0.35
VDDX0.5
VDDX0.65
V
In charge overcurrent state
CAS pin = "L"
VPLU1
0
0.2
0.4
0.4
0.6
V
Charger removal
VRSI threshold
In charge overcurrent state
CAS pin = "H"
VPLU2
VPLD
VRL
0.2
V
V
V
Power-down mode
In discharge overcurrent
state
VDDX0.65 VDDX0.75 VDDX0.85
Load removal
VRSI threshold
VRSI pin pull-up
resistance
2.0
2.4
2.8
In charge overcurrent state,
power-down mode
In discharge overcurrent
state
RPU
RPD
200
500
1000
kΩ
VRSI pin pull-down
resistance
0.5
-2
2
—
4
2
2
2
MΩ
CAS pin = "L"
Without pull-up/-down
resistor
ILPS1
ILPS2
IOL
µA
µA
µA
CAS pin = "L"
VRSI pin input current
Without pull-up/-down
resistor
-3
-0.2
1
CAS pin = "H"
CAS pin = "H"
VRSI pin = "L"
VOL = 5 V
VRSO pin output
current
0.5
VRSO pin output
leakage current
VRSO pin pull-down
resistance
VRSI pin = "H"
VRSO = 36 V
IOLK
0
—
2
µA
CAS pin = "H"
at wake-up
RPDR
200
500
1000
kΩ
8/34
FEDL5233-04
ML5233
⚫ Detection Delay and Monitor Cycle Characteristics (Ta = 25 °C)
VDD=36 V, GND=0 V, Ta=+25°C
Item
Symbol
tOV
Condition
Min.
2.6
Typ.
Max.
Unit
Overvoltage detection delay
(Note)
—
3.0
4.0
sec
Undervoltage detection delay
(Note)
tUV
—
—
—
0.85
70
1.00
100
100
1.65
130
130
sec
ms
ms
Charge overcurrent detection
delay
tOCO
tOCU
Discharge overcurrent
detection delay
70
Short circuit detection delay
Cell voltage monitor cycle
Temperature monitor cycle
Temperature measurement
time
tSC
tDET
tPT
CDLY=10 nF
0.7
320
320
1.0
400
400
1.3
480
480
ms
ms
ms
—
—
tTM
—
2.3
3
3.7
ms
Load removal delay
Charger removal delay
Internal source oscillation
clock cycle
tORL
—
—
70
70
100
100
130
130
ms
ms
tOCHG
tOSC
tOVT
tUVT
—
85
70
100
100
100
100
100
—
115
610
610
130
130
VREG
µs
ms
ms
ms
ms
V
Overvoltage detection delay
for test mode (Note)
Undervoltage detection delay
for test mode (Note)
Cell voltage monitor cycle
for test mode
TSNS pin = VREG
TSNS pin = VREG
TSNS pin = VREG
TSNS pin = VREG
—
70
tDETT
tPTT
70
Temperature monitor cycle
for test mode
70
TSNS pin input voltage
for test mode
VTST
VREG-0.3
(Note) Time lag due to cell voltage monitor cycle should be added on top of these values.
9/34
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ML5233
⚫ Detection Delay and Monitor Cycle Characteristics (Ta = 0 to 60 °C)
VDD=36 V, GND=0 V, Ta=0 to 60°C
Item
Symbol
tOV
Condition
Min.
2.4
Typ.
Max.
Unit
Overvoltage detection delay
(Note)
—
3.0
4.2
sec
Undervoltage detection delay
(Note)
tUV
—
—
—
0.80
50
1.00
100
100
1.75
150
150
sec
ms
ms
Charge overcurrent detection
delay
tOCO
tOCU
Discharge overcurrent
detection delay
50
Short circuit detection delay
Cell voltage monitor cycle
Temperature monitor cycle
Temperature measurement
time
tSC
tDET
tPT
CDLY=10 nF
0.6
300
300
1.0
400
400
1.4
500
500
ms
ms
ms
—
—
tTM
—
2
3
4
ms
Load removal delay
Charger removal delay
Internal source oscillation
clock cycle
tORL
—
—
50
50
100
100
150
150
ms
ms
tOCHG
tOSC
—
80
100
120
µs
(Note) Time lag due to cell voltage monitor cycle should be added on top of these values.
10/34
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ML5233
⚫ Transient Characteristics
VDD=36 V, GND=0 V, Ta=0 to 60°C
Item
Symbol
tDFETR
Condition
Min.
Typ.
Max.
Unit
D_FET pin
output rise time
C_FET pin
output rise time
D_FET pin
output fall time
CL=22 nF, RG=10 kΩ
—
95
400
µs
CL=22 nF, RG=1 0kΩ
RL=1 M
tCFETR
tFETF
—
—
95
1
400
150
µs
µs
CL=22 nF, RG=10 kΩ
◆Measurement circuit
C_FET
D_FET
RG=10kΩ
CL=22 nF
RG=10kΩ
GND
CL=22 nF
RL=1MΩ
◆Timing Diagrams
10 V
0.5 V
D_FET
0 V
0 V
tDFETF
tDFETR
10 V
0.5 V
C_FET
0 V
0 V
tCFETR
(Note) C_FET output fall depends on the time constant of the external loads RL and CL
11/34
FEDL5233-04
ML5233
■ Timing Diagrams
This section shows the timing diagrams of application circuit example 1 (without cascade connection).
⚫ Overvoltage Detection and Recovery
(Note 3)
(Note 2)
VOV
Voltage difference between
adjacent cell monitor pins
(Vn+1 - Vn)
VOVR
tDET
tDET
tDET
tDET
tDET
tDET
tDET
tOV
tDET
tDET
tDET
VOH1
VOH1
D_FET
C_FET
(Note 1)
0 V
GND
GND
VRSI
ISENSE
Overvoltage detection
delay timer operating
Charger present
Load present
Overvoltage state
State
Overvoltage
detected
Recovery from
overvoltage state
(Note 1) C_FET pin is pulled down with a resistor.
(Note 2) Even if the voltage difference between Vn+1 and Vn reaches or exceeds the overvoltage detection
threshold VOV, there may be a time lag before starting the overvoltage detection delay timer
because cell voltages are monitored every 400 ms (typ.).
(Note 3) Even if the voltage difference between Vn+1 and Vn reaches or exceeds the overvoltage release
threshold VOVR, there may be a time lag before recovering from the overvoltage state because cell
voltages are monitored every 400 ms (typ.).
12/34
FEDL5233-04
ML5233
⚫ Overvoltage Detection, Transition to Power-down Mode and Recovery
(Note 2)
(Note 1)
VUVR
VUV
Voltage difference between
adjacent cell monitor pins
tDET
tDET
tDET
tDET
tUV
tDET
tDET
tDET
(Vn+1 - Vn)
VOH1
D_FET
0 V
Hi-Z
VOH1
VOH1
C_FET
VRSI
VPLD
VPC
GND
GND
ISENSE
Undervoltage
detection delay
timer operating
Charger present
Load present
Undervoltage state
Undervoltage detected
State
Power-down
mode
Recovery from
undervoltage state
Charger detected
Recovery from power-down mode
(Note 1) Even if the voltage difference between Vn+1 and Vn reaches or exceeds the undervoltage
detection threshold VUV, there may be a time lag before starting the undervoltage detection delay
timer because cell voltages are monitored every 400 ms (typ.).
(Note 2) Even if the voltage difference between Vn+1 and Vn reaches or exceeds the undervoltage
release threshold VUVR, there may be a time lag before recovering from the undervoltage state
because cell voltages are monitored every 400 ms (typ.).
13/34
FEDL5233-04
ML5233
⚫ Discharge Overcurrent Detection and Recovery
Voltage difference between
adjacent cell monitor pins
(Vn+1 - Vn)
VOH1
D_FET
0 V
0 V
VOH1
C_FET
(Note 1)
VRL
VRSI
GND
GND
tORL
VOCU
ISENSE
tOCU
Load present
Load absent
Load absent
Discharge overcurrent
detected
Discharge overcurrent state
Load removal
State
Recovery from discharge
overcurrent state
(Note 1) C_FET pin is pulled down with a resistor.
14/34
FEDL5233-04
ML5233
⚫ Charge Overcurrent Detection and Recovery
Voltage difference between
adjacent cell monitor pins
(Vn+1 - Vn)
VOH1
D_FET
VOH1
C_FET
(Note 1)
0 V
GND
VPLU
VRSI
tOCO
tOCHG
GND
ISENSE
VOCO
Charger absent
Charger present
Charger absent
State
Charge overcurrent state
Charge overcurrent
detected
Charger removal
Recovery from charge
overcurrent state
(Note 1) C_FET pin is pulled down with a resistor.
15/34
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ML5233
⚫ Short Circuit Detection and Recovery
Voltage difference between
adjacent cell monitor pins
(Vn+1 - Vn)
VOH1
D_FET
0 V
0 V
VOH1
C_FET
(Note 1)
CDLY
VRSI
GND
GND
VRL
tORL
VSHRT
GND
ISENSE
State
tSC
Load absent
Load present
Load absent
Short circuit detected
Short circuit state
Load removal
Recovery from
short circuit state
(Note 1) C_FET pin is pulled down with a resistor.
16/34
FEDL5233-04
ML5233
⚫ High Temperature Detection and Recovery
VNTC
VNTC
Hi-Z
VCHR
VCHD
VDHR
VDHD
0 V
TSNS
tPT
tPT
tPT
tPT
tTM
tTM
VOH1
C_FET
(Note 1)
0 V
VOH1
D_FET
State
0 V
Temperature below
45 °C is detected
Temperature above
75 °C is detected
Temperature between
55 °C and 75 °C is detected
Temperature between
45 °C and 65°C is
detected
Charge permitted
Charge inhibited
Charge inhibited
Charge inhibited
Charge permitted
Discharge permitted
Discharge permitted
Discharge inhibited
Discharge permitted
Discharge permitted
(Note 1) C_FET pin is pulled down with a resistor.
(Note 2) NTC(10kΩ,B=3435) and 4.7kΩ resistor is connected.
17/34
FEDL5233-04
ML5233
■ Functional Description
⚫ States of ML5233
The ML5233 has the following eight states which depend on individual cell voltages and the input
levels of the ISENSE and TSNS pins.
1. Initial state
2. Normal operation state
3. Overvoltage state
4. Undervoltage state (including power-down mode)
5. Discharge overcurrent state
6. Charge overcurrent state
7. Short circuit state
8. High temperature state
Each state is described below, without cascade connection (CAS pin fixed to GND).
1. Initial State
The initial state refers to the period while the battery cells are being connected to the ML5233 and
connection of all the battery cells specified by the CS0 and CS1 pins is completed, before transitioning
to the normal state. In the initial state, when the VREG pin voltage reaches or exceeds the VREG drop
detection threshold, the D_FET pin output is set to the "L" level and the C_FET pin output to the "H"
level, where discharge is inhibited and charge is permitted.
When the VREG pin level reaches or exceeds the VREG drop release threshold, individual cell
voltage monitoring takes place. If all the battery cells specified by the CS0 and CS1 pins reach or
exceed the undervoltage release threshold VUVR, the system transitions to the normal state. Overvoltage
and overcurrent detection is also performed in parallel.
PACK(+)
VDD
VRSI
C_FET
D_FET
GND
ISENSE
PACK(-)
OFF
ON
Figure 1 Initial State
18/34
FEDL5233-04
ML5233
2. Normal Operation State
The normal state refers to the period where all the battery cell voltages do not reach or exceed the
overvoltage/undervoltage detection threshold, the ISENSE pin voltage is below the overcurrent
detection threshold, and the TSNS pin voltage is above the high temperature detection threshold. In the
normal state, both the D_FET and C_FET pin outputs are set to the "H" level, where both charge and
discharge is permitted.
Individual cell voltages are monitored every 0.4 second for performing overvoltage/undervoltage
detection, while the pack temperature is also monitored using an external thermistor every 0.4 second.
The ISENSE pin voltage is always monitored to detect overcurrent in parallel.
PACK(+)
VDD
VRSI
C_FET
D_FET
GND
ISENSE
PACK(-)
OFF
Figure 2 Normal Operation State
ON
19/34
FEDL5233-04
ML5233
3. Overvoltage State
When any one or more battery cell voltages reach or exceed the overvoltage detection threshold VOV
for longer than the overvoltage detection delay time tOV, the system enters the overvoltage state. In the
overvoltage state, the C_FET pin output is set to "Hi-Z" to inhibit charge, while the D_FET pin output
maintains the value in the previous state.
Battery cell voltages decrease gradually by self-discharge or a connected light load. When all of them
reach or exceed the overvoltage detection release threshold VOVR, the system recovers from the
overvoltage state.
PACK(+)
VDD
VRSI
C_FET
D_FET
GND
ISENSE
PACK(-)
Maintains the
OFF
previous value
Figure 3 Overvoltage State
20/34
FEDL5233-04
ML5233
4. Undervoltage State
When any one or more battery cell voltages reach or exceed the undervoltage detection threshold
VUV for longer than the undervoltage detection delay time tUV, the system enters the undervoltage state.
In the undervoltage state, the D_FET pin output is set to the "L" level to inhibit discharge, while the
C_FET pin output maintains the value in the previous state.
In the undervoltage state, a 500 k pull-up resistor is connected between the VRSI pin and VDD.
When the VRSI pin voltage increases and reaches the charger removal VRSI threshold VPLD after
turning off the external discharge FET, the system enters power-down mode to reduce current
consumption. The VRSI pin voltage decreases when a charger is present. If it reaches or exceeds the
charger detection voltage VPC, the system wakes up all the circuits to resume monitoring individual
battery cell voltages.
If the system was in the overvoltage, undervoltage, high temperature or any overcurrent state before
entering power-down mode, these error flags are cleared during power-down. After wake-up, if these
errors are detected again for longer than the specified detection delay time, the system reenters the
corresponding error state.
Battery cell voltages increase gradually while charging, and if all cell voltages reach or exceed the
undervoltage detection release threshold VUVR, the system recovers from the undervoltage state and
the pull-up resistor between VRSI pin and VDD is disconnected.
PACK(+)
VDD
VRSI
C_FET
D_FET
GND
ISENSE
PACK(-)
Maintains the previous value
* OFF in power-down mode
OFF
Figure 4 Undervoltage State (Power-down mode)
21/34
FEDL5233-04
ML5233
5. Discharge Overcurrent State
When the load is connected and ISENSE pin voltage reaches or exceeds the discharge overcurrent
detection threshold VOCU for longer than the discharge overcurrent detection delay time tOCU, the system
enters the discharge overcurrent state, regardless of the individual battery cell voltages. In the discharge
overcurrent state, the D_FET pin output is set to the "L" level to inhibit discharge, while the C_FET pin
output is set to "Hi-Z" to monitor load removal.
In the discharge overcurrent state, the VRSI pin is pulled-down with a 2 M resistor and a backflow
prevention diode. If the load is released, the VRSI pin level approaches the GND level. The system
recovers from the discharge overcurrent state when the VRSI pin level reaches or exceeds the load
disconnection detection threshold VRL for longer than the load disconnection detection delay time tORL
.
PACK(+)
VDD
VRSI
C_FET
D_FET
GND
ISENSE
PACK(-)
OFF
Figure 5 Discharge Overcurrent State
OFF
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FEDL5233-04
ML5233
6. Charge Overcurrent State
When the charger is connected and ISENSE pin voltage reaches or exceeds the charge overcurrent
detection threshold VOCO for longer than the charge overcurrent detection delay time tOCO, the system
enters the charge overcurrent state, regardless of the individual battery cell voltages. In the charge
overcurrent state the C_FET pin output is set to "Hi-Z" to inhibit charge, while the D_FET pin output
maintains the value in the previous state.
In the charge overcurrent state, a 500 k pull-up resistor is connected between the VRSI pin and
VDD pin to detect charger removal. If the charger is removed, the VRSI pin level increases. The system
recovers from the charge overcurrent state when the VRSI pin voltage reaches or exceeds the charger
removal detection threshold VPLU for longer than the charger removal delay time tOCHG
.
PACK(+)
VDD
VRSI
C_FET
D_FET
GND
ISENSE
PACK(-)
Maintains the
OFF
previous value
Figure 6 Charge Overcurrent State
23/34
FEDL5233-04
ML5233
7. Short Circuit State
When the pack is overloaded and the ISENSE pin voltage reaches or exceeds the short circuit
detection threshold VSHRT, the capacitor connected to the CDLY pin is started to charge, regardless of
the battery cell voltages. When the CDLY pin voltage is increased to a specific level, the system enters
the short circuit state. In the short circuit state, the D_FET pin output is set to "L" level to inhibit
discharge, while the C_FET pin output is set to "Hi-Z" to detect load removal. Also, a 2 M pull-down
resistor is connected between the VRSI pin and the GND pin through a backflow prevention diode.
If the load is removed, the VRSI pin level approaches the GND level. The system recovers from the
short circuit state when the VRSI pin level reaches or exceeds the load removal detection threshold VRL
for longer than the load removal detection delay time tORL
.
PACK(+)
VDD
VRSI
C_FET
D_FET
GND
ISENSE
PACK(-)
OFF
OFF
Figure 7 Short Circuit State
24/34
FEDL5233-04
ML5233
8. High Temperature State
Pack temperature is monitored using an external thermistor every 0.4 seconds when the ML5233 is
not in power-down mode, regardless of battery cell voltages. When the TSNS pin voltage reaches or
exceeds the high temperature charge inhibition detection threshold VCHD, the C_FET pin output is set to
the "Hi-Z" state to inhibit charge.
As temperature increases further, if the TSNS pin voltage reaches or exceeds the high temperature
discharge inhibition detection threshold VDHD, the D_FET pin output is set to the "L" level to inhibit
discharge. Temperature monitoring is continued every 0.4 second in the high temperature state, too, and
if the TSNS pin voltage reaches or exceeds the high temperature release threshold, the system recovers
from the high temperature state.
PACK(+)
VNTC
VDD
2.4 V
TSNS
VCHR
VDHR
VCHD
VDHD
C_FET
D_FET
GND
ISENSE
PACK(-)
OFF
Figure 8 High Temperature State
OFF
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FEDL5233-04
ML5233
⚫ Selecting the Number of Battery Cells
Cell count is selectable from predefined 4 values using the CS0 and CS1 pins.
Product code 001 supports 7, 8, 9 or 10 cells, and its configuration is given in the table below.
CS1
CS0
Battery cell number
Unused Vn pins
GND
GND
VREG
VREG
GND
VREG
GND
10 cell
9 cell
8 cell
7 cell
None
V0
V0, V1
V0, V1, V2
VREG
All unused Vn pins should be tied to GND.
⚫ Power-on/Power-off Sequence
Battery cells can be connected in any order, but it is recommend that the GND and VDD pins are
connected first, and then connection continues from lower to higher voltage cells. There are no
restrictions on the power supply voltage rise time at power-on, and power-off sequence or power supply
voltage fall time at power-off.
After power-on, the system usually transitions to the normal state. However, it may transition to the
undervoltage state due to chattering at power-on or other reasons. If it has transitioned to the
undervoltage state and moved to power-down mode, apply the charger connection detection threshold
VPC or lower level to the VRSI pin to power it up again.
⚫ Handling VDD Pin and V0 to V10 Pins
Since the VDD pin is the power supply input, put a noise elimination RC filter in front of the VDD
input for stabilization. If the drive current on the external charge/discharge control FETs is large, the
resistor value of this noise filter should be adjusted so that the voltage drop across the resistor is smaller
than 1 V.
The V0 to V10 pins are the monitor pins for individual cell voltages. Put a noise elimination RC filter
in front of each battery cell to prevent false detection. On a system with less than 10 battery cells,
unused Vn pins should be tied to GND.
⚫ Handling VREG Pin
The VREG pin is the power source of the built-in regulator which supplies power to the internal
modules. Connect a 1 µF or larger capacitor between this pin and GND for stabilization. Do not use it as
a power supply for external circuits since the supply current of the built-in regulator is limited.
⚫ Setting Short Circuit Detection Delay
The short circuit detection delay (tSC) depends on the charge time of the capacitor (CDLY) connected
to the CDLY pin, which is described by the following equation.
Short circuit detection delay tSC [ms] = CDLY [nF] × 0.1
A 1 nF or larger capacitor is recommended for CDLY. For a smaller capacitance, 20 µs (typ.) should be
added as a delay for the short current detection comparator. Note that the external CR filter on the
ISENSE pin also comprises the total delay.
⚫ External Control of Charge/Discharge Control FET
The C_FET and D_FET pin output values can be directly controlled by the /CFOFF and /DFOFF pin
inputs, regardless of the detected state on the ML5233.
When the /CFOFF pin input is set to "L", the C_FET pin output is fixed to “Hi-Z”.
When the /DFOFF pin input is set to "L", the D_FET pin output is fixed to GND.
When the /CFOFF and /DFOFF pin inputs are set to "H", the C_FET and D_FET pin outputs depend on
the detected state on the ML5233.
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FEDL5233-04
ML5233
⚫ Output Pin Values in Each Detection State
The output pin values in each detection state are shown in the table below.
State
D_FET
GND
14 V
No change
GND
C_FET
14 V
14 V
Hi-Z
No change
Hi-Z
VRSI
Hi-Z
Hi-Z
VREG
4.3 V
4.3 V
4.3 V
4.3 V
0 V
Initial state
Normal operation state
Overvoltage state
Undervoltage state
Power-down mode
Discharge overcurrent
state
No change
Pull-up
Pull-up
GND
GND
Hi-Z
Pull-down
4.3 V
Charge overcurrent
state
No change
GND
Hi-Z
Hi-Z
Hi-Z
Pull-up
4.3 V
4.3 V
4.3 V
Short circuit state
High temperature
charge inhibition state
High temperature
discharge inhibition
state
Pull-down
No change
No change
GND
Hi-Z
No change
4.3 V
(Note) "No change" means that the previous pin value is maintained in a new state.
⚫ Unused Pin Treatment
The following table shows how to handle unused pins.
Unused pins
V0 to V5
ISENSE
CDLY
Recommended treatment
Pull down
Pull down
Open
/CFOFF,/DFOFF
VRSO
Pull up
Open
TSNS
VNTC
PULLD
Tied to the VNTC pin
Pull down with a 100 k resistor
Open
⚫ Reducing Monitor Cycles and Detection Delays
The cell monitor cycle and overvoltage/undervoltage detection delays are reduced to 100 ms (typ.) by
applying the VREG level to the TSNS pin. The temperature monitor cycle is also reduced to 100 ms
(typ.), but high temperature detection does not work because the TSNS pin is fixed to the VREG level.
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ML5233
⚫ Cascade Connection
Cascade wiring for three ML5233 devices is shown below.
1. Fix the CAS pin to the VREG level.
2. Connect the higher C_FET pin and the lower /CFOFF pin through a resistor.
3. Connect the higher D_FET pin and the lower /DFOFF pin through a resistor.
4. Connect the highest /CFOFF and /DFOFF pins to VDD pin.
5. Connect the lower VRSO pin and the higher VRSI pin through an NMOS-FET.
6. Connect the lowest VRSI pin to Pack(-) through a diode and a resistor.
7. Leave the top VRSO pin electrically open.
8. Connect the lowest PULLD pin to the NMOS-FET gate, whose drain terminal should be tied to
Pack(-) through a resistor.
Pack(+)
/DFOFF
/CFOFF
VREG
CAS
VDD
ML5233-3
ML5233-2
ML5233-1
VRSO
VRSI
GND
ISENSE
C_FET
D_FET
/DFOFF
/CFOFF
VREG
CAS
VDD
VRSO
GND
VRSI
ISENSE
PULLD
D_FET
C_FET
/DFOFF
/CFOFF
VREG
CAS
VDD
VRSO
GND
VRSI
ISENSE
PULLD
_D_FET
C_FET
Pack(-)
It is recommended that a greater number of cells should be assigned to the lowest IC to drive the
charge/discharge control FETs on the GND correctly. For example, when 7 cells and 10 cells are
cascaded, the 10 cells should be assigned to the lower IC and the 7 cells to the higher one.
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ML5233
⚫ Redefinition of Battery Cell Number
4 cell numbers can be redefined so that one of them is selectable with CS0 and CS1 in the range
shown in the following table.
CS1
CS0
Range of cell numbers
GND
GND
VREG
VREG
GND
VREG
GND
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
VREG
⚫ Redefinition of Detection/Release Threshold Range and Step
The detection/release thresholds can be redefined as shown in the following table.
Since some combinations are unavailable, contact us for details.
Detecting voltage
Overvoltage detection
threshold
Threshold range
3.65 V to 4.35 V
3.5 V to 4.25 V
1.6 V to 3 V
Threshold step
25 mV
Overvoltage release threshold
Undervoltage detection
threshold
Undervoltage release threshold
Discharge overcurrent
detection threshold
Charge overcurrent detection
threshold
Short circuit detection
threshold
High temperature detection
threshold
25 mV
100 mV
100 mV
10 mV
2.3 V to 4.3 V
50 mV to 200 mV
-60 mV to -20 mV
100 mV to 500 mV
0.6 V to 1.2 V
10 mV
10 mV
10 mV
10 mV
High temperature release
threshold
0.7 V to 1.3 V
⚫ Redefinition of Detection Delay Time
The detection delay times can be redefined as shown in the following table.
Settable time
Unit
Detection delay time
Overvoltage detection delay time
Undervoltage detection delay time
1
1
2
2
3
3
4
4
5
5
sec
sec
Discharge overcurrent detection
delay time
Charge overcurrent detection
delay time
25
25
50
50
100
100
200
200
400
400
ms
ms
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FEDL5233-04
ML5233
■ Application Circuit Example 1 (10-cell system)
PACK(+)
RVDD
32
1
VDD
V10
V9
/DFOFF
/CFOFF
VREG
VNTC
TSNS
CS0
CVDD
RCEL
31
30
29
28
2
3
4
CCEL
CREG
V8
RT
V7
5
6
7
27
26
25
24
V6
RNTC
V5
CS1
V4
CAS
8
9
V3
PULLD
CDLY
GND
23
22
V2
10
CDLY
V1
11
12
13
21
20
V0
TEST
VRSO
GND
ISENSE
CIS
VRSI 19
17
C_FET
15
RIS
16 D_FET
RVRS
RISIN
RG
RG
PACK(-)
RGS
The wire length indicated by a dotted line should be minimized, because the voltage
drop due to wire resistance may affect the current detection accuracy.
■ Recommended Values for External Components
Recommended
value
Recommended
value
Component
Component
RGS
RG
RVRS
RIS
RISIN
RT
1 MΩ
10 kΩ to 47 kΩ
1 kΩ
1 mΩ to 5 mΩ
1 kΩ
RVDD
CVDD
RCEL
CCEL
CREG
CIS
510 Ω
10 µF or more
1 kΩ to 10 kΩ
0.1 µF or more
1µF
4.7 kΩ
10 nF
RNTC
10 kΩ, B3435
CDLY
1 nF to 10 nF
(Note) This circuit example and the recommended values of external components are not always
warranted. Evaluation on customer’s application is required and select circuit and parts
depend on customer’s application.
30/34
FEDL5233-04
ML5233
■ Application Circuit Example 2 (15-cell system, 8 cells and 7 cells)
PACK(+)
RVDD
32
1
VDD
V10
V9
/DFOFF
/CFOFF
VREG
VNTC
TSNS
CS0
CVDD
RCEL
31
30
29
28
2
3
4
5
6
7
CCEL
CREG
V8
RT
RVDD
CVDD
V7
32
1
VDD
V10
V9
/DFOFF
/CFOFF
VREG
VNTC
TSNS
CS0
RFON
RFON
27
26
25
24
V6
RNTC
RCEL
31
30
29
28
2
3
4
V5
CS1
CCEL
CREG
V4
CAS
8
9
V8
V3
PULLD
CDLY
GND
RT
V7
5
6
7
23
22
V2
10
27
26
25
24
V6
RNTC
V1
11
12
13
V5
CS1
21
20
V0
TEST
VRSO
V4
CAS
8
9
ROR
GND
ISENSE
V3
PULLD
CDLY
GND
VRSI 19
15
23
22
21
20
V2
10
CDLY
17
16 D_FET
C_FET
V1
11
12
13
RCF
V0
TEST
VRSO
RGU
GND
ISENSE
CIS
VRSI 19
17
C_FET
15
RIS
16 D_FET
RVRS
RISIN
RG
RG
PACK(-)
RGS
■ Recommended Values for External Components
Recommended
value
Recommended
value
Component
Component
RG
RVRS
RIS
RISIN
RT
10 kΩ to 47 kΩ
1 kΩ
1 mΩ to 5 mΩ
1 kΩ
4.7 kΩ
10 kΩ, B3435
5.1 MΩ
RVDD
CVDD
RCEL
CCEL
CREG
CIS
510 Ω
10 µF or more
1 kΩ to 10 kΩ
0.1 µF or more
1 µF
10 nF
1 nF to 10 nF
1 MΩ
RNTC
RGU ,RFON
ROR
CDLY
RGS
1 MΩ
RCF
1.2 MΩ
(Note) This circuit example and the recommended values of external components are not always
warranted. Evaluation on customer’s application is required and select circuit and parts
depend on customer’s application.
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FEDL5233-04
ML5233
■ Package Dimensions
Caution regarding surface mount type packages
Surface mount type packages are susceptible to heat applied in solder reflow and moisture absorbed during
storage. Please contact your local ROHM sales representative for recommended mounting conditions (reflow
sequence, temperature and cycles) and storage environment.
32/34
FEDL5233-04
ML5233
■ Revision History
Page
Before
Document No.
Issue date
Revision description
After
revision
revision
FEDL5233-01
FEDL5333-02
FEDL5333-03
14 Sep, 2015
25 Dec, 2015
25 Mar, 2016
-
-
Initial release, based on FJDL5233-01.
Cascade connection, pin name is corrected.
High temperature charge inhibition detection
threshold (Ta=25℃) is 0.97(min)->0.99(min)
High Temperature Detection and Recovery,
note2 is added.
28
28
6
6
17
17
Application Circuit examples; capacitor
connection of lowest cell is modified.
Note is added
30,31
30,31
Application Circuit example 2; the value of RGU
is modified.
31
31
FEDL5333-04
1 Dec, 2020
-
-
Changed Company name
34
34
Changed “Notes”
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FEDL5233-04
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Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating
conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products
outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within
such usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.
Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of
LAPIS Technology Products, please take safety at your own risk measures such as complying with the derating
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe
procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate
the standard operation of semiconductor products and application examples. You are fully responsible for the
incorporation or any other use of the circuits, software, and information in the design of your product or system.
And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS
Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising
from the use of these circuits, software, and other related information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of
LAPIS Technology or any third party with respect to LAPIS Technology Products or the information contained
in this document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and
application examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any
dispute, concerning such rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer
systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our
Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a
LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,
trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical
systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all
liability for any losses and damages incurred by you or third parties arising by using the Product for purposes
not intended by us. Do not use our Products in applications requiring extremely high reliability, such as
aerospace equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this
document. However, LAPIS Technology does not warrant that such information is error-free and LAPIS
Technology shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the
RoHS Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting
non-compliance with any applicable laws or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide
by the procedures and provisions stipulated in all applicable export laws and regulations, including without
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this
document or LAPIS Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2020 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
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