KS86C6308Q-XX [SAMSUNG]
Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQFP64, 14 X 20 MM, QFP-64;
| 型号： | KS86C6308Q-XX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQFP64, 14 X 20 MM, QFP-64 微控制器 |
| 文件： | 总28页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS86C6308/P6308
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM88RCRI microcontrollers
have an external interface that provides access to external memory and other peripheral devices.
KS86C6308/P6308 MICROCONTROLLER
The KS86C6308/P6308 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The KS86C6308 has 8 K bytes of program
memory on-chip.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
— Five configurable I/O ports (32 pins)
— 20 bit-programmable pins for external interrupts
— 8-bit timer/counter and 16-bit timwe/counter with three operating modes
— Full speed low speed USB function
The KS86C6308/P6308 is a versatile microcontroller that can be used in a wide range of full/low speed USB
support general purpose applications. It is especially suitable for use as a keyboard with hub controller and is
available in a 64-pin SDIP and a 64-pin QFP package.
OTP
The KS86C6308 microcontroller is also available in OTP (One Time Programmable) version, KS86P6308.
KS86P6308 microcontroller has an on-chip 8-Kbyte one-time-programmable EPROM instead of masked ROM.
The KS86P6308 is comparable to KS86C6308, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
FEATURES
CPU
Timer A
•
One 8-bit basic timer for watchdog function and
programmable oscillation stabilization
programmable 8-bit timer internal generation
function interval, capture, PWM mode
match/capture overflow interrupt
•
SAM88RCRI CPU core
Memory
•
•
8-KB Internal program memory(ROM)
256-byte internal register file
(160-byte:General Purpose)
Timer B
Programmable 16-bit timer interval generation
•
function interval, capture, PWM mode
match/capture overflow interrupt
Instruction Set
•
•
41 instructions
IDLE and STOP instructions added for power-
down modes
Universal Serial Bus with HUB
•
•
1 upstream port
4 downstream port and one embedded function
each port supports separated enable LED built-
in 3.3 V voltage regulator
Instruction Execution Time
332ns at 12 MHz fOSC
•
Interrupts
USB/GPIO Function
Upstream port
•
32 interrupt sources with one vector, each
•
source has its pending bits
•
One level, one vector interrupt structure
Operation Temperature Range
- 40 °C to + 85 °C
•
Oscillation Frequency
Operation Voltage Range
4.0 V to 5.5 V
•
•
12 MHz crystal/ceramic oscillator
External clock source
•
Package Types
General I/O
•
•
64-pin SDIP
64-pin QFP
•
Bit programmable five I/O ports (30 pins total)
1-2
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
BLOCK DIAGRAM
DP0/GPIO, DM0/GPIO
DP1, DM1
DP2, DM2
DP3, DM3
DP4, DM4
USB Transceiver
&
Voltage Regulator
3.3 VOUT
LPF
12 MHz
XI
PWREN1
PWREN2
PWREN3
PWREN4
48 MHz
OSC
XO
PLL
USB
Module
OCDET1
OCDET2
OCDET3
OCDET4
SAM88RCRI
CORE
12 MHz
LVD
USB
Device
Control
LEDON0
LEDON1
LEDON2
LEDON3
LEDON4
GANGED
8K
V
DD
SS
SS1
8
ROM
V
B
i
t
Port
Port
Port
Port
Port
P0.0/INT2 - P0.7/INT2
P1.0 - P1.7
V
160 Byte
RAM
TEST
RESET
TMOD
B
U
S
Timer A
(8 Bit)
P2.0/INT0 - P2.7/INT0
Timer B
(16 Bit)
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.1/TACAP/TBOUT
Basic
Timer
P4.0/INT1
P4.1/INT1
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
PIN ASSIGNMENTS
LEDON3
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LEDON4
P1.4
LEDPN2
LEDON1
LEDON0
OCDET4
PWREN4
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
P1.5
P1.6
P1.7
P4.0/INT1
P4.1/INT1
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SDAT /P2.6/INT0
SCLK /P2.7/INT0
VDD/VDD
VSS/VSS
XO/XO
XI/XI
TEST/TEST
LPF
PWREN
3
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
VSS/VSSA
RESET/RESET
TMODE
DP0/GPIO
DM0/GPIO
DP1
VSS1/VSS
OCDET2
PWREN2
ECDET1
PWREN1
3.3VOUT
DM4
DM1
DP2
DM2
DP3
DP4
DM3
Figure 1-2. Pin Assignment Diagram (64-Pin SDIP Package)
1-4
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
1
2
3
4
5
6
7
8
51
50
43
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
PWREN3
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
GANGED
P2.5/INT0
SDAT /P2.6/INT0
SCLK /P2.7/INT0
V
/V
DD DD
9
KS86C6308
(KS86P6308)
V
/V
SS SS
10
11
12
13
14
15
16
17
18
19
XO/XO
XI/XI
TEST/TEST
LPF
VSS/VSSA
RESET/RESET
TMODE
DP0/GPIO
DM0/GPIO
Figure 1-3. Pin Assignment Diagram (64-Pin QFP Package)
1-5
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
PIN DESCRIPTIONS
Table 1-1. KS86C6308/P6308 Pin Descriptions
Pin
Names
I/O
Pin
Description
Pin
Type
Share
Pins
P0.0-P0.7
I/O
B
INT2
Bit-programmable I/O port for Schmitt trigger input or
open-drain output. Port 0 can be individually configured
as external interrupt inputs. Pull-up resistors are
assignable by software.
P1.0-P1.7
P2.0-P2.7
I/O Bit-programmable I/O port for Schmitt trigger input or
open-drain output. Pull-up resistors are assignable by
software.
B
B
–
I/O Bit-programmable I/O port for Schmitt trigger input or
open-drain output. Port 2 can also be individually
configured as external interrupt inputs. Pull-up resistors
are assignable by software.
INT0
P3.0-P3.3
I/O Bit-programmable I/O port for Schmitt trigger input, open-
drain output or push-pull output. Port 3 are designed for
to drive LED directly. P3.3 can be used to system clock
output(CLO) pin. P3.2 PLL clock out for PLL Block.
C
D
P3.3/TACLK/CLO
P3.2/TBCLK/
USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
P4.0-P4.1
3.3 VOUT
I/O Bit-programmable I/O port for Schmitt trigger input or
open-drain output or push-pull output. Port4 can also be
individually configured as external interrupt inputs. In
output mode, pull-up resistors are assignable by
INT1
software. But in input mode, pull-up resistors are fixed.
–
–
3.3 V output from internal voltage regulator
–
–
–
–
X
IN
System clock input and output pin (crystal/ceramic
oscillator, or external clock source)
X
OUT
INT0
INT1
INT2
I
External interrupt for bit-programmable port0, port2 and
port4 pins when set to input mode.
–
P2.0-P2.7
P4.0/P4.1
P0.0/P0.7
RESET
LPF
I
I
I
RESET signal input pin with LVD
A
–
–
–
–
–
Low Pass Filter Pin for PLL
TEST
Test signal input pin (for factory use only; must be
connected to V
)
SS
TMODE
VDD
I
Test signal input pin (for factory use only, must be
connected to V
–
–
)
SS
Power input pin
–
–
–
–
–
–
VSS
VSS1 is a ground power for CPU core.
VSS2 is a ground power for I/O and OSC block.
VSS1
1-6
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
Table 1-1. KS86C6308/P6308 Pin Descriptions (Continued)
Pin
Names
I/O
Pin
Description
Pin
Type
Share
Pins
I/O
These pins are an USB Downstream pins.
K
–
DP1, DM1
DP2, DM2
DP3, DM3
DP4, DM4
DP0/GPIO
DM0/GPIO
I/O
O
These pins are an USB Upstream pin, programmable
port for USB interface or General purpose I/O interface.
–
–
–
LEDON0
Root port LED enable. N-channel open-drain output.
= 0 Turn LED ON. HUB not Suspend
= 1 Turn LED OFF. Reset, Suspend, Transfer in
progress
G
LEDON1-4
O
Four downstream port LED enable. N-channel open-
drain output.
G
–
= 0 Turn LED ON. Port Enable and HUB not Suspend
= 1 Turn LED OFF. Reset, Suspend, Transfer in
progress
OCDET1-4
PWREN1-4
GANGED
I
O
I
Four downstream power sense
= 0 Over Current Detected
= 1 Power Okay
F
G
F
–
–
–
Power on/off control signals. PWREN1 - PWREN4 are
active low, N-CH open-drain outputs.
In GANGED mode, all output are swithed together.
Gang or Individual Power Control of downstream ports
= 0 Individual
= 1 Gang
1-7
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
PIN CIRCUIT DIAGRAMS
VDD
VDD
Output Data
Open Drain
Pull-up
Resistor
Output
DIsable
Noise
Filter
VSS
D0
Input Data
MUX D1
Figure 1-4. Pin Circuit Type A (RESET)
Figure 1-6. Pin Circuit Type C (Port 3)
VDD
VDD
Pull-up
Resistor
Pull-up
Resistor
Pull-up Enable
VDD
Pull-up Enable
Output Data
Output Disable
Open Data
Open Drain
Output
DIsable
VSS
D0
MUX D1
Input Data
VSS
D0
Input Data
MUX D1
Figure 1-5. Pin Circuit Type B (Port 0, 1, 2)
Figure 1-7. Pin Circuit Type D (Port 4)
1-8
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Figure 1-8. Pin Circuit Type F
3.0 V < V <3.6 V
Only on
Upstream Ports
15 KW ± 5 %
or
Equivalent
DP
DMX
X
R
R
R
XD
XDP
XDM
T DP
X
OEN
Speed (Only on Downstream Ports)
TXDM
15 KW ± 5 %
Only on
Downstream
Ports
Figure 1-9. Pin Circuit Type K
1-9
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
Output
Data
Figure 1-10. Pin Circuit Type G
1-10
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
APPLICATION CITCUIT
KS86C6308 (P6308)
DD
V
XI
12 MHz
XO
GANGED
LPF
Downstream
Ports
Upstream Port
V
DD
D-
DD
V
DD
D-
D+
V
DM1
DP1
DM0
DP0
D+
VSS
SS
V
SS
V
Keyboard
Matrix
V
DD
DM2
DP2
D-
D+
VSS
P2.0-P2.7
P0.0-P0.7
DD
V
DM3
DP3
D-
D+
SS
V
P1.0-P1.7
DD
V
DM4
DP4
D-
D+
SS
V
P3.2
P3.1
P3.0
PWREN1
PWREN2
PWREN3
PWREN4
LEDON0
LEDON1
LEDON2
LEDON3
LEDON4
Power Switch
EN
IN
OCDET1
OCDET2
OCDET3
OCDET4
OC
OUT
NOTES:
1. We recommand Power Switch, MIC2525 (by MICREL Semiconductor).
W
W
R2: 15 K
2. R1: 1.5 K
3. For proper operation of the PLL, an external RC filter consisting of series
RC network resistor and capacitor must be connected from the LPF pin to V
4. Port3 can use LED direct drive.
SS
.
5. Upstream D+, D- can use GPIO interface (see GPIOCONINT)
Figure 1-11. Bus-Powered, Gang Port (64-SDIP, 64-QFP)
1-11
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
KS86C6308 (P6308)
XI
12 MHz
XO
GANGED
LPF
Downstream
Ports
Upstream Port
VSS
V
DD
V
DD
V
DD
D-
DM1
DP1
D-
DM0
DP0
D+
V
SS
D+
V
SS
VSS
Keyboard
Matrix
V
DD
DM2
DP2
D-
D+
V
SS
P2.0-P2.7
P0.0-P0.7
V
DD
DM3
DP3
D-
D+
V
SS
P1.0-P1.7
V
DD
D-
D+
DM4
DP4
VSS
P3.2
P3.1
P3.0
IN
OC OUT
EN
PWREN1
OCDET1
LEDON0
LEDON1
LEDON2
LEDON3
LEDON4
EN
IN
OUT
IN
PWREN2
OCDET2
OC
EN
PWREN3
OCDET3
OUT
IN
OC
EN
PWREN4
OCDET4
OC OUT
Power Switching
NOTES:
1. We recommand Power Switch, MIC2525 (by MICREL Semiconductor).
2. For proper operation of the PLL, an external RC filter consisting of series
RC network resistor and capacitor must be connected from the LPF pin to V SS
.
3. Port3 can use LED direct drive.
4. Upstream D+, D- can use GPIO interface (see GPIOCONINT)
Figure 1-12. Bus-Powered, Individual Port (64-SDIP, 64-QFP)
1-12
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
12 ELECTRICAL DATA
OVERVIEW
In this section, the following KS86C6308/P6308 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— Input/Output capacitance
— A.C. electrical characteristics
— Input timing for external interrupt (Ports 0, 2 and 4) DP0/GPIO, DM0/GPIO : GPIO Mode Only
— Input timing for RESET
— Oscillator characteristics
— Oscillation stabilization time
— Clock timing measurement points at XIN
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a reset
— Stop mode release timing when initiated by an external interrupt
— Characteristic curves
12-1
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Unit
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
V
VIN
VO
IOH
All input ports
V
V
– 0.3 to VDD + 0.3
– 18
Output Voltage
Output Current High
All output ports
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 60
+ 30
IOL
Output Current Low
mA
Total pin current for ports 0, 1, 2, 4
+ 100
+ 100
Total pin current for port 3
–
TA
Operating
Temperature
– 40 to + 85
°
°
C
TSTG
Storage
–
– 65 to + 150
C
Temperature
12-2
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
Table 12-2. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
fOSC = 12 MHz
Min
4.0
Typ
Max
5.5
Unit
VDD
Operating Voltage
–
V
VIH1
VIH2
VIL1
VIL2
VOH
All input except VIH2
0.8 VDD
VDD
Input High Voltage
Input Low Voltage
–
–
–
V
V
V
XIN
VDD – 0.5
VDD
0.2 VDD
0.4
All input pins except VIL2
XIN
–
IOH = – 200 µA; All output
VDD – 1.0
Output High
Voltage
–
ports except ports 0, 1, 2, DP’s,
DM’s
VOL
IOL = 1 mA
Output Low
Voltage
–
–
–
–
0.4
3
V
All output ports except DP’s,
DM’s
(4)
VIN = VDD
Input High
µA
ILIH1
Leakage Current
All inputs excepts ILIH2, DP’s,
DM’s
(4)
VIN = VDD
XIN, XOUT, RESET
–
–
–
–
20
µA
µA
ILIH2
(4)
VIN = 0 V
Input Low
– 3
ILIL1
Leakage Current
All inputs excepts ILIL2, DP’s,
DM’s
(4)
VIN = 0 V
–
–
– 20
µA
ILIL2
XIN, XOUT, RESET
12-3
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-2. D.C. Electrical Characteristics (continued)
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.5 V)
°
°
Parameter
Output High
Symbol
Conditions
VOUT = VDD
Min
Typ
Max
Unit
(1)
–
–
3
µA
ILOH
Leakage Current
All I/O pins and output pins
except DP’s and DM’s
(1)
VOUT = 0 V
Output Low
–
–
– 3
µA
ILOL
Leakage Current
All I/O pins and output pins
except DP’s and DM’s
RL
VIN = 0 V
Pull-up Resistors
Supply Current
25
–
50
100
kW
Ports 0, 1, 2, 4, Reset
IDD1
IDD2
IDD3
Normal operation mode :
12 MHz Crystal Oscillator
30
15
mA
Idle mode;
12 MHz Crystal Oscillator
Stop mode: Oscillator stop
500
µA
NOTES:
1. Except X and X
.
IN
OUT
2. Supply current does not include through internal pull-up resistors or external output current loads.
3. Figure 11-3 Transition Rise Timer (tR), Fall Timer (tF) parameter is guaranteed, but not tested.
3. When USB Mode Only in 4.20 V to 5.25 V, DP’s and DP’s satisfy the USB Specification version 1.0.
Table 12-3. Input/Output Capacitance
°
°
(TA = – 40 C to + 85 C, VDD = 0 V)
Parameter
Input
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; Unmeasured pins
are connected to VSS
–
–
10
pF
Capacitance
COUT
CIO
Output
Capacitance
I/O Capacitance
Table 12-4. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, V
= 4.0 V to 5.5 V)
DD
Parameter
Symbol
Conditions
P0, P2 and P4
Min
Typ
Max
Unit
tINTH, tINTL
Interrupt Input
–
200
–
ns
High, Low Width
tRSL
RESET Input Low
Width
–
1000
–
RESET
12-4
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 12-1. Input Timing Measurement Points (Ports 0, 2, and 4)
RSL
t
RESET
0.5 VDD
Figure 12-2. Input Timing for RESET
t
R
tF
0.5V
DD
DP
90%
90%
10%
10%
DM
Figure 12-3. USB Data Signal Timing
12-5
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-5. DPx, DMx Driver Characteristics, Full Speed Operation
Symbol
Parameter
Condition
Min
Max
Unit
tR
CL = 50pF
Rise Time
4
20
ns
tF
CL = 50pF
–
Fall Time
4
20
11
ns
%
tRFM
tR/tF Matching
90
Table 12-6. DPx, DMx Driver Characteristics, Low Speed Operation
Symbol
Parameter
Condition
Min
Max
Unit
tR
CL = 200-600pF
Rise Time
75
300
ns
tF
CL = 200-600pF
–
Fall Time
75
80
300
125
ns
%
tRFM
tR/tF Matching
12-6
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
RS
T D+
X
CL
RS
TXD-
CL
CL = 50 pF
Figure 12-4. Full-Speed Load
RS
T D+
X
3.6 V
CL
RS
TXD-
C
L
CL = 200 pF to 600 pF
Figure 12-5. Low-Speed Load
12-7
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-7. Oscillator Characteristics
°
°
(TA = – 40 C + 85 C)
Oscillator
Circuit
Condition
Min
Typ
Max
Unit
VDD = 4.0V to 5.5V
Main crystal Main
–
12
–
MHz
X
ceramic (fOSC
)
IN
C1
X
OUT
C2
VDD = 4.0V to 5.5V
External clock
–
12
–
X
X
IN
OUT
Table 12-8. Oscillation Stabilization Time
(TA = – 40 C + 85 C, VDD = 4.0 V to 5.5 V)
°
°
Oscillator
Crystal
Symbol
Condition
Min
Typ
Max
Unit
VDD = 4.0V to 5.5V
–
–
–
20
ms
Ceramic
External
–
–
–
–
–
10
XIN input high & low level
width
25
500
ns
NOTE: The oscillator stabilization wait time, t
WAIT
, is determined by the setting in the basic timer control register, BTCON.
Table 12-9. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
VDDDR
Conditions
Stop mode
Min
Typ
Max
Unit
Data Retention
Supply Voltage
2.0
–
6
V
IDDDR
Stop mode; VDDDR = 2.0 V
Data Retention
Supply Current
–
–
500
uA
12-8
KS86C6308/P6408 (Preliminary Spec)
MECHANICAL DATA
13 MECHANICAL DATA
OVERVIEW
The KS86C6308/P6308 is available in a 64-pin SDIP package (Samsung: 64-SDIP-750) and a 64-pin QFP
package (64-QFP-1420F). Package dimensions are shown in Figures 13-1 and 13-2.
#64
#33
0-15
64-SDIP-750
#1
#32
58.20 MAX
± 0.20
57.80
0.45 ± 0.10
± 0.10
1.00
1.778
(1.34)
NOTE : Dimensions are in millimeters.
Figure 13-1. 64-Pin SDIP Package Mechanical Data (64-SDIP-750 )
13-1
MECHANICAL DATA
KS86C6308/P6408 (Preliminary Spec)
± 0.30
23.90
0-8
20.00 ± 0.20
+ 0.10
- 0.05
0.15
0.10 MAX
64-QFP-1420F
#64
+ 0.10
- 0.05
#1
0.40
0.05 MIN
2.65 ± 0.10
3.00 MAX
1.00
0.15 MAX
(1.00)
± 0.20
0.80
NOTE
: Dimensions are in millimeters.
Figure 13-2. 64-Pin QFP Package Mechanical Data (64-QFP-1420F )
13-2
KS86C6308/P6308 (Preliminary Spec)
KS86P6308 OTP
14 KS86P6308 OTP
OVERVIEW
The KS86P6308 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS86C6308 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by
serial data format.
The KS86P6308 is fully compatible with the KS86C6308, both in function and in pin configuration. Because of its
simple programming requirements, the KS86P6308 is ideal for use as an evaluation chip for the KS86C6308.
14-1
KS86P6308 OTP
KS86C6308/P6308 (Preliminary Spec)
LEDON3
LEDPN2
LEDON1
LEDON0
OCDET4
PWREN4
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LEDON4
P1.4
P1.5
P1.6
P1.7
P4.0/INT1
P4.1/INT1
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
SDAT /P2.6/INT0
SCLK /P2.7/INT0
VDD/VDD
VSS/VSS
XO/XO
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
XI/XI
TEST/TEST
LPF
3
PWREN
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
GANGED
OCDET2
PWREN2
ECDET1
PWREN1
VSS/VSSA
RESET/RESET
TMODE
DP0/GPIO
DM0/GPIO
DP1
DM1
DP2
DM2
DP3
3.3VOUT
DM4
DP4
DM3
Figure 14-1. Pin Assignment Diagram (64-Pin SDIP Package)
14-2
KS86C6308/P6308 (Preliminary Spec)
KS86P6308 OTP
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
1
2
3
4
5
6
7
8
51
50
43
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
PWREN3
P3.3/TACLK/CLO
P2.5/INT0
SDAT /P2.6/INT0
SCLK /P2.7/INT0
V
/V
DD DD
9
V
/V
SS SS
10
11
12
13
14
15
16
17
18
19
KS86P6308
XO/XO
XI/XI
TEST/TEST
LPF
VSS/VSSA
RESET/RESET
TMODE
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
GANGED
DP0/GPIO
DM0/GPIO
Figure 14-2. Pin Assignment Diagram (64-Pin QFP Package)
14-3
KS86P6308 OTP
KS86C6308/P6308 (Preliminary Spec)
Table 14-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
Pin Name
P2.6
During Programming
I/O
Pin Name
Pin No.
Function
9 (3)
SDAT
I/O
Serial Data Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned
10 (4)
15 (9)
P2.7
SCLK
TEST
I/O
I
Serial Clock Pin (Input Only Pin)
TEST
Chip Initialization and EPROM Cell Writing
Power Supply Pin (Indicates OTP Mode
Entering) When writing 12.5 V is applied and
when reading.
18 (12)
RESET
RESET
I
0 V: OTP write and test mode
5 V: Operating mode
11(5)/12(6)
VDD / VSS
VDD / VSS
–
Logic Power Supply Pin.
NOTE: ( ) means 64 QFP package.
Table 14-2. Comparison of KS86P6308 and KS86C308 Features
Characteristic KS86P6308 KS86C6308
Program Memory 8-Kbyte EPROM
Operating Voltage (VDD
8-Kbyte mask ROM
4.0 V to 5.25 V
)
4.0 V to 5.25 V
= 5 V, VPP (RESET) = 12.5 V
V
OTP Programming Mode
DD
Pin Configuration
64 SDIP/64 QFP
64 SDIP/64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (RESET) pin of the KS86P6308, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.
Table 14-3. Operating Mode Selection Criteria
V
DD
REG/
MEM
R/W
MODE
VPP
(RESET)
ADDRESS
(A15-A0)
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
14-4
KS86C6308/P6308 (Preliminary Spec)
KS86P6308 OTP
START
Address= First Location
V
DD
=5V, V =12.5V
PP
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
DD
= V = 5 V
PP
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 14-3. OTP Programming Algorithm
14-5
KS86P6308 OTP
KS86C6308/P6308 (Preliminary Spec)
Table 14-4. D.C. Electrical Characteristics
_
_
(TA = – 40 C to + 85 C, VDD = 5.25 V)
Parameter
Symbol
Conditions
Normal mode;
Min
Typ
Max
Unit
IDD1
Supply Current
–
–
30
mA
(note)
12 MHz crystal oscillator
IDD2
IDD3
Idle mode;
12 MHz CPU clock
–
–
15
Stop mode
500
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
14-6
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