S3C9234XX-QT [SAMSUNG]
Microcontroller, 8-Bit, MROM, SAM88RCRI CPU, 8MHz, CMOS, PQFP64;
| 型号： | S3C9234XX-QT |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, MROM, SAM88RCRI CPU, 8MHz, CMOS, PQFP64 微控制器 |
| 文件： | 总230页 (文件大小：770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
21-S3-C9234/P9234-022004
USER'S MANUAL
S3C9234/P9234
8-Bit CMOS
Microcontroller
Revision 1.0
S3C9234/P9234
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.0
Important Notice
The information in this publication has been carefully
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
personal injury or death may occur.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all
claims, costs, damages, expenses, and reasonable
attorney fees arising out of, either directly or
indirectly, any claim of personal injury or death that
may be associated with such unintended or
unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or
manufacture of said product.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.
S3C9234/P9234 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.0
Publication Number: 21-S3-C9234/P9234-022004
© 2004 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BVQI Certificate No 9330) All semiconductor products are designed
and manufactured in accordance with the highest quality standards and
objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Kiheung-Eup
Yongin-City, Kyunggi-Do, Korea
C.P.O. Box #37, Suwon 449-900
TEL: (82)-(331)-209-1907
FAX: (82)-(331)-209-1889
Home-Page URL: Http://www.samsungsemi.com
Printed in the Republic of Korea
Preface
The S3C9234/P9234 Microcontrollers User's Manual is designed for application designers and programmers who
are using the S3C9234/P9234 microcontrollers for application development. It is organized in two main parts:
Part I Programming Model
Part II
Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming
model, instruction set, and interrupt structure. It has six chapters:
Chapter 1
Chapter 2
Chapter 3
Product Overview
Address Spaces
Addressing Modes
Chapter 4
Chapter 5
Chapter 6
Control Registers
Interrupt Structure
SAM88RCRI Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to the 100% with general product descriptions, as well
as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," explains the 100% program and data memory, internal register file, and mapped
control register, and explains how to address them. Chapter 2 also describes working register addressing, as well
as system stack and user-defined stack operations.
Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
CPU.
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in standard format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.
Chapter 5, "Interrupt Structure," describes the 100% interrupt structure in detail and further prepares you for
additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, "SAM88RCRI Instruction Set," describes the features and conventions of the instruction set used for
all S3P9-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed
descriptions of each instruction are presented in a standard format. Each instruction description includes one or
more practical examples of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the SAM8 product family and are reading this manual for the first time, we
recommend that you first read chapters 1–3 carefully. Then, briefly look over the detailed information in chapters
4, 5, and 6. Later, you can reference the information in Part I as necessary.
Part II "hardware Descriptions," has detailed information about specific hardware components of the
S3C9234/P9234 microcontrollers. Also included in Part II are electrical, mechanical, OTP, and development tools
data. It has 12 chapters:
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Clock Circuits
RESET and Power-Down
I/O Ports
Basic Timer
Timer 1
Chapter 13
Chapter 14
Chapter 15
Chapter 16
Chapter 17
Chapter 18
LCD Controller/Driver
Serial I/O Interface
Electrical Data
Mechanical Data
S3P9234 OTP
Watch Timer
Development Tools
Two order forms are included at the back of this manual to facilitate customer order for S3C9234/P9234
microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these
forms, fill them out, and then forward them to your local Samsung Sales Representative.
S3C9234/P9234 MICROCONTROLLERS
iii
Table of Contents
Part I — Programming Model
Chapter 1
Product Overview
SAM88RCRI Product Family......................................................................................................................... 1-1
S3C9234/P9234 Microcontroller ................................................................................................................... 1-1
OTP ............................................................................................................................................................... 1-1
Features ........................................................................................................................................................ 1-2
Block Diagram............................................................................................................................................... 1-3
Pin Assignments............................................................................................................................................ 1-4
Pin Descriptions ............................................................................................................................................ 1-5
Pin Circuit Diagrams...................................................................................................................................... 1-7
Chapter 2
Address Spaces
Overview........................................................................................................................................................ 2-1
Program Memory (ROM)............................................................................................................................... 2-2
Register Architecture..................................................................................................................................... 2-3
Common Working Register Area (C0H–CFH) .............................................................................................. 2-4
System Stack................................................................................................................................................. 2-5
Stack Operations .................................................................................................................................. 2-5
Stack Pointer (SP) ................................................................................................................................ 2-5
Chapter 3
Addressing Modes
Overview........................................................................................................................................................ 3-1
Register Addressing Mode (R) ............................................................................................................. 3-2
Indirect Register Addressing Mode (IR) ............................................................................................... 3-3
Indexed Addressing Mode (X).............................................................................................................. 3-7
Direct Address Mode (DA).................................................................................................................... 3-10
Relative Address Mode (RA)................................................................................................................ 3-12
Immediate Mode (IM)............................................................................................................................ 3-12
S3C9234/P9234 MICROCONTROLLERS
v
Table of Contents (Continued)
Chapter 4
Control Registers
Overview........................................................................................................................................................4-1
Chapter 5
Interrupt Structure
Overview........................................................................................................................................................5-1
Interrupt Processing Control Points......................................................................................................5-1
Enable/Disable Interrupt Instructions (EI, DI) .......................................................................................5-1
Interrupt Pending Function Types.........................................................................................................5-2
Interrupt Priority.....................................................................................................................................5-2
Interrupt Source Service Sequence......................................................................................................5-3
Interrupt Service Routines ....................................................................................................................5-3
Generating Interrupt Vector Addresses ................................................................................................5-3
S3C9234/P9234 Interrupt Structure .....................................................................................................5-4
Chapter 6
SAM88RCRI Instruction Set
Overview........................................................................................................................................................6-1
Register Addressing..............................................................................................................................6-1
Addressing Modes ................................................................................................................................6-1
Flags Register (FLAGS)........................................................................................................................6-4
Flag Descriptions ..................................................................................................................................6-4
Instruction Set Notation.........................................................................................................................6-5
Condition Codes ...................................................................................................................................6-9
Instruction Descriptions.........................................................................................................................6-10
vi
S3C9234/P9234 MICROCONTROLLERS
Table of Contents (Continued)
Part II — Hardware Descriptions
Chapter 7
Clock Circuit
Overview........................................................................................................................................................ 7-1
System Clock Circuit ............................................................................................................................ 7-1
CPU Clock Notation.............................................................................................................................. 7-1
Main Oscillator Circuits......................................................................................................................... 7-2
Sub Oscillator Circuits .......................................................................................................................... 7-2
Clock Status During Power-Down Modes ............................................................................................ 7-3
System Clock Control Register (CLKCON).......................................................................................... 7-4
Clock Output Control Register (CLOCON)........................................................................................... 7-5
Oscillator Control Register (OSCCON) ................................................................................................ 7-6
Switching the CPU Clock...................................................................................................................... 7-7
Stop Control Register (STPCON)......................................................................................................... 7-8
Chapter 8
RESET and Power-Down
System Reset................................................................................................................................................ 8-1
Overview............................................................................................................................................... 8-1
Power-Down Modes...................................................................................................................................... 8-2
Stop Mode ............................................................................................................................................ 8-2
Idle Mode.............................................................................................................................................. 8-3
Hardware Reset Values........................................................................................................................ 8-4
Chapter 9
I/O Ports
Overview........................................................................................................................................................ 9-1
Port Data Registers .............................................................................................................................. 9-2
Port 0 .................................................................................................................................................... 9-3
Port 1 .................................................................................................................................................... 9-4
Port 2 .................................................................................................................................................... 9-8
Port 3 .................................................................................................................................................... 9-12
Port 4 .................................................................................................................................................... 9-14
Port 5 .................................................................................................................................................... 9-15
Port 6 .................................................................................................................................................... 9-16
Chapter 10
Basic Timer
Overview........................................................................................................................................................ 10-1
Basic Timer Control Register (BTCON) ............................................................................................... 10-2
Basic Timer Function Description......................................................................................................... 10-3
S3C9234/P9234 MICROCONTROLLERS
vii
Table of Contents(Continued)
Chapter 11
Timer 1
One 16-Bit Timer Mode (Timer 1)..................................................................................................................11-1
Overview ...............................................................................................................................................11-1
Function Description .............................................................................................................................11-1
Two 8-Bit Timers Mode (Timer A and B).......................................................................................................11-4
Overview ...............................................................................................................................................11-4
Function Description .............................................................................................................................11-7
Chapter 12
Watch Timer
Overview........................................................................................................................................................12-1
Watch Timer Control Register (WTCON) .............................................................................................12-2
Watch Timer Circuit Diagram ........................................................................................................................12-3
Chapter 13
LCD Controller/Driver
Overview........................................................................................................................................................13-1
LCD Circuit Diagram.............................................................................................................................13-2
LCD Ram Address Area .......................................................................................................................13-3
LCD Control Register (LCON) ..............................................................................................................13-4
LCD Voltage Dividing Resistor .............................................................................................................13-5
Common (COM) Signals.......................................................................................................................13-6
Segment (SEG) Signals........................................................................................................................13-6
Chapter 14
Serial I/O Interface
Overview........................................................................................................................................................14-1
Programming Procedure.......................................................................................................................14-1
SIO Control Registers (SIOCON) .........................................................................................................14-2
SIO Pre-Scaler Register (SIOPS).........................................................................................................14-3
Sio Block Diagram .........................................................................................................................................14-3
Serial I/O Timing Diagram (SIO)...........................................................................................................14-4
viii
S3C9234/P9234 MICROCONTROLLERS
Table of Contents (Concluded)
Chapter 15
Electrical Data
Overview........................................................................................................................................................ 15-1
Chapter 16
Mechanical Data
Overview........................................................................................................................................................ 16-1
Chapter 17
S3P9234 OTP
Overview........................................................................................................................................................ 17-1
Operating Mode Characteristics........................................................................................................... 17-3
Chapter 18
Development Tools
Overview........................................................................................................................................................ 18-1
Shine..................................................................................................................................................... 18-1
SAMA Assembler.................................................................................................................................. 18-1
SASM86................................................................................................................................................ 18-1
HEX2ROM............................................................................................................................................ 18-1
Target Boards....................................................................................................................................... 18-1
TB9234 Target Board........................................................................................................................... 18-3
Idle LED................................................................................................................................................ 18-5
Stop LED .............................................................................................................................................. 18-5
S3C9234/P9234 MICROCONTROLLERS
ix
List of Figures
Figure
Title
Page
Number
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
Block Diagram......................................................................................................................... 1-3
S3C9234 64-QFP Pin Assignments........................................................................................ 1-4
Pin Circuit Type A ................................................................................................................... 1-7
Pin Circuit Type B ................................................................................................................... 1-7
Pin Circuit Type E-4 (P1, P2).................................................................................................. 1-7
Pin Circuit Type H-8 (P3) ........................................................................................................ 1-8
Pin Circuit Type H-9 (P0, P4, P5, P6)..................................................................................... 1-8
Pin Circuit Type H-4................................................................................................................ 1-9
2-1
2-2
2-3
2-4
S3C9234/P9234 Program Memory Address Space............................................................... 2-2
Internal Register File Organization ......................................................................................... 2-3
16-Bit Register Pairs ............................................................................................................... 2-4
Stack Operations..................................................................................................................... 2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Register Addressing................................................................................................................ 3-2
Working Register Addressing ................................................................................................. 3-2
Indirect Register Addressing to Register File ......................................................................... 3-3
Indirect Register Addressing to Program Memory.................................................................. 3-4
Indirect Working Register Addressing to Register File........................................................... 3-5
Indirect Working Register Addressing to Program or Data Memory ...................................... 3-6
Indexed Addressing to Register File....................................................................................... 3-7
Indexed Addressing to Program or Data Memory with Short Offset....................................... 3-8
Indexed Addressing to Program or Data Memory with Long Offset ....................................... 3-9
Direct Addressing for Load Instructions.................................................................................. 3-10
Direct Addressing for Call and Jump Instructions................................................................... 3-11
Relative Addressing ................................................................................................................ 3-12
Immediate Addressing ............................................................................................................ 3-12
3-9
3-10
3-11
3-12
3-13
4-1
Register Description Format ................................................................................................... 4-4
S3C9234/P9234 MICROCONTROLLERS
xi
List of Figures (Continued)
Figure
Title
Page
Number
Number
5-1
5-2
5-3
S3C9-Series Interrupt Type.....................................................................................................5-1
Interrupt Function Diagram......................................................................................................5-2
S3C9234/P9234 Interrupt Structure........................................................................................5-5
6-1
System Flags Register (FLAGS).............................................................................................6-4
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
Crystal/Ceramic Oscillator (fx).................................................................................................7-2
External Oscillator (fx) .............................................................................................................7-2
RC Oscillator (fx) .....................................................................................................................7-2
Crystal/Ceramic Oscillator (fxt)................................................................................................7-2
External Oscillator (fxt) ............................................................................................................7-2
System Clock Circuit Diagram.................................................................................................7-3
System Clock Control Register (CLKCON).............................................................................7-4
Clock Output Control Register (CLOCON)..............................................................................7-5
Clock Output Block Diagram ...................................................................................................7-5
Oscillator Control Register (OSCCON)...................................................................................7-6
STOP Control Register (STPCON) .........................................................................................7-8
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
S3C9234/P9234 I/O Port Data Register Format.....................................................................9-2
Port 0 Control Register (P0CON)............................................................................................9-3
Port 1 High-Byte Control Register (P1CONH) ........................................................................9-5
Port 1 Low-Byte Control Register (P1CONL)..........................................................................9-5
Port 1 Pull-up Control Register (P1PUR)................................................................................9-6
Port 1 Interrupt Control Register (P1INT)................................................................................9-6
Port 1 Interrupt Pending Bits (INTPND.2-.0)...........................................................................9-7
Port 2 High-byte Control Register (P2CONH).........................................................................9-9
Port 2 Low-byte Control Register (P2CONL) ..........................................................................9-9
Port 2 Pull-up Control Register (P2PUR)................................................................................9-10
Port 2 Interrupt Control Register (P2INT)................................................................................9-11
Port 2 Interrupt Pending Bits (INTPND.7-.4)...........................................................................9-11
Port 3 High Byte Control Register (P3CONH).........................................................................9-12
Port 3 Low Byte Control Register (P3CONL)..........................................................................9-13
Port 3 Pull-up Control Register (P3PUR)................................................................................9-13
Port 4 High-Byte Control Register (P4CONH) ........................................................................9-14
Port 4 Low-Byte Control Register (P4CONL)..........................................................................9-14
Port 5 High-Byte Control Register (P5CONH) ........................................................................9-15
Port 5 Low-Byte Control Register (P5CONL)..........................................................................9-15
Port 6 Control Register (P6CON)............................................................................................9-16
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
xii
S3C9234/P9234 MICROCONTROLLERS
List of Figures (Continued)
Figure
Title
Page
Number
Number
10-1
10-2
Basic Timer Control Register (BTCON).................................................................................. 10-2
Basic Timer Block Diagram..................................................................................................... 10-4
11-1
11-2
11-3
11-4
11-5
11-6
Timer 1 Control Register (TACON)......................................................................................... 11-2
Timer 1 Block Diagram (One 16-bit Mode)............................................................................. 11-3
Timer A Control Register (TACON) ........................................................................................ 11-5
Timer B Control Register (TBCON) ........................................................................................ 11-6
Timer A Block Diagram(Two 8-bit Timers Mode).................................................................... 11-8
Timer B Block Diagram (Two 8-bit Timers Mode)................................................................... 11-9
12-1
12-2
Watch Timer Control Register (WTCON) ............................................................................... 12-2
Watch Timer Circuit Diagram.................................................................................................. 12-3
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
LCD Function Diagram............................................................................................................ 13-1
LCD Circuit Diagram ............................................................................................................... 13-2
LCD Display Data RAM Organization..................................................................................... 13-3
LCD Control Register (LCON) ................................................................................................ 13-4
Internal Voltage Dividing Resistor Connection ....................................................................... 13-5
Select/No-Select Signals in Static Display Mode.................................................................... 13-6
Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode.................................................. 13-7
Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode.................................................. 13-7
LCD Signal and Wave Forms Example in 1/2 Duty, 1/2 Bias Display Mode.......................... 13-8
LCD Signals and Wave Forms Example in 1/3 Duty, 1/3 Bias Display Mode........................ 13-9
LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode........................ 13-10
14-1
14-2
14-3
14-4
14-5
Serial I/O Module Control Register (SIOCON) ....................................................................... 14-2
SIO Prescaler Register (SIOPS)............................................................................................. 14-3
SIO Functional Block Diagram................................................................................................ 14-3
Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)........................... 14-4
Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)............................ 14-4
S3C9234/P9234 MICROCONTROLLERS
xiii
List of Figures (Concluded)
Figure
Title
Page
Number
Number
15-1
15-2
15-3
15-4
15-5
15-6
Stop Mode Release Timing When Initiated by an External Interrupt ......................................15-5
Stop Mode Release Timing When Initiated by a RESET........................................................15-6
Input Timing for External Interrupts.........................................................................................15-7
Input Timing for RESET...........................................................................................................15-8
Serial Data Transfer Timing ....................................................................................................15-8
Clock Timing Measurement at XIN ..........................................................................................15-10
15-7
15-8
Clock Timing Measurement at XTIN ........................................................................................15-11
Operating Voltage Range........................................................................................................15-12
16-1
64-Pin QFP Package Dimensions (64-QFP-1420F)...............................................................16-1
17-1
17-2
S3P9234 Pin Assignments (64-QFP-1420F) ..........................................................................17-2
Standard Operating Voltage Range........................................................................................17-5
18-1
18-2
18-3
18-4
SMDS Product Configuration (SMDS2+) ................................................................................18-2
TB9234 Target Board Configuration .......................................................................................18-3
Connectors (J101, J102) for TB9234......................................................................................18-6
S3C9234 Probe Adapter for 64-QFP Package .......................................................................18-6
xiv
S3C9234/P9234 MICROCONTROLLERS
List of Tables
Table
Title
Page
Number
Number
1-1
4-1
Pin Descriptions ...................................................................................................................... 1-5
System and Peripheral Control Registers............................................................................... 4-2
6-1
6-2
6-3
6-4
6-5
6-6
Instruction Group Summary.................................................................................................... 6-2
Flag Notation Conventions...................................................................................................... 6-5
Instruction Set Symbols .......................................................................................................... 6-5
Instruction Notation Conventions............................................................................................ 6-6
Opcode Quick Reference........................................................................................................ 6-7
Condition Codes...................................................................................................................... 6-9
8-1
Register Values after RESET ................................................................................................. 8-4
9-1
9-2
S3C9234/P9234 Port Configuration Overview ....................................................................... 9-1
Port Data Register Summary.................................................................................................. 9-2
13-1
LCD Clock Signal Frame Frequency ...................................................................................... 13-3
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
Absolute Maximum Ratings .................................................................................................... 15-2
D.C. Electrical Characteristics ................................................................................................ 15-2
Data Retention Supply Voltage in Stop Mode ........................................................................ 15-5
Input/Output Capacitance ....................................................................................................... 15-6
A.C. Electrical Characteristics................................................................................................. 15-7
Main Oscillation Characteristics.............................................................................................. 15-9
Sub Oscillation Characteristics ............................................................................................... 15-9
Main Oscillation Stabilization Time ......................................................................................... 15-10
Sub Oscillation Stabilization Time........................................................................................... 15-11
17-1
17-2
17-3
17-4
Descriptions of Pins Used to Read/Write the EPROM ........................................................... 17-3
Comparison of S3P9234 and S3C9234 Features .................................................................. 17-3
Operating Mode Selection Criteria.......................................................................................... 17-3
D.C. Electrical Characteristics ................................................................................................ 17-4
18-1
18-2
18-3
Power Selection Settings for TB9234 ..................................................................................... 18-4
The SMDS2+ Tool Selection Setting ...................................................................................... 18-5
Using Single Header Pins as the Input Path for External Trigger Sources ............................ 18-5
S3C9234/P9234 MICROCONTROLLERS
xv
List of Programming Tips
Description
Page
Number
Chapter 2: Address Spaces
Addressing the Common Working Register Area ......................................................................................... 2-4
Standard Stack Operations Using PUSH and POP...................................................................................... 2-6
Chapter 5: Interrupt Structure
How to clear an interrupt pending bit ............................................................................................................ 5-6
Chapter 7: Clock Circuits
Switching the CPU clock ............................................................................................................................... 7-7
How to Use Stop Instruction.......................................................................................................................... 7-8
S3C9234/P9234 MICROCONTROLLERS
xvii
List of Register Descriptions
Register
Identifier
Full Register Name
Page
Number
BTCON
CLKCON
CLOCON
FLAGS
Basic Timer Control Register..................................................................................... 4-5
System Clock Control Register.................................................................................. 4-6
Clock Output Control Register ................................................................................... 4-7
System Flags Register............................................................................................... 4-8
Interrupt Pending Register......................................................................................... 4-9
LCD Control Register................................................................................................. 4-10
Oscillator Control Register......................................................................................... 4-11
Port 0 Control Register .............................................................................................. 4-12
Port 1 Control Register High Byte.............................................................................. 4-13
Port 1 Control Register Low Byte............................................................................... 4-14
Port 1 Interrupt Enable Register ................................................................................ 4-15
Port 1 Pull-up Resistors Enable Register .................................................................. 4-16
Port 2 Control Register High Byte.............................................................................. 4-17
Port 2 Control Register Low Byte............................................................................... 4-18
Port 2 Interrupt Enable Register ................................................................................ 4-19
Port 2 Pull-up Resistors Enable Register .................................................................. 4-20
Port 3 Control Register High Byte.............................................................................. 4-21
Port 3 Control Register Low Byte............................................................................... 4-22
Port 3 Pull-up Resistors Enable Register .................................................................. 4-23
Port 4 Control Register High Byte.............................................................................. 4-24
Port 4 Control Register Low Byte............................................................................... 4-25
Port 5 Control Register High Byte.............................................................................. 4-26
Port 5 Control Register Low Byte............................................................................... 4-27
Port 6 Control Register .............................................................................................. 4-28
SIO Control Register.................................................................................................. 4-29
Stop Control Register................................................................................................. 4-30
System Mode Register............................................................................................... 4-31
Timer 1/A Control Register ........................................................................................ 4-32
Timer B Control Register ........................................................................................... 4-33
Watch Timer Control Register.................................................................................... 4-34
INTPND
LCON
OSCCON
P0CON
P1CONH
P1CONL
P1INT
P1PUR
P2CONH
P2CONL
P2INT
P2PUR
P3CONH
P3CONL
P3PUR
P4CONH
P4CONL
P5CONH
P5CONL
P6CON
SIOCON
STPCON
SYM
TACON
TBCON
WTCON
S3C9234/P9234 MICROCONTROLLERS
xix
List of Instruction Descriptions
Instruction
Mnemonic
Full Instruction Name
Page
Number
ADC
ADD
AND
CALL
CCF
CLR
COM
CP
Add With Carry........................................................................................................... 6-11
Add............................................................................................................................. 6-12
Logical AND ............................................................................................................... 6-13
Call Procedure ........................................................................................................... 6-14
Complement Carry Flag............................................................................................. 6-15
Clear........................................................................................................................... 6-16
Complement............................................................................................................... 6-17
Compare .................................................................................................................... 6-18
Decrement.................................................................................................................. 6-19
Disable Interrupts....................................................................................................... 6-20
Enable Interrupts........................................................................................................ 6-21
Idle Operation............................................................................................................. 6-22
Increment ................................................................................................................... 6-23
Interrupt Return.......................................................................................................... 6-24
Jump........................................................................................................................... 6-25
Jump Relative ............................................................................................................ 6-26
Load ........................................................................................................................... 6-27
Load Memory ............................................................................................................. 6-29
Load Memory and Decrement ................................................................................... 6-31
Load Memory and Increment..................................................................................... 6-32
No Operation.............................................................................................................. 6-33
Logical OR ................................................................................................................. 6-34
Pop From Stack ......................................................................................................... 6-35
Push To Stack............................................................................................................ 6-36
Reset Carry Flag........................................................................................................ 6-37
Return......................................................................................................................... 6-38
Rotate Left.................................................................................................................. 6-39
Rotate Left Through Carry ......................................................................................... 6-40
Rotate Right ............................................................................................................... 6-41
Rotate Right Through Carry....................................................................................... 6-42
Subtract With Carry.................................................................................................... 6-43
Set Carry Flag............................................................................................................ 6-44
Shift Right Arithmetic.................................................................................................. 6-45
Stop Operation........................................................................................................... 6-46
Subtract...................................................................................................................... 6-47
Test Complement Under Mask .................................................................................. 6-48
Test Under Mask........................................................................................................ 6-49
Logical Exclusive OR ................................................................................................. 6-50
DEC
DI
EI
IDLE
INC
IRET
JP
JR
LD
LDC/LDE
LDCD/LDED
LDCI/LDEI
NOP
OR
POP
PUSH
RCF
RET
RL
RLC
RR
RRC
SBC
SCF
SRA
STOP
SUB
TCM
TM
XOR
S3C9234/P9234 MICROCONTROLLERS
xxi
S3C9234/P9234
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range
of integrated peripherals, and supports OTP device.
A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9234/P9234 MICROCONTROLLER
The S3C9234 can be used for dedicated control functions in a variety of applications, and is especially designed for
application with FRS or etc.
The S3C9234/P9234 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9234/P9234 has 4K-byte of program
ROM, and 208-byte of RAM (including 16-byte of working register and 16-byte LCD display RAM).
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
—
—
—
—
—
—
7 configurable I/O ports including ports shared with segment/common drive outputs
7-bit programmable pins for external interrupts
One 8-bit basic timer for oscillation stabilization and watch-dog functions
Two 8-bit timer/counters with selectable operating modes
Watch timer for real time
8-bit serial I/O interface
OTP
The S3C9234 microcontroller is also available in OTP (One Time Programmable) version. S3P9234 microcontroller
has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM.
The S3P9234 is comparable to S3C9234, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9234/P9234
FEATURES
CPU
LCD Controller/Driver
·
SAM88RCRI CPU core
·
32 segments and 4 common terminals
·
·
Static, 1/2 duty, 1/3 duty, and 1/4 duty selectable
Internal resistor circuit for LCD bias
Memory
·
·
4K ´ 8 bits program memory (ROM)
8-bit Serial I/O Interface
208 ´ 8 bits data memory (RAM)
(Including LCD data memory)
·
·
·
·
8-bit transmit/receive mode
8-bit receive mode
Instruction Set
LSB-first or MSB-first transmission selectable
Internal or external clock source
·
·
41 instructions
Idle and Stop instructions added for power-down
modes
Two Power-Down Modes
52 I/O Pins
·
·
Idle mode: only CPU clock stops
Stop mode: system clock and CPU clock stop
·
·
I/O: 16 pins
I/O: 36 pins (sharing with LCD signal outputs)
Oscillation Sources
Interrupts
·
Crystal, ceramic, or RC for main clock
Main clock frequency: 0.4 MHz - 8MHz
·
·
·
·
11 interrupt source and 1 vector
One interrupt level
32.768 kHz crystal oscillation circuit for
sub clock
8-Bit Basic Timer
Instruction Execution Times
500nS at 8MHz fx(minimum)
·
·
Watchdog timer function
3 kinds of clock source
·
Operating Voltage Range
Two 8-Bit Timer/Counters
·
·
2.0 V to 5.5 V at 0.4 - 4.2MHz
2.7 V to 5.5 V at 0.4 - 8.0MHz
·
·
·
The programmable 8-bit timer/counters
External event counter function
Configurable as one 16-bit timer/counters
Operating Temperature Range
-30 °C to +85 °C
·
Watch Timer
·
·
Interval time: 3.91mS, 0.25S, 0.5S, and 1S
at 32.768 kHz
Package Type
64-pin QFP
·
0.5/1/2/4 kHz Selectable buzzer output
1-2
S3C9234/P9234
PRODUCT OVERVIEW
BLOCK DIAGRAM
TAOUT/P1.4
T1CLK/P1.3
8-Bit Timer/
CounterA
8-Bit Timer/
CounterB
16-Bit
Timer/
Counter1
X
IN
X
OUT
RESET XTIN
XTOUT
TBOUT/P1.5
Watchdog
Timer
Basic Timer
P0.0-P0.3/
COM0-COM3
I/O Port 0
I/O Port 1
Port I/O and Interrupt
Control
P1.0/INT
P1.1/INT
P1.2/INT
Watch Timer
BUZ/P1.7
P1.3/T1CLK
P1.4/TAOUT
P1.5/TBOUT
P1.6/CLKOUT
P1.7/BUZ
COM0-COM3/P0.0-P0.3
SEG0-SEG7/P6.7-P6.0
SEG8-SEG15/P5.7-P5.0
SEG16-SEG23/P4.7-P4.0
SEG24-SEG31/P3.7-P3.0
LCD
Driver/
SAM88RCRI CPU
Controller
P2.0/SCK
P2.1/SO
P2.2/SI
P2.3
I/O Port 2
P2.4/INT
P2.5/INT
P2.6/INT
P2.7/INT
208-Byte
Register
File
P2.0/SCK
P2.1/SO
P2.2/SI
4-Kbyte
ROM
SIO
P3.0-P3.7/
SEG31-SEG24
P6.0-P6.7/
SEG7-SEG0
I/O Port 3
I/O Port 4
I/O Port 6
I/O Port 5
P4.0-P4.7/
SEG23-SEG16
P5.0-P5.7/
SEG15-SEG8
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9234/P9234
PIN ASSIGNMENTS
COM0/P0.0
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13/P5.2
SEG14/P5.1
SEG15/P5.0
SEG16/P4.7
SEG17/P4.6
SEG18/P4.5
SEG19/P4.4
SEG20/P4.3
SEG21/P4.2
SEG22/P4.1
SEG23/P4.0
SEG24/P3.7
SEG25/P3.6
SEG26/P3.5
SEG27/P3.4
SEG28/P3.3
SEG29/P3.2
SEG30/P3.1
SEG31/P3.0
COM1/P0.1
COM2/P0.2
COM3/P0.3
BIAS
VLC0
VLC1
VLC2
S3C9234(S3P9234)
V
DD
SS
OUT
IN
9
V
10
11
12
13
14
15
16
17
18
19
X
(64-QFP-1420F)
X
TEST
XTIN
XTOUT
RESET
P1.0/INT
P1.1/INT
P1.2/INT
Figure 1-2. S3C9234 64-QFP Pin Assignments
1-4
S3C9234/P9234
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions
Pin Description
Pin Names
Pin
Type
Circuit
Type
Pin No.
Shared
Functions
P0.0 - P0.3
I/O
I/O port with bit-programmable pins;
H-9
1 - 4
COM0-COM3
Input or push-pull output and software
assignable pull-ups.
P1.0 - P1.2
P1.3
P1.4
P1.5
P1.6
I/O
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups;
P1.0 – P1.2 are alternately used for external
interrupt input(noise filters, interrupt enable and
pending control).
E-4
17 – 19
20
21
22
23
INT
T1CLK
TAOUT
TBOUT
CLKOUT
BUZ
P1.7
24
P2.0
P2.1
P2.2
I/O
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
E-4
25
26
27
SCK
SO
SI
P2.3
28
-
P2.4 – P2.7
29 - 32
INT
P3.0 - P3.7
P4.0 - P4.7
P5.0 – P5.7
P6.0 – P6.7
RESET
I/O I/O port with bit-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups.
H-8
H-9
H-9
H-9
33 - 40
41 - 48
49 - 56
57 - 64
SEG31-SEG24
SEG23-SEG16
SEG15-SEG8
SEG7-SEG0
I/O I/O port with bit-programmable pins;
Input or push-pull output and software assignable
pull-ups.
I/O I/O port with bit-programmable pins;
Input or push-pull output and software assignable
pull-ups.
I/O I/O port with 2bits-programmable pins;
Input or push-pull output and software assignable
pull-ups.
I
System reset pin
B
–
16
–
–
XT ,XT
–
Crystal oscillator pins for sub clock.
14, 15
IN OUT
X ,X
–
Main oscillator pins.
–
12, 11
–
IN OUT
TEST
I
Test input: it must be connected to V
SS
–
–
13
–
–
V
,V
–
Power input pins
9, 10
DD SS
BAIS
–
–
LCD power control pin
–
–
5
–
–
VLC0–VLC2
INT
LCD power supply pin
6 – 8
I/O
External interrupts input pins.
E-4
17 – 19
29 – 32
P1.0 – P1.2
P2.4 – P2.7
1-5
PRODUCT OVERVIEW
Pin Names
S3C9234/P9234
Table 1-1. Pin Descriptions (Continued)
Pin
Pin Description
Circuit
Pin No.
Shared
Type
Type
E-4
E-4
E-4
E-4
E-4
E-4
Functions
T1CLK
I/O
I/O
I/O
I/O
I/O
I/O
Timer 1/A external clock input.
Timer 1/A clock output.
Timer B clock output.
20
21
P1.3
P1.4
TAOUT
TBOUT
CLKOUT
BUZ
22
P1.5
System clock output.
23
P1.6
Output pin for buzzer signal.
24
P1.7
SCK, SO, SI
Serial clock, serial data output, and serial
data input.
25 – 27
P2.0 – P2.2
COM0-COM3
I/O
I/O
LCD common signal outputs.
LCD segment signal outputs.
H-9
H-9
1 – 4
P0.0 – P0.3
SEG0 – SEG7
SEG8 – SEG15
SEG16 – SEG23
64 – 57
56 – 49
48 – 41
P6.7 – P6.0
P5.7 – P5.0
P4.7 – P4.0
SEG24 – SEG31
I/O
LCD segment signal outputs.
H-8
40 – 33
P3.7 – P3.0
1-6
S3C9234/P9234
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
V
DD
Pull-Up
Resistor
P-Channel
N-Channel
In
In
Noise Filter
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-4. Pin Circuit Type B
VDD
Pull-up
Resistor
V
DD
Resistor
Enable
Open-Drain
Data
P-CH
N-CH
I/O
Output
Disable
Figure 1-5. Pin Circuit Type E-4 (P1, P2)
1-7
PRODUCT OVERVIEW
S3C9234/P9234
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open-Drain
Data
P-CH
I/O
N-CH
Output Disable 1
SEG
Output Disable 2
Circuit
Type H-4
Figure 1-6. Pin Circuit Type H-8 (P3)
VDD
Pull-up
Resistor
VDD
Resistor
Enable
P-CH
I/O
Data
N-CH
Output Disable 1
COM/SEG
Output Disable 2
Circuit
Type H-4
Figure 1-7. Pin Circuit Type H-9 (P0, P4, P5, P6)
1-8
S3C9234/P9234
PRODUCT OVERVIEW
VLC0
VLC1
Out
COM/SEG
Output Disable
VLC2
VSS
Figure 1-8. Pin Circuit Type H-4
1-9
PRODUCT OVERVIEW
S3C9234/P9234
NOTES
1-10
S3C9234/P9234
ADDRESS SPACES
2
ADDRESS SPACES
OVERVIEW
The S3C9234/P9234 microcontroller has three kinds of address space:
— Program memory (ROM)
— Internal register file
— LCD display register file
A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine
when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data
between the CPU and the internal register file.
The S3C9234 has 4K bytes of mask - programmable program memory on-chip. The S3C9234/P9234 microcontroller
has 192 bytes general-purpose registers in its internal register file and the 16 bytes for LCD display memory is
implemented in the internal register file too. 48 bytes in the register file are mapped for system and peripheral control
functions.
2-1
ADDRESS SPACES
S3C9234/P9234
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program code or table data. The S3P9234 has 4K bytes of mask - programmable
program memory. The program memory address range is therefore 0H-0FFFH. The first 2 bytes of the ROM (0000H–
0001H) are an interrupt vector address. The program reset address in the ROM is 0100H.
(Decimal)
4,096
(Hex)
0FFFH
4K bytes
Internal
Program
Memory
Area
256
Program Start
0100H
2
1
0
0002H
0001H
0000H
Interrupt
Vector
Figure 2-1. S3C9234/P9234 Program Memory Address Space
2-2
S3C9234/P9234
ADDRESS SPACES
REGISTER ARCHITECTURE
The upper 64 bytes of the S3C9234/P9234's internal register file are addressed as working registers, system control
registers and peripheral control registers. The lower 192 bytes of internal register file (00H–BFH) is called the general
purpose register space.
For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the
additional of one or more register pages at general purpose register space (00H–BFH).
FFH
Peripheral Control
Registers
E0H
DFH
64 Bytes of
Common Area
System Control
Registers
D0H
CFH
Working Registers
C0H
BFH
LCD Display Registers and
General Purpose Registers
B0H
AFH
192 Bytes
General Purpose
Register File
and Stack Area
00H
Byte
Figure 2-2. Internal Register File Organization
2-3
ADDRESS SPACES
S3C9234/P9234
COMMON WORKING REGISTER AREA (C0H–CFH)
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
This16-byte address range is called common area. That is, locations in this area can be used as working registers
by operations that address any location on any page in the register file. Typically, these working registers serve as
temporary buffers for data operations between different pages.
The Register (R) addressing mode can be used to access this area
Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the
address of the first 8-bit register is always an even number and the address of the next register is an odd number.
The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte
is always stored in the next (+ 1) odd-numbered register.
MSB
Rn
LSB
n = Even address
Rn + 1
Figure 2-3. 16-Bit Register Pairs
F
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples:
1. LD
0C2H,40H
; Invalid addressing mode!
Use working register addressing instead:
LD
R2,40H
;
;
R2 (C2H) ¬ the value in location 40H
2. ADD
0C3H,#45H
Invalid addressing mode!
Use working register addressing instead:
ADD R3,#45H R3 (C3H) ¬ R3 + 45H
;
2-4
S3C9234/P9234
ADDRESS SPACES
SYSTEM STACK
S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations. The S3C9234/P9234 architecture supports stack
operations in the internal register file.
STACK OPERATIONS
Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of
the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their
original locations. The stack address is always decremented before a push operation and incremented after a pop
operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure
2-4.
High Address
PCL
PCL
PCH
Top of
stack
PCH
Top of
stack
Flags
Stack contents
after a call
instruction
Stack contents
after an
Low Address
interrupt
Figure 2-4. Stack Operations
STACK POINTER (SP)
Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,
the SP value is undetermined.
Because only internal memory space is implemented in the S3C9234/P9234, the SP must be initialized to an 8-bit
value in the range 00H–AFH.
NOTE
In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means
that a Stack Pointer access invalid stack area.
2-5
ADDRESS SPACES
S3C9234/P9234
F
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP
instructions:
LD
SP,#0B8H
;
;
SP ¬ B8H (Normally, the SP is set to 0B8H by the
initialization routine)
•
•
•
PUSH
PUSH
PUSH
SYM
WTCON
20H
;
;
;
;
Stack address 0B7H ¬ SYM
Stack address 0B6H ¬ WTCON
Stack address 0B5H ¬ 20H
Stack address 0B4H ¬ R3
PUSH
R3
•
•
•
POP
POP
POP
POP
R3
20H
WTCON
SYM
;
;
;
;
R3 ¬ Stack address 0B4H
20H ¬ Stack address 0B5H
WTCON ¬ Stack address 0B6H
SYM ¬ Stack address 0B7H
2-6
S3C9234/P9234
ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are
available for each instruction. The addressing modes and their symbols are as follows:
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Relative Address (RA)
— Immediate (IM)
3-1
ADDRESSING MODES
S3C9234/P9234
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register
addressing differs from Register addressing because it uses a 16-byte working register space in the register file and
a 4-bit register within that space (see Figure 3-2).
Program Memory
Register File
OPERAND
8-bit Register
File Address
dst
Point to One
Rigister in Register
File
OPCODE
One-Operand
Instruction
(Example)
Value used in
Instruction Execution
Sample Instruction:
DEC CNTR
;
Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File
CFH
.
.
.
.
Program Memory
4-Bit
Working Register
4 LSBs
dst
src
OPERAND
Point to the
Woking Register
(1 of 16)
OPCODE
Two-Operand
Instruction
(Example)
C0H
Sample Instruction:
ADD R1, R2
;
Where R1 = C1H and R2 = C2H
Figure 3-2. Working Register Addressing
3-2
S3C9234/P9234
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location.
Program Memory
Register File
ADDRESS
8-Bit Register
File Address
dst
Point to One
Rigister in Register
File
OPCODE
One-Operand
Instruction
(Example)
Address of Operand
used by Instruction
OPERAND
Value used in
Instruction Execution
Sample Instruction:
RL
@SHIFT
;
Where SHIFT is the label of an 8-Bit register address
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES
S3C9234/P9234
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory
Example
REGISTER
PAIR
dst
Instruction
References
Program
Points to
Rigister Pair
OPCODE
16-Bit
Memory
Address
Points to
Program
Memory
Program Memory
OPERAND
Sample Instructions:
Value used in
Instruction
CALL
JP
@RR2
@RR2
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
S3C9234/P9234
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
CFH
.
.
.
.
Program Memory
4-Bit
4 LSBs
Working
Register
Address
dst
src
OPERAND
Point to the
Woking Register
(1 of 16)
OPCODE
C0H
Sample Instruction:
OR R6, @R2
Value used in
Instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
S3C9234/P9234
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File
CFH
.
.
.
.
Program Memory
4-Bit Working
Register Address
dst
src
Register
Pair
Next 3 Bits Point
to Working
OPCODE
Example Instruction
References either
Program Memory or
Data Memory
C0H
Register Pair
(1 of 8)
16-Bit
address
points to
program
memory
or data
Program Memory
or
Data Memory
LSB Selects
memory
Value used in
Instruction
OPERAND
Sample Instructions:
LCD
LDE
LDE
R5,@RR6
R3,@RR14
@RR4, R8
; Program memory access
; External data memory access
; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
S3C9234/P9234
ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations
in the internal register file or in external memory.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of
–128 to +127. This applies to external memory accesses only (see Figure 3-8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in
a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see
Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD).
The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program
memory, and for external data memory, when implemented.
Register File
~
~
~
~
Value used in
Instruction
OPERAND
+
Program Memory
Base Address
4 LSBs
dst
src
INDEX
Two-Operand
Instruction
Example
Point to One of the
Woking Register
(1 of 16)
OPCODE
Sample Instruction:
LD R0, #BASE[R1]
;
Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
S3C9234/P9234
INDEXED ADDRESSING MODE (Continued)
Program Memory
Register File
XS (OFFSET)
4-Bit Working
NEXT 3 Bits
Register
Pair
dst
src
Register Address
Point to Working
Register Pair
(1 of 8)
OPCODE
16-Bit
address
added to
offset
LSB Selects
+
16-Bits
8-Bits
Program Memory
or
Data Memory
Value used in
Instruction
OPERAND
16-Bits
Sample Instructions:
LDC
LDE
R4, #04H[RR2]
R4,#04H[RR2]
; The values in the program address (RR2 + #04H)
are loaded into register R4.
; Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3C9234/P9234
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory
Register File
XL
H
L
(OFFSET)
(OFFSET)
src
XL
Register
Pair
NEXT 3 Bits
4-Bit Working
Register Address
dst
Point to Working
Register Pair
(1 of 8)
OPCODE
16-Bit
address
added to
offset
LSB Selects
+
16-Bits
8-Bits
Program Memory
or
Data Memory
Value used in
Instruction
OPERAND
16-Bits
Sample Instructions:
LDC
R4, #1000H[RR2]
; The values in the program address (RR2 +
#1000H)
are loaded into register R4.
LDE
R4, #1000H[RR2]
; Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
3-9
ADDRESSING MODES
S3C9234/P9234
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load
operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Address
Used
Program Memory
Upper Address Byte
Lower Address Byte
LSB Selects Program
dst/src "0" or "1"
OPCODE
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Sample Instructions:
LDC
LDE
R5,1234H
R5,1234H
;
;
The values in the program address (1234H)
are loaded into register R5.
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3C9234/P9234
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Program
Memory
Address
Used
Lower Address Byte
Upper Address Byte
OPCODE
Sample Instructions:
JP
CALL
C,JOB1
DISPLAY
;
;
Where JOB1 is a 16-bit immediate address
Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES
S3C9234/P9234
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in
the instruction. The displacement value is then added to the current PC value. The result is the address of the next
instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately
following the current instruction.
The instructions that support RA addressing is JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current
PC Value
+
Displacement
OPCODE
Current Instruction
Signed
Displacement Value
Sample Instructions:
JR
ULT,$ + OFFSET
;
Where OFFSET is a value in the range + 127 to - 128
Figure 3-12. Relative Addressing
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. Immediate addressing mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The Operand value is in the instruction)
Sample Instruction:
LD R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
S3C9234/P9234
CONTROL REGISTERS
4
CONTROL REGISTERS
OVERVIEW
In this section, detailed descriptions of the S3C9234/P9234 control registers are presented in an easy-to-read
format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use
them as a quick-reference source when writing application programs.
System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the
standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More information
about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this
manual.
4-1
CONTROL REGISTERS
S3C9234/P9234
Table 4-1. System and Peripheral Control Registers
Register Name
Mnemonic Address(Page 0)
R/W
RES ET Value(bit)
Decimal
208
Hex
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
7
0
0
0
–
0
x
0
0
0
x
0
6
0
0
0
–
0
x
0
0
0
x
0
5
0
0
0
–
0
x
0
0
0
x
0
4
0
0
0
–
0
x
0
0
0
x
0
3
0
0
0
0
0
–
0
0
–
x
2
0
0
0
0
0
–
0
0
0
x
1
0
0
0
–
0
–
0
–
0
x
0
0
0
0
0
0
–
0
0
0
x
SIO Control Register
SIOCON
SIODATA
SIOPS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SIO Data Register
209
SIO Prescaler Register
Oscillator Control Register
System Clock Control Register
System Flags Register
Stop Control Register
LCD Control Register
Interrupt Pending Register
Stack Pointer
210
OSCCON
CLKCON
FLAGS
STPCON
LCON
211
212
213
214
215
INTPND
SP
216
217
Watch Timer Control Register
WTCON
218
0
0
0
0
Location DBH is not mapped.
Basic Timer Control Register
Basic Timer Counter
BTCON
BTCNT
220
221
DCH
DDH
R/W
R
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
Location DEH is not mapped.
System Mode Register
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
Timer A Counter
SYM
P0
223
224
225
226
227
228
229
230
231
232
233
234
235
236
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
x
x
x
x
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
–
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
P1
P2
P3
P4
P5
P6
TACNT
TBCNT
TADATA
TBDATA
TACON
TBCON
Timer B Counter
R
Timer A Data Register
Timer B Data Register
Timer 1/A Control Register
Timer B Control Register
R/W
R/W
R/W
R/W
4-2
S3C9234/P9234
CONTROL REGISTERS
Table 4-1. System and Peripheral Control Registers (Continued)
Register Name
Mnemonic Address(Page 0)
R/W
RES ET Value(bit)
Decimal
237
Hex
EDH
EEH
EFH
F0H
7
0
0
0
0
6
0
0
0
0
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Port 0 Control Register
P0CON
P1CONH
P1CONL
P1PUR
R/W
R/W
R/W
R/W
Port 1 Control Register(High Byte)
Port 1 Control Register(Low Byte)
238
239
Port 1 Pull-up Resistor Enable
Register
240
Port 1 Interrupt Control Register
Port 2 Control Register (High Byte)
Port 2 Control Register (Low Byte)
P1INT
P2CONH
P2CONL
P2PUR
241
242
243
244
F1H
F2H
F3H
F4H
R/W
R/W
R/W
R/W
–
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 2 Pull-up Resistor Enable
Register
Port 2 Interrupt Control Register
Port 3 Control Register (High Byte)
Port 3 Control Register (Low Byte)
P2INT
P3CONH
P3CONL
P3PUR
245
246
247
248
F5H
F6H
F7H
F8H
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 3 Pull-up Resistor Enable
Register
Port 4 Control Register (High Byte)
Port 4 Control Register (Low Byte)
Port 5 Control Register (High Byte)
Port 5 Control Register (Low Byte)
Port 6 Control Register
P4CONH
P4CONL
P5CONH
P5CONL
P6CON
249
250
251
252
253
254
F9H
FAH
FBH
FCH
FDH
FEH
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
Clock Output Control Register
CLOCON
Location FFH is not mapped.
NOTES:
1. An "x" means that the bit value is undefined following reset.
2. A dash("-") means that the bit is neither used nor mapped, but the bit is read as "0".
4-3
CONTROL REGISTERS
S3C9234/P9234
Bit number(s) that is/are appended to the
register name for bit addressing
Name of individual
bit or bit function
Register address
(hexadecimal)
Register
Full Register name
mnemonic
D5H
FLAGS - System Flags Register
.7
.6
.5
.4
.3
.2
.1
.0
Bit Identifier
RESET Value
Read/Write
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
0
R/W
0
R/W
.7
Carry Flag (C)
0
1
Operation dose not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit7
.6
Zero Flag
0
1
Operation result is a non-zero value
Operation result is zero
.5
Sign Flag
0
1
Operation generates positive number (MSB = "0")
Operation generates negative number (MSB = "1")
R = Read-only
W = Write-only
R/W = Read/write
' - ' = Not used
Description of the
effect of specific
bit settings
RESET value notation:
'-' = Not used
'x' = Undetermind value
'0' = Logic zero
'1' = Logic one
Addressing mode or
Bit number:
MSB = Bit 7
LSB = Bit 0
modes you can use to
modify register values
(1-bit, 4-bit, or 8-bit)
Figure 4-1. Register Description Format
4-4
S3C9234/P9234
CONTROL REGISTERS
BTCON— Basic Timer Control Register
DCH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.4
.3-.2
Watchdog Timer Function Disable Code (for System Reset)
1
0
1
0
Disable watchdog timer function
Enable watchdog timer function
Any other value
Basic Timer Clock Selection Bits
0
0
1
1
0
1
0
1
fxx/4096
fxx/1024
fxx/128
fxx/16
.1
.0
Basic Timer Counter Clear Bit
0
1
No effect
Clear the basic timer counter value
(Automatically cleared to "0" after being cleared basic timer counter)
Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters
0
1
No effect
Clear clock frequency dividers
(Automatically cleared to "0" after being cleared clock frequency dividers)
NOTE: The fxx is the selected clock for system (main clock or sub clock).
4-5
CONTROL REGISTERS
S3C9234/P9234
CLKCON — System Clock Control Register
D4H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Oscillator IRQ Wake-up Function Enable Bit
0
1
Enable IRQ for main oscillator wake-up function
Disable IRQ for main oscillator wake-up function
.6-.5
.4-.3
Bits 6-5
0
Always logic zero
CPU Clock (System Clock) Frequency Selection Bits
0
0
1
1
0
1
0
1
Select fxx/16
Select fxx/8
Select fxx/2
Non-divided clock (fxx)
.2-.0
Bits 2-0
Always logic zero
0
4-6
S3C9234/P9234
CONTROL REGISTERS
CLOCON — Clock Output Control Register
FEH
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
–
.2
–
.1
0
.0
0
RES ET Value
Read/Write
–
–
–
–
–
–
R/W
R/W
.7-.2
.1-.0
Bits 7-2
0
Always logic zero
Clock Output Frequency Selection Bits
0
0
1
1
0
1
0
1
Select fxx/64
Select fxx/16
Select fxx/8
Select fxx/4
4-7
CONTROL REGISTERS
S3C9234/P9234
FLAGS — System Flags Register
D5H
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
–
.2
–
.1
–
.0
–
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
–
–
–
–
.7
Carry Flag (C)
0
1
Operation does not generate a carry or borrow condition
Operation generates a carry-out or borrow into high-order bit 7
.6
Zero Flag (Z)
0
1
Operation result is a non-zero value
Operation result is zero
.5
Sign Flag (S)
0
1
Operation generates a positive number (MSB = "0")
Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V)
0
1
Operation result is £ +127 or ³ –128
Operation result is > +127 or < –128
.3-.0
Not used for S3C9234/P9234.
4-8
S3C9234/P9234
CONTROL REGISTERS
INTPND — Interrupt Pending Register
D8H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
–
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
.7
.6
.5
.4
P2.7's Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
P2.6's Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
P2.5's Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
P2.4's Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
.3
.2
Not used for S3C9234/P9234.
P1.2's Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
.1
.0
P1.1's Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
P1.0's Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
4-9
CONTROL REGISTERS
S3C9234/P9234
LCON— LCD Control Register
D7H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
–
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
.7
Internal LCD Dividing Resistors Enable Bit
0
1
Enable internal LCD dividing resistors
Disable internal LCD dividing resistors
.6-.5
LCD Clock Selection Bits
9
0
0
1
1
0
1
0
1
fw/2 (64 Hz)
8
fw/2 (128 Hz)
7
fw/2 (256 Hz)
6
fw/2 (512 Hz)
.4-.2
LCD Duty and Bias Selection Bits
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
1/4duty, 1/3bias
1/3duty, 1/3bias
1/3duty, 1/2bias
1/2duty, 1/2bias
Static
.1
.0
Not used for S3C9234/P9234.
LCD Display Control Bits
0
1
All LCD signals are low (Turn off the P-Tr)
Turn display on (Turn on the P-Tr)
NOTE: "x" means don't care.
4-10
S3C9234/P9234
CONTROL REGISTERS
OSCCON— Oscillator Control Register
D3H
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
0
.2
0
.1
–
.0
0
RES ET Value
Read/Write
–
–
–
–
R/W
R/W
–
R/W
.7-.4
.3
Not used for S3C9234/P9234.
Main Oscillator Control Bit
0
1
Main oscillator RUN
Main oscillator STOP
.2
Sub Oscillator Control Bit
0
1
Sub oscillator RUN
Sub oscillator STOP
.1
.0
Not used for S3C9234/P9234.
System Clock Selection Bit
0
1
Select main oscillator for system clock
Select sub oscillator for system clock
4-11
CONTROL REGISTERS
S3C9234/P9234
P0CON– Port 0 Control Register
EDH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P0.3/COM3 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (COM3)
P0.2/COM2 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (COM2)
P0.1/COM1 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (COM1)
P0.0/COM0 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (COM0)
4-12
S3C9234/P9234
CONTROL REGISTERS
P1CONH— Port 1 Control Register High Byte
EEH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P1.7/BUZ Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (BUZ)
P1.6/CLKOUT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (CLKOUT)
P1.5/TBOUT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (TBOUT)
P1.4/TAOUT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (TAOUT)
4-13
CONTROL REGISTERS
S3C9234/P9234
P1CONL – Port 1 Control Register Low Byte
EFH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P1.3/T1CLK Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode (T1CLK)
N-channel open-drain output mode
Push-pull output mode
Not available
P1.2/INT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
P1.1/INT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
P1.0/INT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
4-14
S3C9234/P9234
CONTROL REGISTERS
P1INT –Port 1 Interrupt Enable Register
F1H
Bit Identifier
.7
–
.6
–
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
Not used for S3C9234/P9234.
P1.2/INT External Interrupt Configuration Bits
0
0
1
1
0
1
0
1
Disable interrupt
Enable interrupt by falling edge
Enable interrupt by rising edge
Enable interrupt by both falling and rising edge
.3-.2
P1.1/INT External Interrupt Configuration Bits
0
0
1
1
0
1
0
1
Disable interrupt
Enable interrupt by falling edge
Enable interrupt by rising edge
Enable interrupt by both falling and rising edge
.1-.0
P1.0/INT External Interrupt Configuration Bits
0
0
1
1
0
1
0
1
Disable interrupt
Enable interrupt by falling edge
Enable interrupt by rising edge
Enable interrupt by both falling and rising edge
4-15
CONTROL REGISTERS
S3C9234/P9234
P1PUR–Port 1 Pull-up Resistors Enable Register
F0H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P1.7's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P1.6's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P1.5's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P1.4's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P1.3's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P1.2's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P1.1's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P1.0's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE: A pull-up resistor of port1 is automatically disabled when the corresponding pin is selected as push-pull
output or alternative function.
4-16
S3C9234/P9234
CONTROL REGISTERS
P2CONH–Port 2 Control Register High Byte
F2H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P2.7/INT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
P2.6/INT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
P2.5/INT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
P2.4/INT Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
4-17
CONTROL REGISTERS
S3C9234/P9234
P2CONL – Port 2 Control Register Low Byte
F3H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P2.3 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
P2.2/SI Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode (SI)
N-channel open-drain output mode
Push-pull output mode
Not available
P2.1/SO Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SO)
P2.0/SCK Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode (SCK)
N-channel open-drain output mode
Push-pull output mode
Alternative function (SCK)
4-18
S3C9234/P9234
CONTROL REGISTERS
P2INT — Port 2 Interrupt Enable Register
F5H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P2.7/INT External Interrupt Edge Selection Bit
0
1
Select falling edge
Select rising edge
P2.7/INT External Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.6/INT External Interrupt Edge Selection Bit
0
1
Select falling edge
Select rising edge
P2.6/INT External Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.5/INT External Interrupt Edge Selection Bit
0
1
Select falling edge
Select rising edge
P2.5/INT External Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.4/INT External Interrupt Edge Selection Bit
0
1
Select falling edge
Select rising edge
P2.4/INT External Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
4-19
CONTROL REGISTERS
S3C9234/P9234
P2PUR–Port 2 Pull-up Resistors Enable Register
F4H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P2.7's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.6's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.5's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.4's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.3's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.2's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.1's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.0's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE: A pull-up resistor of port 2 is automatically disabled when the corresponding pin is selected as push-pull output or
alternative function.
4-20
S3C9234/P9234
CONTROL REGISTERS
P3CONH– Port 3 Control Register High Byte
F6H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P3.7/SEG24 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG24)
P3.6/SEG25 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG25)
P3.5/SEG26 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG26)
P3.4/SEG27 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG27)
4-21
CONTROL REGISTERS
S3C9234/P9234
P3CONL –Port 3 Control Register Low Byte
F7H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P3.3/SEG28 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG28)
P3.2/SEG29 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG29)
P3.1/SEG30 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG30)
P3.0/SEG31 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG31)
4-22
S3C9234/P9234
CONTROL REGISTERS
P3PUR–Port 3 Pull-up Resistors Enable Register
F8H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P3.7's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P3.6's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P3.5's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P3.4's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P3.3's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P3.2's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P3.1's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P3.0's Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE: A pull-up resistor of port3 is automatically disabled when the corresponding pin is selected as push-pull
output or alternative function.
4-23
CONTROL REGISTERS
S3C9234/P9234
P4CONH– Port 4 Control Register High Byte
F9H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P4.7/SEG16 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG16)
P4.6/SEG17 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG17)
P4.5/SEG18 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG18)
P4.4/SEG19 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG19)
4-24
S3C9234/P9234
CONTROL REGISTERS
P4CONL–Port 4 Control Register Low Byte
FAH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P4.3/SEG20 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG20)
P4.2/SEG21 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG21)
P4.1/SEG22 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG22)
P4.0/SEG23 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG23)
4-25
CONTROL REGISTERS
S3C9234/P9234
P5CONH– Port 5 Control Register High Byte
FBH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P5.7/SEG8 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG8)
P5.6/SEG9 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG9)
P5.5/SEG10 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG10)
P5.4/SEG11 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG11)
4-26
S3C9234/P9234
CONTROL REGISTERS
P5CONL – Port 5 Control Register Low Byte
FCH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P5.3/SEG12 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG12)
P5.2/SEG13 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG13)
P5.1/SEG14 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG14)
P5.0/SEG15 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG15)
4-27
CONTROL REGISTERS
S3C9234/P9234
P6CON– Port 6 Control Register
FDH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.4
.3-.2
.1-.0
P6.7-P6.6/SEG0-SEG1 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG0-SEG1)
P6.5-P6.4/SEG2-SEG3 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG2-SEG3)
P6.3-P6.2/SEG4-SEG5 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG4-SEG5)
P6.1-P6.0/SEG6-SEG7 Configuration Bits
0
0
1
1
0
1
0
1
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG6-SEG7)
4-28
S3C9234/P9234
CONTROL REGISTERS
SIOCON — SIO Control Register
D0H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.1
SIO Shift Clock Selection Bit
0
1
Internal clock (P.S clock)
External clock (SCK)
Data Direction Control Bit
0
1
MSB-first mode
LSB-first mode
SIO Mode Selection Bit
0
1
Receive-only mode
Transmit/Receive mode
Shift Clock Edge Selection Bit
0
1
Tx at falling edges, Rx at rising edges
Tx at rising edges, Rx at falling edges
SIO Counter Clear and Shift Start Bit
0
1
No action
Clear 3-bit counter and start shifting
SIO Shift Operation Enable Bit
0
1
Disable shifter and clock counter
Enable shifter and clock counter
SIO Interrupt Enable Bit
0
1
Disable SIO interrupt
Enable SIO interrupt
SIO Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
4-29
CONTROL REGISTERS
S3C9234/P9234
STPCON– Stop Control Register
D6H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.0
Stop Control Bits
1
0
1
0
0
1
0
1
Enable Stop instruction
Disable Stop instruction
Other values
NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP
instruction will not execute.
4-30
S3C9234/P9234
CONTROL REGISTERS
SYM — System Mode Register
DFH
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
–
–
–
–
R/W
R/W
R/W
R/W
.7-.4
.3
Not used for S3C9234/P9234.
Global Interrupt Enable Bit
0
1
Disable all interrupt (DI instruction)
Enable all interrupt (EI instruction)
.2-.0
Page Selection Bits
Page 0
Other values Not available
0
0
0
4-31
CONTROL REGISTERS
S3C9234/P9234
TACON— Timer 1/A Control Register
EBH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Timer 1 Mode Selection Bit
0
1
Two 8-bit timers mode (Timer A/B)
One 16-bit timer mode (Timer 1)
.6-.4
Timer 1/A Clock Selection Bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fxx/512
fxx/256
fxx/64
fxx/8
fxx (system clock)
fxt (sub clock)
T1CLK (external clock)
Not available
.3
.2
.1
.0
Timer 1/A Counter Clear Bit
0
1
No effect
Clear the timer 1/A counter (when write)
Timer 1/A Counter Enable Bit
0
1
Disable counting operation
Enable counting operation
Timer 1/A Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
Timer 1/A Interrupt Pending Bit
0
1
No interrupt pending bit (when read), Clear pending bit (when write)
Interrupt is pending (when read)
4-32
S3C9234/P9234
CONTROL REGISTERS
TBCON— Timer B Control Register
ECH
Bit Identifier
.7
–
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Not used for S3C9234/P9234.
.6-.4
Timer B Clock Selection Bits
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
fxx/512
fxx/256
fxx/64
fxx/8
fxt (sub clock)
.3
.2
.1
.0
Timer B Counter Clear Bit
0
1
No effect
Clear the timer B counter (when write)
Timer B Counter Enable Bit
0
1
Disable counting operation
Enable counting operation
Timer B Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
Timer B Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
4-33
CONTROL REGISTERS
S3C9234/P9234
WTCON— Watch Timer Control Register
DAH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RES ET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Watch Timer Clock Selection Bit
7
0
1
Select main clock divided by 2 (fx/128)
Select sub clock (fxt)
.6
Watch Timer Interrupt Enable Bit
0
1
Disable watch timer interrupt
Enable watch timer interrupt
.5-.4
Buzzer Signal Selection Bits
0
0
1
1
0
1
0
1
0.5 kHz
1 kHz
2 kHz
4 kHz
.3-.2
Watch Timer Speed Selection Bits
0
0
1
1
0
1
0
1
Set watch timer interrupt to 1s
Set watch timer interrupt to 0.5s
Set watch timer interrupt to 0.25s
Set watch timer interrupt to 3.91ms
.1
.0
Watch Timer Enable Bit
0
1
Disable watch timer; Clear frequency dividing circuits
Enable watch timer
Watch Timer Interrupt Pending Bit
0
1
No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
4-34
S3C9234/P9234
INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt
sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H.
VECTOR
SOURCES
S1
S2
S3
Sn
0000H
0001H
NOTES:
1. The SAM88RCRI interrupt has only one vector address (0000H-0001H).
2. The number of Sn value is expandable.
Figure 5-1. S3C9-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The system-
level control points in the interrupt structure are therefore:
— Global interrupt enable and disable (by EI and DI instructions)
— Interrupt source enable and disable settings in the corresponding peripheral control register(s)
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
The system mode register, SYM (DFH), is used to enable and disable interrupt processing.
SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An
Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to
enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during
normal operation, we recommend that you use the EI and DI instructions for this purpose.
5-1
INTERRUPT STRUCTURE
S3C9234/P9234
INTERRUPT PENDING FUNCTION TYPES
When the interrupt service routine has executed, the application program's service routine must clear the appropriate
pending bit before the return from interrupt subroutine (IRET) occurs.
INTERRUPT PRIORITY
Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of
source which is executed in interrupt service routine.
"EI" Instruction
S
R
Q
Interrupt Pending
Register
Execution
RESET
Source
Interrupts
Vector
Interrupt
Cycle
Interrpt priority
is determind by
software polling
method
Source
Interrupt
Enable
Global Interrupt
Control (EI, Di instruction)
Figure 5-2. Interrupt Function Diagram
5-2
S3C9234/P9234
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request pending bit to "1".
2. The CPU generates an interrupt acknowledge signal.
3. The service routine starts and the source's pending flag is cleared to "0" by software.
4. Interrupt priority must be determined by software polling method.
INTERRUPT SERVICE ROUTINES
Before an interrupt request can be serviced, the following conditions must be met:
— Interrupt processing must be enabled (EI, SYM.3 = "1")
— Interrupt must be enabled at the interrupt's source (peripheral control register)
If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The
CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0")
to disable all subsequent interrupts.
2. Save the program counter and status flags to stack.
3. Branch to the interrupt vector to fetch the service routine's address.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the
PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request.
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt
processing follows this sequence:
1. Push the program counter's low-byte value to stack.
2. Push the program counter's high-byte value to stack.
3. Push the FLAGS register values to stack.
4. Fetch the service routine's high-byte address from the vector address 0000H.
5. Fetch the service routine's low-byte address from the vector address 0001H.
6. Branch to the service routine specified by the 16-bit vector address.
5-3
INTERRUPT STRUCTURE
S3C9234/P9234
S3C9234/P9234 INTERRUPT STRUCTURE
The S3C9234/P9234 microcontroller has eleven peripheral interrupt sources:
— Timer 1/A interrupt
— Timer B interrupt
— SIO interrupt
— Watch Timer interrupt
— Three external interrupts for port 1
— Four external interrupts for port 2
5-4
S3C9234/P9234
INTERRUPT STRUCTURE
Vector
Enable/Disable
Pending
Sources
INTPND.0
P1.0 External Interript
P1.1 External Interript
P1.2 External Interript
P1INT.0
P1INT.1
P1INT.2
INTPND.1
INTPND.2
INTPND.4
INTPND.5
P2.4 External Interript
P2.5 External Interript
P2.6 External Interript
P2.7 External Interrupt
Timer 1/A Interrupt
P2INT.4
P2INT.5
P2INT.6
P2INT.7
TACON.1
INTPND.6
INTPND.7
0000H
0001H
SYM.3
(EI, DI)
TACON.0
TBCON.0
SIOCON.0
Timer B Interrupt
SIO Interrupt
TBCON.1
SIOCON.1
Watch Timer Interrupt
WTCON.0
WTCON.6
Figure 5-3. S3C9234/P9234 Interrupt Structure
5-5
INTERRUPT STRUCTURE
S3C9234/P9234
F
Programming Tip — How to Clear an Interrupt Pending Bit
As the following examples are shown, a load instruction should be used to clear an interrupt pending bit of INTPND
register.
Examples:
1.
LD
INTPND, #11111011B
WTCON, #11111110B
; Clear P1.2's interrupt pending bit
·
·
·
IRET
2.
AND
; Clear watch timer interrupt pending bit
·
·
·
IRET
5-6
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
6
SAM88RCRI INSTRUCTION SET
OVERVIEW
The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit
arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O
control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and
shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set.
REGISTER ADDRESSING
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit program memory or data memory addresses. For detailed
information about register addressing, please refer to Section 2, "Address Spaces".
ADDRESSING MODES
There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and
Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes".
6-1
SAM88RI INSTRUCTION SET
S3C9234/P9234
Table 6-1. Instruction Group Summary
Operands Instruction
Mnemonic
Load Instructions
CLR
dst
Clear
LD
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst
Load
LDC
Load program memory
Load external data memory
LDE
LDCD
LDED
LDCI
LDEI
POP
PUSH
Load program memory and decrement
Load external data memory and decrement
Load program memory and increment
Load external data memory and increment
Pop from stack
src
Push to stack
Arithmetic Instructions
ADC
ADD
CP
dst,src
dst,src
dst,src
dst
Add with carry
Add
Compare
DEC
INC
Decrement
Increment
Subtract with carry
Subtract
dst
SBC
SUB
dst,src
dst,src
Logic Instructions
AND
COM
OR
dst,src
dst
Logical AND
Complement
dst,src
dst,src
Logical OR
XOR
Logical exclusive OR
6-2
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued)
Mnemonic
Operands
Instruction
Program Control Instructions
CALL
IRET
JP
dst
Call procedure
Interrupt return
cc,dst
dst
Jump on condition code
Jump unconditional
Jump relative on condition code
Return
JP
JR
cc,dst
RET
Bit Manipulation Instructions
TCM
TM
dst,src
dst,src
Test complement under mask
Test under mask
Rotate and Shift Instructions
RL
dst
dst
dst
dst
dst
Rotate left
RLC
RR
Rotate left through carry
Rotate right
RRC
SRA
Rotate right through carry
Shift right arithmetic
CPU Control Instructions
CCF
DI
Complement carry flag
Disable interrupts
Enable interrupts
Enter Idle mode
No operation
EI
IDLE
NOP
RCF
SCF
STOP
Reset carry flag
Set carry flag
Enter Stop mode
6-3
SAM88RI INSTRUCTION SET
FLAGS REGISTER (FLAGS)
S3C9234/P9234
The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits,
FLAGS.4 – FLAGS.7, can be tested and used with conditional jump instructions;
FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load
instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register.
For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur
to the Flags register producing an unpredictable result.
System Flags Register (FLAGS)
D5H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Carry flag (C)
Not mapped
Zero flag (Z)
Sign flag (S)
Overflow flag (V)
Figure 6-1. System Flags Register (FLAGS)
FLAG DESCRIPTIONS
Overflow Flag (FLAGS.4, V)
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than – 128. It is
also cleared to "0" following logic operations.
Sign Flag (FLAGS.5, S)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic
zero indicates a positive number and a logic one indicates a negative number.
Zero Flag (FLAGS.6, Z)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that
test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.
Carry Flag (FLAGS.7, C)
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7
position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Program instructions can set, clear, or complement the carry flag.
6-4
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
INSTRUCTION SET NOTATION
Table 6-2. Flag Notation Conventions
Flag
Description
Carry flag
C
Z
S
V
0
1
*
Zero flag
Sign flag
Overflow flag
Cleared to logic zero
Set to logic one
Set or cleared according to operation
Value is unaffected
Value is undefined
–
x
Table 6-3. Instruction Set Symbols
Symbol
Description
Destination operand
dst
src
@
Source operand
Indirect register address prefix
Program counter
PC
FLAGS
#
Flags register (D5H)
Immediate operand or register address prefix
Hexadecimal number suffix
Decimal number suffix
Binary number suffix
H
D
B
opc
Opcode
6-5
SAM88RI INSTRUCTION SET
S3C9234/P9234
Table 6-4. Instruction Notation Conventions
Description Actual Operand Range
Notation
cc
r
Condition code
See list of condition codes in Table 6-6.
Rn (n = 0–15)
Working register only
rr
Working register pair
RRp (p = 0, 2, 4, ..., 14)
R
Register or working register
Register pair or working register pair
reg or Rn (reg = 0–255, n = 0–15)
RR
reg or RRp (reg = 0–254, even number only, where
p = 0, 2, ..., 14)
Ir
IR
Indirect working register only
@Rn (n = 0–15)
Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)
Irr
Indirect working register pair only
@RRp (p = 0, 2, ..., 14)
IRR
Indirect register pair or indirect working
register pair
@RRp or @reg (reg = 0–254, even only, where
p = 0, 2, ..., 14)
X
Indexed addressing mode
#reg[Rn] (reg = 0–255, n = 0–15)
XS
Indexed (short offset) addressing mode
#addr[RRp] (addr = range –128 to +127, where
p = 0, 2, ..., 14)
xl
Indexed (long offset) addressing mode
#addr [RRp] (addr = range 0–8191, where
p = 0, 2, ..., 14)
da
ra
Direct addressing mode
Relative addressing mode
addr (addr = range 0–8191)
addr (addr = number in the range +127 to –128 that is
an offset relative to the address of the next instruction)
im
Immediate addressing mode
#data (data = 0–255)
6-6
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
Table 6-5. Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
1
2
3
4
5
6
7
U
P
P
E
R
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DEC
R1
DEC
IR1
ADD
r1,r2
ADD
r1,Ir2
ADD
R2,R1
ADD
IR2,R1
ADD
R1,IM
RLC
R1
RLC
IR1
ADC
r1,r2
ADC
r1,Ir2
ADC
R2,R1
ADC
IR2,R1
ADC
R1,IM
INC
R1
INC
IR1
SUB
r1,r2
SUB
r1,Ir2
SUB
R2,R1
SUB
IR2,R1
SUB
R1,IM
JP
IRR1
SBC
r1,r2
SBC
r1,Ir2
SBC
R2,R1
SBC
IR2,R1
SBC
R1,IM
OR
r1,r2
OR
r1,Ir2
OR
R2,R1
OR
IR2,R1
OR
R1,IM
POP
R1
POP
IR1
AND
r1,r2
AND
r1,Ir2
AND
R2,R1
AND
IR2,R1
AND
R1,IM
N
I
COM
R1
COM
IR1
TCM
r1,r2
TCM
r1,Ir2
TCM
R2,R1
TCM
IR2,R1
TCM
R1,IM
PUSH
R2
PUSH
IR2
TM
r1,r2
TM
r1,Ir2
TM
R2,R1
TM
IR2,R1
TM
R1,IM
B
B
L
E
LD
r1, x, r2
RL
R1
RL
IR1
LD
r2, x, r1
CP
r1,r2
CP
r1,Ir2
CP
R2,R1
CP
IR2,R1
CP
R1,IM
LDC
r1, Irr2, xL
CLR
R1
CLR
IR1
XOR
r1,r2
XOR
r1,Ir2
XOR
R2,R1
XOR
IR2,R1
XOR
R1,IM
LDC
r2, Irr2, xL
RRC
R1
RRC
IR1
LDC
r1,Irr2
LD
r1, Ir2
H
E
X
SRA
R1
SRA
IR1
LDC
r2,Irr1
LD
IR1,IM
LD
Ir1, r2
RR
R1
RR
IR1
LDCD
r1,Irr2
LDCI
r1,Irr2
LD
R2,R1
LD
R2,IR1
LD
R1,IM
LDC
r1, Irr2, xs
CALL
IRR1
LD
IR2,R1
CALL
DA1
LDC
r2, Irr1, xs
6-7
SAM88RI INSTRUCTION SET
S3C9234/P9234
Table 6-5. Opcode Quick Reference (Continued)
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
8
9
A
B
C
D
E
F
U
LD
r1,R2
LD
r2,R1
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
P
P
E
R
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
N
I
IDLE
STOP
DI
B
B
L
E
EI
RET
IRET
RCF
SCF
CCF
NOP
H
E
X
LD
r1,R2
LD
r2,R1
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
6-8
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
CONDITION CODES
The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a
compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
Table 6-6. Condition Codes
Binary
0000
Mnemonic
Description
Flags Set
F
T
C
Always false
Always true
Carry
–
1000
–
(1)
C = 1
0111
(1)
NC
Z
No carry
Zero
C = 0
Z = 1
Z = 0
1111
(1)
0110
(1)
NZ
Not zero
1110
1101
0101
0100
1100
PL
MI
Plus
S = 0
S = 1
V = 1
V = 0
Z = 1
Minus
OV
NOV
EQ
Overflow
No overflow
Equal
(1)
0110
(1)
NE
Not equal
Z = 0
1110
1001
0001
1010
0010
GE
LT
Greater than or equal
Less than
(S XOR V) = 0
(S XOR V) = 1
(Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1
C = 0
GT
Greater than
LE
Less than or equal
Unsigned greater than or equal
(1)
UGE
1111
(1)
ULT
Unsigned less than
C = 1
0111
1011
0011
UGT
ULE
Unsigned greater than
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
Unsigned less than or equal
NOTES:
1. Indicate condition codes that are related to two different mnemonics but which test the same flag.
For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
6-9
SAM88RI INSTRUCTION SET
S3C9234/P9234
INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction in the SAM88RCRI
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The
following information is included in each instruction description:
— Instruction name (mnemonic)
— Full instruction name
— Source/destination format of the instruction operand
— Shorthand notation of the instruction's operation
— Textual description of the instruction's effect
— Specific flag settings affected by the instruction
— Detailed description of the instruction's format, execution time, and addressing mode(s)
— Programming example(s) explaining how to use the instruction
6-10
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
ADC — Add With Carry
ADC
dst,src
Operation:
dst ¨ dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand and
the sum is stored in the destination. The contents of the source are unaffected. Two's-complement
addition is performed. In multiple precision arithmetic, this instruction permits the carry from the
addition of low-order operands to be carried into the addition of high-order operands.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
12
13
r
r
r
lr
dst
src
3
3
6
6
14
15
R
R
R
IR
dst
6
16
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H
= 0AH:
ADC
ADC
ADC
ADC
ADC
R1,R2
®
®
®
®
®
R1 = 14H, R2 = 03H
R1 = 1BH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 32H
R1,@R2
01H,02H
01H,@02H
01H,#11H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and
the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and
the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
6-11
SAM88RI INSTRUCTION SET
S3C9234/P9234
ADD — Add
ADD
dst,src
Operation:
dst ¨ dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
02
03
r
r
r
lr
dst
src
3
3
6
6
04
05
R
R
R
IR
dst
6
06
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD
ADD
ADD
ADD
ADD
R1,R2
®
®
®
®
®
R1 = 15H, R2 = 03H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
R1,@R2
01H,02H
01H,@02H
01H,#25H
In the first example, destination working register R1 contains 12H and the source working register R2
contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.
6-12
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
AND — Logical AND
AND
dst,src
Operation:
dst ¨ dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in
the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source
are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
52
53
r
r
r
lr
dst
src
3
3
6
6
54
55
R
R
R
IR
dst
6
56
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND
AND
AND
AND
AND
R1,R2
®
®
®
®
®
R1 = 02H, R2 = 03H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
R1,@R2
01H,02H
01H,@02H
01H,#25H
In the first example, destination working register R1 contains the value 12H and the source working
register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with
the destination operand value 12H, leaving the value 02H in register R1.
6-13
SAM88RI INSTRUCTION SET
S3C9234/P9234
CALL — Call Procedure
CALL
dst
Operation:
SP
@SP
SP
@SP
PC
¨
¨
¨
¨
¨
SP – 1
PCL
SP –1
PCH
dst
The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The specified
destination address is then loaded into the program counter and points to the first instruction of a
procedure. At the end of the procedure the return instruction (RET) can be used to return to the
original program flow. RET pops the top of the stack back into the program counter.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
opc
dst
3
14
F6
DA
dst
2
12
F4
IRR
Examples:
Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H:
CALL
1521H
®
SP = 0B0H
(Memory locations 00H = 1AH, 01H = 4AH, where 4AH
is the address that follows the instruction.)
SP = 0B0H (00H = 1AH, 01H = 49H)
CALL
@RR0
®
In the first example, if the program counter value is 1A47H and the stack pointer contains the value
0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The
stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the
address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack location
01H (because the two-byte instruction format was used). The PC is then loaded with the value
1521H, the address of the first instruction in the program sequence to be executed.
6-14
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
CCF — Complement Carry Flag
CCF
Operation:
C ¨ NOT C
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if
C = "0", the value of the carry flag is changed to logic one.
Flags:
C: Complemented.
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
EF
Example:
Given: The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing
its value from logic zero to logic one.
6-15
SAM88RI INSTRUCTION SET
S3C9234/P9234
CLR — Clear
CLR
dst
Operation:
dst ¨ "0"
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
B0
B1
R
IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
CLR
00H
@01H
®
®
Register 00H = 00H
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value
to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing
mode to clear the 02H register value to 00H.
6-16
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
COM — Complement
COM
dst
Operation:
dst ¨ NOT dst
The contents of the destination location are complemented (one's complement); all "1s" are changed
to "0s", and vice-versa.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
60
61
R
IR
Examples:
Given: R1 = 07H and register 07H = 0F1H:
COM
COM
R1
@R1
®
®
R1 = 0F8H
R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and
vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value of
destination register 07H (11110001B), leaving the new value 0EH (00001110B).
6-17
SAM88RI INSTRUCTION SET
S3C9234/P9234
CP — Compare
CP
dst,src
Operation:
dst – src
The source operand is compared to (subtracted from) the destination operand, and the appropriate
flags are set accordingly. The contents of both operands are unaffected by the comparison.
Flags:
C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
A2
A3
r
r
r
lr
dst
src
3
3
6
6
A4
A5
R
R
R
IR
dst
6
A6
R
IM
Examples:
1. Given: R1 = 02H and R2 = 03H:
CP R1,R2
®
Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value
03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value
(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".
2. Given: R1 = 05H and R2 = 0AH:
CP
JP
INC
LD
R1,R2
UGE,SKIP
R1
SKIP
R3,R1
In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and
the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes,
the value 06H remains in working register R3.
6-18
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
DEC — Decrement
DEC
dst
Operation:
dst ¨ dst – 1
The contents of the destination operand are decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, dst value is –128(80H) and result value is
+127(7FH); cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
00
01
R
IR
Examples:
Given: R1 = 03H and register 03H = 10H:
DEC
DEC
R1
@R1
®
®
R1 = 02H
Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one,
leaving the value 0FH.
6-19
SAM88RI INSTRUCTION SET
S3C9234/P9234
DI — Disable Interrupts
DI
Operation:
SYM (2) ¨ 0
Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt
processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU
will not service them while interrupt processing is disabled.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
8F
Example:
Given: SYM = 04H:
DI
If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register
and clears SYM.2 to "0", disabling interrupt processing.
6-20
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
EI — Enable Interrupts
EI
Operation:
SYM (2) ¨ 1
An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be
serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled
(by executing a DI instruction), it will be serviced when you execute the EI instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
9F
Example:
Given: SYM = 00H:
EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement
"EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt
processing).
6-21
SAM88RI INSTRUCTION SET
S3C9234/P9234
IDLE — Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
6F
–
–
Example:
The instruction
IDLE
stops the CPU clock but not the system clock.
6-22
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
INC — Increment
INC
dst
Operation:
dst ¨ dst + 1
The contents of the destination operand are incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is –128(80H);
cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
dst | opc
1
4
rE
r
r = 0 to F
opc
dst
2
4
4
20
21
R
IR
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC
INC
INC
R0
00H
@R0
®
®
®
R0 = 1CH
Register 00H = 0DH
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC
R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it contains
the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of
register 1BH from 0FH to 10H.
6-23
SAM88RI INSTRUCTION SET
S3C9234/P9234
IRET — Interrupt Return
IRET
IRET
Operation:
FLAGS ¨ @SP
SP ¨ SP + 1
PC ¨ @SP
SP ¨ SP + 2
SYM(2) ¨ 1
This instruction is used at the end of an interrupt service routine. It restores the flag register and the
program counter. It also re-enables global interrupts.
Flags:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
IRET
(Normal)
Bytes
Cycles
Opcode
(Hex)
opc
1
6
BF
6-24
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
JP — Jump
JP
cc,dst
dst
(Conditional)
JP
(Unconditional)
Operation:
If cc is true, PC ¨ dst
The conditional JUMP instruction transfers program control to the destination address if the condition
specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is
executed. The unconditional JP simply replaces the contents of the PC with the contents of the
specified register pair. Control then passes to the statement addressed by the PC.
Flags:
No flags are affected.
(1)
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(2)
(3)
8
cc | opc
dst
3
ccD
DA
cc = 0 to F
opc
dst
2
8
30
IRR
NOTES:
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four
bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
JP
C,LABEL_W
@00H
®
®
LABEL_W = 1000H, PC = 1000H
PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that
location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents of
the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6-25
SAM88RI INSTRUCTION SET
S3C9234/P9234
JR — Jump Relative
JR
cc,dst
Operation:
If cc is true, PC ¨ PC + dst
If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program counter;
otherwise, the instruction following the JR instruction is executed (See list of condition codes).
The range of the relative address is +127, –128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(1)
(2)
6
cc | opc
dst
2
ccB
RA
cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four
bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H:
JR C,LABEL_X PC = 1FF7H
®
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass
control to the statement whose address is now in the PC. Otherwise, the program instruction
following the JR would be executed.
6-26
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
LD — Load
LD
dst,src
dst ¨ src
Operation:
The contents of the source are loaded into the destination. The source's contents are unaffected.
No flags are affected.
Flags:
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
IM
R
dst | opc
src | opc
opc
src
dst
2
4
4
rC
r8
r
r
2
2
3
3
4
r9
R
r
r = 0 to F
dst | src
4
4
C7
D7
r
lr
r
Ir
opc
src
dst
src
6
6
E4
E5
R
R
R
IR
opc
dst
6
6
E6
D6
R
IM
IM
IR
opc
opc
opc
src
dst
x
3
3
3
6
6
6
F5
87
97
IR
r
R
x [r]
r
dst | src
src | dst
x
x [r]
6-27
SAM88RI INSTRUCTION SET
S3C9234/P9234
LD — Load
LD
(Continued)
Examples:
Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
R0,#10H
R0,01H
01H,R0
R1,@R0
@R0,R1
00H,01H
02H,@00H
00H,#0AH
@00H,#10H
@00H,02H
®
®
®
®
®
®
®
®
®
®
R0 = 10H
R0 = 20H, register 01H = 20H
Register 01H = 01H, R0 = 01H
R1 = 20H, R0 = 01H
R0 = 01H, R1 = 0AH, register 01H = 0AH
Register 00H = 20H, register 01H = 20H
Register 02H = 20H, register 00H = 01H
Register 00H = 0AH
Register 00H = 01H, register 01H = 10H
Register 00H = 01H, register 01H = 02, register 02H = 02H
R0 = 0FFH, R1 = 0AH
R0,#LOOP[R1]®
#LOOP[R0],R1®
Register 31H = 0AH, R0 = 01H, R1 = 0AH
6-28
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
LDC/LDE — Load Memory
LDC/LDE
dst,src
Operation:
dst ¨ src
This instruction loads a byte from program or data memory into a working register or vice-versa. The
source values are unaffected. LDC refers to program memory and LDE to data memory. The
assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data
memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
1.
2.
3.
4.
5.
opc
opc
opc
opc
opc
dst | src
src | dst
dst | src
src | dst
dst | src
2
10
C3
D3
E7
F7
A7
r
Irr
2
3
3
4
10
12
12
14
Irr
r
XS
XS
r
XS [rr]
r
XS [rr]
r
XL
XL
XL [rr]
L
H
6.
7.
opc
opc
opc
opc
opc
src | dst
dst | 0000
src | 0000
dst | 0001
src | 0001
XL
XL
4
4
4
4
4
14
14
14
14
14
B7
A7
B7
A7
B7
XL [rr]
r
DA
r
L
H
DA
DA
DA
DA
DA
DA
DA
DA
r
L
L
L
L
H
H
H
H
8.
DA
r
9.
DA
r
10.
DA
NOTES:
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte.
3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes.
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used
in formats 9 and 10, are used to address data memory.
6-29
SAM88RI INSTRUCTION SET
S3C9234/P9234
LDC/LDE — Load Memory
LDC/LDE
(Continued)
Examples:
Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations
0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory
locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and
1104H = 98H:
LDC
R0,@RR2
R0,@RR2
@RR2,R0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
R0 ¨ contents of program memory location 0104H
R0 = 1AH, R2 = 01H, R3 = 04H
R0 ¨ contents of external data memory location 0104H
R0 = 2AH, R2 = 01H, R3 = 04H
11H (contents of R0) is loaded into program memory
location 0104H (RR2),
working registers R0, R2, R3 Æ no change
11H (contents of R0) is loaded into external data memory
location 0104H (RR2),
working registers R0, R2, R3 Æ no change
R0 ¨ contents of program memory location 0061H
(01H + RR4),
R0 = AAH, R2 = 00H, R3 = 60H
R0 ¨ contents of external data memory location 0061H
(01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H
LDE
LDC *
LDE
LDC
LDE
@RR2,R0
R0,#01H[RR4]
R0,#01H[RR4]
(note)
LDC
LDE
LDC
LDE
LDC
LDE
#01H[RR4],R0
#01H[RR4],R0
R0,#1000H[RR2]
R0,#1000H[RR2]
R0,1104H
;
;
;
;
;
;
;
;
;
;
;
;
11H (contents of R0) is loaded into program memory
location 0061H (01H + 0060H)
11H (contents of R0) is loaded into external data memory
location 0061H (01H + 0060H)
R0 ¨ contents of program memory location 1104H
(1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
R0 ¨ contents of external data memory location 1104H
(1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
R0 ¨ contents of program memory location 1104H,
R0 = 88H
R0,1104H
R0 ¨ contents of external data memory location 1104H,
R0 = 98H
(note)
LDC
LDE
1105H,R0
;
;
;
11H (contents of R0) is loaded into program memory
location 1105H, (1105H) ¨ 11H
11H (contents of R0) is loaded into external data memory
1105H,R0
;
location 1105H, (1105H) ¨ 11H
NOTE: These instructions are not supported by masked ROM type devices.
6-30
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
LDCD/LDED — Load Memory and Decrement
LDCD/LDED
Operation:
dst,src
dst ¨ src
rr ¨ rr – 1
These instructions are used for user stacks or block transfers of data from program or data memory
to the register file. The address of the memory location is specified by a working register pair. The
contents of the source location are loaded into the destination location. The memory address is then
decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes ‘Irr’ an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E2
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:
LDCD
R8,@RR6
;
;
;
;
;
;
0CDH (contents of program memory location 1033H) is
loaded into R8 and RR6 is decremented by one
R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ¬ RR6 - 1)
0DDH (contents of data memory location 1033H) is
loaded into R8 and RR6 is decremented by one
(RR6 ¬ RR6 - 1) R8 = 0DDH, R6 = 10H, R7 = 32H
LDED
R8,@RR6
6-31
SAM88RI INSTRUCTION SET
S3C9234/P9234
LDCI/LDEI — Load Memory and Increment
LDCI/LDEI
Operation:
dst,src
dst ¨ src
rr ¨ rr + 1
These instructions are used for user stacks or block transfers of data from program or data memory
to the register file. The address of the memory location is specified by a working register pair. The
contents of the source location are loaded into the destination location. The memory address is then
incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr'
even for program memory and odd for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E3
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI
R8,@RR6
;
;
;
;
;
;
0CDH (contents of program memory location 1033H) is
loaded into R8 and RR6 is incremented by one
(RR6 ¨ RR6 + 1) R8 = 0CDH, R6 = 10H, R7 = 34H
0DDH (contents of data memory location 1033H) is
loaded into R8 and RR6 is incremented by one
(RR6 ¨ RR6 + 1) R8 = 0DDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
6-32
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
NOP — No Operation
NOP
Operation:
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
FF
Example:
When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution
time.
6-33
SAM88RI INSTRUCTION SET
S3C9234/P9234
OR — Logical OR
OR
dst,src
Operation:
dst ¨ dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
42
43
r
r
r
lr
dst
src
3
3
6
6
44
45
R
R
R
IR
dst
6
46
R
IM
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H
= 8AH:
OR
OR
OR
OR
OR
R0,R1
®
®
®
®
®
R0 = 3FH, R1 = 2AH
R0,@R2
00H,01H
01H,@00H
00H,#02H
R0 = 37H, R2 = 01H, register 01H = 37H
Register 00H = 3FH, register 01H = 37H
Register 00H = 08H, register 01H = 0BFH
Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the
statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in
destination register R0.
The other examples show the use of the logical OR instruction with the various addressing modes
and formats.
6-34
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
POP — Pop From Stack
POP
dst
Operation:
dst ¨ @SP
SP ¨ SP + 1
The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags:
No flags affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
50
51
R
IR
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register
0BBH = 55H:
POP
POP
00H
@00H
®
®
Register 00H = 55H, SP = 0BCH
Register 00H = 01H, register 01H = 55H, SP = 0BCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads
the contents of location 0BBH (55H) into destination register 00H and then increments the stack
pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.
6-35
SAM88RI INSTRUCTION SET
S3C9234/P9234
PUSH — Push To Stack
PUSH
src
Operation:
SP ¨ SP – 1
@SP ¨ src
A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)
into the location addressed by the decremented stack pointer. The operation then adds the new
value to the top of the stack.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
src
2
8
8
70
71
R
IR
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H:
PUSH
PUSH
40H
®
®
Register 40H = 4FH, stack register 0BFH = 4FH,
SP = 0BFH
Register 40H = 4FH, register 4FH = 0AAH, stack register
0BFH = 0AAH, SP = 0BFH
@40H
In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value
4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the
contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP
points to location 0BFH.
6-36
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
RCF — Reset Carry Flag
RCF
RCF
Operation:
C ¨ 0
The carry flag is cleared to logic zero, regardless of its previous value.
Flags:
C: Cleared to "0".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
CF
Example:
Given: C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
6-37
SAM88RI INSTRUCTION SET
S3C9234/P9234
RET — Return
RET
Operation:
PC ¨ @SP
SP ¨ SP + 2
The RET instruction is normally used to return to the previously executing procedure at the end of a
procedure entered by a CALL instruction. The contents of the location addressed by the stack
pointer are popped into the program counter. The next statement that is executed is the one that is
addressed by the new program counter value.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
8
AF
Example:
Given: SP = 0BCH, (SP) = 101AH, and PC = 1234:
RET PC = 101AH, SP = 0BEH
®
The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of
the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low
byte and the instruction at location 101AH is executed. The stack pointer now points to memory
location 0BEH.
6-38
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
RL — Rotate Left
RL
dst
Operation:
C ¨ dst (7)
dst (0) ¨ dst (7)
dst (n + 1) ¨ dst (n), n = 0–6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is
moved to the bit zero (LSB) position and also replaces the carry flag.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
90
91
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL
RL
00H
@01H
®
®
Register 00H = 55H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL
00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting
the carry and overflow flags.
6-39
SAM88RI INSTRUCTION SET
S3C9234/P9234
RLC — Rotate Left Through Carry
RLC
dst
Operation:
dst (0) ¨ C
C ¨ dst (7)
dst (n + 1) ¨ dst (n), n = 0–6
The contents of the destination operand with the carry flag are rotated left one bit position. The initial
value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
10
11
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC
RLC
00H
@01H
®
®
Register 00H = 54H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC
00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the
initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The
MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6-40
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
RR — Rotate Right
RR
dst
Operation:
C ¨ dst (0)
dst (7) ¨ dst (0)
dst (n) ¨ dst (n + 1), n = 0–6
The contents of the destination operand are rotated right one bit position. The initial value of bit zero
(LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
E0
E1
R
IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR
RR
00H
@01H
®
®
Register 00H = 98H, C = "1"
Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR
00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7,
leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the
C flag to "1" and the sign flag and overflow flag are also set to "1".
6-41
SAM88RI INSTRUCTION SET
S3C9234/P9234
RRC — Rotate Right Through Carry
RRC
dst
Operation:
dst (7) ¨ C
C ¨ dst (0)
dst (n) ¨ dst (n + 1), n = 0–6
The contents of the destination operand and the carry flag are rotated right one bit position. The initial
value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
C0
C1
R
IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC
RRC
00H
@01H
®
®
Register 00H = 2AH, C = "1"
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC
00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry
flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B)
in destination register 00H. The sign flag and overflow flag are both cleared to "0".
6-42
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
SBC — Subtract With Carry
SBC
dst,src
Operation:
dst ¨ dst – src – c
The source operand, along with the current value of the carry flag, is subtracted from the destination
operand and the result is stored in the destination. The contents of the source are unaffected.
Subtraction is performed by adding the two's-complement of the source operand to the destination
operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the
subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.
Flags:
C: Set if a borrow occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
f the result is the same as the sign of the source; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise, indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
32
33
r
r
r
lr
dst
src
3
3
6
6
34
35
R
R
R
IR
dst
6
36
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register
03H = 0AH:
SBC
SBC
SBC
SBC
SBC
R1,R2
®
®
®
®
®
R1 = 0CH, R2 = 03H
R1 = 05H, R2 = 03H, register 03H = 0AH
Register 01H = 1CH, register 02H = 03H
Register 01H = 15H,register 02H = 03H, register 03H = 0AH
Register 01H = 95H; C, S, and V = "1"
R1,@R2
01H,02H
01H,@02H
01H,#8AH
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the
statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.
6-43
SAM88RI INSTRUCTION SET
S3C9234/P9234
SCF — Set Carry Flag
SCF
Operation:
Flags:
C ¨ 1
The carry flag (C) is set to logic one, regardless of its previous value.
C: Set to "1".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
DF
Example:
The statement
SCF
sets the carry flag to logic one.
6-44
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
SRA — Shift Right Arithmetic
SRA
dst
Operation:
dst (7) ¨ dst (7)
C ¨ dst (0)
dst (n) ¨ dst (n + 1), n = 0–6
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
7
6
0
C
Flags:
C: Set if the bit shifted from the LSB position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
D0
D1
R
IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA
SRA
00H
@02H
®
®
Register 00H = 0CD, C = "0"
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA
00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit
7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH
(11001101B) in destination register 00H.
6-45
SAM88RI INSTRUCTION SET
S3C9234/P9234
STOP — Stop Operation
STOP
Operation:
The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to
enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and
I/O port control and data registers are retained. Stop mode can be released by an external reset
operation or External interrupt input. For the reset operation, the RESET pin must be held to Low
level until the required oscillation stabilization interval has elapsed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
7F
–
–
Example:
The statement
STOP
halts all microcontroller operations.
6-46
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
SUB — Subtract
SUB
dst,src
Operation:
dst ¨ dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the two's
complement of the source operand to the destination operand.
Flags:
C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign
of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
22
23
r
r
r
lr
dst
src
3
3
6
6
24
25
R
R
R
IR
dst
6
26
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB
SUB
SUB
SUB
SUB
SUB
R1,R2
®
®
®
®
®
®
R1 = 0FH, R2 = 03H
R1 = 08H, R2 = 03H
Register 01H = 1EH, register 02H = 03H
Register 01H = 17H, register 02H = 03H
Register 01H = 91H; C, S, and V = "1"
Register 01H = 0BCH; C and S = "1", V = "0"
R1,@R2
01H,02H
01H,@02H
01H,#90H
01H,#65H
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value
(12H) and stores the result (0FH) in destination register R1.
6-47
SAM88RI INSTRUCTION SET
S3C9234/P9234
TCM — Test Complement Under Mask
TCM
dst,src
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
The TCM statement complements the destination operand, which is then ANDed with the source
mask. The zero (Z) flag can then be checked to determine the result. The destination and source
operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
62
63
r
r
r
lr
dst
src
3
3
6
6
64
65
R
R
R
IR
dst
6
66
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H
= 23H:
TCM
TCM
TCM
TCM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "1"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
TCM
00H,#34
®
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the
value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1"
value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be
tested to determine the result of the TCM operation.
6-48
S3C9234/P9234
SAM88RCRI INSTRUCTION SET
TM — Test Under Mask
TM
dst,src
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask),
which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the
result. The destination and source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
72
73
r
r
r
lr
dst
src
3
3
6
6
74
75
R
R
R
IR
dst
6
76
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H
= 23H:
TM
TM
TM
TM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "0"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
TM
00H,#54H
®
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the
value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0"
value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and
can be tested to determine the result of the TM operation.
6-49
SAM88RI INSTRUCTION SET
S3C9234/P9234
XOR— Logical Exclusive OR
XOR
dst,src
Operation:
dst ¨ dst XOR src
The source operand is logically exclusive-ORed with the destination operand and the result is stored
in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the
corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
B2
B3
r
r
r
lr
dst
src
3
3
6
6
B4
B5
R
R
R
IR
dst
6
B6
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H
= 23H:
XOR
XOR
XOR
XOR
R0,R1
®
®
®
®
R0 = 0C5H, R1 = 02H
R0,@R1
00H,01H
00H,@01H
R0 = 0E4H, R1 = 02H, register 02H = 23H
Register 00H = 29H, register 01H = 02H
Register 00H = 08H, register 01H = 02H,
register 02H = 23H
XOR
00H,#54H
®
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the
value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and
stores the result (0C5H) in the destination register R0.
6-50
S3C9234/P9234
CLOCK CIRCUITS
7
CLOCK CIRCUITS
OVERVIEW
The S3C9234/P9234 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and
peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU
clock frequency, is determined by CLKCON register settings.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
— Crystal, ceramic resonator, RC oscillation source (main clock only), or an external clock
— Oscillator stop and wake-up functions
— Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)
— Clock circuit control register, CLKCON
— Oscillator control register, OSCCON
— Clock output control register, CLOCON
CPU CLOCK NOTATION
In this document, the following notation is used for descriptions of the CPU clock:
fx main clock
fxt sub clock
fxx selected system clock
7-1
CLOCK CIRCUITS
S3C9234/P9234
MAIN OSCILLATOR CIRCUITS
SUB OSCILLATOR CIRCUITS
XIN
XTIN
XOUT
XTOUT
32.768 kHz
Figure 7-4. Crystal/Ceramic Oscillator (fxt)
Figure 7-1. Crystal/Ceramic Oscillator (fx)
XTIN
XTOUT
X
IN
XOUT
Figure 7-5. External Oscillator (fxt)
Figure 7-2. External Oscillator (fx)
XIN
R
XOUT
Figure 7-3. RC Oscillator (fx)
7-2
S3C9234/P9234
CLOCK CIRCUITS
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset
operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When
the fx is selected as system clock).
— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt
structure, timer A/B, and watch timer. Idle mode is released by a reset or by an external or
internal interrupts.
Stop Release
INT
Main-System
Oscillator
Circuit
Sub-system
Oscillator
Circuit
Watch Timer
fX
fXT
LCD Controller
Selector 1
fXX
Stop
OSCCON.3
OSCCON.0
Stop
OSCCON.2
1/1-1/4096
STOP OSC
inst.
Basic Timer
Timer/Counters
Frequency
Dividing
Circuit
Watch Timer
LCD Controller
SIO
STPCON
1/1 1/2 1/8 1/16
CLKCON.4-.3
Selector 2
CPU
Figure 7-6. System Clock Circuit Diagram
7-3
CLOCK CIRCUITS
S3C9234/P9234
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the
following functions:
— Oscillator IRQ wake-up function enable/disable
— Oscillator frequency divide-by value
CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ "wake-up" enable bit is CLKCON.7.
After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock
speed to fx, fx/2, or fx/8 by setting the CLKCON, and you can change system clock from main clock to sub clock
by setting the OSCCON.
System Clock Control Register (CLKCON)
D4H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main oscillator
wake-up function in power down
mode
1 = Disable IRQ for main oscillator
wake-up function in power down
mode
Not used for S3C9234/P9234 (must keep always "0")
Divide-by selection bits for
CPU clock frequency:
00 = fxx/16
01 = fxx/8
10 = fXx/2
11 = fxx
Not used for S3C9234/P9234 (must keep always "0")
Figure 7-7. System Clock Control Register (CLKCON)
7-4
S3C9234/P9234
CLOCK CIRCUITS
CLOCK OUTPUT CONTROL REGISTER (CLOCON)
The clock output control register, CLOCON, is located in address FEH. It is read/write addressable and has the
following functions;
— Clock Output Frequency Selection
After a reset, fxx/64 is select for Clock Output Frequency because the reset value of CLOCON.1-.0 is "0".
Clock Output Control Register (CLOCON)
FEH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Clock Output Frequency Selection Bits:
00 = Select fxx/64
01 = Select fxx/16
Not used for S3C9234/P9234.
(Must keep always "0")
10 = Select fxx/8
11 = Select fxx/4
Figure 7-8. Clock Output Control Register (CLOCON)
CLOCON.1-.0
P1CONH.5-.4
fxx/64
fxx/16
fxx/8
MUX
CLKOUT
fxx/4
Figure 7-9. Clock Output Block Diagram
7-5
CLOCK CIRCUITS
S3C9234/P9234
OSCILLATOR CONTROL REGISTER (OSCCON)
The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the
following functions:
— System clock selection
— Main oscillator control
— Sub oscillator control
OSCCON.0 register settings select Main clock or Sub clock as system clock.
After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0".
The main oscillator can be stopped or run by setting OSCCON.3.
The sub oscillator can be stopped or run by setting OSCCON.2.
Oscillator Control Register (OSCCON)
D3H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
System clock selection bit:
0 = Main oscillator select
1 = Sub oscillator select
Not used for S3C9234/P9234
Not used for S3C9234/P9234
Sub oscillator control bit:
0 = Sub oscillator RUN
1 = Sub oscillator STOP
Main oscillator control bit:
0 = Main oscillator RUN
1 = Main oscillator STOP
Figure 7-10. Oscillator Control Register (OSCCON)
7-6
S3C9234/P9234
CLOCK CIRCUITS
SWITCHING THE CPU CLOCK
Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as
the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch
dynamically between main and sub clocks and to modify operating frequencies.
OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the system clock. OSCCON .3 start or stop main
clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4–.3 control the frequency divider
circuit, and divide the selected fxx clock by 1, 2, 8, or 16.
For example, you are using the default system clock (normal operating mode and a main clock of fx/16) and you
want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set OSCCON.0
to "1", take a delay, and OSCCON.3 to "1" sequently. This switches the clock from fx to fxt and stops main clock
oscillation.
The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to
enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main
clock by setting OSCCON.0 to "0".
F
PROGRAMMING TIP — Switching the CPU clock
1. This example shows how to change from the main clock to the sub clock:
MA2SUB OR
CALL
OSCCON,#01H
DLY16
OSCCON,#08H
;
;
;
Switches to the sub clock
Delay 16ms
Stop the main clock oscillation
OR
RET
2. This example shows how to change from sub clock to main clock:
SUB2MA AND
OSCCON,#0F7H
DLY16
OSCCON,#0FEH
;
;
;
Start the main clock oscillation
Delay 16 ms
Switch to the main clock
CALL
AND
RET
DLY16
DEL
LD
R0,#20H
NOP
DEC
JR
R0
NZ,DEL
RET
7-7
CLOCK CIRCUITS
S3C9234/P9234
STOP CONTROL REGISTER (STPCON)
The STOP control register, STPCON, is located in address D6H. It is read/write addressable and has the following
functions:
— Enable/Disable STOP instruction
After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".
If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B".
Stop Control Register (STPCON)
D6H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
STOP control bits:
10100101 = Enable STOP instruction
Other values = Disable STOP instruction
Figure 7-11. STOP Control Register (STPCON)
F
PROGRAMMING TIP — How to Use Stop Instruction
This example shows how to go STOP mode when a main clock is selected as the system clock.
LD
STOPCON,#1010010B
STOPCON,#00000000B
;
;
Enable STOP instruction
Enter STOP mode
STOP
NOP
NOP
NOP
LD
;
;
Release STOP mode
Disable STOP instruction
7-8
S3C9234/P9234
RES ET and POWER-DOWN
8
RES ET and POWER-DOWN
SYSTEM RESET
OVERVIEW
During a power-on reset, the voltage at V goes to High level and the RESET pin is forced to Low level. The RESET
DD
signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure
brings S3C9234/P9234 into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum
time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a
reset operation is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both V and RESET are High level), the RESET
DD
pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their
default hardware values (see Table 8-1).
In summary, the following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watchdog function (basic timer) is enabled.
— Ports 0-6 are set to schmitt trigger input mode and all pull-up resistors are disabled for the I/O port pin circuits.
— Peripheral control and data registers are disabled and reset to their default hardware values.
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location
0100H (and 0101H) is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing '1010B' to the upper nibble of BTCON.
8-1
RES ET and POWER-DOWN
S3C9234/P9234
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted.
All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But
the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch timer clock
source. The data stored in the internal register file are retained in stop mode. Stop mode can be released in one of
three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of
watch timer), or by an external interrupt.
Example:
LD
STOPCON,#10100101B
STOP
NOP
NOP
NOP
LD
STOPCON,#00000000B
NOTES
1. Do not use stop mode if you are using an external clock source because X input must be restricted
IN
internally to V to reduce current leakage.
SS
2. In application programs, a STOP instruction must be immediately followed by at least three NOP
instructions. This ensures an adequate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructions are not used after STOP instruction,
leakage current could be flown because of the floating state in the internal bus.
3. To enable/disable STOP instruction, the STOPCON register should be written with
10100101B/other values before/after stop instruction.
Using RESET to Release Stop Mode
Stop mode is released when the RESET signal goes active (Low level): all system and peripheral control registers
are reset to their default hardware values and the contents of all data registers are retained. When the programmed
oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program
instruction stored in ROM location 0100H.
Using an External Interrupt to Release Stop Mode
External interrupts can be used to release stop mode. For the S3C9234 microcontroller, we recommend using the
INT interrupt, P1 and P2.
8-2
S3C9234/P9234
RES ET and POWER-DOWN
Using an Internal Interrupt to Release Stop Mode
An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode
if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release
stop mode. That is, you had better use the idle instruction instead of stop one when sub clock is selected as the
system clock.
Please note the following conditions for Stop mode release:
— If you release stop mode using an internal or external interrupt, the current values in system and peripheral
control registers are unchanged.
— If you use an internal or external interrupt for stop mode release, you can also program the duration of the
oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before
entering stop mode.
— If you use an interrupt to release stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains unchanged
and the currently selected clock value is used.
— The internal or external interrupt is serviced when the stop mode release occurs. Following the IRET from the
service routine, the instruction immediately following the one that initiated stop mode is executed.
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some
peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but
the following peripherals, which remain active:
— Interrupt logic
— Basic timer
— Timer 1 (Timer A and B)
— Watch timer
— LCD controller
I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.
Idle Mode Release
You can release Idle mode in one of two ways:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of
all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the hardware
reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the only
way you can release Idle mode.
2. Activate any enabled interrupt — internal or external. When you use an interrupt to release Idle mode,
the 2-bit CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is
used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the
instruction immediately following the one which initiated Idle mode is executed.
8-3
RES ET and POWER-DOWN
S3C9234/P9234
HARDWARE RES ET VALUES
Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers
following a RESET operation in normal operating mode. The following notation is used in these table to represent
specific RESET values:
— A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively.
— An 'x' means that the bit value is undefined following RESET.
— A dash ('–') means that the bit is either not used or not mapped.
Table 8-1. Register Values after RES ET
Register Name
Mnemonic
Address
Bit Values after RES ET
Dec Hex
208 D0H
209 D1H
210 D2H
211 D3H
212 D4H
213 D5H
214 D6H
215 D7H
216 D8H
217 D9H
218 DAH
7
0
0
0
–
0
x
0
0
0
x
0
6
0
0
0
–
0
x
0
0
0
x
0
5
0
0
0
–
0
x
0
0
0
x
0
4
0
0
0
–
0
x
0
0
0
x
0
3
0
0
0
0
0
–
0
0
–
x
2
0
0
0
0
0
–
0
0
0
x
1
0
0
0
–
0
–
0
–
0
x
0
0
0
0
0
0
–
0
0
0
x
SIO Control Register
SIOCON
SIODATA
SIOPS
SIO Data Register
SIO Prescaler Register
Oscillator Control Register
System Clock Control Register
System Flags Register
Stop Control Register
LCD Control Register
OSCCON
CLKCON
FLAGS
STPCON
LCON
Interrupt Pending Register
Stack Pointer
INTPND
SP
Watch Timer Control Register
WTCON
0
0
0
0
Locations DBH is not mapped.
Basic Timer Control Register
Basic Timer Counter
BTCON
BTCNT
220 DCH
221 DDH
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
Locations DEH is not mapped.
System Mode Register
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
SYM
P0
P1
P2
P3
P4
P5
P6
223 DFH
224 E0H
225 E1H
226 E2H
227 E3H
228 E4H
229 E5H
230 E6H
x
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8-4
S3C9234/P9234
RES ET and POWER-DOWN
Table 8-1. Register Values after RES ET (Continued)
Register Name
Mnemonic
Address
Bit Values after RES ET
Dec Hex
231 E7H
232 E8H
233 E9H
234 EAH
235 EBH
236 ECH
237 EDH
238 EEH
239 EFH
240 F0H
241 F1H
242 F2H
243 F3H
244 F4H
245 F5H
246 F6H
247 F7H
248 F8H
249 F9H
250 FAH
251 FBH
252 FCH
253 FDH
254 FEH
7
0
0
1
1
0
–
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
–
6
0
0
1
1
0
0
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
–
5
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
4
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
2
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer A Counter
TACNT
TBCNT
Timer B Counter
Timer A Data Register
TADATA
TBDATA
TACON
TBCON
P0CON
P1CONH
P1CONL
P1PUR
Timer B Data Register
Timer 1/A Control Register
Timer B Control Register
Port 0 Control Register
Port 1 Control Register(High Byte)
Port 1 Control Register(Low Byte)
Port 1 Pull-up Resistor Enable Register
Port 1 Interrupt Control Register
Port 2 Control Register(High Byte)
Port 2 Control Register(Low Byte)
Port 2 Pull-up Resistor Enable Register
Port 2 Interrupt Control Register
Port 3 Control Register(High Byte)
Port 3 Control Register(Low Byte)
Port 3 Pull-up Resistor Enable Register
Port 4 Control Register(High Byte)
Port 4 Control Register(Low Byte)
Port 5 Control Register(High Byte)
Port 5 Control Register(Low Byte)
Port 6 Control Register
P1INT
P2CONH
P2CONL
P2PUR
P2INT
P3CONH
P3CONL
P3PUR
P4CONH
P4CONL
P5CONH
P5CONL
P6CON
CLOCON
Clock Output Control Register
Location FFH is not mapped.
8-5
RES ET and POWER-DOWN
S3C9234/P9234
NOTES
8-6
S3C9234/P9234
I/O PORTS
9
I/O PORTS
OVERVIEW
The S3C9234/P9234 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 4-bit, port 1-port 6 are 8-
bit ports. This gives a total of 52 I/O pins. Each port can be flexibly configured to meet application design
requirements.
The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All
ports of the S3C9234/P9234 can be configured to input or output mode. P0 and P3-P6 are shared with LCD signals.
Table 9-1 gives you a general overview of S3C9234/P9234 I/O port functions.
Table 9-1. S3C9234/P9234 Port Configuration Overview
Port
Configuration Options
0
1-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
P0.0-P0.3 can alternately used as outputs for LCD common signals.
1
2
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
Alternatively P1.0-P1.2 can be used as input for external interrupts INT and P1.3-P1.7 can be
used as T1CLK, TAOUT, TBOUT, CLKOUT, BUZ.
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups.
Alternatively P2.4-P2.7 can be used as input for external interrupts INT and P2.0-P2.2 can be
used as SCK, SO, and SI.
3
4
5
6
1-bit programmable I/O port.
Input or push-pull, open-drain output and software assignable pull-ups.
Alternatively P3 can be used as outputs for LCD segment signals.
1-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
Alternatively P4 can be used as outputs for LCD segment signals.
1-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
Alternatively P5 can be used as outputs for LCD segment signals.
2-bit programmable I/O port.
Input or push-pull output and software assignable pull-ups.
Alternatively P6 can be used as outputs for LCD segment signals.
9-1
I/O PORTS
S3C9234/P9234
PORT DATA REGISTERS
Table 9-2 gives you an overview of the register locations of all seven S3C9234/P9234 I/O port data registers. Data
registers for ports 0, 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1.
Table 9-2. Port Data Register Summary
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Mnemonic
Decimal
224
Hex
E0H
E1H
E2H
E3H
E4H
E5H
E6H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0
P1
P2
P3
P4
P5
P6
225
226
227
228
229
230
S3C9234/P9234 I/O Port Data Register Format (n = 0-6)
.7 .6 .5 .4 .3 .2 .1 .0
MSB
LSB
Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0
Figure 9-1. S3C9234/P9234 I/O Port Data Register Format
9-2
S3C9234/P9234
PORT 0
I/O PORTS
Port 0 is an 4-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading
the port 0 data register, P0 at location E0H in page 0. P0.0-P0.3 can serve as inputs (with or without pull-up), as
push-pull output. You can be configured the following alternative functions.
— Low-nibble pins (P0.0-P0.3): COM0-COM3
Port 0 Control register (P0CON)
Port 0 has a 8-bit control register: P0CON for P0.0-P0.3. A reset clears the P0CON register to "00H", configuring
pins to input mode. You use control register setting to select input (with or without pull-up) or push-pull output mode
and enable the alternative functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 0 control register must also be enabled in the associated peripheral module.
Port 0 Control Register (P0CON)
EDH, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0.3/COM3 P0.2/COM2 P0.1/COM1 P0.0/COM0
P0CON bit-pair pin configuration settings:
00
01
10
11
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (CPM3-COM0)
Figure 9-2. Port 0 Control Register (P0CON)
9-3
I/O PORTS
PORT 1
S3C9234/P9234
Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading
the port 1 data register, P1 at location E1H in page 0. P1.0-P1.7 can serve as inputs (with or without pull-up), as
outputs (push-pull or open-drain) or you can be configured the following functions.
— Low-nibble pins (P1.0-P1.3): INT, T1CLK
— High-nibble pins (P1.4-P1.7): TAOUT, TBOUT, CLKOUT, BUZ
Port 1 Control Register (P1CONH, P1CONL)
Port 1 has two 8-bit control register: P1CONH for P1.4-P1.7 and P1CONL for P1.0-P1.3. A reset clears the P1CONH
and P1CONL register to "00H", configuring P1.0-P1.2 pins to input mode with interrupt and P1.3-P1.7 input mode.
You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative
functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 1 control register must also be enabled in the associated peripheral module.
Port 1 Pull-up Resistor Control Register (P1PUR)
Using the port 1 pull-up resistor control register, P1PUR (F0H, page 0), you can configure pull-up resistors to
individual port 1 pins.
Port 1 Interrupt Control Registers (P1INT, INTPND.2-.0)
To process external interrupts at the port 1 pins, two additional control registers are provided: the port 1 interrupt
control register P1INT (F1H, page 0), the port 1 interrupt pending bits INTPND.2-.0 (D8H, page 0).
The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests by
polling the INTPND.2-.0 register at regular intervals.
When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding INTPND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU
that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the
clear the pending condition by writing a "0" to the corresponding INTPND bit.
9-4
S3C9234/P9234
I/O PORTS
Port 1 Control Register, High Byte (P1CONH)
EEH, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.7/BUZ P1.6/CLKOUT P1.5/TBOUT P1.4/TAOUT
P1CONH bit-pair pin configuration settings:
00
01
10
11
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function
(BUZ, CLKOUT, TBOUT, TAOUT)
Figure 9-3. Port 1 High-Byte Control Register (P1CONH)
Port 1 Control Register, Low Byte (P1CONL)
EFH, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.3/T1CLK P1.2/INT
P1.1/INT
P1.0/INT
P1CONL bit-pair pin configuration settings:
00
01
10
11
Schmitt trigger input mode (T1CLK)
N-channel open-drain output mode
Push-pull output mode
Not available
Figure 9-4. Port 1 Low-Byte Control Register (P1CONL)
9-5
I/O PORTS
S3C9234/P9234
Port 1 Pull-up Control Register (P1PUR)
F0H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.7 P1.6 P1.5 P1.4
P1PUR bit configuration settings:
P1.3 P1.2 P1.1 P1.0
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
A pull-up resistor of port1 is automatically disabled when the
corresponding pin is selected as push-pull output or alternative
function.
Figure 9-5. Port 1 Pull-up Control Register (P1PUR)
Port 1 Interrupt Control Register (P1INT)
F1H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
P1.2 (INT)
P1.1 (INT)
P1.0 (INT)
P1INT bit configuration settings:
00
01
10
11
Disable interrupt
Enable interrupt by falling edge
Enable interrupt by rising edge
Enable interrupt by both falling and rising edge
Figure 9-6. Port 1 Interrupt Control Register (P1INT)
9-6
S3C9234/P9234
I/O PORTS
Port 1 Interrupt Pending Bits (INTPND.2-.0)
D8H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.7 P2.6 P2.5 P2.4 Not P1.2 P1.1 P1.0
(INT) (INT) (INT) (INT) used (INT) (INT) (INT)
INTPND bit configuration settings:
0
1
No interrupt pending (when read), clear pending bit (when write)
Interrupt is pending (when read)
Figure 9-7. Port 1 Interrupt Pending Bits (INTPND.2-.0)
9-7
I/O PORTS
PORT 2
S3C9234/P9234
Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading
the port 2 data register, P2 at location E2H in page 0. P2.0-P2.7 can serve as inputs (with or without pull-up), as
outputs (push-pull or open-drain) or you can be configured the following functions.
— Low-nibble pins (P2.0-P2.3): SCK, SO, SI
— High-nibble pins (P2.4-P2.7): INT
Port 2 Control Register (P2CONH, P2CONL)
Port 2 has two 8-bit control register: P2CONH for P2.4-P2.7 and P2CONL for P2.0-P2.3. A reset clears the
P2CONH/P2CONL register to "00H", configuring P2.4-P2.7 pins to input mode with interrupt and P2.0-P2.3 input
mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the
alternative functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 2 control register must also be enabled in the associated peripheral module.
Port 2 Pull-up Resistor Control Register (P2PUR)
Using the port 2 pull-up resistor control register, P2PUR (F4H, page 0), you can configure pull-up resistors to
individual port 2 pins.
Port 2 Interrupt Control Registers (P2INT, INTPND.4-.7)
To process external interrupts at the port 2 pins, two additional control registers are provided: the port 2 interrupt
control register P2INT (F5H, page 0), the port 2 interrupt pending bits INTPND.4-.7 (D8H, page 0).
The port 2 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests by
polling the INTPND.4-.7 register at regular intervals.
When the interrupt enable bit of any port 2 pin is "1", a rising or falling edge at that pin will generate an interrupt
request. The corresponding INTPND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU
that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the
clear the pending condition by writing a "0" to the corresponding INTPND bit.
9-8
S3C9234/P9234
I/O PORTS
Port 2 Control Register, High Byte (P2CONH)
F2H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.7 (INT)
P2.6 (INT)
P2.5 (INT)
P2.4 (INT)
P2CONH bit-pair pin configuration settings:
00
01
10
11
Schmitt trigger input mode
N-channel open-drain output mode
Push-pull output mode
Not available
Figure 9-8. Port 2 High-byte Control Register (P2CONH)
Port 2 Control Register, Low Byte (P2CONL)
F3H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.3
P2.2/SI
P2.1/SO
P2.0/SCK
P2CONL bit-pair pin configuration settings:
00
01
10
11
Schmitt trigger input mode (SI,SCK)
N-channel open-drain output mode
Push-pull output mode
Alternative function (SCK, SO)
Figure 9-9. Port 2 Low-byte Control Register (P2CONL)
9-9
I/O PORTS
S3C9234/P9234
Port 2 Pull-up Control Register (P2PUR)
F4H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P2PUR bit configuration settings:
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
A pull-up resistor of port2 is automatically disabled when the
corresponding pin is selected as push-pull output or alternative
function.
Figure 9-10. Port 2 Pull-up Control Register (P2PUR)
9-10
S3C9234/P9234
I/O PORTS
Port 2 Interrupt Control Register (P2INT)
F5H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
EDG INT EDG INT EDG INT EDG INT
INT bit configuration settings:
0
1
Disable interrupt
Enable interrupt
EDG bit configuration settings:
0
1
Select falling edge
Select rising edge
Figure 9-11. Port 2 Interrupt Control Register (P2INT)
Port 2 Interrupt Pending Bits (INTPND.7-.4)
D8H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.7 P2.6 P2.5 P2.4 Not P1.2 P1.1 P1.0
(INT) (INT) (INT) (INT) used (INT) (INT) (INT)
INTPND bit configuration settings:
0
1
No interrupt pending (when read), clear pending bit (when write)
Interrupt is pending (when read)
Figure 9-12. Port 2 Interrupt Pending Bits (INTPND.7-.4)
9-11
I/O PORTS
PORT 3
S3C9234/P9234
Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading
the port 3 data register, P3 at location E3H in page 0. P3.0-P3.7 can serve as inputs (with or without pull-up), as
outputs (push-pull or open-drain) or you can be configured the following functions.
— Low-nibble pins (P3.0-P3.3): SEG31-SEG28
— High-nibble pins (P3.4-P3.7): SEG27-SEG24
Port 3 Control Register (P3CONH, P3CONL)
Port 3 has two 8-bit control register: P3CONH for P3.4-P3.7 and P3CONL for P3.0-P3.1. A reset clears the P3CON
register to "00H", configuring all pins to input mode. You use control register setting to select input or output mode
(push-pull or open-drain).
When programming this port, please remember that any alternative peripheral I/O function you configure using the
port 3 control register must also be enabled in the associated peripheral module.
Port 3 Pull-up Resistor Control Register (P3PUR)
Using the port 3 pull-up resistor control register, P3PUR (F8H, page 0), you can configure pull-up resistors to
individually port 3 pins.
Port 3 Control Register, High Byte (P3CONH)
F6H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.7/SEG24 P3.6/SEG25 P3.5/SEG26 P3.4/SEG27
P3CONH bit-pair pin configuration settings:
00
01
10
11
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative fumction (SEG24-SEG27)
Figure 9-13. Port 3 High Byte Control Register (P3CONH)
9-12
S3C9234/P9234
I/O PORTS
Port 3 Control Register, Low Byte (P3CONL)
F7H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.3/SEG28 P3.2/SEG29 P3.1/SEG30 P3.0/SEG31
P3CONL bit-pair pin configuration settings:
00
01
10
11
Input mode
N-channel open-drain output mode
Push-pull output mode
Alternative function (SEG28-SEG31)
Figure 9-14. Port 3 Low Byte Control Register (P3CONL)
Port 3 Pull-up Control Register (P3PUR)
F8H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P3PUR bit configuration settings:
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
A pull-up resistor of port3 is automatically disabled when the
corresponding pin is selected as push-pull output or alternative
function.
Figure 9-15. Port 3 Pull-up Control Register (P3PUR)
9-13
I/O PORTS
PORT 4
S3C9234/P9234
Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading
the port 4 data register, P4 at location E4H in page 0. P4.0-P4.7 can serve as inputs (with or without pull-up), as
push-pull outputs:
— Low-nibble pins (P4.0-P4.3): SEG23-SEG20
— High-nibble pins (P4.4-P4.7): SEG19-SEG16
Port 4 Control Registers (P4CONH, P4CONL)
Port 4 has two 8-bit control registers: P4CONH for P4.4-P4.7 and P4CONL for P4.0-P4.3. A reset clears the
P4CONH and P4CONL registers to "00H", configuring all pins to input mode. You use control registers setting to
select input or output mode.
Port 3 Control Register, High Byte (P4CONH)
F9H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.7/SEG16 P4.6/SEG17 P4.5/SEG18 P4.4/SEG19
P4CONH bit-pair pin configuration settings:
00
01
10
11
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG16-SEG19)
Figure 9-16. Port 4 High-Byte Control Register (P4CONH)
Port 4 Control Register, Low Byte (P4CONL)
FAH, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.3/SEG20 P4.2/SEG21 P4.1/SEG22 P4.0/SEG23
P4CONH bit-pair pin configuration settings:
00
01
10
11
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG20-SEG23)
Figure 9-17. Port 4 Low-Byte Control Register (P4CONL)
9-14
S3C9234/P9234
PORT 5
I/O PORTS
Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading
the port 5 data register, P5 at location E5H in page 0. P5.0-P5.7 can serve as inputs (with or without pull-up), as
push-pull outputs.
— Low-nibble pins (P5.0-P5.3): SEG15-SEG12
— High-nibble pins (P5.4-P5.7): SEG11-SEG8
Port 5 Control Registers (P5CONH, P5CONL)
Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P5CONL for P5.0-P5.3. A reset clears the
P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers setting to
select input or output mode.
Port 5 Control Register, High Byte (P5CONH)
FBH, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P5.7/SEG8 P5.6/SEG9 P5.5/SEG10 P5.4/SEG11
P5CONH bit-pair pin configuration settings:
00
01
10
11
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG8-SEG11)
Figure 9-18. Port 5 High-Byte Control Register (P5CONH)
Port 5 Control Register, Low Byte (P5CONL)
FCH, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P5.3/SEG12 P5.2/SEG13 P5.1/SEG14 P5.0/SEG15
P5CONL bit-pair pin configuration settings:
00
01
10
11
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG12-SEG15)
Figure 9-19. Port 5 Low-Byte Control Register (P5CONL)
9-15
I/O PORTS
PORT 6
S3C9234/P9234
Port 6 is an 8-bit I/O port with bit-pair configurable pins. Port 6 pins are accessed directly by writing or reading the
port 6 data register, P6 at location E6H in page 0. P6.0-P6.7 can serve as inputs or as push-pull outputs:
— Low-nibble pins (P6.0-P6.3): SEG7-SEG4
— High-nibble pins (P6.4-P6.7): SEG3-SEG0
Port 6 Control Register (P6CON)
Port 6 has a 8-bit control register: P6CON for P6.0-P6.7. A reset clears the P6CON registers to "00H", configuring all
pins to input mode. You use control registers setting to select input or output mode.
Port 6 Control Register (P6CON)
FDH, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P6.7-P6.6/
P6.5-P6.4/ P6.3-P6.2/
P6.1-P6.0/
SEG0-SEG1 SEG2-SEG3 SEG4-SEG5 SEG6-SEG7
P6CON bit-pair pin configuration settings:
00
01
10
11
Input mode
Input with pull-up resistor
Push-pull output mode
Alternative function (SEG0-SEG7)
Figure 9-20. Port 6 Control Register (P6CON)
9-16
S3C9234/P9234
BASIC TIMER
10 BASIC TIMER
OVERVIEW
Basic timer (BT) can be used in two different ways:
— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
— To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
The functional components of the basic timer block are:
— Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer
— 8-bit basic timer counter, BTCNT (DDH, read-only)
— Basic timer control register, BTCON (DCH, read/write)
10-1
BASIC TIMER
S3C9234/P9234
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter
and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH,
and is read/write addressable using Register addressing mode.
A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of
fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register
control bits BTCON.7–BTCON.4.
The 8-bit basic timer counter, BTCNT (page 0, DDH), can be cleared at any time during normal operation by writing a
"1" to BTCON.1. To clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to
BTCON.0.
Basic TImer Control Register (BTCON)
DCH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Divider clear bit for basic timer
and timer counters:
0 = No effect
Watchdog function enable bits:
1010B = Disable watchdog timer
Other Value = Enable watchdog timer
1 = Clear divider
Basic timer counter clear bit:
0 = No effect
1 = Clear BTCNT
Basic timer input clock selection bits:
00 = fXX /4096
01 = fXX /1024
10 = fXX /128
11 = fXX /16
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
S3C9234/P9234
BASIC TIMER
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any
value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H",
automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the
current CLKCON register setting), divided by 4096, as the BT clock.
A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be
cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will
not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the
basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear
instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop
mode has been released by an external interrupt.
In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value
then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and
an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has
elapsed and to gate the clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when stop mode is released:
1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode
release and oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an
external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock
source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.
10-3
BASIC TIMER
S3C9234/P9234
RESET or STOP
Bit 1
Bits 3, 2
Basic Timer Control Register
(Write '1010xxxxB' to Disable)
Data Bus
f
f
f
f
XX /4096
XX /1024
XX /128
XX /16
Clear
8-Bit Up Counter
(BTCNT, Read-Only)
f
XX
DIV
MUX
OVF
RESET
Start the CPU (note)
R
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
Figure 10-2. Basic Timer Block Diagram
10-4
S3C9234/P9234
TIMER 1
11 TIMER 1
ONE 16-BIT TIMER MODE (TIMER 1)
The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a
16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.
— One 16-bit timer mode (Timer 1)
— Two 8-bit timers mode (Timer A and B)
OVERVIEW
The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate
TACON setting.
Timer 1 has the following functional components:
— Clock frequency divider (fxx divided by 512, 256, 64, 8, or 1, fxt, and T1CLK: External clock) with multiplexer
— 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA)
— Timer 1 match interrupt generation
— Timer 1 control register, TACON (page 0, EBH, read/write)
FUNCTION DESCRIPTION
Interval Timer Function
The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT).
The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is
disabled, the application's service routine can detect a pending condition of T1INT by the software and execute it's
sub-routine. When this case is used, the T1INT pending bit must be cleared by the application sub-routine by writing
a "0" to the TACON.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
timer 1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt and
clears the counter.
If, for example, you write the value 32H and 10H to TADATA and TBDATA, respectively, and 8EH to TACON, the
counter will increment until it reaches 3210H. At this point, the timer 1 interrupt request is generated, the counter
value is reset, and counting resumes.
11-1
TIMER 1
S3C9234/P9234
Timer 1 Control Register (TACON)
You use the timer 1 control register, TACON, to
— Enable the timer 1 operating (interval timer)
— Select the timer 1 input clock frequency
— Clear the timer 1 counter, TACNT and TBCNT
— Enable the timer 1 interrupt
TACON is located in page 0, at address EBH, and is read/write addressable using register addressing mode.
A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of
fxx/512, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during normal operation by
writing a "1" to TACON.3.
To enable the timer 1 interrupt, you must write TACON.7, TACON.2, and TACON.1 to "1".
To generate the exact time interval, you should write TACON.3 and TACON.0 to "10B", which cleared counter and
interrupt pending bit. To detect an interrupt pending condition when T1INT is disabled, the application program polls
pending bit, TACON.0. When a "1" is detected, a timer 1 interrupt is pending. When the T1INT sub-routine has been
serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit,
TACON.0.
Timer A Control Register (TACON)
EBH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
One 16-bit timer or Two 8-bit timers
mode:
0 = Two 8-bit timers mode (Timer A/B)
Timer 1 interrupt pending bit:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)
1 = One 16-bit timer mode (Timer 1)
Timer 1/A interrupt enable bit:
0 = Disable interrupt
Timer 1/A clock selection bits:
000 = fxx/512
1 = Enable interrupt
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = fxt (sub clock)
110 = T1CLK (external clock)
111 = Not available
Timer 1/A counter enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer 1/A counter clear bit:
0 = No affect
1 = Clear the timer 1/A counter (when write)
Figure 11-1. Timer 1 Control Register (TACON)
11-2
S3C9234/P9234
TIMER 1
BTCON.0
TACON.6-.4
1/512
1/256
1/64
1/8
R
TACON.3
Data Bus
TACON.2
(XIN or XTIN
)
LSB
MSB
M
U
X
DIV
fxx
Clear
TBCNT TACNT
R
TACON.1
1/1
Match
TACON.0
16-Bit Comparator
LSB MSB
fxt
T1INT
T1CLK
TAOUT
TBDATA TADATA
Buffer Buffer
Match Signal
T1CLR
TBDATA TADATA
Data Bus
NOTE:
When one 16-bit timer mode (TACON.7 <- "1": Timer 1)
Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
11-3
TIMER 1
S3C9234/P9234
TWO 8-BIT TIMERS MODE (TIMER A and B)
OVERVIEW
The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using
the appropriate TACON and TBCON setting, respectively.
Timer A and B have the following functional components:
— Clock frequency divider with multiplexer
– fxx divided by 512, 256, 64, 8 or 1, fxt, and T1CLK (External clock) for timer A
– fxx divided by 512, 256, 64 or 8 and fxt for timer B
— 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA)
— Timer A have I/O pin for match output (TAOUT)
— Timer A match interrupt generation
— Timer A control register, TACON (page 0, EBH, read/write)
— Timer B have I/O pin for match output (TBOUT)
— Timer B match interrupt generation
— Timer B control register, TBCON (page 0, ECH, read/write)
Timer A and B Control Register (TACON, TBCON)
You use the timer A and B control register, TACON and TBCON, to
— Enable the timer A (interval timer mode) and B operating (interval timer mode)
— Select the timer A and B input clock frequency
— Clear the timer A and B counter, TACNT and TBCNT
— Enable the timer A and B interrupt
11-4
S3C9234/P9234
TIMER 1
TACON and TBCON are located in page 0, at address EBH and ECH, and is read/write addressable using register
addressing mode.
A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of
fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by
writing a "1" to TACON.3.
A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency of
fxx/512, and disables timer A interrupt. You can clear the timer B counter at any time during normal operation by
writing a "1" to TBCON.3.
To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2
(TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3
(TBCON.3) and TACON.0 (TBCON.0), which cleared counter and interrupt pending bit. To detect an interrupt pending
condition when TAINT and TBINT is disabled, the application program polls pending bit, TACON.0 and TBCON.0.
When a "1" is detected, a timer A interrupt (TAINT) and timer B interrupt (TBINT) is pending. When the TAINT and
TBINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer
A and B interrupt pending bit, TACON.0 and TBCON.0.
Timer A Control Register (TACON)
EBH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
One 16-bit timer or Two 8-bit timers
mode:
0 = Two 8-bit timers mode (Timer A/B)
Timer A interrupt pending bit:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)
1 = One 16-bit timer mode (Timer 1)
Timer A interrupt enable bit:
0 = Disable interrupt
Timer 1/A clock selection bits:
000 = fxx/512
1 = Enable interrupt
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = fxt (sub clock)
110 = T1CLK (external clock)
111 = Not available
Timer A counter enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer A counter clear bit:
0 = No affect
1 = Clear the timer 1/A counter (when write)
Figure 11-3. Timer A Control Register (TACON)
11-5
TIMER 1
S3C9234/P9234
Timer B Control Register (TBCON)
ECH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Timer B interrupt pending bits:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)
Timer B clock selection bits:
000 = fxx/512
001 = fxx/256
Timer B match interrupt enable bit:
0 = Disable match interrupt
1 = Enable match interrupt
010 = fxx/64
011 = fxx/8
100 = fxt (sub clock)
Timer B count enable bit:
0 = Disable counting operating
1 = Enable counting operating
Timer B counter clear bit:
0 = No effect
1 = Clear the timer B counter (when write)
Figure 11-4. Timer B Control Register (TBCON)
11-6
S3C9234/P9234
TIMER 1
FUNCTION DESCRIPTION
Interval Timer Function (Timer A and Timer B)
The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match
interrupt (TBINT).
The timer A match interrupt pending condition (TACON.0) and the timer B match interrupt pending condition
(TBCON.0) must be cleared by software in the application's interrupt service by means of writing a "0" to the
TACON.0 and TBCON.0 interrupt pending bit.
Even though TAINT and TBINT are disabled, the application's service routine can detect a pending condition of
TAINT and TBINT by the software and execute it's sub-routine. When this case is used, the TAINT and TBINT
pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit
TACON.0 and TBCON.0.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to the
timer A or timer B reference data registers, TADATA or TBDATA. The match signal generates corresponding match
interrupt and clears the counter.
If, for example, you write the value 20H to TADATA and 0EH to TACON, the counter will increment until it
reaches 20H. At this point, the timer A interrupt request is generated, the counter value is cleared, and counting
resumes and you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will increment
until it reaches 10H. At this point, TB interrupt request is generated, the counter value is cleared and
counting resumes.
11-7
TIMER 1
S3C9234/P9234
BTCON.0
TACON.6-.4
1/512
1/256
1/64
1/8
R
Data Bus
TACNT
TACON.3
MSB
TACON.2
(XIN or XTIN
)
LSB
M
U
X
DIV
fxx
Clear
(8-Bit Up-Counter)
R
TACON.1
1/1
Match
TACON.0
8-Bit Comparator
fxt
TAINT
T1CLK
TAOUT
LSB
MSB
TADATA Buffer
Match Signal
TACLR
TADATA Register
Data Bus
NOTE:
When two 8-bit timers mode (TACON.7 <- "0": Timer A)
Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)
11-8
S3C9234/P9234
TIMER 1
BTCON.0
TBCON.6-.4
R
1/512
1/256
1/64
1/8
TBCON.3
MSB
Data Bus
TBCNT
TBCON.2
M
U
X
(XIN or XTIN
)
LSB
DIV
fxx
Clear
(8-Bit Up-Counter)
R
TBCON.1
Match
TBCON.0
8-Bit Comparator
fxt
TBINT
TBOUT
LSB
MSB
TBDATA Buffer
Match Signal
TBCLR
TBDATA Register
Data Bus
NOTE:
When two 8-bit timers mode (TACON.7 <- "0": Timer B)
Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
11-9
TIMER 1
S3C9234/P9234
NOTES
11-10
S3P9234 (Preliminary Spec)
WATCH TIMER
12 WATCH TIMER
OVERVIEW
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To
start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".
And if you want to service watch timer overflow interrupt, then set the WTCON.6 to "1".
The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application's
interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit.
After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically
set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting Watch timer
speed selection bits (WTCON.3 – .2).
The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By
setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt
every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences.
Also, you can select watch timer clock source by setting the WTCON.7 appropriately value.
The watch timer supplies the clock frequency for the LCD controller (f
the LCD controller does not operate.
). Therefore, if the watch timer is disabled,
LCD
Watch timer has the following functional components:
— Real Time and Watch-Time Measurement
7
— Using a Main or Sub Clock Source (Main clock divided by 2 (fx/128) or Sub clock(fxt))
— Clock Source Generation for LCD Controller (f
)
LCD
— I/O pin for Buzzer Output Frequency Generator (P1.7, BUZ)
— Timing Tests in High-Speed Mode
— Watch timer overflow interrupt generation
— Watch timer control register, WTCON (page 0, DAH, read/write)
12-1
WATCH TIMER
S3P9234 (Preliminary Spec)
WATCH TIMER CONTROL REGISTER (WTCON)
The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and
Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is
read/write addressable using register addressing mode.
A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock.
So, if you want to use the watch timer, you must write appropriate value to WTCON.
Watch Timer Control Register (WTCON)
DAH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Watch timer clock selection bit:
0 = Main clock divided by
27(fx/128)
Watch timer interrupt pending bits:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)
1 = Sub clock (fxt)
Watch timer INT Enable/Disable bit:
0 = Disable watch timer INT
1 = Enable watch timer INT
Watch timer Enable/Disable bit:
0 = Disable watch timer;
clear frequency dividing circuits
1 = Enable watch timer
Buzzer signal selection bits:
00 = 0.5 kHz
01 = 1 kHz
10 = 2 kHz
11 = 4 kHz
Watch timer speed selection bits:
00 = Set watch timer interrupt to 1 s
01 = Set watch timer interrupt to 0.5 s
10 = Set watch timer interrupt to 0.25 s
11 = Set watch timer interrupt to 3.91 ms
Figure 12-1. Watch Timer Control Register (WTCON)
12-2
S3P9234 (Preliminary Spec)
WATCH TIMER
WATCH TIMER CIRCUIT DIAGRAM
WTCON.7
WTCON.6
WT INT Enable
BUZ (P1.7)
WTCON.6
WTCON.5
WTCON.4
MUX
WTINT
8
fW/64 (0.5 kHz)
WTCON.3
WTCON.2
WTCON.1
f
W
/32 (1 kHz)
/16 (2 kHz)
W/8 (4 kHz)
fW
f
Enable/Disable
Selector
Circuit
WTCON.0
WTCON.0
(Pending Bit)
fW
/27
/213
/214
/215
fW
Frequency
Dividing
Circuit
Clock
Selector
f
W
fW
f
W
(1 Hz)
LCD = 2048 Hz
32.768 kHz
f
fxt fx/128
f
X
= Main clock (where fx = 4.19 MHz)
fxt = Sub clock (32,768 Hz)
= Watch timer frequency
fW
Figure 12-2. Watch Timer Circuit Diagram
12-3
WATCH TIMER
S3P9234 (Preliminary Spec)
NOTES
12-4
S3C9234/P9234
LCD CONTROLLER/DRIVER
13 LCD CONTROLLER/DRIVER
OVERVIEW
The S3C9234/P9234 microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel. Its
LCD block has the following components:
— LCD controller/driver
— Display RAM (B0H-BFH of page 0) for storing display data
— 32 segment output pins (SEG0–SEG31)
— 4 common output pins (COM0–COM3)
— Three LCD operating power supply pins (V
-V
)
LC0 LC2
— Bias pin for controlling the driver and bias voltage
— LCD bias by Internal/External register
Bit setting in the LCD control register, LCON, determine the LCD frame, duty and bias.
The LCD control register, LCON, is used to turn the LCD display on or off, to select LCD clock frequency, to select
bias and duty, and switch the current to the dividing resistor for the LCD display. Data written to the LCD display
RAM can be transferred to the segment signal pins automatically without program control.
When a sub clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and
idle modes.
Bias
1
V
LC0-VLC2
LCD
Controller/
Driver
3
4
COM0-COM3
SEG0-SEG31
8
32
Figure 13-1. LCD Function Diagram
13-1
LCD CONTROLLER/DRIVER
LCD CIRCUIT DIAGRAM
S3C9234/P9234
SEG31/P3.0
Port
Latch
SEG/Port
Driver
SEG16/P4.7
SEG15/P5.0
SEG0/P6.7
LCD
Display
RAM
(0B0H-0BFH)
COM2/P0.3
COM1/P0.2
COM/Port
Driver
f
LCD
COM0/P0.1
Timing
Controller
Bias
LCON
LCD
Voltage
Controller
V
V
V
LC0
LC1
LC2
Figure 13-2. LCD Circuit Diagram
13-2
S3C9234/P9234
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA
RAM addresses of page 0 are used as LCD data memory. When the bit value of a display segment is "1", the LCD
display is turned on; when the bit value is "0", the display is turned off.
Display RAM data are sent out through segment pins SEG0–SEG31 using a direct memory access (DMA) method
that is synchronized with the f
signal. RAM addresses in this location that are not used for LCD
LCD
display can be allocated to general-purpose use.
COM0 b0 b4 b0 b4 b0 b4 b0 b4 b0 b4
COM1 b1 b5 b1 b5 b1 b5 b1 b5 b1 b5
COM2 b2 b6 b2 b6 b2 b6 b2 b6 b2 b6
COM3 b3 b7 b3 b7 b3 b7 b3 b7 b3 b7
0B0H 0B1H 0B2H 0B3H 0B4H
b0 b4 b0 b4 b0 b4
b1 b5 b1 b5 b1 b5
b2 b6 b2 b6 b2 b6
b3 b7 b3 b7 b3 b7
0BDH 0BEH 0BFH
Figure 13-3. LCD Display Data RAM Organization
Table 13-1. LCD Clock Signal Frame Frequency
LCDCK Frequency (f
)
Static
1/2 Duty
1/3 Duty
1/4 Duty
LCD
64 Hz
128 Hz
256Hz
512 Hz
64
32
64
21
43
16
32
128
256
512
128
256
85
64
171
128
13-3
LCD CONTROLLER/DRIVER
S3C9234/P9234
LCD CONTROL REGISTER (LCON)
A LCON is located in page 0, at address D7H, and is read/write addressable using register addressing mode. It has
the following control functions.
— LCD duty and bias selection
— LCD clock selection
— LCD display control
— Internal/External LCD dividing resistors selection
The LCON register is used to turn the LCD display on/off, to select duty and bias, to select LCD clock and control
the flow of the current to the dividing in the LCD circuit. Following a RESET, all LCON values are cleared to "0". This
turns off the LCD display, select 1/4 duty and 1/3 bias, select 64Hz for LCD clock, and Enable internal LCD dividing
resistors.
The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also
referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch timer
should be enabled when the LCD display is turned on.
LCD Control Register (LCON)
D7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Internal LCD dividing register enable bits:
0 = Enable internal LCD dividing resistors
1 = Disable internal LCD dividing resistors
LCD display control bit:
0 = All LCD signals are low
(Turn off the R-Tr)
1 = Turn display on
(Turn on the P-Tr)
LCD clock selection bits:
00 = fw/29 (64 Hz)
Not used
01 = fw/28 (128 Hz)
10 = fw/27 (256 Hz)
11 = fw/26 (512 Hz)
LCD duty and bias selection bits:
000 = 1/4 duty, 1/3 bias
001 = 1/3 duty, 1/3 bias
010 = 1/3 duty, 1/2 bias
011 = 1/2 duty, 1/2 bias
1xx = static
Figure 13-4. LCD Control Register (LCON)
13-4
S3C9234/P9234
LCD CONTROLLER/DRIVER
LCD VOLTAGE DIVIDING RESISTOR
Static and 1/3 Bias (VLCD = 3V at VDD = 5V)
1/2 Bias (VLCD = 2.5V at VDD = 5V)
S3C9234
S3C9234
V
DD
VDD
LCON.0
LCON.0
Bias
Bias
2R LCON.7 = 0: Enable internal resistors
2R LCON.7 = 0: Enable internal resistors
V
V
V
LC0
V
V
V
LC0
R
R
R
R
LC1
LC2
LC1
LC2
V
LCD
VLCD
R
R
V
SS
VSS
Static and 1/3 Bias (VLCD = 5V at VDD = 5V)
Voltage Dividing Resistor Adjustment
S3C9234
S3C9234
V
DD
VDD
LCON.0
LCON.0
Bias
Bias
LCON.7 = 0: Enable internal resistors
LCON.7 = 1: Disable internal resistors
2R
R''
R'
R'
R'
V
V
V
LC0
V
V
V
LC0
R
R
R
LC1
LC2
LC1
LC2
V
LCD
VLCD
V
SS
VSS
NOTES:
1. R = Internal LCD dividing resistors. The resistors can be disconnected by LCON.7.
2. R' = External LCD dividing resistors.
3. R'' = External resistor to adjust VLCD
.
Figure 13-5. Internal Voltage Dividing Resistor Connection
13-5
LCD CONTROLLER/DRIVER
COMMON (COM) SIGNALS
S3C9234/P9234
The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
— In 1/4 duty mode, COM0-COM3 pins are selected
— In 1/3 duty mode, COM0-COM2 pins are selected
— In 1/2 duty mode, COM0-COM1 pins are selected
SEGMENT (SEG) SIGNALS
The 31 LCD segment signal pins are connected to corresponding display RAM locations at page 0. Bits of the
display RAM are synchronized with the common signal output pins.
When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When
the display bit is "0", a 'no-select' signal to the corresponding segment pin.
Select
Non-Select
FR
1 Frame
V
V
LC0
SS
COM
SEG
V
V
LC0
SS
V
V
LC0
SS
COM-SEG
-VLC0
Figure 13-6. Select/No-Select Signals in Static Display Mode
13-6
S3C9234/P9234
LCD CONTROLLER/DRIVER
Select
Non-Select
FR
1 Frame
V
V
V
LC 0
LC1, 2
ss
COM
V
V
V
LC 0
LC1, 2
ss
SEG
V
V
V
LC 0
LC1, 2
ss
COM-SEG
-VLC1, 2
-VLC 0
Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode
Select
Non-Select
FR
1 Frame
V
VLC0
VLC1
VSLCS2
COM
V
VLC0
VLC1
VSLCS2
SEG
VLC0
V
VLC1
VSLCS2
-V
COM-SEG
-VLC2
-VLLCC01
Figure 13-8. Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode
13-7
LCD CONTROLLER/DRIVER
S3C9234/P9234
0
1
0
1
SEG0.0 x C0
SEG1.0 x C0
SEG2.1 x C1
1 Frame
FR
V
V
V
LC0
LC1, 2
SS
COM0
V
V
V
LC0
LC1, 2
SS
COM1
SEG0
SEG1
V
V
V
LC0
LC1, 2
SS
V
V
V
LC0
LC1, 2
SS
SEG3.1 x C1
V
V
V
LC0
LC1, 2
SS
COM0
-SEG0
-VLC0
-VLC1, 2
V
V
V
LC0
LC1, 2
SS
COM0
-SEG1
-VLC1, 2
-VLC0
V
V
V
LC0
LC1, 2
SS
COM1
-SEG0
-VLC1, 2
-VLC0
V
V
V
LC0
LC1, 2
SS
COM1
-SEG1
-VLC1, 2
-VLC0
NOTE:
VLC2 = VLC1
Figure 13-9. LCD Signal and Wave Forms Example in 1/2 Duty, 1/2 Bias Display Mode
13-8
S3C9234/P9234
LCD CONTROLLER/DRIVER
0
1
2
0
1
2
SEG2.0 x C0
SEG2.1 x C1
SEG0.2 x C2
1 Frame
FR
V
V
V
V
LC0
LC1
LC2
SS
COM0
V
V
V
V
LC0
LC1
LC2
SS
COM1
COM2
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
LC0
LC1
LC2
SS
SEG0
SEG1
SEG1.6 x C2
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM0
-SEG0
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM0
-SEG1
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM1
-SEG0
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM1
-SEG1
Figure 13-10. LCD Signals and Wave Forms Example in 1/3 Duty, 1/3 Bias Display Mode
13-9
LCD CONTROLLER/DRIVER
S3C9234/P9234
0
1
2
3
0
1
2
3
SEG1.4 x C0
SEG0.1 x C1
SEG0.3 x C3
FR
1 Frame
V
V
V
V
LC0
LC1
LC2
SS
COM0
V
V
V
V
LC0
LC1
LC2
SS
COM1
COM2
COM3
SEG0
SEG1
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
LC0
LC1
LC2
SS
SEG1.7 x C3
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
LC0
LC1
LC2
SS
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM0
-SEG0
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM0
-SEG1
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM1
-SEG0
V
V
V
V
-VLC2
-VLC1
-VLC0
LC0
LC1
LC2
SS
COM1
-SEG1
Figure 13-11. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode
13-10
S3C9234/P9234
SERIAL I/O INTERFACE
14 SERIAL I/O INTERFACE
OVERVIEW
Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The
components of SIO function block are:
— 8-bit control register (SIOCON)
— Clock selector logic
— 8-bit data buffer (SIODATA)
— 8-bit prescaler (SIOPS)
— 3-bit serial clock counter
— Serial data I/O pins (SI, SO)
— Serial clock input/output pin (SCK)
The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.
PROGRAMMING PROCEDURE
To program the SIO module, follow these basic steps:
1. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P2CON register if necessary.
2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation,
SIOCON.2 must be set to "1" to enable the data shifter.
3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1".
4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation
starts.
5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) are set to "1" and SIO
interrupt request is generated.
14-1
SERIAL I/O INTERFACE
S3C9234/P9234
SIO CONTROL REGISTERS (SIOCON)
The control register for serial I/O interface module, SIOCON, is located at D0H in page 0. It has the control setting
for SIO module.
— Clock source selection (internal or external) for shift clock
— Interrupt enable
— Edge selection for shift operation
— Clear 3-bit counter and start shift operation
— Shift operation (transmit) enable
— Mode selection (transmit/receive or receive-only)
— Data direction selection (MSB first or LSB first)
A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source
at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the
interrupt are disabled. The selected data direction is MSB-first.
Serial I/O Module Control Register (SIOCON)
D0H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
SIO interrupt pending bit:
SIO shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK)
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending
Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode
SIO interrupt enable bit:
0 = Disable SIO interrupt
1 = Enable SIO interrupt
SIO mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode
SIO shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter
Shift clock edge selection bit:
SIO counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting
0 = tX
at falling edeges, rx at rising edges.
1 = tX
at rising edeges, rx at falling edges.
Figure 14-1. Serial I/O Module Control Register (SIOCON)
14-2
S3C9234/P9234
SERIAL I/O INTERFACE
SIO PRE-SCALER REGISTER (SIOPS)
The prescaler register for serial I/O interface module, SIOPS, are located at D2H in page 0.
The value stored in the SIO pre-scaler register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows:
Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.
SIO Pre-scaler Register (SIOPS)
D2H, Page 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate = (fXX/4)/(SIOPS + 1)
Figure 14-2. SIO Prescaler Register (SIOPS)
SIO BLOCK DIAGRAM
SIO INT
3-Bit Counter
SIOCON.0
Pending
Clear
CLK
SIOCON.1
(Interrupt Enable)
SIOCON.3
SIOCON.7
SIOCON.4
(Edge Select)
SIOCON.2
(Shift Enable)
SIOCON.5
(Mode Select)
M
U
X
SCK
fxx /2
SIOPS (D2H, page 0)
8-bit P.S. 1/2
CLK
8-Bit SIO Shift Buffer
SO
(SIODATA, D1H, page 0)
SIOCON.6
(LSB/MSB First
Mode Select)
8
SI
Data Bus
Figure 14-3. SIO Functional Block Diagram
14-3
SERIAL I/O INTERFACE
S3C9234/P9234
SERIAL I/O TIMING DIAGRAM (SIO)
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
SIO INT
Set SIOCON.3
Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
SCK
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
SIO INT
Set SIOCON.3
Figure 14-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
14-4
S3C9234/P9234
ELECTRICAL DATA
15 ELECTRICAL DATA
OVERVIEW
In this chapter, S3C9234/P9234 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
—
—
—
—
—
—
—
—
—
—
—
—
—
Absolute maximum ratings
D.C. electrical characteristics
Data retention supply voltage in Stop mode
Stop mode release timing when initiated by an external interrupt
Stop mode release timing when initiated by a Reset
I/O capacitance
A.C. electrical characteristics
Input timing for external interrupts
Input timing for RESET
Serial data transfer timing
Oscillation characteristics
Oscillation stabilization time
Operating voltage range
15-1
ELECTRICAL DATA
S3C9234/P9234
Table 15-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
– 0.3 to + 6.5
Unit
Supply voltage
V
–
V
V
DD
Input voltage
V
Ports 0–6
– 0.3 to V + 0.3
DD
I
O
Output voltage
Output current High
V
–
– 0.3 to V + 0.3
DD
V
I
One I/O pin active
– 15
mA
OH
All I/O pins active
One I/O pin active
– 60
+ 30
Output current Low
I
mA
OL
Total pin current for ports
–
+ 100
°
Operating temperature
Storage temperature
T
– 30 to + 85
C
A
°
T
–
– 65 to + 150
C
STG
Table 15-2. D.C. Electrical Characteristics
°
°
(T = – 30 C to + 85 C, V
= 2.0 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating Voltage
V
fx = 0 – 4.2MHz, fxt = 32.8kHz
2.0
–
5.5
V
DD
fx = 0 – 8.0MHz
2.7
–
–
5.5
Input High
voltage
V
V
V
V
V
V
V
All input pins except for V , V
IH2 IH3
0.7 V
V
V
V
V
V
IH1
IH2
IH3
IL1
IL2
IL3
OH
DD
DD
DD
DD
DD
Ports 1-2,
0.8 V
RESET
and XT , XT
X , X
V
V
– 0.1
IN OUT
IN
OUT
DD
DD
Input Low voltage
All input pins except for V , V
IL2 IL3
–
–
0.3 V
0.2 V
0.1
DD
DD
Ports 1-2,
RESET
X , X , XT , XT
OUT
IN OUT
IN
Output High
voltage
V
= 4.5 to 5.5 V;
– 1.0
–
–
–
V
V
DD
All output ports; I = –1 mA
OH
Output Low
voltage
V
V
I
= 4.5 to 5.5 V
DD
–
2.0
2.0
OL1
OL2
= 15mA
OL
Ports 1-2
= 4.5 to 5.5 V
V
V
–
–
–
–
V
DD
I
= 10mA
OL
All output ports except for V
OL1
Input High leakage
current
I
V = V
DD
3
mA
LIH1
I
All input pins except for I
LIH2
I
V = V
DD
20
LIH2
I
X , X , XT , XT
OUT
IN OUT
IN
15-2
S3C9234/P9234
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 30 C to + 85 C, V
= 2.0 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Low
I
V = 0 V;
–
–
–3
mA
I
LIL1
leakage current
All input pins except
, I
RESET
LIL2
I
V = 0 V;
I
–20
LIL2
X , X , XT , XT
OUT
IN OUT
IN
Output High
leakage current
I
V
= V
DD
–
–
–
–
3
LOH
O
All output pins
= 0 V
Output Low
I
V
–3
LOL
O
leakage current
All output pins
°
Pull-Up Resistor
R
25
50
100
kW
V = 0 V; V = 5V, T = 25 C
L1
I
DD
A
Ports 0–6
°
50
100
250
150
400
V
= 3V, T = 25 C
A
DD
°
R
150
V = 0 V; V = 5V, T = 25 C
L2
I
DD
A
RES ET
°
= 3V, T = 25 C
A
300
300
500
600
700
V
DD
Oscillator Feed
back Resistors
R
V
X
= 5 V, T = 25 °C
1500
kW
OSC1
DD
A
= V , X
= 0V
IN
DD OUT
R
V
= 5 V, T = 25 °C
1500
3000
4500
OSC2
DD
A
XT = V , XT = 0 V
OUT
IN
DD
LCD Voltage
Dividing Resistor
R
T = 25 °C
100
–
150
–
200
120
kW
LCD
A
V
V
- 15 mA per common pin
- 15 mA per common pin
mV
½
-COMi½
LCD
DC
DS
Voltage Drop
(i = 0-3)
V
V
V
–
–
120
½ LCD-SEGx½
Voltage Drop
(x = 0–31)
Middle Output
V
2.7 V to 5.5 V, 1/3 bias
0.6V –0.2 0.6V
DD
0.6V +
DD
V
=
LC0
DD
DD
(1)
Voltage
LCD clock = 0Hz, V
= V
0.2
LC1
DD
V
V
0.4V –0.2 0.4V
DD
0.4V
+
LC1
DD
DD
0.2
0.2V –0.2 0.2V
0.2V
+
LC2
DD
DD
DD
0.2
NOTE: It is middle output voltage when the Bias pin and the V
pin are opened.
LC0
15-3
ELECTRICAL DATA
S3C9234/P9234
Table 15-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 30 C to + 85 C, V
= 2.0 V to 5.5 V)
A
DD
Unit
Parameter
Symbol
Conditions
8.0 MHz
Min
Typ
Max
(1)
(2)
Run mode:
= 5 V ± 10%
–
6.0
12.0
mA
Supply current
I
DD1
V
DD
Crystal oscillator
C1 = C2 = 22pF
4.0 MHz
8.0 MHz
2.6
2.5
5.2
5.0
V
= 3 V ± 10%
DD
4.0 MHz
8.0 MHz
1.2
1.3
2.4
3.0
(2)
Idle mode:
= 5 V ± 10%
I
DD2
V
DD
Crystal oscillator
C1 = C2 = 22pF
4.0 MHz
0.9
0.8
1.8
1.6
V
= 3 V ± 10%
8.0 MHz
4.0 MHz
DD
0.4
0.8
(3)
(3)
(4)
Run mode: V = 3 V ± 10%,
15.0
30.0
mA
I
DD
DD3
32 kHz crystal oscillator
Idle mode: V = 3 V ± 10%,
6.0
0.5
15.0
3.0
I
DD
DD4
32 kHz crystal oscillator
Stop mode; V = 5 V ± 10%,
I
DD
DD5
°
T = 25 C
A
Stop mode; V = 3 V ± 10%,
0.3
2.0
DD
°
T = 25 C
A
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and
external output current loads.
2.
3.
4.
I
I
I
and I
include power consumption for subsystem clock oscillation.
DD1
DD3
DD5
DD2
and I
are current when main system clock oscillation stops and the subsystem clock is used.
DD4
is current when main system clock and subsystem clock oscillation stops.
5. Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.
15-4
S3C9234/P9234
ELECTRICAL DATA
Table 15-3. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 30 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply
voltage
V
–
2.0
–
5.5
V
DDDR
°
Data retention supply
current
I
–
–
1
mA
Stop mode, T = 25 C
DDDR
A
V
= 2.0 V
DDDR
Idle Mode
(Basic Timer Active)
Stop Mode
Normal
Operating Mode
Data Retention Mode
V
DD
VDDDR
Execution of
STOP Instruction
0.8 VDD
tWAIT
NOTE:
tWAIT is the same as 16 x 1/BT clock.
Figure 15-1. Stop Mode Release Timing When Initiated by an External Interrupt
15-5
ELECTRICAL DATA
S3C9234/P9234
Oscillation
Stabilization
TIme
RESET
Occurs
Stop Mode
Normal
Operating Mode
Data Retention Mode
V
DD
VDDDR
Execution of
STOP Instrction
RESET
0.8 VDD
0.2 V DD
tWAIT
NOTE:
tWAIT is the same as 16 ´ 1/BT clock.
Figure 15-2. Stop Mode Release Timing When Initiated by a
Table 15-4. Input/Output Capacitance
RESET
°
(T = 25 C, V = 0 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
C
IN
f = 1 MHz; unmeasured pins
–
–
10
pF
capacitance
are connected to V
SS
Output
C
OUT
capacitance
I/O capacitance
C
IO
15-6
S3C9234/P9234
ELECTRICAL DATA
Table 15-5. A.C. Electrical Characteristics
°
°
(T = – 30 C to + 85 C, V = 2.0 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SCK cycle time
t
External SCK source
1,000
–
–
ns
KCY
Internal SCK source
External SCK source
1,000
500
SCK high, low width
t
, t
KH KL
Internal SCK source
External SCK source
t
/2–50
KCY
SI setup time to SCK
high
t
t
250
SIK
KSI
Internal SCK source
External SCK source
250
400
SI hold time to SCK high
Internal SCK source
External SCK source
400
–
Output delay for SCK to
SO
t
–
300
ns
KSO
Internal SCK source
All interrupt
250
–
Interrupt input, High, Low
width
t
500
10
700
–
ns
,
INTH
V
= 3 V
t
DD
INTL
RSL
input Low width
t
Input
= 3 V
–
ms
RESET
V
DD
tINTL
tINTH
External
Interrupt
0.8 V DD
0.2 V DD
NOTE:
The unit t CPU means one CPU clock period.
Figure 15-3. Input Timing for External Interrupts
15-7
ELECTRICAL DATA
S3C9234/P9234
tRSL
RESET
0.2 VDD
Figure 15-4. Input Timing for
RESET
tKCY
tKL
tKH
SCK
0.8VDD
0.2VDD
tSIK
tKSI
0.8V DD
SI
0.2V DD
tKSO
SO
Output Data
Figure 15-5. Serial Data Transfer Timing
15-8
S3C9234/P9234
ELECTRICAL DATA
Table 15-6. Main Oscillation Characteristics
°
°
(T = – 30 C to + 85 C)
A
Oscillator
Clock Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
C1
Main oscillation
frequency
2.7 V – 5.5 V
0.4
–
8
MHz
X
X
IN
OUT
2.0 V – 5.5 V
2.7 V – 5.5 V
0.4
0.4
–
–
4.2
8
Ceramic
Oscillator
C1
Main oscillation
frequency
X
X
IN
OUT
2.0 V – 5.5 V
2.7 V – 5.5 V
0.4
0.4
–
–
4.2
8
External
Clock
X input frequency
IN
XIN
XOUT
2.0 V – 5.5 V
5.0 V
0.4
0.4
–
–
4.2
2
RC
Oscillator
Frequency
Frequency
MHz
X
IN
R
XOUT
3.0 V
0.4
–
1
Table 15-7. Sub Oscillation Characteristics
°
°
(T = – 30 C to + 85 C)
A
Oscillator
Clock Configuration
Parameter
Test Condition
Min
Typ
32.768
Max
Units
Crystal
C1
Sub oscillation
frequency
2.0 V – 5.5 V
32
35
kHz
X
X
IN
OUT
External
clock
XT input
IN
2.0 V – 5.5 V
32
–
100
XIN
frequency
XOUT
15-9
ELECTRICAL DATA
S3C9234/P9234
Table 15-8. Main Oscillation Stabilization Time
°
°
(T = – 30 C to + 85 C, V = 2.0 V to 5.5 V)
A
DD
Oscillator
Test Condition
Min
–
Typ
–
Max
Unit
ms
Crystal
fx > 1 MHz
30
10
Ceramic
Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage
range.
–
–
ms
External clock
X
input high and low width (t , t
)
62.5
–
1250
ns
IN
XH XL
1/fx
tXL
tX
X
IN
V
DD-0.1 V
0.1 V
Figure 15-6. Clock Timing Measurement at X
IN
15-10
S3C9234/P9234
ELECTRICAL DATA
Table 15-9. Sub Oscillation Stabilization Time
°
°
(T = – 30 C to + 85 C, V = 2.0 V to 5.5 V)
A
DD
Oscillator
Test Condition
Min
–
Typ
–
Max
10
Unit
s
Crystal
–
External clock
XT input high and low width (t , t
)
5
–
15
ms
IN
XH XL
1/fxt
tXTL
tXTH
XTIN
V
DD-0.1 V
0.1 V
Figure 15-7. Clock Timing Measurement at XT
IN
15-11
ELECTRICAL DATA
S3C9234/P9234
Instruction Clock
fx (Main/Sub oscillation frequency)
2 MHz
8 MHz
4 MHz
1.0 MHz
400 kHz
6.25 kHz (main)/8.2 kHz(sub)
400 kHz (main)/32.8 kHz(sub)
1
2
6
2.7
5.5
Supply Voltage (V)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 15-8. Operating Voltage Range
15-12
S3C9234/P9234
MECHANICAL DATA
16 MECHANICAL DATA
OVERVIEW
The S3C9234/P9234 microcontroller is currently available in a 64-QFP-1420F package.
23.90
20.00
±
±
0.30
0.20
0-8
+ 0.10
0.15 - 0.05
0.10 MAX
64-QFP-1420F
#64
+ 0.10
0.40 - 0.05
#1
0.05 MIN
2.65
3.00 MAX
1.00
0.15 MAX
(1.00)
±
0.10
0.80 + 0.20
NOTE: Dimensions are in millimeters.
Figure 16-1. 64-Pin QFP Package Dimensions (64-QFP-1420F)
16-1
MECHANICAL DATA
S3C9234/P9234
NOTES
16-2
S3C9234/P9234
S3P9234 OTP
17 S3P9234 OTP
OVERVIEW
The S3P9234 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9234
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P9234 is fully compatible with the S3C9234, both in function and in pin configuration. Because of its simple
programming requirements, the S3P9234 is ideal for use as an evaluation chip for the S3C9234.
17-1
S3P9234 OTP
S3C9234/P9234
COM0/P0.0
COM1/P0.1
COM2/P0.2
COM3/P0.3
BIAS
VLC0
SDAT/VLC1
SCLK/VLC2
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13/P5.2
SEG14/P5.1
SEG15/P5.0
SEG16/P4.7
SEG17/P4.6
SEG18/P4.5
SEG19/P4.4
SEG20/P4.3
SEG21/P4.2
SEG22/P4.1
SEG23/P4.0
SEG24/P3.7
SEG25/P3.6
SEG26/P3.5
SEG27/P3.4
SEG28/P3.3
SEG29/P3.2
SEG30/P3.1
SEG31/P3.0
S3P9234
V
V
DD/VDD
SS/VSS
OUT
IN
9
10
11
12
13
14
15
16
17
18
19
X
(64-QFP-1420F)
X
V
PP/TEST
XTIN
XTOUT
RESET/RESET
P1.0/INT
P1.1/INT
P1.2/INT
Figure 17-1. S3P9234 Pin Assignments (64-QFP-1420F)
17-2
S3C9234/P9234
S3P9234 OTP
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
VLC1
Pin Name
Pin No.
I/O
Function
SDAT
7
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
VLC2
TEST
SCLK
8
I/O
I
Serial clock pin. Input only pin.
V
(TEST)
13
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
PP
16
I
I
Chip initialization
RESET
RESET
/V
V
/V
V
9 / 10
Logic power supply pin. V should be tied to
DD
DD SS
DD SS
+ 5 V during programming.
NOTE: Parentheses indicate pin number for 64-pin-QFP-1420F package.
Table 17-2. Comparison of S3P9234 and S3C9234 Features
Characteristic
Program Memory
Operating Voltage (V
S3P9234
S3C9234
4 Kbyte mask ROM
2.0 V to 5.5 V
4 Kbyte EPROM
2.0 V to 5.5 V
)
DD
OTP Programming Mode
V
= 5 V, V (TEST)=12.5V
DD PP
Pin Configuration
64-QFP
User Program 1 time
64-QFP
EPROM Programmability
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V (TEST) pin of the S3P72C8, the EPROM programming mode is entered.
PP
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
V
V
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
DD
PP
5 V
5 V
0
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
0
0
1
EPROM program
EPROM verify
12.5 V
12.5 V
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
17-3
S3P9234 OTP
S3C9234/P9234
Table 17-4. D.C. Electrical Characteristics
°
°
(T = – 30 C to + 85 C, V
= 2.0 V to 5.5 V)
A
DD
Unit
Parameter
Symbol
Conditions
8.0 MHz
Min
Typ
Max
(1)
I
Run mode:
= 5 V ± 10%
–
6.0
12.0
mA
Supply current
DD1
V
DD
Crystal oscillator
C1 = C2 = 22pF
4.0 MHz
8.0 MHz
2.6
2.5
5.2
5.0
V
= 3 V ± 10%
DD
4.0 MHz
8.0 MHz
1.2
1.3
2.4
3.0
I
Idle mode:
= 5 V ± 10%
DD2
V
DD
Crystal oscillator
C1 = C2 = 22pF
4.0 MHz
0.9
0.8
1.8
1.6
V
= 3 V ± 10%
8.0 MHz
4.0 MHz
DD
0.4
0.8
I
Run mode: V = 3 V ± 10%,
15.0
30.0
mA
DD3
DD
32 kHz crystal oscillator
I
Idle mode: V = 3 V ± 10%,
6.0
0.5
15.0
3.0
DD4
DD
32 kHz crystal oscillator
I
Stop mode; V = 5 V ± 10%,
DD5
DD
°
T = 25 C
A
Stop mode; V = 3 V ± 10%,
0.3
2.0
DD
°
T = 25 C
A
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and
external output current loads.
2.
3.
4.
I
I
I
and I
include power consumption for subsystem clock oscillation.
DD1
DD3
DD5
DD2
and I
are current when main system clock oscillation stops and the subsystem clock is used.
DD4
is current when main system clock and subsystem clock oscillation stops.
5. Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.
17-4
S3C9234/P9234
S3P9234 OTP
Instruction Clock
fx (Main/Sub oscillation frequency)
2 MHz
8 MHz
4 MHz
1.0 MHz
400 kHz
6.25 kHz (main)/8.2 kHz(sub)
400 kHz (main)/32.8 kHz(sub)
1
2
6
2.7
5.5
Supply Voltage (V)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 17-2. Standard Operating Voltage Range
17-5
S3P9234 OTP
S3C9234/P9234
NOTES
17-6
S3C9234/P9234
DEVELOPMENT TOOLS
18 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turn key form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool
including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7,
S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also
offers support software that includes debugger, assembler, and a program for setting options.
SHINE
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It
has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved,
scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object
code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data
and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary
definition (DEF) file with device specific information.
SASM86
The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source
file containing assembly language statements and translates into a corresponding source code, object code and
comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It
produces the relocatable object code only, so the user should link object file. Object files can be linked with other
object files and loaded into memory.
HEX2ROM
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value “FF” is filled into the unused ROM area up to the maximum ROM size of the target device
automatically.
TARGET BOARDS
Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are
included with the device-specific target board.
18-1
DEVELOPMENT TOOLS
S3C9234/P9234
IBM-PC AT or Compatible
RS-232C
SMDS2+
Target
Application
System
PROM/OTP Writer Unit
RAM Break/Display Unit
Trace/Timer Unit
Probe
Adapter
TB9234
Target
POD
SAM8 Base Unit
Board
EVA
Chip
Power Supply Unit
Figure 18-1. SMDS Product Configuration (SMDS2+)
18-2
S3C9234/P9234
DEVELOPMENT TOOLS
TB9234 TARGET BOARD
The TB9234 target board is used for the S3C9234 microcontroller. It is supported by the SMDS2+ development
system.
REV.0
To User_VCC
TB9234
'2003. 05. 28
OFF
ON
RESET
IDLE
STOP
7411
U2
U3
B1
Y1
R7
R8
JP6
CB
+
25
R5
R4
1
3
4
6
20
J101
J102
40
30
20
10
1
64QFP
64QFP
1
9
2
1
9
2
160
150
140
130
B3
CN1
50
60
70
80
10
10
10
19
29
20
30
19
29
20
30
90 100 110 120
1
51
76 26
C14
R9
39
40
39
40
R10
C11
SMDS2
SMDS2+
Figure 18-2. TB9234 Target Board Configuration
18-3
DEVELOPMENT TOOLS
S3C9234/P9234
Table 18-1. Power Selection Settings for TB9234
Operating Mode
"To User_V
"
Comments
CC
Settings
The SMDS2/SMDS2+ supplies
to the target board
To User_VCC
V
CC
Off
On
Target
System
(evaluation chip) and the target
system.
TB9234
V
CC
SS
V
V
CC
SMDS2/SMDS2+
The SMDS2/SMDS2+ supplies
To User_VCC
V
only to the target board
CC
External
Off
On
Target
System
(evaluation chip). The target
system must have its own
power supply.
V
CC
TB9234
V
SS
V
CC
SMDS2/SMDS2+
NOTE: The following symbol in the "To User_V " Setting column indicates the electrical short (off) configuration:
CC
18-4
S3C9234/P9234
DEVELOPMENT TOOLS
SMDS2+ Selection (SAM8)
In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for
SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
Table 18-2. The SMDS2+ Tool Selection Setting
"SW1" Setting
SMDS2 SMDS2+
Operating Mode
R/W
SMDS2+
R/W
Target
Board
Table 18-3. Using Single Header Pins as the Input Path for External Trigger Sources
Target Board Part
Comments
Connector from
External Trigger
Sources of the
External
Triggers
Application System
Ch1
Ch2
You can connect an external trigger source to one of the two external
trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace
functions.
IDLE LED
The Green LED is ON when the evaluation chip (S3E9230) is in idle mode.
STOP LED
The Red LED is ON when the evaluation chip (S3E9230) is in stop mode.
18-5
DEVELOPMENT TOOLS
S3C9234/P9234
J101
J102
COM0/P0.0
COM2/P0.2
BIAS
1
3
5
7
2
4
6
COM1/P0.1
COM3/P0.3
VLC0
VLC2
GND
XIN
XTIN
RESET
P1.1/INT
P1.3/T1CLK
P1.5/TBOUT
P1.7/BUZ
P2.1/SO
P2.3
P2.5/INT
P2.7/INT
N.C
SEG31/P3.0
SEG29/P3.2
SEG27/P3.4
SEG25/P3.6
SEG23/P4.0
SEG21/P4.2
SEG19/P4.4
SEG17/P4.6
SEG15/P5.0
SEG13/P5.2
SEG11/P5.4
SEG9/P5.6
SEG7/P6.0
SEG5/P6.2
SEG3/P6.4
SEG1/P6.6
N.C
1
3
5
7
2
4
6
SEG30/P3.1
SEG28/P3.3
SEG26/P3.5
SEG24/P3.7
SEG23/P4.1
SEG20/P4.3
SEG18/P4.5
SEG16/P4.7
SEG14/P5.1
SEG12/P5.3
SEG10/P5.5
SEG8/P5.7
SEG6/P6.1
SEG4/P6.3
SEG2/P6.5
SEG0/P6.7
N.C
VLC1
8
8
V
DD
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
X
OUT
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
TEST
XTOUT
P1.0/INT
P1.2/INT
P1.4/TAOUT
P1.6/CLKOUT
P2.0/SCK
P2.2/SI
P2.4/INT
P2.6/INT
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
Figure 18-3. Connectors (J101, J102) for TB9234
Target Board
Target Board
J101
J102
2 33 34
J102
J101
1
33 34 1
2
Target Cable for 40-pin Connector
Part Name: AS40D-A
Order Code: SM6306
31 32 63 64
63 64 31 32
Figure 18-4. S3C9234 Probe Adapter for 64-QFP Package
18-6
S3C9 SERIES MASK ROM ORDER FORM
Product description:
Device Number: S3C9__________- ___________(write down the ROM code number)
Product Order Form: Package Pellet Wafer
Package Type: __________
Package Marking (Check One):
Standard
Custom A
(Max 10 chars)
Custom B
(Max 10 chars each line)
@ YWW
Device Name
@ YWW
@ YWW
SEC
Device Name
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities:
Deliverable
ROM code
Required Delivery Date
Quantity
Comments
–
Not applicable
See ROM Selection Form
Customer sample
Risk order
See Risk Order Sheet
Please answer the following questions:
For what kind of product will you be using this order?
F
New product
Upgrade of an existing product
Other
Replacement of an existing product
If you are replacing an existing product, please indicate the former product name
(
)
F
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price
Product quality
Features and functions
Delivery on time
Development system
Used same micom before
Technical support
Quality of documentation
Samsung reputation
Mask Charge (US$ / Won):
Customer Information:
____________________________
Company Name:
___________________
________________________
(Person placing the order)
Telephone number
_________________________
Signatures:
__________________________________
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C9 SERIES
REQUEST FOR PRODUCTION AT CUSTOMER RISK
Customer Information:
Company Name:
Department:
Telephone Number:
Date:
________________________________________________________________
________________________________________________________________
__________________________
__________________________
Fax: _____________________________
Risk Order Information:
Device Number:
S3C9________- ________ (write down the ROM code number)
Package:
Number of Pins: ____________
Package Type: _____________________
Intended Application:
Product Model Number:
________________________________________________________________
________________________________________________________________
Customer Risk Order Agreement:
We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order
product to be in full compliance with all SEC production specifications and, to this extent, agree to assume
responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule:
Risk Order Quantity:
Delivery Schedule:
_____________________ PCS
Delivery Date (s)
Quantity
Comments
Signatures:
_______________________________
(Person Placing the Risk Order)
_______________________________________
(SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C9234 MASK OPTION SELECTION FORM
Device Number:
S3C9234-__________(write down the ROM code number)
Attachment (Check one):
Diskette
PROM
Customer Checksum:
Company Name:
________________________________________________________________
________________________________________________________________
________________________________________________________________
Signature (Engineer):
Please answer the following questions:
F
Application (Product Model ID: _______________________)
Audio
Video
Telecom
LCD Databank
Caller ID
LCD
Game
Industrials
Home Appliance
Office Automation
Remocon
Other
Please describe in detail its application
__________________________________________________________________________
_
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3P9 SERIES OTP FACTORY WRITING ORDER FORM (1/2)
Product Description:
Device Number:
S3P9________-________(write down the ROM code number)
Product Order Form:
Package
Package Type:
Pellet
Wafer
If the product order form is package:
_____________________
Package Marking (Check One):
Standard
Custom A
(Max 10 chars)
Custom B
(Max 10 chars each line)
@ YWW
Device Name
@ YWW
@ YWW
SEC
Device Name
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantity:
ROM Code Release Date
Required Delivery Date of Device
Quantity
Please answer the following questions:
F
What is the purpose of this order?
New product development
Upgrade of an existing product
Other
Replacement of an existing microcontroller
If you are replacing an existing microcontroller, please indicate the former microcontroller name
(
)
F
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price
Product quality
Features and functions
Delivery on time
Development system
Used same micom before
Technical support
Quality of documentation
Samsung reputation
Customer Information:
Company Name:
___________________
Telephone number
_________________________
Signatures:
________________________
(Person placing the order)
__________________________________
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3P9234 OTP FACTORY WRITING ORDER FORM (2/2)
Device Number:
S3P9234 - __________(write down the ROM code number)
Customer Checksums:
Company Name:
_______________________________________________________________
________________________________________________________________
________________________________________________________________
Signature (Engineer):
Read Protection(1):
Yes
No
Please answer the following questions:
F
F
Are you going to continue ordering this device?
Yes
If so, how much will you be ordering?
No
_________________pcs
Application (Product Model ID: _______________________)
Audio
Video
Telecom
LCD Game
Office Automation
LCD Databank
Industrials
Remocon
Caller ID
Home Appliance
Other
Please describe in detail its application
__________________________________________________________________________
NOTES
1. Once you choose a read protection, you cannot read again the programming code from the EPROM.
2. OTP Writing will be executed in our manufacturing site.
3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors
occurred from the writing program.
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
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