S3P7434-QZ_技术文档

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

OVERVIEW

The S3C7414/C7424/C7434 single-chip CMOS microcontroller has been designed for very high performance

using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontroller).

With an A/D converter, LED direct drive pins, an 8-bit serial I/O interface, and an 8-bit timer/counter, the

S3C7414/C7424/C7434 offers you an excellent design solution for a wide variety of home appliance applications

— electric fans, cookers, boilers, and air conditioners, for example.

Up to 35 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts

provide fast response to internal and external events.

In addition, the S3C7414/C7424/C7434's advanced CMOS technology provides for low power consumption and a

wide operating voltage range.

OTP

The S3C7414/C7424/C7434 microcontroller is also available in OTP (One Time Programmable) version,

S3P7414/P7424/P7434. S3P7414/P7424/P7434 microcontroller has an on-chip 4-Kbyte one-time-programmable

EPROM instead of masked ROM. The S3P7414/P7424/P7434 is comparable to S3C7414/C7424/C7434, in

function, in D.C. electrical characteristics and in pin configuration.

DEVELOPMENT SUPPORT

The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based develop-

ment environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its

window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction

timing, and performance measurement applications.

The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and

accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard

hex files that also contain program control data for SMDS compatibility.

1-1

PRODUCT OVERVIEW

S3C7414/P7414/C7424/P7424/C7434/P7434

FEATURES SUMMARY

Memory

Built-in reset circuit (S3C7434 only)

Built-in power-on reset circuit

•

256 ´ 4-bit RAM

4,096 ´ 8-bit ROM

Interrupts

•

Five internal vectored interrupts

(INTB, INTT0, INTT1, INTS, INTAD)

35 I/O Pins

•

I/O: 31 pins including 8 LED direct drive pins

Three external vectored interrupts

(INT0, INT1, INT4)

(S3C7414/C7434)

18 pins including 8 LED direct drive pins

(S3C7424)

Two quasi-interrupts (INT2, INTW)

•

Input only: 4 pins

Bit Sequential Carrier

A/D Converter

•

Supports 16-bit serial data transfer in

arbitrary format

•

6-channel with 8-bit resolution

22.89 µs conversion speed at 4.19 MHz

Memory-Mapped I/O Structure

Data memory bank 15

•

Basic Timer

•

One 8-bit basic timer

Two Power-Down Modes

Watchdog timer functions

Four interval clock selection

•

Idle mode (only CPU clock stops)

Stop mode (system oscillation stops)

Timer/Counters

Oscillation Sources

•

Two 8-bit timer/counter (TC0, TC1)

Programmable 8-bit timer

External event counter

•

Crystal, Ceramic, or RC for system clock

Crystal, Ceramic: 0.4–6.0 MHz

RC: 4 MHz (typ)

Arbitrary clock frequency output

PWM output mode (TC1)

CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

Watch Timer

•

0.95, 1.91, 15.3 µs at 4.19 MHz

0.67, 1.33, 10.7 µs at 6.0 MHz

•

One watch timer 8-bit

Time interval generation: 0.5 s, 3.9 ms at

4.19 MHz

Operating Temperature

•

Four frequency outputs to BUZ pin

°

•

– 40 C to 85 C

8-bit Serial I/O Interface

Operating Voltage Range

•

8-bit transmit/receive mode

•

1.8 V to 5.5 V (S3C7414/C7424)

2.5 V to 5.5 V (S3C7434)

8-bit receive mode

LSB-first or MSB-first transmission selectable

Internal or external clock source

Package Type

42-pin SDIP, 44-pin QFP (S3C7414/C7434)

30-pin SDIP, 28-pin SOP (S3C7424)

•

1-2

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

S3C7434

Table 1-1. Comparision Table

S3C7414 S3C7424

Feature

Core

ROM

RAM

I/O

SAM47

Same

SAM47

4 K bytes

Same

256 nibbles

35 (4 input only)

None

Same

21 (3 input only)

None

35 (4 input only)

Built in/ Typ: 2.0 V

Same

POR ⁽¹⁾

SIO

8-bit SIO x 1

8-bit timer/counter

Same

Timer0

Same

Timer1(PWM)

8-bit timer/counter

(8-bit PWM x 1)

Same

Watchdog timer

Watch-dog

Same

4 selectable interval

ADC

8-bit x 6

None ⁽²⁾

8-bit x 4

Same

8-bit x 6

Same

AV_SS

Interrupt

External x 3

Internal x 5

External x 2

Internal x 5

External x 3

Internal x 5

Quasi x 2 (KS0–KS3)

Quasi x 1 ( – )

Quasi x 2 (KS0–KS3)

Power down

Oscillator

Stop/Idle

Same

Crystal, Ceramic, RC

0.4–6 MHz

1.8–5.5 V

Same

Operating frequency

Operating voltage

OTP/MTP

Same

1.8–5.5 V

Same

2.5–5.5 V

Same

OTP

Package

42SDIP/44QFP

30SDIP/28SOP

42SDIP/44QFP

NOTES

1. POR (power on reset)/Typ 2.0 V low voltage detector.

2. Internal A/D converter ground (bonded to V internally)

SS

1-3

PRODUCT OVERVIEW

S3C7414/P7414/C7424/P7424/C7434/P7434

BLOCK DIAGRAM

BASIC

TIMER

WATCH

TIMER

INT0, INT1, INT2,INT4

X

IN

X

OUT

8-BIT

TIMER/

RESET

P0.0/

P0.1/SO

P0.2/SI

P0.3/BUZ

SCK

COUNTER 0

I/O PORT 2

I/O PORT 0

INTERRUPT

CONTROL

BLOCK

INSTRUCTION

REGISTER

CLOCK

8-BIT

TIMER/

SERIAL

I/O

COUNTER 1

PROGRAM

COUNTER

INTERNAL

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

P4.0-4.3

P5.0-5.3

I/O PORT 4

I/O PORT 5

INTERRUPTS

INPUT

PORT 1

PROGRAM

STATUS WORD

INSTRUCTION DECODER

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

P2.0-P2.3/

AD0-AD3

I/O PORT 2

ARITHMETIC

AND

LOGIC UNIT

I/O PORT 6

I/O PORT 7

I/O PORT 8

STACK

POINTER

A/D

CONVERTER

AV

REF

P7.0-7.3

P3.0/AD4

P3.1/AD5

P3.2/CLO/TCL1

P3.3/PWM / TCLO1

P8.0/TCL0

P8.1/TCLO0

P8.2

I/O PORT 3

256x 4-BIT

DATA

MEMORY

4 K BYTE

PROGRAM

MEMORY

Figure 1-1. S3C7414/C7424/C7434Simplified Block Diagram

1-4

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

PIN ASSIGNMENTS

P8.2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

P2.0/AD0

P2.1/AD1

P2.2/AD2

P2.3/AD3

P3.0/AD4

P3.1/AD5

AVREF

1

2

3

4

5

6

7

8

P8.1/TCLO0

P8.0/TCL0

P7.3

P7.2

P7.1

P7.0

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

P0.1/SO

P0.0/SCK

P5.3

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0

9

S3C7414

10

11

12

13

14

15

16

17

18

19

20

21

VDD

VSS

XOUT

XIN

TEST

P4.1

P4.2

RESET

P4.3

(42-SDIP)

P5.0

P5.1

P5.2

Figure 1-2. S3C7414 Pin Assignment (42-SDIP)

1-5

PRODUCT OVERVIEW

S3C7414/P7414/C7424/P7424/C7434/P7434

P7.2

P7.1

P7.0

33

32

31

30

29

28

27

26

25

24

23

AVREF

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

1

2

3

4

5

6

7

8

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P4.0

VDD

VSS

XOUT

XIN

TEST

P4.1

P4.2

S3C7414

(44-QFP)

9

10

11

Figure 1-3. S3C7414 Pin Assignment (44-QFP)

1-6

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

VDD

P4.0

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VSS

XOUT

XIN

TEST

P4.1

P4.2

RESET

NC

1

2

3

4

5

6

7

8

P3.3/PWM/TCLO1

P3.2/CLO/TCL1

AVREF

NC

S3C7424

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

P4.3

P5.0

P5.1

P5.2

9

(30-SDIP)

10

11

12

13

14

15

P5.3

P0.0/SCK

P0.1/SO

Figure 1-4. S3C7424 Pin Assignment (30-SDIP)

VDD

P4.0

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VSS

XOUT

XIN

TEST

P4.1

P4.2

1

2

3

4

5

6

7

8

P3.3/PWM/TCLO1

P3.2/CLO/TCL1

AVREF

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

S3C7424

RESET

P4.3

P5.0

P5.1

P5.2

P5.3

9

(28-SOP)

10

11

12

13

14

P0.0/SCK

P0.1/SO

Figure 1-5. S3C7424 Pin Assignment (28-SOP)

1-7

PRODUCT OVERVIEW

S3C7414/P7414/C7424/P7424/C7434/P7434

P8.2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

P2.0/AD0

P2.1/AD1

P2.2/AD2

P2.3/AD3

P3.0/AD4

P3.1/AD5

AVREF

1

2

3

4

5

6

7

8

P8.1/TCLO0

P8.0/TCL0

P7.3

P7.2

P7.1

P7.0

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

P0.1/SO

P0.0/SCK

P5.3

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0

9

S3C7434

10

11

12

13

14

15

16

17

18

19

20

21

VDD

VSS

XOUT

XIN

TEST

P4.1

P4.2

RESET

P4.3

(42-SDIP)

P5.0

P5.1

P5.2

Figure 1-6. S3C7434 Pin Assignment (42-SDIP)

1-8

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

P7.2

P7.1

P7.0

33

32

31

30

29

28

27

26

25

24

23

AVREF

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

1

2

3

4

5

6

7

8

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P4.0

VDD

VSS

XOUT

XIN

TEST

P4.1

P4.2

S3C7434

(44-QFP)

9

10

11

Figure 1-7. S3C7434 Pin Assignment (44-QFP)

1-9

PRODUCT OVERVIEW

S3C7414/P7414/C7424/P7424/C7434/P7434

PIN DESCRIPTIONS

Table 1-2. S3C7414/C7434 Pin Descriptions

Description

Pin Name Pin Type

Number

Share Pin

P0.0

P0.1

P0.2

P0.3

I/O

4-bit I/O port.

24 (18)

25 (19)

26 (20)

27 (21)

SCK

SO

SI

1-bit or 4-bit read/write and test is possible.

Individual pins are software configurable as input or

output.

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

BUZ

P1.0

P1.1

P1.2

P1.3

I

4-bit input port.

28 (23)

29 (24)

30 (25)

31 (26)

INT0

INT1

INT2

INT4

1-bit and 4-bit read and test is possible.

3-bit pull-up resistors are individually assignable by

software to pins P1.0, P1.1, and P1.2.

P2.0

P2.1

P2.2

P2.3

I/O

4-bit I/O port.

N-channel open-drain output.

1-bit or 4-bit write and test is possible.

Individual pins are software configurable as AD input

or output.

1 (38)

2 (39)

3 (40)

4 (41)

AD0

AD1

AD2

AD3

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

P3.0

P3.1

P3.2

P3.3

I/O

Same as Port 0 (P0.0–P0.3)

5 (42)

6 (43)

8 (2)

AD4

AD5

CLO/TCL1

PWM/TCLO1

9 (3)

P4.0

P4.1

P4.2

P4.3

4-bit I/O ports.

10 (4)

16 (10)

17 (11)

19 (13)

20–23

–

Ports 4 and 5 can be configured individually as n-

channel open-drain or as CMOS push-pull output by

software.

1-bit and 4-bit read/write and test is possible.

Ports 4 and 5 can be paired to enable 8-bit data

transfer.

P5.0–P5.3

(14–17)

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

P6.0–P6.3

P7.0–P7.3

I/O

Same as Port 0 except port 8 is a 3-bit I/O port

32–35

(27–30)

36–39

KS0–KS3

–

(31–34)

40 (35)

41 (36)

42 (37)

P8.0

P8.1

P8.2

TCL0

TCLO0

–

1-10

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

Table 1-2. S3C7414/C7434 Pin Descriptions (Continued)

Pin Name Pin Type

Description

Number

Share Pin

I/O

Serial I/O interface clock signal

24 (18)

P0.0

SCK

SO

I/O

Serial data output

Serial data input

25 (19)

26 (20)

27 (21)

P0.1

P0.2

P0.3

SI

BUZ

2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the

watch timer clock frequency of 32.768 kHz

INT0, INT1

I

External interrupts. The triggering edge for INT0 and

INT1 is selectable. Only INT0 is synchronized with the

system clock.

28–29

(23–24)

P1.0, P1.1

INT2

INT4

I

Quasi-interrupt input with rising edge detection

30 (25)

31 (26)

P1.2

P1.3

External interrupts with detection of rising and falling

edges

AD0–AD3

AD4–AD5

I/O

A/D converter analog inputs

1–4

(38–41)

5–6

P2.0–P2.3

P3.0–P3.1

(42–43)

TCL0

I/O

External clock input for timer/counter0

Timer/counter clock output

Clock output

40 (35)

41 (36)

8 (2)

P8.0

P8.1

TCLO0

CLO

P3.2

TCL1

External clock input for timer/counter1

PWM output

8 (2)

P3.2

PWM

9 (3)

P3.3

TCLO1

KS0–KS3

Timer/counter clock output1

Quasi-interrupt input with falling edge detection

9 (3)

P3.3

32–35

P6.0–P6.3

(27–30)

V_DD

V_SS

–

I

Main power supply

Ground

11 (5)

12 (6)

–

Reset signal

18 (12)

RESET

X_IN, X_out

–

Crystal, ceramic, or RC oscillator signal for system

clock.

14, 13

(8, 7)

AV_REF

TEST

NC

–

I

A/D converter analog reference voltage

7 (1)

15 (9)

–

Test signal input (must be connected to V_SS

)

–

No connection (no bonding pin)

(22, 44)

NOTE: Parentheses indicate 44-QFP pin number.

1-11

PRODUCT OVERVIEW

Pin Name Pin Type

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 1-3. S3C7424 Pin Descriptions

Description

Number

Share Pin

P0.0

P0.1

P0.2

P0.3

I/O

4-bit I/O port.

14 (13)

15 (14)

16 (15)

17 (16)

SCK

SO

SI

1-bit or 4-bit read/write and test is possible.

Individual pins are software configurable as input or

output.

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

BUZ

P1.0

P1.1

P1.2

I

4-bit input port.

18 (17)

19 (18)

20 (19)

INT0

INT1

INT2

1-bit and 4-bit read and test is possible.

3-bit pull-up resistors are individually assignable by

software to pins P1.0, P1.1, and P1.2.

P2.0

P2.1

P2.2

P2.3

I/O

4-bit I/O port.

N-channel open-drain output.

1-bit or 4-bit write and test is possible.

Individual pins are software configurable as AD input

or output.

21 (20)

22 (21)

23 (22)

24 (23)

AD0

AD1

AD2

AD3

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

P3.2

P3.3

I/O

Same as Port 0 (P0.0–P0.3)

27 (25)

28 (26)

CLO/TCL1

PWM/TCLO1

P4.0

P4.1

P4.2

P4.3

4-bit I/O ports.

29 (27)

5 (5)

6 (6)

–

Ports 4 and 5 can be configured individually as n-

channel open-drain or as CMOS push-pull output by

software.

9 (8)

1-bit and 4-bit read/write and test is possible.

Ports 4 and 5 can be paired to enable 8-bit data

transfer.

P5.0–P5.3

10–13

(9–12)

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

1-12

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

Table 1-3. S3C7424 Pin Descriptions (Continued)

Pin Name Pin Type

Description

Number

Share Pin

I/O

Serial I/O interface clock signal

14 (13)

P0.0

SCK

SO

I/O

Serial data output

Serial data input

15 (14)

16 (15)

17 (16)

P0.1

P0.2

P0.3

SI

BUZ

2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the

watch timer clock frequency of 32.768 kHz

INT0, INT1

I

External interrupts. The triggering edge for INT0 and

INT1 is selectable. Only INT0 is synchronized with the

system clock.

18, 19

(17, 18)

P1.0, P1.1

INT2

I

Quasi-interrupt input with rising edge detection

A/D converter analog inputs

20 (19)

P1.2

AD0–AD3

I/O

21–24

P2.0–P2.3

(20–23)

CLO

I/O

–

Clock output

27 (25)

28 (26)

30 (28)

1 (1)

P3.2

P3.3

–

TCL1

PWM

TCLO1

External clock input for timer/counter1

PWM output

Timer/counter clock output1

Main power supply

Ground

V

DD

V

SS

–

I

Reset signal

7 (7)

–

RESET

X_IN, X_OUT

–

Crystal, ceramic, or RC oscillator signal for system

clock.

3, 2

(3, 2)

–

AV_REF

TEST

NC

–

I

Internal A/D converter analog reference voltage

26 (24)

4 (4)

–

Test signal input (must be connected to V_SS

)

–

No connection (no bonding pin)

8, 25

NOTE: Parentheses indicate 28-SOP pin number.

1-13

PRODUCT OVERVIEW

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 1-4. Overview of S3C7414/C7424/C7434Pin Data

Pin Names

Share Pins

I/O Type

Reset Value

Input

Circuit Type

Type D

P0.0–P0.3

I/O

I

SCK, SO, SI, BUZ

INT0 ^(note)

INT1 ^(note)

INT2 ^(note)

P1.0

P1.1

P1.2

Input

Type A-1

P1.3

INT4

I

Input

AD input

Input

Type A

P2.0–P2.3

AD0–AD3

I/O

Type F-3

P3.0

P3.1

P3.2

P3.3

AD4

AD5

CLO/TCL1

TCLO1/PWM

Type F

Type D

P4.0–P4.3

P5.0–P5.3

–

I/O

Input

Type E

KS0 ^(note)

KS1 ^(note)

KS2 ^(note)

KS3 ^(note)

Type D

P6.0

P6.1

P6.2

P6.3

I/O

Type D

P7.0–P7.3

–

Input

TCL0 ^(note)

TCLO0

–

P8.0

P8.1

P8.2

V_DD, V_SS

X_IN, X_OUT

–

I

–

Type B-2 ^(note)

–

RESET

AV_REF

–

TEST

NC

–

I

–

NOTE: A noise filter circuit is built-in.

1-14

S3C7414/P7414/C7424/P7424/C7434/P7434

PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

V

DD

P-CHANNEL

1M

W

IN

RESET

7pF

-

N CHANNEL

Figure 1-10. Pin Circuit Type B-2

Figure 1-8. Pin Circuit Type A

V

DD

V

DD

P-CHANNEL

OUT

PULL-UP

RESISTOR

ENABLE

DATA

N-CHANNEL

OUTPUT

DISABLE

IN

CIRCUIT TYPE A

Figure 1-9. Pin Circuit Type A-1

Figure 1-11. Pin Circuit Type C

1-15

PRODUCT OVERVIEW

KS57C4104/P4104/C4204/P4204 MICROCONTROLLER (Preliminary Spec)

V

DD

V

DD

PULL-UP

RESISTOR

ENABLE

PULL-UP

RESISTOR

ENABLE

DATA

CIRCUIT

TYPE C

IN/OUT

OUTPUT

DISABLE

DATA

CIRCUIT

TYPE C

I/O

OUTPUT

DISABLE

DATA

CIRCUIT TYPE A

TO ADC

ADC INPUT SELECT

Figure 1-12. Pin Circuit Type D

Figure 1-14. Pin Circuit Type F

V

DD

V

DD

V

DD

PNE

PULL-UP

RESISTOR

ENABLE

PULL-UP

RESISTOR

ENABLE

IN/OUT

DATA

OUTPUT

DISABLE

IN/OUT

DATA

OUTPUT

DISABLE

DATA

TO ADC

INPUT

ADC INPUT SELECT

Figure 1-15. Pin Circuit Type F-3

Figure 1-13. Pin Circuit Type E

1-16

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESS SPACES

2

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM maps for S3C7 devices are mask programmable at the factory. In its standard configuration, the device's

4096 ´ 8-bit program memory has four areas that are directly addressable by the program counter (PC):

— 16-byte area for vector addresses

— 16-byte general-purpose area

— 96-byte instruction reference area

— 3968-byte general-purpose area

General-Purpose Program Memory

Two program memory areas are allocated for general-purpose use: One area is 16 bytes and the other is 3968

bytes.

Vector Addresses

A 16-byte vector address area is used to store the vector addresses required to execute system resets and

interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the

enable memory bank (EMB) and enable register bank (ERB) flags that are used to initialize the corresponding

service routines. The 16-byte area can be used alternately as general-purpose ROM.

REF Instructions

Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF

instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte

instructions, and three-byte instructions which are stored in the look-up table. Unused look-up table addresses

can be used as general-purpose ROM.

Table 2-1. Program Memory Address Ranges

ROM Area Function

Vector address area

Address Ranges

0000H–000FH

0010H–001FH

0020H–007FH

0080H–0FFFH

Area Size (in Bytes)

16

General-purpose program memory

REF instruction look-up table area

General-purpose program memory

96

3968

2-1

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

GENERAL-PURPOSE MEMORY AREAS

The 16-byte area at ROM locations 0010H–001FH and the 3968-byte area at ROM locations 0080H–0FFFH are

used as general-purpose program memory. Unused locations in the vector address area and REF instruction

look-up table areas can be used as general-purpose program memory. However, care must be taken not to

overwrite live data when writing programs that use special-purpose areas of the ROM.

VECTOR ADDRESS AREA

The 16-byte vector address area of the ROM is used to store the vector addresses for executing system resets

and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable

memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service

routines. 16-byte vector addresses are organized as follows:

EMB

PC7

ERB

PC6

0

PC11

PC3

PC10

PC2

PC9

PC1

PC8

PC0

PC5

PC4

To set up the vector address area for specific programs, use the instruction VENTn. The programming tip on the

next page explains how to do this.

0000H

7

6

5

4

3

2

1

0

VECTOR

ADDRESS AREA

(16 Bytes)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

000EH

RESET

INTB/INT4

INT0

000FH

0010H

GENERAL-PURPOSE

AREA

(16 Bytes)

001FH

0020H

INSTRUCTION

REFERENCE AREA

(96 Bytes)

INT1

INTS

007FH

0080H

INTT0

INTT1

INTAD

GENERAL-PURPOSE

AREA

(3968 Bytes)

0FFFH

Figure 2-1. ROM Address Structure

Figure 2-2. Vector Address Map

2-2

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESS SPACES

+

PROGRAMMING TIP — Defining Vectored Interrupts

The following examples show you several ways you can define the vectored interrupt and instruction reference

areas in program memory:

1. When all vector interrupts are used:

ORG

0000H

;

VENT0

VENT1

VENT2

VENT3

VENT4

VENT5

VENT6

VENT7

1,0,RESET

0,0,INTB

0,0,INT0

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address

; EMB ¬ 0, ERB ¬ 0; Jump to INT0 address

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address

; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTAD address

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

0,0,INTAD

2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations

must be skipped with the assembly instruction ORG so that jumps will address the correct locations:

ORG

0000H

;

VENT0

VENT1

1,0,RESET

0,0,INTB

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address

;

ORG

0006H

; INT0 interrupt not used

VENT3

VENT4

0,0,INT1

0,0,INTS

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address

;

ORG

VENT6

VENT7

000CH

0,0,INTT1

0,0,INTAD

; INTT0 interrupt not used

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTAD address

ORG

0010H

2-3

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — Defining Vectored Interrupts (Continued)

3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not

written by a ORG instruction as in Example 2, a CPU malfunction will occur:

ORG

0000H

;

VENT0

VENT1

VENT3

VENT4

VENT5

VENT6

VENT7

1,0,RESET

0,0,INTB

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

0,0,INTAD

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address

; EMB ¬ 0, ERB ¬ 0; Jump to INT0 address

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address

; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address

;

ORG

0010H

General-purpose ROM area

In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but

VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU

malfunction to occur.

2-4

S3C7414/P7414/C7424/P7424/C7434/P7434

INSTRUCTION REFERENCE AREA

ADDRESS SPACES

Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in ad-

dresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or

look-up table. Locations in the REF look-up table may contain two one-byte instructions, a single two-byte

instruction, or three-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are

referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the

reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are

three ways to the REF instruction:

By using REF instructions to execute instructions larger than one byte, you can improve program execution time

considerably by reducing the number of program steps. In summary, there are three ways you can use the REF

instruction:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions,

— Branching to any location by referencing a branch instruction stored in the look-up table,

— Calling subroutines at any location by referencing a call instruction stored in the look-up table.

+

PROGRAMMING TIP — Using the REF Look-Up Table

Here is one example of how to use the REF instruction look-up table:

ORG

0020H

;

JMAIN

KEYCK

WATCH

INCHL

TJP

BTSF

TCALL

LD

INCS

•

MAIN

; 0, MAIN

KEYFG

CLOCK

@HL,A

HL

; 1, KEYFG CHECK

; 2, CALL CLOCK

; 3, (HL) ¬ A

•

ABC

LD

ORG

EA,#00H

0080

; 47, EA ¬ #00H

;

MAIN

NOP

•

REF

KEYCK

JMAIN

WATCH

INCHL

; BTSF KEYFG (1-byte instruction)

; KEYFG = 1, jump to MAIN (1-byte instruction)

; KEYFG = 0, call CLOCK (1-byte instruction)

; LD @HL,A

; INCS HL

REF

ABC

; LD EA,#00H (1-byte instruction)

•

2-5

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

DATA MEMORY (RAM)

OVERVIEW

In its standard configuration, the 256 ´ 4-bit data memory has three areas:

— 32 ´ 4-bit working register area

— 224 ´ 4-bit general-purpose area in bank 0 (also used as stack area)

— 128 ´ 4-bit area for memory-mapped I/O addresses

To make it easier to reference, the data memory area has two memory banks — bank 0 and bank 15. The select

memory bank instruction (SMB) is used to select the bank you want to select as working data memory. Data

stored in RAM locations are 1-, 4-, and 8-bit addressable.

Initialization values for the data memory area are not defined by hardware and must therefore be initialized by

program software following RESET. However, when RESET signal is generated in power-down mode, the data

memory contents are held.

000H

WORKING REGISTER

(32 x 4 Bits)

01FH

020H

BANK 0

GENERAL-PURPOSE

REGISTER

AND STACK AREA

(224 x 4 Bits)

0FFH

F80F

~

PERIPHERAL CONTROL

AND DATA REGISTERS

(128 x 4 Bits)

BANK 15

FFFH

Figure 2-3. Data Memory (RAM) Map

2-6

S3C7414/P7414/C7424/P7424/C7434/P7434

Memory Banks 0 and 15

ADDRESS SPACES

Bank 0

(000H–0FFH)

The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;

the next 224 nibbles (020H–0FFH) can be used both as stack area and as

general-purpose data memory. Use the stack area for implementing

subroutine calls and returns, and for interrupt processing.

Bank 15

(F80H–FFFH)

The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed

RAM locations for each peripheral hardware register: the port latches, timers,

peripherals controls, etc. are mapped into this area.

Data Memory Addressing Modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0 or 15. When the

EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or

indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0 and bank 15.

With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic one, all

two data memory banks can be accessed according to the current SMB value.

For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to

address RAM locations, remember to use the even-numbered register address as the instruction operand.

Working Registers

The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2,

and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.

Register A is used as a 4-bit accumulator and register pair EA is an 8-bit extended accumulator. The carry flag

bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for

indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable

to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.

Table 2-2. Data Memory Organization and Addressing

Addresses

000H–01FH

020H–0FFH

F80H–FFFH

Register Areas

Working registers

Bank

EMB Value

SMB Value

0

0, 1

0

Stack and general-purpose registers

Peripheral hardware registers

15

0, 1

15

+

PROGRAMMING TIP — Clearing Data Memory Bank 0

Clear bank 0 of the data memory area:

RAMCLR

RMCL0

BITS

SMB

LD

EMB

0

HL,#10H

A,#0H

@HL,A

HL

; RAM (010H–0FFH) clear

INCS

JR

RMCL0

2-7

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

WORKING REGISTERS

Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store

intermediate results during program execution, as well as pointer values used for indirect addressing. Unused

registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-

bit units or, using paired registers, as 8-bit units.

000H

0001

002H

A

E

L

003H

H

X

WORKING

REGISTER

BANK 0

004H

005H

006H

007H

008H

W

Z

DATA

MEMORY

BANK 0

Y

REGISTER

BANK 1

A

Y

...

00FH

010H

REGISTER

BANK 2

017H

018H

REGISTER

BANK 3

01FH

Figure 2-4. Working Register Map

2-8

S3C7414/P7414/C7424/P7424/C7434/P7434

Working Register Banks

ADDRESS SPACES

For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2,

and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection

instruction (SRB n) and by setting the status of the register bank enable flag (ERB).

Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou-

tines. Following this convention helps to prevent possible data corruption during program execution due to con-

tention in register bank addressing.

Table 2-3. Working Register Organization and Addressing

ERB Setting

SRB Settings

Selected Register Bank

3

2

1

x

0

1

0

x

0

1

0

1

0

1

0

Always set to bank 0

Bank 0

0

Bank 1

Bank 2

Bank 3

NOTE: 'x' means don't care.

Paired Working Registers

Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and

A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data

manipulation.

The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z

always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit

registers or four 8-bit double registers in each of the four working register banks.

(MSB)

(LSB)

(MSB)

(LSB)

Y

W

H

E

Z

X

L

A

Figure 2-5. Register Pair Configuration

2-9

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

Special-Purpose Working Registers

Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also

be used as a 1-bit accumulator.

8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register

serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working

registers as program loop counters by letting you transfer a value to the L register and increment or decrement it

using a single instruction.

1 BIT

ACCUMULATOR

-

C

4 BIT

ACCUMULATOR

-

A

8 BIT

ACCUMULATOR

-

EA

Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator

Recommendation for Multiple Interrupt Processing

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

2-10

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESS SPACES

+

PROGRAMMING TIP — Selecting the Working Register Area

The following examples show the correct programming method for selecting working register area:

1. When ERB = "0":

VENT2

;

1,0,INT0

; EMB ¬ 1, ERB ¬ 0, Jump to INT0 address

INT0

PUSH

SRB

PUSH

SMB

LD

INCS

LD

POP

IRET

SB

2

HL

WX

YZ

EA

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

EA

YZ

WX

HL

SB

; PUSH current SMB, SRB

; Instruction does not execute because ERB = "0"

; PUSH HL register contents to stack

; PUSH WX register contents to stack

; PUSH YZ register contents to stack

; PUSH EA register contents to stack

; POP EA register contents from stack

; POP YZ register contents from stack

; POP WX register contents from stack

; POP HL register contents from stack

; POP current SMB, SRB

The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an

interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and

SRB values, as shown in Example 2 below.

2. When ERB = "1":

VENT2

;

1,1,INT0

; EMB ¬ 1, ERB ¬ 1, Jump to INT0 address

INT0

PUSH

SRB

SMB

LD

INCS

LD

POP

IRET

SB

2

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

SB

; Store current SMB, SRB

; Select register bank 2 because of ERB = "1"

; Restore SMB, SRB

2-11

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

STACK OPERATIONS

STACK POINTER (SP)

The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data

memory set aside for temporary storage of stack addresses. The SP can be read or written by 8-bit control

instructions.When addressing the SP, bit 0 must always remain cleared to logic zero.

F80H

F81H

SP3

SP7

SP2

SP6

SP1

SP5

"0"

SP4

There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack

(pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the

last data to be written to the stack.

The program counter contents and program status word are stored in the stack area prior to the execution of a

CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out)

type. The stack area is located in general-purpose data memory bank 0.

During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine

has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed.

The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the en-

able memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas

can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s).

Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack

pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.

NOTE

A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or

interrupt routines are used continuously, the stack area should be set in accordance with the maximum

number of subroutine levels. To do this, estimate the number of nibbles that will be used for the

subroutines or interrupts and set the stack area correspondingly.

+

PROGRAMMING TIP — Initializing the Stack Pointer

To initialize the stack pointer (SP):

1. When EMB = "1":

SMB

LD

15

EA,#00H

SP,EA

; Select memory bank 15

; Bit 0 of accumulator A is always cleared to "0"

; Stack area initial address (0FFH) ¬ (SP) – 1

2. When EMB = "0":

LD

EA,#00H

SP,EA

; Memory addressing area (000H–07FH, F80H–FFFH)

2-12

S3C7414/P7414/C7424/P7424/C7434/P7434

PUSH OPERATIONS

ADDRESS SPACES

Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the

stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number

determined by the type of push operation and then points to the next available stack location.

PUSH Instructions

A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are

referenced by the stack pointer: one for the upper register value and another for the lower register. After the

PUSH has executed, the SP is decremented by two and points to the next available stack location.

CALL Instructions

When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit

stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag

are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up

to the number of levels permitted in the stack.

Interrupt Routines

An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the

stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is

decremented by six and points to the next available stack location. During an interrupt sequence, subroutines

may be nested up to the number of levels which are permitted in the stack area.

INTERRUPT

PUSH

(After PUSH, SP

CALL

(After CALL, SP

(When INT is acknowledged,

SP

SP – 6)

SP – 2)

SP – 6)

SP – 6

SP – 5

SP – 4

SP – 3

SP – 2

SP – 1

SP

SP – 6

SP – 5

SP – 4

SP – 3

SP – 2

SP – 1

SP

PC11– PC8

0

PC3 – PC0

PC7 – PC4

PC3 – PC0

PC7 – PC4

SP – 2

SP – 1

SP

LOWER REGISTER

UPPER REGISTER

0

EMB ERB

IS1 IS0 EMB ERB

PSW

C

0

C

SC2 SC1 SC0

Figure 2-7. Push-Type Stack Operations

2-13

ADDRESS SPACES

POP OPERATIONS

S3C7414/P7414/C7424/P7424/C7434/P7434

For each push operation there is a corresponding pop operation to write data from the stack back to the source

register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET;

for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined

by the type of operation and points to the next free stack location.

POP Instructions

A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and

SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register.

After the POP has executed, the SP is incremented by two and points to the next free stack location.

RET and SRET Instructions

The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP

to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and

the ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack

location.

IRET Instructions

The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-

bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has

executed, the SP is incremented by six and points to the next free stack location.

POP

SP + 2)

RET OR SRET

(P SP + 6)

IRET

(SP SP + 6)

(SP

SP

LOWER REGISTER

UPPER REGISTER

SP

PC11 – PC8

SP + 1

SP + 2

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

PC3 – PC0

PC7 – PC4

PC3 – PC0

PC7 – PC4

0

EMB ERB

IS1 IS0 EMB ERB

PSW

0

C

SC2 SC1 SC0

Figure 2-8. Pop-Type Stack Operations

2-14

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESS SPACES

BIT SEQUENTIAL CARRIER (BSC)

The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM

control instructions. RESET clears all BSC bit values to logic zero.

Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing

(memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit

data by moving the bit location sequentially and then incrementing or decrementing the value of the L register.

BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names

BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately.

If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L

register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3.

Table 2-4. BSC Register Organization

Name

BSC0

BSC1

BSC2

BSC3

Address

FC0H

Bit 3

Bit 2

Bit 1

Bit 0

BSC0.3

BSC1.3

BSC2.3

BSC3.3

BSC0.2

BSC1.2

BSC2.2

BSC3.2

BSC0.1

BSC1.1

BSC2.1

BSC3.1

BSC0.0

BSC1.0

BSC2.0

BSC3.0

FC1H

FC2H

FC3H

+

PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data

To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:

BITS

SMB

LD

SMB

LD

LDB

INCS

JR

EMB

15

EA,#37H

BSC0,EA

EA,#59H

BSC2,EA

0

L,#0H

C,BSC0.@L

P3.0,C

L

;

; BSC0 ¬ A, BSC1 ¬ E

;

; BSC2 ¬ A, BSC3 ¬ E

;

AGN

; P3.0 ¬ C

AGN

RET

2-15

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

PROGRAM COUNTER (PC)

A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a

reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address.

Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-

byte REF instruction which is used to reference instructions stored in the ROM.

PROGRAM STATUS WORD (PSW)

The program status word (PSW) is an 8-bit word, that defines system status and program execution status and

which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW

values are mapped as follows:

(MSB)

IS1

(LSB)

ERB

SC0

FB0H

FB1H

IS0

EMB

SC1

C

SC2

The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific

bit or bits being addressed. The PSW can be addressed during program execution regardless of the current

value of the enable memory bank (EMB) flag.

Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the in-

terrupt has been processed, the PSW values are popped from the stack back to the PSW address.

When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the

carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all

cleared to logic zero.

Table 2-5. Program Status Word Bit Descriptions

PSW Bit Identifier

Description

Interrupt status flags

Enable memory bank flag

Enable register bank flag

Carry flag

Bit Addressing

Read/Write

R/W

IS1, IS0

1, 4

1

EMB

R/W

ERB

C

1

R/W

1

R/W

SC2, SC1, SC0

Program skip flags

8

R

2-16

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERRUPT STATUS FLAGS (IS0, IS1)

ADDRESS SPACES

PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1

flags directly using 1-bit RAM control instructions

By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process

multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit

determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status

flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined

by the IPR.

When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically

incremented to the next status. Then, when the interrupt service routine ends with an IRET instruction, IS0 and

IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings.

Table 2-6. Interrupt Status Flag Bit Settings

IS1

Value

IS0

Value

Status of Currently

Executing Process

Effect of IS0 and IS1 Settings

on Interrupt Request Control

0

1

0

1

All interrupt requests are serviced

Only high-priority interrupt as determined in the interrupt

priority register (IPR) is serviced

1

0

1

2

–

No more interrupt requests are serviced

Not applicable; these bit settings are undefined

Since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter-

rupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI in-

struction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI

instruction to re-enable interrupt processing.

+

PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing

The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:

INTB

DI

; Disable interrupt

BITR

BITS

EI

IS1

IS0

; IS1 ¬ 0

; Allow interrupts according to IPR priority level

; Enable interrupt

2-17

ADDRESS SPACES

EMB FLAG (EMB)

S3C7414/P7414/C7424/P7424/C7434/P7434

The EMB flag occupies bit location 1 of the PSW in RAM bank 15. The EMB flag is used to allocate specific

address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it

controls the addressing mode for data memory banks 0 or 15.

When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H–07FH of

memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", you can access gen-

eral-purpose areas of bank 0 and bank 15 by using the appropriate SMB value.

+

PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks

EMB flag settings for memory bank selection:

1. When EMB = "0":

SMB

LD

SMB

LD

0

; Non-essential instruction, since EMB = "0"

; (F90H) ¬ A, bank 15 is selected

; (034H) ¬ A, bank 0 is selected

; Non-essential instruction, since EMB = "0"

; (020H) ¬ A, bank 0 is selected

90H,A

34H,A

15

20H,A

90H,A

; (F90H) ¬ A, bank 15 is selected

2. When EMB = "1":

SMB

LD

SMB

LD

0

; Select memory bank 0

90H,A

34H,A

15

20H,A

90H,A

; (090H) ¬ A, bank 0 is selected

; (034H) ¬ A, bank 0 is selected

; Select memory bank 15

; Program error, but assembler does not detect it

; (F90H) ¬ A, bank 15 is selected

2-18

S3C7414/P7414/C7424/P7424/C7434/P7434

ERB FLAG (ERB)

ADDRESS SPACES

The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the

ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank

selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area,

regardless of the current value of the register bank selection register (SRB).

When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This

automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in

program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is

executed.

During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW

bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored

interrupt are defined using VENTn instructions.

+

PROGRAMMING TIP — Using the ERB Flag to Select Register Banks

ERB flag settings for register bank selection:

1. When ERB = "0":

SRB

1

; Register bank 0 is selected (since ERB = "0", the

; SRB is configured to bank 0)

; Bank 0 EA ¬ #34H

; Bank 0 HL ¬ EA

; Register bank 0 is selected

; Bank 0 YZ ¬ EA

LD

SRB

LD

SRB

LD

EA,#34H

HL,EA

2

YZ,EA

3

; Register bank 0 is selected

; Bank 0 WX ¬ EA

WX,EA

2. When ERB = "1":

SRB

LD

SRB

LD

SRB

LD

1

; Register bank 1 is selected

; Bank 1 EA ¬ #34H

EA,#34H

HL,EA

2

YZ,EA

3

; Bank 1 HL ¬ Bank 1 EA

; Register bank 2 is selected

; Bank 2 YZ ¬ BANK2 EA

; Register bank 3 is selected

; Bank 3 WX ¬ Bank 3 EA

WX,EA

2-19

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

SKIP CONDITION FLAGS (SC2, SC1, SC0)

The skip condition flags SC2, SC1, and SC0 indicate the current program skip conditions and are set and reset

automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions.

Direct manipulation of the SC2, SC1, and SC0 bits is not allowed.

CARRY FLAG (C)

The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving

a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations

involving bit-addressed data memory.

If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry

flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained

during power-down mode, but when normal operating mode resumes, its value is undefined.

The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other

bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag.

Table 2-7. Valid Carry Flag Manipulation Instructions

Operation Type

Instructions

Carry Flag Manipulation

Set carry flag to "1"

Direct manipulation

SCF

RCF

CCF

Clear carry flag to "0" (reset carry flag)

Invert carry flag value (complement carry flag)

Test carry and skip if C = "1"

BTST C

LDB (operand) ⁽¹⁾,C

LDB C,(operand) ⁽¹⁾

BAND C,(operand) ⁽¹⁾

Bit transfer

Load carry flag value to the specified bit

Load contents of the specified bit to carry flag

Boolean manipulation

AND the specified bit with contents of carry flag and save

the result to the carry flag

BOR C,(operand) ⁽¹⁾

BXOR C,(operand) ⁽¹⁾

OR the specified bit with contents of carry flag and save

the result to the carry flag

XOR the specified bit with contents of carry flag and save

the result to the carry flag

INTn ⁽²⁾

IRET

Interrupt routine

Save carry flag to stack with other PSW bits

Return from interrupt

Restore carry flag from stack with other PSW bits

NOTES:

1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b.

2. 'INTn' refers to the specific interrupt being executed and is not an instruction.

2-20

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESS SPACES

+

PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator

1. Set the carry flag to logic one:

SCF

; C ¬ 1

LD

ADC

EA,#0C3H

HL,#0AAH

EA,HL

; EA ¬ #0C3H

; HL ¬ #0AAH

; EA ¬ #0C3H + #0AAH + #1H, C ¬ 1

2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0:

LD

H,#3H

; Set the upper four bits of the address to the H register

; value

LDB

BAND

LDB

C,@H+0FH.3

C,P3.3

P5.0,C

; C ¬ bit 3 of 3FH

; C ¬ C AND P3.3

; Output result from carry flag to P5.0

2-21

ADDRESS SPACES

S3C7414/P7414/C7424/P7424/C7434/P7434

NOTES

2-22

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESS MODES

3

ADDRESSING MODES

OVERVIEW

The enable memory bank flag, EMB, controls the two addressing modes for data memory. When you enable the

EMB flag, you can address the entire RAM area. When you clear the EMB flag to logic zero, the addressable

RAM is restricted to specific areas.

The EMB flag works in connection with the select memory bank instruction, SMB n. You will recall that the SMB

n instruction is used to select RAM bank 0 or 15. The SMB setting is always contained in the upper four bits of a

12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to the

memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0 or 15.

Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used.

In addition, there are several RAM locations that can always be addressed using specific addressing methods,

regardless of the current EMB flag setting.

Here are a few things to remember about addressing data memory areas:

— When you address peripheral hardware locations in bank 15, you can use the mnemonic for the memory-

mapped hardware component as the operand in place of the actual address location.

— Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing.

— With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the

instruction specifies a register which contains the operand's address.

3-1

ADDRESS MODES

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESSING

MODE

DA

DA.b

@HL

@H + DA.b

@WX

@WL

mema.b memb.@L

RAM

EMB = 0

EMB = 1

EMB = 0

EMB = 1

X

AREAS

000H

WORKING

REGISTERS

01FH

020H

07FH

080H

SMB = 0

BANK 0

(GENERAL

REGISTERS

AND STACK)

0FFH

F80H

FB0H

FBFH

FC0H

BANK 15

(PERIPHERAL

HARDWARE

REGISTERS)

SMB = 15

FF0H

FFFH

NOTES

1. 'X' means don't care.

2. Blank columns indicate RAM areas that are not addressable, given the addressing method

and enable memory bank (EMB) flag setting shown in the column headers.

Figure 3-1. RAM Address Structure

3-2

S3C7414/P7414/C7424/P7424/C7434/P7434

EMB AND ERB INITIALIZATION VALUES

ADDRESS MODES

The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt

vector address.

When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, ini-

tializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is

written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the

interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine

has completed.

At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by

using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR)

despite the current SMB setting.

+

PROGRAMMING TIP — Initializing the EMB and ERB Flags

The following assembly instructions show how to initialize the EMB and ERB flag settings:

ORG

VENT0

VENT1

VENT2

VENT3

VENT4

VENT5

VENT6

VENT7

•

0000H

; ROM address assignment

1,0,RESET

0,1,INTB

0,1,INT0

0,1,INT1

0,1,INTS

0,1,INTT0

0,1,INTT1

0,1,INTAD

; EMB ¬ 1, ERB ¬ 0, branch RESET

; EMB ¬ 0, ERB ¬ 1, branch INTB

; EMB ¬ 0, ERB ¬ 1, branch INT0

; EMB ¬ 0, ERB ¬ 1, branch INT1

; EMB ¬ 0, ERB ¬ 1, branch INTS

; EMB ¬ 0, ERB ¬ 1, branch INTT0

; EMB ¬ 0, ERB ¬ 1, branch INTT1

; EMB ¬ 0, ERB ¬ 1, branch INTAD

•

RESET

BITR

EMB

3-3

ADDRESS MODES

S3C7414/P7414/C7424/P7424/C7434/P7434

ENABLE MEMORY BANK SETTINGS

EMB = "1"

When you set the enable memory bank flag, EMB, to logic one, you can address the data memory bank

specified by the select memory bank (SMB) value (0 or 15) using 1-, 4-, or 8-bit instructions. You can use both

direct and indirect addressing modes. The addressable RAM areas when the EMB flag is set to logic one are as

follows:

If SMB = 0,

000H–0FFH

F80H–FFFH

If SMB = 15,

EMB = "0"

When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of

the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is

used.

If EMB = "0", the addressable area is restricted to locations 000H–07FH in bank 0 and to locations F80H–FFFH

in bank 15 for direct addressing. For indirect addressing, only locations 000H–0FFH in bank 0 are addressable,

regardless of SMB value.

To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to

"1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of

ROM address 0000H.

EMB-Independent Addressing

You can address several areas of the data memory at any time, despite the status of the EMB flag. These ex-

ceptions are described in Table 3-1.

Table 3-1. RAM Addressing Not Affected by the EMB Value

Address

Addressing Method

Affected Hardware

Program Examples

000H–0FFH

4-bit indirect addressing using WX

and WL register pairs;

Not applicable

LD

A,@WX

8-bit indirect addressing using SP

PUSH

POP

FB0H–FBFH

FF0H–FFFH

1-bit direct addressing

PSW,

IEx, IRQx, I/O

BITS

BITR

EMB

IE1

FC0H–FFFH

1-bit indirect addressing using the

L register

BSC,

I/O

BTST FC3H.@L

BAND C,P3.@L

3-4

S3C7414/P7414/C7424/P7424/C7434/P7434

SELECT BANK REGISTER (SB)

ADDRESS MODES

The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register con-

sists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown

in Figure 3-2.

During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB

instruction. You later restore the value to the SB using the POP SB instruction.

SMB (F83H)

SMB 2 SMB 1

SRB (F82H)

SRB 1

SB

REGISTER

SMB 3

SMB 0

0

SRB 0

Figure 3-2. SMB and SRB Values in the SB Register

Select Register Bank (SRB) Instruction

The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The

SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3. One of the four register banks is selected by the

combination of ERB flag status and the SRB value that you set using the 'SRB n' instruction. The current SRB

value is retained until another register is requested by program software.

PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and

subroutine calls. RESET clears the 4-bit SRB value to logic zero.

Select Memory Bank (SMB) Instruction

To select one of the two available data memory banks, you must execute an SMB n instruction specifying the

number of the memory bank you want (0 or 15). For example, the instruction 'SMB 1' selects bank 1 and

'SMB 15' selects bank 15. You must also remember to enable the memory bank you select by the appropriate

enable memory bank flag (EMB) setting.

The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not

specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB

value to logic zero.

PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area

during interrupts and subroutine calls.

3-5

ADDRESS MODES

S3C7414/P7414/C7424/P7424/C7434/P7434

DIRECT AND INDIRECT ADDRESSING

You can directly address 1-bit, 4-bit, and 8-bit data stored in data memory locations using a specific register or bit

address as the instruction operand.

In indirect addressing the instruction specifies a specific register pair which contain the address of the operand.

The S3C7 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an

even-numbered RAM address must always be used as the instruction operand, and the address register can be

HL, WX, or WL of the selected register bank.

1-BIT ADDRESSING

Table 3-2. 1-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag Addressable

Memory

Bank

Hardware I/O

Mapping

Setting

Area

DA.b

Direct: bit is indicated by the

0

000H–07FH

F80H–FFFH

Bank 0

–

RAM address (DA), memory

bank selection, and specified

bit number (b).

Bank 15

All 1-bit

addressable

peripherals

(SMB = 15)

1

x

000H–FFFH

SMB = 0, 15

Bank 15

mema.b

Direct: bit is indicated by ad-

dressable area (mema) and

bit number (b).

FB0H–FBFH

FF0H–FFFH

IS0, IS1, EMB,

ERB, IEx,

IRQx, Pn.n

memb.@L

Indirect: lower two bits of reg-

ister L as indicated by the up-

per 10 bits of RAM area

(memb) and the upper two

bits of register L.

x

FC0H–FFFH

Bank 15

BSCn.x

Pn.n

@H + DA.b

Indirect: bit indicated by the

0

1

000H–0FFH

000H–FFFH

Bank 0

–

lower four bits of the address

(DA), memory bank selection,

and the H register identifier.

SMB = 0, 15

All 1-bit

addressable

peripherals

(SMB = 15)

NOTE: 'x' means don't care.

3-6

S3C7414/P7414/C7424/P7424/C7434/P7434

ADDRESS MODES

+

PROGRAMMING TIP — 1-Bit Addressing Modes

1-Bit Direct Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

BITS

BTST

BITS

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

; Non-essential instruction, since EMB = "0"

; 34H.3 ¬ 1

; F85H.3 (BMOD.3) ¬ 1

; If FBAH.0 (IRQW) = 1, skip

; Else if FBAH.0 (IRQW) = 0, F85H.3 (BMOD.3) ¬ 1

; FF3H.0 (P3.0) ¬ 1

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

EQU

SMB

BITS

BTST

BITS

; Select memory bank 0

; 34H.3 ¬ 1

; 85H.3 ¬ 1

; If 0BAH.0 = 1, skip

; Else if 0BAH.0 = 0, 085H.3 ¬ 1

; FF3H.0 (P3.0) ¬ 1

3-7

ADDRESS MODES

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — 1-Bit Addressing Modes (Continued)

1-Bit Indirect Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

LD

34H.3

85H.3

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

; Non-essential instruction, since EMB = "0"

; H ¬ #0BH

; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

; Else if 0BAH.0 = 0, FBAH.0 (IRQW) ¬ 1

BTSTZ

BITS

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

EQU

SMB

LD

BTSTZ

BITS

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

; Select memory bank 0

; H ¬ #0BH

; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

; Else if 0BAH.0 = 0, 0BAH.0 ¬ 1

3-8

S3C7414/P7414/C7424/P7424/C7434/P7434

4-BIT ADDRESSING

ADDRESS MODES

Table 3-3. 4-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag

Setting

Addressable

Area

Memory

Bank

Hardware I/O

Mapping

DA

Direct: 4-bit address indicated

0

000H–07FH

F80H–FFFH

Bank 0

–

by the RAM address (DA) and

the memory bank selection

Bank 15

All 4-bit

addressable

peripherals

(SMB = 15)

1

0

000H–FFFH

000H–0FFH

SMB = 0, 15

Bank 0

–

@HL

Indirect: 4-bit address indi-

cated by the memory bank

selection and register HL

1

000H–FFFH

SMB = 0, 15

All 4-bit

addressable

peripherals

(SMB = 15)

@WX

@WL

Indirect: 4-bit address indi-

cated by register WX

x

000H–0FFH

Bank 0

–

Indirect: 4-bit address indi-

cated by register WL

NOTE: 'x' means don't care.

+

PROGRAMMING TIP — 4-Bit Addressing Modes

4-Bit Direct Addressing

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

SMB

LD

46H

8EH

15

A,P3

0

; Non-essential instruction, since EMB = "0"

; A ¬ (P3)

; Non-essential instruction, since EMB = "0"

; (046H) ¬ A

ADATA,A

BDATA,A

LD

; (F8EH) ¬ A

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

A,P3

0

EQU

SMB

LD

SMB

LD

; Select memory bank 15

; A ¬ (P3)

; Select memory bank 0

; (046H) ¬ A

ADATA,A

BDATA,A

LD

; (08EH) ¬ A

3-9

ADDRESS MODES

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Continued)

4-Bit Indirect Addressing

1. If EMB = "0", compare bank 0, locations 040H–046H with 060H–066H:

ADATA

BDATA

EQU

SMB

LD

CPSE

SRET

DECS

JR

46H

66H

15

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

; Non-essential instruction, since EMB = "0"

COMP

; A ¬ bank 0 (040H–046H)

; If bank 0 (060H–066H) = A, skip

L

COMP

RET

2. If EMB = "1", exchange bank 0, 040H–046H with 060H–066H:

ADATA

BDATA

EQU

SMB

LD

46H

66H

0

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

; Select memory bank 0

TRANS

; A ¬ bank 0 (040H–046H)

; Bank 0 (060H–066H) ¬ A

XCHD

JR

3-10

S3C7414/P7414/C7424/P7424/C7434/P7434

8-BIT ADDRESSING

ADDRESS MODES

Table 3-4. 8-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag

Setting

Addressable

Area

Memory

Bank

Hardware I/O

Mapping

DA

Direct: 8-bit address indicated

0

000H–07FH

F80H–FFFH

Bank 0

–

by the RAM address (DA =

even number) and memory

bank selection

Bank 15

All 8-bit

addressable

peripherals

1

0

1

000H–FFFH

000H–0FFH

000H–FFFH

SMB = 0, 15

Bank 0

(SMB = 15)

–

@HL

Indirect: the 8-bit address

indicated by the memory bank

selection and register HL; (the

4-bit L register value must be

an even number)

SMB = 0, 15

All 8-bit

addressable

peripherals

(SMB = 15)

+

PROGRAMMING TIP — 8-Bit Addressing Modes

8-Bit Direct Addressing

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

46H

8EH

15

EA,P4

ADATA,EA

BDATA,EA

; Non-essential instruction, since EMB = "0"

; E ¬ (P5), A ¬ (P4)

; (046H) ¬ A, (047H) ¬ E

; (F8EH) ¬ A, (F8FH) ¬ E

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

EA,P4

0

EQU

SMB

LD

SMB

LD

; Select memory bank 15

; E ¬ (P5), A ¬ (P4)

; Select memory bank 0

; (046H) ¬ A, (047H) ¬ E

; (08EH) ¬ A, (08FH) ¬ E

ADATA,EA

BDATA,EA

LD

3-11

ADDRESS MODES

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — 8-Bit Addressing Modes (Continued)

8-Bit Indirect Addressing

1. If EMB = "0":

ADATA

EQU

LD

8EH

HL,#ADATA

EA,@HL

; A ¬ (08EH), E ¬ (08FH)

2. If EMB = "1":

ADATA

EQU

46H

SMB

LD

0

; Bank 0 select

HL,#ADATA

EA,@HL

; A ¬ (046H), E ¬ (047H)

3-12

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

4

MEMORY MAP

OVERVIEW

To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank

15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the

specific memory location.

Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank

flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the

current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless

of the current EMB value.

I/O MAP FOR HARDWARE REGISTERS

Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations

F80H–FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map

gives you the following information:

— Register address

— Register name (mnemonic for program addressing)

— Bit values (both addressable and non-manipulable)

— Read-only, write-only, or read and write addressability

— 1-bit, 4-bit, or 8-bit data manipulation characteristics

4-1

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 4-1. I/O Map for Memory Bank 15

Memory Bank 15

Addressing Mode

Address

F80H

Register

Bit 3

.3

Bit 2

.2

Bit 1

.1

Bit 0

"0"

R/W

1-Bit

4-Bit

8-Bit

SP

R/W

No

Yes

F81H

.7

.6

.5

.4

F82H

SB

“0”

SRB1

SMB1

SRB0

SMB0

R/W

No

Yes

F83H

SMB3

SMB2

Location F84H is reserved.

F85H

F86H

F87H

F88H

F89H

BMOD

BCNT

.3

.2

.1

.5

.1

.5

.0

.4

.0

.4

W

R

.3

Yes

No

Yes

.7

.6

WMOD

TMOD0

"0"

.7

.2

W

No

.3

No

Yes

"0"

Locations F8AH–F8FH are not mapped.

F90H

F91H

F92H

F93H

F94H

F95H

F96H

F97H

F98H

F99H

F9AH

.3

"0"

.2

.6

"0"

.5

"0"

.4

W

TOE1

"0"

TOE0

TOL1

.2

–

"0"

.0

R/W

R

Yes

No

Yes

No

TOL0

.1

TCNT0

TREF0

.3

R

Yes

.7

.6

.5

.4

.3

.2

.1

.0

W

No

Yes

.3

No

Yes

No

.7

.6

.5

.4

WDMOD

WDFLAG

TMOD1

.3

.2

.1

.0

.7

.6

.5

.4

WDTCF

"0"

Locations F9BH–F9FH are not mapped.

FA0H

FA1H

.3

.2

.6

"0"

.5

.0

.4

W

Yes

"0"

Locations FA2H–FA3H are not mapped.

FA4H

FA5H

TCNT1

TREF1

.3

.7

.2

.6

.1

.5

.0

.4

R

No

Yes

Locations FA6H–FA7H are not mapped.

FA8H

FA9H

.3

.7

.2

.6

.1

.5

.0

.4

W

Locations FAAH–FAFH are not mapped.

4-2

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

Table 4-1. I/O Map for Memory Bank 15 (Continued)

Memory Bank 15

Addressing Mode

Address

FB0H

FB1H

FB2H

FB3H

FB4H

FB5H

FB6H

Register

Bit 3

IS1

C ⁽¹⁾

IME

.3

Bit 2

IS0

SC2

.2

Bit 1

EMB

SC1

.1

Bit 0

ERB

SC0

.0

R/W

R

1-Bit

Yes

No

4-Bit

Yes

No

8-Bit

PSW

Yes

IPR

W

.3

Yes

No

PCON

IMOD0

IMOD1

IMOD2

.2

.1

.0

W

No

.3

"0"

.1

.0

"0"

.1

.0

"0"

.0

Location FB7H is not mapped.

IRQ4 IEB IRQB

Location FB9H is not mapped.

FB8H

IE4

R/W

Yes

No

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

FC0H

FC1H

FC2H

FC3H

"0"

IEAD

"0"

IE1

"0"

.3

"0"

IRQAD

"0"

IEW

IET1

IET0

IES

IE0

IE2

.1

IRQW

IRQT1

IRQT0

IRQS

IRQ0

IRQ2

.0

"0"

IRQ1

"0"

BSC0

BSC1

BSC2

BSC3

.2

R/W

Yes

.7

.6

.5

.4

.3

.2

.1

.0

.7

.6

.5

.4

Locations FC4H–FCFH are not mapped.

"0" .1 .0

Locations FD1H–FD7H are not mapped.

FD0H

CLMOD

ADATA

.3

W

No

Yes

No

FD8H

FD9H

FDAH

FDBH

FDCH

FDDH

.3

.7

.2

.6

.1

.5

.0

.4

R

Yes

ADMOD

AFLAG

.3

.2

.1

.0

R/W

Yes

No

Yes

No

(2)

ADSTR

PUR3

PUR7

EOC

PUR2

PUR6

"0"

PUMOD1

PUR1

PUR5

PUR0

PUR4

W

Yes

4-3

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 4-1. I/O Map for Memory Bank 15 (Concluded)

Memory Bank 15

Addressing Mode

Address

FDEH

FDFH

FE0H

Register

Bit 3

"0"

.3

Bit 2

"0"

.2

Bit 1

"0"

.1

Bit 0

PUR8

"0"

R/W

1-Bit

4-Bit

8-Bit

PUMOD2

W

No

Yes

SMOD

SBUF

.0

W

.3

No

Yes

FE1H

.7

.6

.5

"0"

Locations FE2H–FE3H are not mapped.

FE4H

FE5H

.3

.7

.2

.6

.1

.5

.0

.4

R/W

No

Yes

Locations FE6H–FE7H are not mapped.

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

FF0H

FF1H

FF2H

FF3H

FF4H

FF5H

FF6H

FF7H

FF8H

PMG1

PMG2

PMG3

PMG4

PM0.3

"0"

PM0.2

"0"

PM0.1

PM5

PM2.1

PM3.1

PM6.1

"0"

PM0.0

PM4

PM2.0

PM3.0

PM6.0

"0"

W

PM2.3

PM3.3

PM6.3

"0"

PM2.2

PM3.2

PM6.2

"0"

PM7.3

"0"

PM7.2

PM8.2

.2

PM7.1

PM8.1

.1

PM7.0

PM8.0

.0

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

.3

R/W

R

Yes

No

.3

.2

.1

.0

.3

.2

.1

.0

R/W

.3

.2

.1

.0

.3

.2

.1

.0

Yes

No

.3

.2

.1

.0

.3

.2

.1

.0

.3

.2

.1

.0

–

.2

.1

.0

Location FF9H is not mapped.

FFAH

FFBH

PNE

PNE4.3 PNE4.2 PNE4.1 PNE4.0

PNE5.3 PNE5.2 PNE5.1 PNE5.0

W

No

Yes

NOTES:

1. The carry flag can be read or written by specific bit manipulation instructions only.

2. The ADSTR bit of the AFLAG register is 1- or 4-bit write-only; the EOC bit is 1- or 4-bit read-only.

4-4

S3C7414/P7414/C7424/P7424/C7434/P7434

REGISTER DESCRIPTIONS

MEMORY MAP

In this section, register descriptions are presented in a consistent format to familiarize you with the memory-

mapped I/O locations in bank 15 of the RAM. Figure 4-1 describes features of the register description format.

Register descriptions are arranged in alphabetical order. Programmers can use this section as a quick-reference

source when writing application programs.

Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are

not included in these descriptions. More detailed information about how these registers are used is included in

Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module

descriptions.

4-5

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

Register and bit IDs

used for bit addressing

Name of individual

bit or related bits

Associated

hardware module

Register location

in RAM bank 15

Register ID

Register name

CLMOD — Clock Output Mode Control Register

CPU

FD0H

3

2

1

0

Bit

Identifier

.3

.2

.1

.0

Value

Read/Write

Bit Addressing

0

W

4

0

W

4

0

W

4

0

W

4

RESET

Enable/Disable Clock Output Control Bit

CLMOD.3

0

1

Disable clock output

Enable clock output

Bit 2

CLMOD.2

0

Always logic zero

Clock Source and Frequency Selection Control

Bits

CLMOD.1 – .0

0

1

0

1

0

1

Select CPU clock source

Select main system clock fx/8 (524 kHz at 4.19 MHz)

Select main system clock fx/16 (262 kHz at 4.19 MHz)

Select main system clock fx/64 (65.5 kHz at 4.19 MHz)

R = Read-only

W= Write-only

R/W= Read/write

Bit value immediately

Bit number in

MSB to LSB

order

following a

RESET

Type of addressing

that must be used to

address the bit (1-bit,

4-bit, or 8-bit)

Description of the

effect of specific bit

settings

Bit identifier used

for bit addressing

Figure 4-1. Register Description Format

4-6

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

ADMOD— A/D Converter Mode Control Register

A/D

FDAH

Bit

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

ADMOD.3

Not used for S3C7414/C7424/C7434

ADMOD.2 – .0

A/D Converter Analog Channel Selection Bits

0

1

0

1

0

1

0

1

0

1

Select input channel AD0 (pin P2.0)

Select input channel AD1 (pin P2.1)

Select input channel AD2 (pin P2.2)

Select input channel AD3 (pin P2.3)

Select input channel AD4 (pin P3.0)

Select input channel AD5 (pin P3.1)

4-7

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

AFLAG— A/D Converter Control Register

A/D

FDBH

Bit

3

ADSTR

0

2

EOC

0

1

"0"

0

"0"

0

Identifier

RESET Value

Read/Write

W

R

W

Bit Addressing

1/4

ADSTR

EOC

A/D Conversion Start Control Flag (Write-Only)

1

Enable A/D converter (When the ADSTR bit is set to "1", the A/D converter

starts operating and the ADSTR bit is then cleared automatically.)

A/D Conversion Status Check Flag (Read-Only)

0

1

A/D conversion completed

A/D conversion is not completed; start of a new conversion is blocked

.1 – .0

Bits 1–0

Always logic zero

0

4-8

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

BMOD— Basic Timer Mode Register

BT

F85H

Bit

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

Bit Addressing

1/4

BMOD.3

Basic Timer Restart Bit

Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero

1

BMOD.2 – .0

Input Clock Frequency and Signal Stabilization Interval Control Bits

fx / 2¹²(1.02 kHz)

²⁰/ fx (250 ms)

0

1

0

1

0

1

0

1

Input clock frequency:

Signal stabilization interval:

2

fx / 2⁹(8.18 kHz)

2¹⁷/ fx (31.3 ms)

Input clock frequency:

Signal stabilization interval:

fx / 2⁷(32.7 kHz)

2¹⁵/ fx (7.82 ms)

Input clock frequency:

Signal stabilization interval:

fx / 2⁵(131 kHz)

2¹³/ fx (1.95 ms)

Input clock frequency:

Signal stabilization interval:

NOTES:

1. Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by

an interrupt. The stabilization interval can also be interpreted as "Interrupt Interval Time".

2. When a RESET occurs, the oscillation stabilization time is 31.3 ms (2¹⁷/fx) at 4.19 MHz.

3. 'fx' is the system clock rate given a clock frequency of 4.19 MHz.

4-9

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

CLMOD — Clock Output Mode Register

CPU

FD0H

Bit

3

.3

0

2

"0"

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

CLMOD.3

Enable/Disable Clock Output Control Bit

0

1

Disable clock output

Enable clock output

CLMOD.2

Bit 2

0

Always logic zero

CLMOD.1 – .0

Clock Source and Frequency Selection Control Bits

0

Select CPU clock source fx/4, fx/8, or fx/64 (1.05 MHz, 524 kHz,

or 65.6 kHz)

0

1

0

1

Select system clock fx/8 (524 kHz)

Select system clock fx/16 (262 kHz)

Select system clock fx/64 (65.5 kHz)

NOTE: 'fx' is the system clock, given a clock frequency of 4.19 MHz.

4-10

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

IEAD, IRQAD— INTAD Interrupt Enable/Request Flags

IET1, IRQT1— INTT0 Interrupt Enable/Request Flags

CPU

FBBH

Bit

3

IEAD

0

2

IRQAD

0

1

IET1

0

IRQT1

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IEAD

INTAD Interrupt Enable Flag

0

1

Disable INTAD interrupt requests

Enable INTAD interrupt requests

IRQAD

IET1

INTAD Interrupt Request Flag

–

Generate INTAD interrupt (This bit is set and cleared automatically by

hardware when an analog-to-digital conversion is completed.)

INTT1 Interrupt Enable Flag

0

1

Disable INTT1 interrupt requests

Enable INTT1 interrupt requests

IRQT1

INTT1 Interrupt Request Flag

–

Generate INTT1 interrupt (This bit is set and cleared automatically by

hardware when contents of TCNT1 and TREF1 registers match.)

4-11

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

IE0, 1, IRQ0, 1— INT0, 1 Interrupt Enable/Request Flags

CPU

FBEH

Bit

3

IE1

0

2

IRQ1

0

1

IE0

0

IRQ0

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IE1

INT1 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT1 pin

Enable interrupt requests at the INT1 pin

IRQ1

IE0

INT1 Interrupt Request Flag

–

Generate INT1 interrupt (This bit is set and cleared by hardware when rising or

falling edge detected at INT1 pin.)

INT0 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT0 pin

Enable interrupt requests at the INT0 pin

IRQ0

INT0 Interrupt Request Flag

–

Generate INT0 interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge detected at INT0 pin.)

4-12

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

IE2, IRQ2— INT2 Interrupt Enable/Request Flags

CPU

FBFH

Bit

3

"0"

0

2

"0"

0

1

0

Identifier

IE2

IRQ2

0

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IE2

Bits 3–2

0

Always logic zero

INT2 Interrupt Enable Flag

0

1

Disable INT2 interrupt requests at the INT2 pin or KS0–KS3 pins

Enable INT2 interrupt requests at the INT2 pin or KS0–KS3 pins

IRQ2

INT2 Interrupt Request Flag

Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically

–

by hardware when a rising edge is detected at INT2 or when a falling edge is

detected at one of the KS0–KS3 pins. Since INT2 is a quasi-interrupt, IRQ2

flag must be cleared by software.)

4-13

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

IE4, IRQ4— INT4 Interrupt Enable/Request Flags

IEB, IRQB— INTB Interrupt Enable/Request Flags

CPU

FB8H

Bit

3

IE4

0

2

IRQ4

0

1

IEB

0

IRQB

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IE4

INT4 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT4 pin

Enable interrupt requests at the INT4 pin

IRQ4

IEB

INT4 Interrupt Request Flag

–

Generate INT4 interrupt (This bit is set and cleared automatically by hardware

when rising and falling signal edge detected at INT4 pin.)

INTB Interrupt Enable Flag

0

1

Disable INTB interrupt requests

Enable INTB interrupt requests

IRQB

INTB Interrupt Request Flag

–

Generate INTB interrupt (This bit is set and cleared automatically by hardware

when reference interval signal received from basic timer.)

NOTE: When two interrupts share the same service routine start address, interrupt processing may occur in one of two

ways. First, when only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been

serviced. Second, when two interrupts are enabled, the request flag is not automatically cleared so that the user has

an opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared manually

using a BTSTZ instruction.

4-14

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

IES, IRQS— INTS Interrupt Enable/Request Flags

CPU

FBDH

Bit

3

"0"

0

2

"0"

0

1

IES

0

IRQS

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IES

Bits 3–2

0

Always logic zero

INTS Interrupt Enable Flag

0

1

Disable INTS interrupt requests

Enable INTS interrupt requests

IRQS

INTS Interrupt Request Flag

–

Generate INTS interrupt (This bit is set and cleared automatically by hardware

when serial data transfer completion signal received from serial I/O interface.)

4-15

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

IET0, IRQT0— INTT0 Interrupt Enable/Request Flags

CPU

FBCH

Bit

3

"0"

0

2

"0"

0

1

IET0

0

IRQT0

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IET0

Bits 3–2

0

Always logic zero

INTT0 Interrupt Enable Flag

0

1

Disable INTT0 interrupt requests

Enable INTT0 interrupt requests

IRQT0

INTT0 Interrupt Request Flag

–

Generate INTT0 interrupt (This bit is set and cleared automatically by

hardware when contents of TCNT0 and TREF0 registers match.)

4-16

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

IEW, IRQW— INTW Interrupt Enable/Request Flags

CPU

FBAH

Bit

3

"0"

0

2

"0"

0

1

IEW

0

IRQW

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IEW

Bits 3–2

0

Always logic zero

INTW Interrupt Enable Flag

0

1

Disable INTW interrupt requests

Enable INTW interrupt requests

IRQW

INTW Interrupt Request Flag

–

Generate INTW interrupt (This bit is set when the timer interval is set to 0.5

seconds or 3.19 milliseconds at 4.19 MHz.)

NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.

4-17

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

IMOD0— External Interrupt 0 (INT0) Mode Register

CPU

FB4H

Bit

3

.3

0

2

"0"

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD0.3

Interrupt Sampling Clock Selection Bit

0

1

Select CPU clock as a sampling clock

Select sampling clock frequency of the selected system clock (fx/64)

IMOD0.2

Bit 2

0

Always logic zero

IMOD0.1 – .0

External Interrupt Mode Control Bits

0

1

0

1

0

1

Interrupt requests are triggered by a rising signal edge

Interrupt requests are triggered by a falling signal edge

Interrupt requests are triggered by both rising and falling signal edges

Interrupt request flag (IRQx) cannot be set to logic one

4-18

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

IMOD1— External Interrupt 1 (INT1) Mode Register

CPU

FB5H

Bit

3

"0"

0

2

"0"

0

1

"0"

0

.0

0

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD1.3 – .1

IMOD1.0

Bits 3–1

0

Always logic zero

External Interrupt 1 Edge Detection Control Bit

0

1

Rising edge detection

Falling edge detection

4-19

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

IMOD2— External Interrupt 2 (INT2) Mode Register

CPU

FB6H

Bit

3

"0"

0

2

"0"

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD2.3 – .2

IMOD2.1 – .0

Bits 3

0

Always logic zero

External Interrupt 2 Edge Detection Selection Bit

0

1

0

1

0

1

Select rising edge at INT2 pin

Select falling edge at KS0–KS1

Select falling edge at KS0–KS2

Select falling edge at KS0–KS3

4-20

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

IPR— Interrupt Priority Register

CPU

FB2H

Bit

3

IME

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

Bit Addressing

1/4

IME

Interrupt Master Enable Bit (MSB)

0

1

Disable all interrupt processing

Enable processing of all interrupt service requests

IPR.2 – .0

Interrupt Priority Assignment Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal interrupt processing according to default priority settings

Process INTB and INT4 interrupts at highest priority

Process INT0 interrupts at highest priority

Process INT1 interrupts at highest priority

Process INTS interrupts at highest priority

Process INTT0 interrupts at highest priority

Process INTT1 interrupts at highest priority

Process INTAD interrupts at highest priority

NOTE: During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more

interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown

below. Using the IPR settings, you can select specific interrupts for high-priority processing in the event of

contention. When the high-priority (IPR) interrupt has been processed, waiting interrupts are handled according to

their default priorities. The default priorities are as follows ('1' is highest priority; '7' is lowest priority):

INTB, INT4

INT0

INT1

1

2

3

4

5

6

7

INTS

INTT0

INTT1

INTAD

4-21

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

PCON— Power Control Register

CPU

FB3H

Bit

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

PCON.3 – .2

PCON.1 – .0

CPU Operating Mode Control Bits

0

1

0

1

0

Enable normal CPU operating mode

Initiate idle power-down mode

Initiate stop power-down mode

CPU Clock Frequency Selection Bits

0

1

0

1

Select fx/64

Select fx/8

Select fx/4

NOTE: 'fx' is the system clock.

4-22

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

PMG1 — Port I/O Mode Flags (Group 1: Ports 0, 4, 5)

I/O

FE9H, FE8H

Bit

7

"0"

0

6

"0"

0

5

PM5

0

4

PM4

0

3

PM0.3

0

2

1

0

Identifier

PM0.2

PM0.1

PM0.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7

Bit 7

0

Always logic zero

.6

Bit 6

0

PM5

Port 5 I/O Mode Selection Flag

0

1

Set port 5 to input mode

Set port 5 to output mode

PM4

Port 4 I/O Mode Selection Flag

0

1

Set port 4 to input mode

Set port 4 to output mode

PM0.3

PM0.2

PM0.1

PM0.0

P0.3 I/O Mode Selection Flag

0

1

Set P0.3 to input mode

Set P0.3 to output mode

P0.2 I/O Mode Selection Flag

0

1

Set P0.2 to input mode

Set P0.2 to output mode

P0.1 I/O Mode Selection Flag

0

1

Set P0.1 to input mode

Set P0.1 to output mode

P0.0 I/O Mode Selection Flag

0

1

Set P0.0 to input mode

Set P0.0 to output mode

4-23

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

PMG2 — Port I/O Mode Flags (Group 2: Ports 2, 3)

I/O

FEBH, FEAH

Bit

7

PM3.3

0

6

PM3.2

0

5

PM3.1

0

4

PM3.0

0

3

PM2.3

0

2

1

0

Identifier

PM2.2

PM2.1

PM2.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PM3.3

PM3.2

PM3.1

PM3.0

PM2.3

PM2.2

PM2.1

PM2.0

P3.3 I/O Mode Selection Flag

0

1

Set P3.3 to input mode

Set P3.3 to output mode

P3.2 I/O Mode Selection Flag

0

1

Set P3.2 to input mode

Set P3.2 to output mode

P3.1 I/O Mode Selection Flag

0

1

Set P3.1 to AD input mode

Set P3.1 to output mode

P3.0 I/O Mode Selection Flag

0

1

Set P3.0 to AD input mode

Set P3.0 to output mode

P2.3 I/O Mode Selection Flag

0

1

Set P2.3 to AD input mode

Set P2.3 to output mode

P2.2 I/O Mode Selection Flag

0

1

Set P2.2 to AD input mode

Set P2.2 to output mode

P2.1 I/O Mode Selection Flag

0

1

Set P2.1 to AD input mode

Set P2.1 to output mode

P2.0 I/O Mode Selection Flag

0

1

Set P2.0 to AD input mode

Set P2.0 to output mode

4-24

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

PMG3 — Port I/O Mode Flags (Group 3: Port 6)

I/O

FEDH, FECH

Bit

7

"0"

0

6

"0"

0

5

"0"

0

4

"0"

0

3

PM6.3

0

2

1

0

Identifier

PM6.2

PM6.1

PM6.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7–.4

Bits 4–7

0

Always logic zero

PM6.3

P6.3 I/O Mode Selection Flag

0

1

Set P6.3 to input mode

Set P6.3 to output mode

PM6.2

PM6.1

PM6.0

P6.2 I/O Mode Selection Flag

0

1

Set P6.2 to input mode

Set P6.2 to output mode

P6.1 I/O Mode Selection Flag

0

1

Set P6.1 to input mode

Set P6.1 to output mode

P6.0 I/O Mode Selection Flag

0

1

Set P6.0 to input mode

Set P6.0 to output mode

4-25

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

PMG4 — Port I/O Mode Flags (Group 3: Ports 7, 8)

I/O

FEFH, FEEH

Bit

7

"0"

0

6

PM8.2

0

5

PM8.1

0

4

PM8.0

0

3

PM7.3

0

2

1

0

Identifier

PM7.2

PM7.1

PM7.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7

Bits 7

0

Always logic zero

PM8.2

P8.2 I/O Mode Selection Flag

0

1

Set P8.2 to input mode

Set P8.2 to output mode

PM8.1

PM8.0

PM7.3

PM7.2

PM7.1

PM7.0

P8.1 I/O Mode Selection Flag

0

1

Set P8.1 to input mode

Set P8.1 to output mode

P8.0 I/O Mode Selection Flag

0

1

Set P8.0 to input mode

Set P8.0 to output mode

P7.3 I/O Mode Selection Flag

0

1

Set P7.3 to input mode

Set P7.3 to output mode

P7.2 I/O Mode Selection Flag

0

1

Set P7.2 to input mode

Set P7.2 to output mode

P7.1 I/O Mode Selection Flag

0

1

Set P7.1 to input mode

Set P7.1 to output mode

P7.0 I/O Mode Selection Flag

0

1

Set P7.0 to input mode

Set P7.0 to output mode

4-26

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

PNE — N-Channel Open-Drain Mode Register

I/O

FFBH, FFAH

Bit

7

6

5

4

3

2

1

0

Identifier

PNE5.3 PNE5.2 PNE5.1 PNE5.0 PNE4.3 PNE4.2 PNE4.1 PNE4.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PNE5.3

PNE5.2

PNE5.1

PNE5.0

PNE4.3

PNE4.2

PNE4.1

PNE4.0

P5.3 N-Channel Open-Drain Configurable Bit

0

1

Configure P5.3 as a push-pull

Configure P5.3 as a n-channel open-drain

P5.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P5.2 as a push-pull

Configure P5.2 as a n-channel open-drain

P5.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P5.1 as a push-pull

Configure P5.1 as a n-channel open-drain

P5.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P5.0 as a push-pull

Configure P5.0 as a n-channel open-drain

P4.3 N-Channel Open-Drain Configurable Bit

0

1

Configure P4.3 as a push-pull

Configure P4.3 as a n-channel open-drain

P4.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P4.2 as a push-pull

Configure P4.2 as a n-channel open-drain

P4.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P4.1 as a push-pull

Configure P4.1 as a n-channel open-drain

P4.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P4.0 as a push-pull

Configure P4.0 as a n-channel open-drain

4-27

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

PSW— Program Status Word

CPU

FB1H, FB0H

Bit

7

C

6

SC2

0

5

SC1

0

4

SC0

0

3

IS1

0

2

IS0

0

1

0

Identifier

EMB

ERB

0

(1)

RESET Value

Read/Write

R/W

(2)

R

8

R

8

R

8

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

C

Carry Flag

0

1

No overflow or borrow condition exists

An overflow or borrow condition does exist

SC2 – SC0

IS1, IS0

Skip Condition Flags

0

1

No skip condition exists; no direct manipulation of these bits is allowed

A skip condition exists; no direct manipulation of these bits is allowed

Interrupt Status Flags

0

1

Service all interrupt requests

Service only the high-priority interrupt(s) as determined in the interrupt

priority register (IPR)

1

0

1

Do not service any more interrupt requests

Undefined

EMB

Enable Data Memory Bank Flag

0

Restrict program access to data memory to bank 15 (F80H–FFFH) and to

the locations 000H–07FH in the bank 0 only

1

Enable full access to data memory banks 0 and 15

ERB

Enable Register Bank Flag

0

1

Select register bank 0 as working register area

Select register banks 0, 1, 2, or 3 as working register area in accordance with

the select register bank (SRB) instruction operand

NOTES:

1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during

power-down mode (IDLE or STOP), the current value of the carry flag is retained.

2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for

detailed information.

4-28

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

PUMOD1 — Pull-Up Resistor Mode Register 1

I/O

FDDH, FDCH

Bit

7

PUR7

0

6

PUR6

0

5

PUR5

0

4

PUR4

0

3

PUR3

0

2

1

0

PUR0

0

Identifier

PUR2

PUR1

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PUR7

PUR6

PUR5

PUR4

PUR3

PUR2

PUR1

PUR0

Connect/Disconnect Port 7 Pull-Up Resistor Control Bit

0

1

Disconnect port 7 pull-up resistor

Connect port 7 pull-up resistor

Connect/Disconnect Port 6 Pull-Up Resistor Control Bit

0

1

Disconnect port 6 pull-up resistor

Connect port 6 pull-up resistor

Connect/Disconnect Port 5 Pull-Up Resistor Control Bit

0

1

Disconnect port 5 pull-up resistor

Connect port 5 pull-up resistor

Connect/Disconnect Port 4 Pull-Up Resistor Control Bit

0

1

Disconnect port 4 pull-up resistor

Connect port 4 pull-up resistor

Connect/Disconnect Port 3 Pull-Up Resistor Control Bit

0

1

Disconnect port 3 pull-up resistor

Connect port 3 pull-up resistor

Connect/Disconnect Port 2 Pull-Up Resistor Control Bit

0

1

Disconnect port 2 pull-up resistor

Connect port 2 pull-up resistor

Connect/Disconnect Port 1 Pull-Up Resistor Control Bit

0

1

Disconnect port 1 pull-up resistor

Connect port 1 pull-up resistor

Connect/Disconnect Port 0 Pull-Up Resistor Control Bit

0

1

Disconnect port 0 pull-up resistor

Connect port 0 pull-up resistor

4-29

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

PUMOD2 — Pull-Up Resistor Mode Register 2

I/O

FDFH, FDEH

Bit

7

"0"

0

6

"0"

0

5

"0"

0

4

"0"

0

3

"0"

0

2

1

0

Identifier

"0"

PUR8

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7– .1

PUR8

Bits 7–1

0

Always cleared to logic zero

Connect/Disconnect Port 8 Pull-Up Resistor Control Bit

0

1

Disconnect port 8 pull-up resistor

Connect port 8 pull-up resistor

4-30

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

SMOD — Serial I/O Mode Register

SIO

FE1H, FE0H

Bit

7

.7

0

6

.6

0

5

.5

0

4

"0"

0

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

1/8

SMOD.7 – .5

Serial I/O Clock Selection and SBUF R/W Status Control Bits

0

1

0

1

x

Use an external clock at the SCK pin;

Enable SBUF when SIO operation is halted or when SCKB goes high

Use the TOL0 clock from timer/counter 0;

Enable SBUF when SIO operation is halted or when SCKB goes high

Use the selected CPU clock (fx/4, 8, or 64; 'fx' is the system clock)

then, enable SBUF read/write operation. 'x' means 'don't care.'

4.09 kHz clock (fx/2¹⁰)

1

0

1

0

1

262 kHz clock (fx/2⁴); Note: You cannot select a fx/2⁴clock fre-

quency if you have selected a CPU clock of fx/64

NOTE: All kHz frequency ratings assume a system clock of 4.19 MHz.

SMOD.4

SMOD.3

Bit 4

0

Always logic zero

Initiate Serial I/O Operation Bit

1

Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial trans-

mission. When SIO transmission starts, this bit is cleared by hardware to logic

zero

SMOD.2

Enable/Disable SIO Data Shifter and Clock Counter Bit

0

Disable the data shifter and clock counter; the contents of IRQS flag is retained

when serial transmission is completed

1

Enable the data shifter and clock counter; The IRQS flag is set to logic one when

serial transmission is completed

SMOD.1

SMOD.0

Serial I/O Transmission Mode Selection Bit

0

1

Receive-only mode

Transmit-and-receive mode

LSB/MSB Transmission Mode Selection Bit

0

1

Transmit the most significant bit (MSB) first

Transmit the least significant bit (LSB) first

4-31

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

TMOD0— Timer/Counter 0 Mode Register

T/C0

F91H, F90H

Bit

7

"0"

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

"0"

0

"0"

0

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

1/8

TMOD0.7

Bit 7

0

Always logic zero

TMOD0.6 – .4

Timer/Counter 0 Input Clock Selection Bits

0

1

0

1

0

1

0

1

0

1

External clock input at TCL0 pin on rising edge

External clock input at TCL0 pin on falling edge

10

Internal system clock (fx) of 4.19 MHz/2 (4.09 kHz)

6

Select clock: fx/2 (65.5 kHz at 4.19 MHz)

4

Select clock: fx/2 (262 kHz at 4.19 MHz)

Select clock: fx (4.19 MHz)

TMOD0.3

TMOD0.2

Clear Counter and Resume Counting Control Bit

Clear TCNT0, IRQT0, and TOL0 and resume counting immediately

(This bit is cleared automatically when counting starts.)

1

Enable/Disable Timer/Counter 0 Bit

0

1

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

TMOD0.1

TMOD0.0

Bit 1

0

Always logic zero

Bit 0

0

4-32

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

TMOD1— Timer/Counter 1 Mode Register

T/C1

FA1H, FA0H

Bit

7

"0"

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

"0"

0

.0

0

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

1/8

TMOD1.7

Bit 7

0

Always logic zero

TMOD1.6 – .4

Timer/Counter 1 Input Clock Selection Bit

0

1

0

1

0

1

0

1

0

1

External clock input at TCL1 pin on rising edge

External clock input at TCL1 pin on falling edge

Selected clock: fx/2¹⁰(4.09 kHz at 4.19 MHz)

Selected clock: fx/2⁶(65.5 kHz at 4.19 MHz)

Selected clock: fx/2⁴(262 kHz at 4.19 MHz)

Selected clock: fx (4.19 MHz)

TMOD1.3

TMOD1.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT1, IRQT1, and TOL1 and resume counting immediately

(This bit is cleared automatically cleared to logic zero immediately after

counting resumes.)

Enable/Disable Timer/Counter 1 Bit

0

1

Disable timer/counter 1; retain TCNT1 contents

Enable timer/counter 1

TMOD1.1

TMOD1.0

Bit 1

0

Always logic zero

Timer/Counter 1 Mode Selection Bit

0

1

Normal timer/counter mode

PWM mode

4-33

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

TOE— Timer Output Enable Flag Register

T/C

F92H

Bit

3

TOE1

0

2

TOE0

0

1

–

0

"0"

0

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

W

Bit Addressing

1/4

TOE1

TOE0

Timer/Counter 1 Output Enable Flag

0

1

Disable timer/counter 1 output at the TCLO1 pin

Enable timer/counter 1 output at the TCLO1 pin

Timer/Counter 0 Output Enable Flag

0

1

Disable timer/counter 0 output at the TCLO0 pin

Enable timer/counter 0 output at the TCLO0 pin

.1

.0

Bit 1

0

Undefined

Bit 0

0

Always logic zero

4-34

S3C7414/P7414/C7424/P7424/C7434/P7434

MEMORY MAP

WDMOD — Watch-Dog Timer Mode Register

F99H, F98H

Bit

7

.7

1

6

.6

0

5

.5

1

4

.4

0

3

.3

0

2

.2

1

.1

0

.0

1

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7 - .0

Watch-Dog Timer Enable/Disable Control

5AH

Disable watch-dog timer function

Enable watch-dog timer function

Any other value

WDFLAG — Watch-Dog Timer Flag

F9AH

Bit

3

2

“0”

0

1

“0”

0

“0”

0

Identifier

WDTCF

RESET Value

Read/Write

Bit Addressing

0

W

1

–

.3

Watch-dog timer’s counter clear bit

Clear and restart the watch-dog timer’s counter

1

NOTE: Instruction that clear the watch-dog timer (“BITS WDTCF”) should be executed at proper points in a program within

a given period. If not executed within a given period and watch-dog timer overflows, RESET signal is generated and

system is restarted with reset status.

4-35

MEMORY MAP

S3C7414/P7414/C7424/P7424/C7434/P7434

WMOD — Watch Timer Mode Register

WT

F89H, F88H

Bit

7

.7

0

6

"0"

0

5

.5

0

4

.4

0

3

"0"

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

WMOD.7

Enable/Disable Buzzer Output Bit

0

1

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

WMOD.6

Bit 6

0

Always logic zero

WMOD.5 – .4

Output Buzzer Frequency Selection Bits

0

1

0

1

0

1

fw/16 buzzer (BUZ) signal output (2 kHz)

fw/8 buzzer (BUZ) signal output (4 kHz)

fw/4 buzzer (BUZ) signal output (8 kHz)

fw/2 buzzer (BUZ) signal output (16 kHz)

WMOD.3

WMOD.2

Bit 3

0

Always logic zero

Enable/Disable Watch Timer Bit

0

1

Disable watch timer and clear frequency dividing circuits

Enable watch timer

WMOD.1

WMOD.0

Watch Timer Speed Control Bit

0

1

Normal speed; set IRQW to 0.5 seconds at 4.19 MHz

High-speed operation; set IRQW to 3.91 ms at 4.19 MHz

Watch timer Clock Selection Bit

Must be set to zero

0

NOTE: A system clock frequency (fx) of 4.19 MHz and a watch timer clock (fw) of 32.768 kHz are assumed.

4-36

S3C7414/P7414/C7424/P7424/C7434/P7434

OSCILLATOR CIRCUITS

6

OSCILLATOR CIRCUITS

OVERVIEW

The S3C7414/C7424/C7434 has a system clock circuit. The CPU and peripheral hardware operate on the system

clock frequency supplied through these on-chip circuits. Specifically, a clock is required by the following

peripheral modules:

— Basic timer

— Timer/counter 0

— Timer/counter 1

— Watch timer

— Serial I/O interface

— Clock output circuit

— A/D converter

The system clock frequency can be divided by 4, 8, or 64. By manipulating PCON bits 1 and 0, you can select

one of the following frequencies as the cpu clock.

fx

4

fx

8

fx

64

,

When the PCON register is cleared to zero after RESET, the normal CPU operating mode is enabled, a system

clock of fx/64 is selected.

Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle

power-down mode.

6-1

OSCILLATOR CIRCUITS

S3C7414/P7414/C7424/P7424/C7434/P7434

SYSTEM

OSCILLATOR

CIRCUIT

fx

Xin

Xout

WATCH TIMER

BASIC TIMER

FREQUENCY

DIVIDING

CIRCUIT

TIMER/COUNTER 0

TIMER/COUNTER 1

CLOCK OUTPUT CIRCUIT

A/D CONVERTER

OSCILLATOR

STOP

1/2

1/16

CPU

SELECTOR

CLOCK

1/4

CPU STOP SIGNAL

(IDLE MODE)

PCON.0

PCON.1

PCON.2

PCON.3

IDLE

WAIT RELEASE SIGNAL

OSCILLATOR

CONTROL

CIRCUIT

INTERNAL

SIGNAL

STOP

RESET

POWER-DOWN RELEASE SIGNAL

PCON.3,2 CLEAR

Figure 6-1. Clock Circuit Diagram

6-2

S3C7414/P7414/C7424/P7424/C7434/P7434

SYSTEM OSCILLATOR CIRCUITS

OSCILLATOR CIRCUITS

X

IN

X

IN

R

X

OUT

X

OUT

Figure 6-4. RC Oscillator

Figure 6-2. Crystal/Ceramic Oscillator

X

IN

X

OUT

Figure 6-3. External Oscillator

6-3

OSCILLATOR CIRCUITS

S3C7414/P7414/C7424/P7424/C7434/P7434

POWER CONTROL REGISTER (PCON)

The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control

CPU operating and power-down modes. PCON can be addressed directly by 4-bit write instructions or by the

instructions IDLE and STOP.

FB3H

PCON.3

PCON.2

PCON.1

PCON.0

PCON bits 3 and 2 are controlled by the STOP and IDLE instructions to engage the idle and stop power-down

modes. Idle and stop modes can be initiated by these instruction despite the current value of the enable memory

bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency.

RESET sets PCON register values to logic zero. PCON.1 and PCON.0 divide the frequency (fx) by 64, 8, and 4.

PCON.3 and PCON.2 enable normal CPU operating mode.

Table 6-1. Power Control Register (PCON) Organization

PCON Bit Settings

Resulting CPU Operating Mode

PCON.3

PCON.2

0

1

0

1

0

Normal CPU operating mode

Idle power-down mode

Stop power-down mode

PCON Bit Settings

Resulting CPU Clock Frequency

PCON.1

PCON.0

0

1

0

1

fx/64

fx/8

fx/4

+

PROGRAMMING TIP — Setting the CPU Clock

To set the CPU clock to 0.95 µs at 4.19 MHz:

BITS

SMB

LD

EMB

15

A,#3H

PCON,A

LD

6-4

S3C7414/P7414/C7424/P7424/C7434/P7434

INSTRUCTION CYCLE TIMES

OSCILLATOR CIRCUITS

The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by

4, 8, or 64). Table 6-2 shows corresponding cycle times in microseconds.

Table 6-2. Instruction Cycle Times for CPU Clock Rates

Selected

CPU Clock

Resulting Frequency

Oscillation

Source

Cycle Time (µsec)

fx/64

fx/8

65.5 kHz

524.0 kHz

1.05 MHz

fx = 4.19 MHz

15.3

1.91

0.95

fx/4

CLOCK OUTPUT MODE REGISTER (CLMOD)

The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the

CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions

only.

FD0H

CLMOD.3

"0"

CLMOD.1

CLMOD.0

RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without

initiating clock oscillation), and disables clock output.

CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four

possible clock sources and frequencies: normal CPU clock, fx/8, fx/16, or fx/64.

Table 6-3. Clock Output Mode Register (CLMOD) Organization

CLMOD Bit Settings

Resulting Clock Output

CLMOD.1

CLMOD.0

Clock Source

Frequency

1.05 MHz, 524 kHz, 65.5 kHz

524 kHz

0

1

0

1

0

1

CPU clock (fx/4, fx/8, fx/64)

fx/8

fx/16

fx/64

262 kHz

65.5 kHz

CLMOD.3

Result of CLMOD.3 Setting

0

1

Clock output is disabled

Clock output is enabled

NOTE: Frequencies assume that fx = 4.19 MHz.

6-5

OSCILLATOR CIRCUITS

CLOCK OUTPUT CIRCUIT

S3C7414/P7414/C7424/P7424/C7434/P7434

The clock output circuit, used to output clock pulses to the CLO pin, has the following components:

— 4-bit clock output mode register (CLMOD)

— Clock selector

— Output latch

— Port mode flag

— CLO output pin (P3.2)

CLO

CLMOD.3

CLMOD.2

4

CLMOD.1

CLOCK

P3.2 OUTPUT LATCH

PM3.2

SELECTOR

CLMOD.0

CLOCKS

(fx/8, fx/16, fx/64, CPU clock)

Figure 6-5. CLO Output Pin Circuit Diagram

CLOCK OUTPUT PROCEDURE

To output clock pulses to the CLO pin, follow this general procedure:

1. Disable clock output by clearing CLMOD.3 to logic zero.

2. Set the clock output frequency (CLMOD.1, CLMOD.0)).

3. Load a "0" to the output latch of the CLO pin (P3.2).

4. Set the P3.2 mode flag (PM3.2) to output mode.

5. Enable clock output by setting CLMOD.3 to logic one.

+

PROGRAMMING TIP — CPU Clock Output to the CLO Pin

To output the CPU clock to the CLO pin:

BITS

SMB

LD

BITR

LD

EMB

15

; Or BITR EMB

EA,#40H

PMG2,EA

P3.2

A,#9H

CLMOD,A

; P3.2 ¬ Output mode

; Clear P3.2 output latch

LD

6-6

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERRUPTS

7

INTERRUPTS

OVERVIEW

The S3C7414/C7424/C7434's interrupt control circuit has five functional components:

— Interrupt enable flags (IEx)

— Interrupt request flags (IRQx)

— Interrupt mask enable register (IME)

— Interrupt priority register (IPR)

— Power-down release signal circuit

Three kinds of interrupts are supported:

— Internal interrupts generated by on-chip processes

— External interrupts generated by external peripheral devices

— Quasi-interrupts used for edge detection and as clock sources

Table 7-1. Interrupt Types and Corresponding Port Pin(s)

Interrupt Type

External interrupts

Interrupt Name

INT0, INT1, INT4

Corresponding Port Pin

P1.0, P1.1, P1.3

Not applicable

Internal interrupts

Quasi-interrupts

INTB, INTT0, INTT1, INTAD, INTS

INT2

P1.2, P6.0–P6.3 (KS0–KS3)

Not applicable

INTW

7-1

INTERRUPTS

S3C7414/P7414/C7424/P7424/C7434/P7434

Vectored Interrupts

Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program

software. A vectored interrupt is generated when the following flags and register settings, corresponding to the

specific interrupt (INTn) are set to logic one:

— Interrupt enable flag (IEx)

— Interrupt master enable flag (IME)

— Interrupt request flag (IRQx)

— Interrupt status flags (IS0, IS1)

— Interrupt priority register (IPR)

If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is

loaded into the program counter and the program starts executing the service routine from this address.

EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM

during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction.

The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the

main routine, as well as during service routines. Any changes that are made to enable flag values during a

service routine are not stored in the vector address.

When an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the pro-

gram status word (PSW), and the enable flag values for the interrupt is fetched from the respective vector

address. Then, if necessary, you can modify the enable flags during the interrupt service routine. When the

interrupt service routine is returned to the main routine by the IRET instruction, the original values saved in the

stack are restored and the main program continues program execution with these values.

Software-Generated Interrupts

To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the

interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met,

and the service routine can be initiated.

Multiple Interrupts

By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and

thereby process multiple interrupts simultaneously.

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

Power-Down Mode Release

An interrupt (with the exception of INT0 and INTAD) can be used to release power-down mode (stop or idle).

Interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. Even if

the IME flag is cleared to zero, power-down mode will be released by an interrupt request signal when the

interrupt enable flag has been set. In such cases, the interrupt routine will not be executed since IME = "0".

7-2

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERRUPTS

Interrupt is generated (INT xx)

Request flag (IRQx) <-- 1

NO

IEx = 1?

YES

Retain value until IEx = 1

Generate corresponding vector interrupt

and release power-down mode

NO

IME = 1?

Retain value until IME = 1

YES

Retain value until interrupt

service routine is completed

IS1,0 = 0,0?

NO

IS1,0 = 0,1 ?

YES

NO

High-priority interrupt?

YES

IS1,0 = 0,1

IS1,0 = 1,0

Store contents of PC and PSW in the stack area;

set PC contents to corresponding vector address

Are both interrupt sources

YES

of shared vector address used?

IRQx flag value remains 1

NO

Reset corresponding IRQx flag

Jump to interrupt start address

Verify interrupt source and clear

IRQx with a BTSTZ instruction

Figure 7-1. Interrupt Execution Flowchart

7-3

INTERRUPTS

S3C7414/P7414/C7424/P7424/C7434/P7434

IE2 IEW IEAD IET1 IET0 IES IE1 IE0 IE4 IEB

IMOD1 IMOD0

IRQB

IRQ4

INTB

INT4

INT0

INT1

@

IRQ0

#

@

IRQ1

IRQS

IRQT0

IRQT1

IRQAD

IRQW

IRQ2

INTS

INTT0

INTT1

INTAD

INTW

INT2

KS0–KS3

SELECTOR

IMOD2

POWER-DOWN

MODE

RELEASE

SIGNAL

IME

IPR

INTERRUPT CONTROL UNIT

IS1 IS0

VECTOR

INTERRUPT

GENERATOR

= NOISE FILTERING CIRCUIT

@ = EDGE DETECTION CIRCUIT

#

Figure 7-2. Interrupt Control Circuit Diagram

7-4

S3C7414/P7414/C7424/P7424/C7434/P7434

MULTIPLE INTERRUPTS

INTERRUPTS

The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter-

rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service

routine for a lower-priority request is accepted during the execution of a higher priority routine.

Two-Level Interrupt Handling

Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits

in the PSW are both logic zero, program execution mode is normal and all interrupt requests are serviced (see

Figure 7-3).

Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one ("0" ® "1" or "1" ® "0"), and the

values are stored in the stack along with the other PSW bits. After the interrupt routine has been serviced, the

modified IS1 and IS0 values are automatically restored from the stack by an IRET instruction.

IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable

memory bank flag (EMB). Before you can modify an interrupt status flag, however, you must first disable

interrupt processing with a DI instruction.

When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt

currently defined by the interrupt priority register (IPR).

NORMAL PROGRAM

PROCESSING

(STATUS 0)

HIGH OR LOW LEVEL INTERRUPT

PROCESSING

(STATUS 1)

HIGH LEVEL INTERRUPT

PROCESSING

(STATUS 2)

INT DISABLE

SET IPR

INT ENABLE

LOW OR

HIGH LEVEL

INTERRUPT

GENERATED

HIGH-LEVEL

INTERRUPT

GENERATED

Figure 7-3. Two-Level Interrupt Handling

7-5

INTERRUPTS

S3C7414/P7414/C7424/P7424/C7434/P7434

Multi-Level Interrupt Handling

With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter-

rupt is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1 (see Table 7-2).

When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1"

and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority

request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority

level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7-4).

Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling

Process Status

Before INT

IS1 IS0

Effect of ISx Bit Setting

After INT ACK

IS1

0

IS0

1

0

1

0

All interrupt requests are serviced.

0

1

Only high-priority interrupts as determined by the

current settings in the IPR register are serviced.

1

0

2

–

1

0

1

No additional interrupt requests will be serviced.

Value undefined

–

NORMAL PROGRAM

PROCESSING

(STATUS 0)

SINGLE

INTERRUP

2-LEVEL

INTERRUPT

INT DISABLE

3-LEVEL

INTERRUPT

SET IPR

INT DISABLE

STATUS 1

INT ENABLE

MODIFY STATUS

INT ENABLE

LOW OR

HIGH LEVEL

INTERRUPT

GENERATED

STATUS 0

HIGH-LEVEL

INTERRUPT

GENERATED

LOW OR HIGH

LEVEL

STATUS 1 STATUS 2

INTERRUPT

GENERATED

STATUS 0

Figure 7-4. Multi-Level Interrupt Handling

7-6

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERRUPT PRIORITY REGISTER (IPR)

INTERRUPTS

The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic

zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI

instruction.

FB2H

IME

IPR.2

IPR.1

IPR.0

By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or

you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by

a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by

any other interrupt source.

Table 7-3. Standard Interrupt Priorities

Interrupt

INTB, INT4

INT0

Default Priority

1

2

3

4

5

6

7

INT1

INTS

INTT0

INTT1

INTAD

The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if

an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the

IME flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the

current enable memory bank (EMB) value.

Table 7-4. Interrupt Priority Register Settings

IPR.2

IPR.1

IPR.0

Result of IPR Bit Setting

Normal interrupt handling according to default priority settings

Process INTB and INT4 interrupts at the highest priority

Process INT0 interrupts at the highest priority

Process INT1 interrupts at the highest priority

Process INTS interrupts at the highest priority

Process INTT0 interrupts at the highest priority

Process INTT1 interrupts at the highest priority

Process INTAD interrupts at the highest priority

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NOTE: During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more

interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown

in Table 7-3. Using the IPR settings, you can select specific interrupts for high-priority processing in the event of

contention. When the high-priority (IPR) interrupt has been processed, waiting interrupts are handled according to

their default priorities.

7-7

INTERRUPTS

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — Setting the INT Interrupt Priority

The following instruction sequence sets the INT1 interrupt to high priority:

BITS

SMB

DI

EMB

15

; IPR.3 (IME) ¬ 0

LD

A,#3H

IPR,A

EI

; IPR.3 (IME) ¬ 1

EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (IMOD0, IMOD1)

The following components are used to process external interrupts at the INT0 and INT1 pin:

— Noise filtering circuit for INT0

— Edge detection circuit

— Two mode registers, IMOD0 and IMOD1

The mode registers are used to control the triggering edge of the input signal. IMOD0 and IMOD1 settings let you

choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The INT4 interrupt

is an exception since its input signal generates an interrupt request on both rising and falling edges.

FB4H

FB5H

IMOD0.3

"0"

IMOD0.1

"0"

IMOD0.0

IMOD1.0

IMOD0 and IMOD1 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic zero,

selecting rising edges as the trigger for incoming interrupt requests.

Table 7-5. IMOD0 and IMOD1 Register Organization

IMOD0

IMOD0.3

0

IMOD0.1

IMOD0.0

Effect of IMOD0 Settings

Select CPU clock for sampling

Select fx/64 sampling clock

Rising edge detection

0

1

0

1

0

1

0

1

Falling edge detection

Both rising and falling edge detection

IRQ0 flag cannot be set to "1"

IMOD1

0

IMOD1.0

Effect of IMOD1 Settings

Rising edge detection

0

1

Falling edge detection

7-8

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERRUPTS

EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (Continued)

When a sampling clock rate of fx/64 is used for INT0, an interrupt request flag must be cleared before 16 ma-

chine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take

the following precautions when you use it:

— To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of

the clock selected by IMOD0. This is true even when the INT0 pin is used for general-purpose input.

— Since the INT0 input sampling clock does not operate during stop or idle mode, you cannot use INT0 to re-

lease power-down mode.

INT0

NOISE

EDGE DETECTION

IRQ0

IRQ1

CLOCK

SELECTOR

CPU clock

fx/64

INT1

EDGE DETECTION

IMOD0

IMOD1

P1.1

P1.0

Figure 7-5. Circuit Diagram for INT0 and INT1 Pins

When modifying the IMOD0 and IMOD1 registers, it is possible to accidentally set an interrupt request flag. To

avoid unwanted interrupts, take these precautions when writing your programs:

1. Disable all interrupts with a DI instruction.

2. Modify the IMOD0 or IMOD1 register.

3. Clear all relevant interrupt request flags.

4. Enable the interrupt by setting the appropriate IEx flag.

5. Enable all interrupts with an EI instructions.

7-9

INTERRUPTS

S3C7414/P7414/C7424/P7424/C7434/P7434

EXTERNAL INTERRUPT 2 MODE REGISTER (IMOD2)

The mode register for external interrupts at the INT2 pin, IMOD2 is addressable only by 4-bit write instructions.

RESET clears all IMOD2 bits to logic zero.

FB6H

"0"

“0”

IMOD2.1 IMOD2.0

When IMOD2 is cleared to logic zero, INT2 uses the rising edge of an incoming signal as the interrupt request

trigger. If a rising edge is detected at the INT2 pin, or when a falling edge is detected at any one of the pins KS0–

KS3, the IRQ2 flag is set to logic one and a release signal for power-down mode is generated.

Table 7-6. IMOD2 Register Bit Settings

IMOD2

0

IMOD2.1

IMOD2.0

Effect of IMOD2 Settings

Select rising edge at INT2 pin

Select falling edge at KS0–KS1

Select falling edge at KS0–KS2

Select falling edge at KS0–KS3

0

1

0

1

0

1

7-10

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERRUPTS

RISING EDGE

DETECTION

INT2

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

FALLING

EDGE

DETECTION

CIRCUIT

CLOCK

SELECTOR

IRQ2

IMOD2

To generate a key interrupt on a falling edge at KS0-KS3, all KS0-KS3 pins

must be configured to input mode.

NOTE:

Figure 7-6. Circuit Diagram for INT2 and KS0–KS3 Pins

+

PROGRAMMING TIP — Using INT2 as a Key Input Interrupt

When the INT2 interrupt is used as a key interrupt, the key interrupt source pin must be set to input:

1. When KS0–KS2 are selected:

BITS

SMB

LD

EMB

15

A,#2H

LD

IMOD2,A

EA,#00H

PMG3,EA

EA,#40H

PUMOD1,EA

; (IMOD2) ¬ #2H, KS0–KS2 falling edge select

; P6 ¬ Input mode

LD

; Enable P6 pull-up resistors

7-11

INTERRUPTS

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERRUPT FLAGS

There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in-

terrupt, the interrupt master enable flag, which enables or disables all interrupt processing.

Interrupt Master Enable Flag (IME)

The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an

IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the

IME flag is set to logic one.

The IME flag is located in the IPR register (IPR.3), and can be directly be manipulated by EI and DI instructions,

regardless of the current value of the enable memory bank flag (EMB).

IME

0

IPR.2

IPR.1

IPR.0

Effect of Bit Settings

Inhibit all interrupts

Enable all interrupts

1

Interrupt Enable Flags (IEx)

IEx flags, when set to logic one, enable specific interrupt requests to be serviced. When the interrupt request flag

is set to logic one, an interrupt will not be serviced until its corresponding IEx flag is also enabled.

Interrupt enable flags can be read, written, or tested directly by 1-bit instructions (BITS and BITR) or 4-bit

instructions. IEx flags can be addressed directly at their specific RAM addresses, despite the current value of the

enable memory bank (EMB) flag.

Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses

Address

FB8H

Bit 3

IE4

0

Bit 2

Bit 1

IEB

Bit 0

IRQB

IRQW

IRQT1

IRQT0

IRQS

IRQ0

IRQ4

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

0

IEW

IET1

IET0

IES

IEAD

0

IRQAD

0

IE1

0

IRQ1

0

IE0

IE2

IRQ2

NOTES:

1. IEx refers generically to all interrupt enable flags.

2. IRQx refers generically to all interrupt request flags.

3. IEx = 0 is interrupt disable mode.

4. IEx = 1 is interrupt enable mode.

7-12

S3C7414/P7414/C7424/P7424/C7434/P7434

Interrupt Request Flags (IRQx)

INTERRUPTS

Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions. IRQx flags can be addressed

directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag.

When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then

automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt

request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt

service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary,

follow these guidelines for using IRQx flags:

1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.

2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the

exception of IRQW and IRQ2).

3. If IRQx is set to "1" by software, an interrupt is also generated.

When two interrupts share the same service routine start address, interrupt processing may occur in one of two

ways:

1. When only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been

serviced.

2. When two interrupts are enabled, the request flag is not automatically cleared so that the user has an

opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared

manually using a BTSTZ instruction.

Table 7-8. Interrupt Request Flag Conditions and Priorities

Interrupt

Source

Internal /

External

Pre-condition for IRQx Flag Setting

Interrupt

Priority

IRQ Flag

Name

INTB

INT4

INT0

INT1

INTS

I

Reference time interval signal from basic timer

Both rising and falling edges detected at INT4

Rising or falling edge detected at INT0 pin

Rising or falling edge detected at INT1 pin

1

2

3

4

IRQB

IRQ4

IRQ0

IRQ1

IRQS

E

I

Completion signal for serial transmit-and-re-

ceive or receive-only operation

INTT0

INTT1

I

Signals for TCNT0 and TREF0 registers match

Signals for TCNT1 and TREF1 registers match

Analog-to-digital conversion is completed

5

6

7

–

IRQT0

IRQT1

IRQAD

IRQ2

INTAD

I

INT2 ^(note)

E

Rising edge detected at INT2 or else a falling

edge is detected at any of the KS0–KS3 pins

INTW

I

Time interval of 0.5 secs or 3.19 msecs

–

IRQW

NOTE: The quasi-interrupt INT2 is only used for testing incoming signals.

7-13

INTERRUPTS

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — Enabling the INTB and INT4 Interrupts

To simultaneously enable INTB and INT4 interrupts:

INTB

DI

BTSTZ

JR

IRQB

INT4

; IRQB = 1 ?

; If no, INT4 interrupt; if yes, INTB interrupt is processed

•

EI

IRET

;

INT4

BITR

IRQ4

; INT4 is processed

•

EI

IRET

NOTE: When two interrupts share the same service routine start address, interrupt processing may occur in one of two

ways. First, when only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been

serviced. Second, when two interrupts are enabled, the request flag is not automatically cleared so that the user has

an opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared manually

using a BTSTZ instruction.

7-14

S3C7414/P7414/C7424/P7424/C7434/P7434

POWER-DOWN

8

POWER-DOWN

OVERVIEW

The S3C7414/C7424/C7434 microcontroller has two power-down modes to reduce power consumption: idle and

stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP

instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops

while peripherals and the oscillation source continue to operate normally.

When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and

the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has

elapsed, normal CPU operation resumes.

In stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware

components are powered-down. The effect of stop mode on specific peripheral hardware components — CPU,

basic timer, serial I/O, timer/counter, and watch timer — and on external interrupt requests, is detailed in Table

8-1.

NOTE

Do not use stop mode if you are using an external clock source because X_INinput must be restricted

internally to V_SSto reduce current leakage.

Idle or stop modes are terminated either by a RESET, or by an interrupt with the exception of INT0 and INTAD,

which are enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by

RESET input, a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt

request flag are set to "1", power-down mode is released immediately upon entering power-down mode.

When an interrupt is used to release power-down mode, the operation differs depending on the value of the

interrupt master enable flag (IME):

— If the IME flag = "0", program execution is started immediately after the instruction which issues the request

to enter power-down mode. The interrupt request flag remains set to logic one.

— If the IME flag = "1", two instructions are executed after the power-down mode release. Then, the vectored

interrupt is initiated. However, when the release signal is caused by INT2 or INTW, the operation is identical

to the IME = 0 condition. That is, a vector interrupt is not generated.

8-1

POWER-DOWN

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 8-1. Hardware Operation During Power-Down Modes

Operation

Stop Mode (STOP)

Idle Mode (IDLE)

Clock oscillator

System clock oscillation stops

CPU clock oscillation stops (system

clock oscillation continues)

Basic timer

Basic timer stops

Basic timer operates (with IRQB set at

each reference interval)

Serial interface

Operates if a clock other than the CPU

clock is selected as the serial I/O clock

Operates only if external SCK input is

selected as the serial I/O clock

Timer/Counter 0

Timer/Counter 1

Operates only if TCL0 is selected as the Timer/Counter 0 operates

counter clock

Operates only if TCL1 is selected as the Timer/Counter 1 operates

counter clock

A/D converter

Watch timer

A/D converter is disabled

Watch timer operates

Watch timer operation is stopped

External interrupts

INT1, INT2, and INT4 are acknowledged; INT1, INT2, and INT4 are acknowledged;

INT0 is not serviced

CPU

All CPU operations are disabled

Power-down mode

release signal

Interrupt request signals (except INT0

and INTAD) are enabled by an interrupt

Interrupt request signals (except INT0

and INTAD) are enabled by an interrupt

enable flag or by RESET input

8-2

S3C7414/P7414/C7424/P7424/C7434/P7434

IDLE MODE TIMING DIAGRAMS

POWER-DOWN

OSCILLATION

STABILIZATION

(31.3 ms / 4.19 MHz)

IDLE

INSTRUCTION

RESET

NORMAL MODE

IDLE MODE

NORMAL MODE

NORMAL OSCILLATION

CLOCK

SIGNAL

Figure 8-1. Timing When Idle Mode is Released by RESET

IDLE

INSTRUCTION

MODE

RELEASE

SIGNAL

INTERRUPT ACKNOWLEDGE (IME = 1)

NORMAL MODE

IDLE

NORMAL OSCILLATION

CLOCK

SIGNAL

Figure 8-2. Timing When Idle Mode is Released by an Interrupt

8-3

POWER-DOWN

S3C7414/P7414/C7424/P7424/C7434/P7434

STOP MODE TIMING DIAGRAMS

OSCILLATION

STABILIZATION

(31.3 ms / 4.19 MHz)

STOP

INSTRUCTION

RESET

NORMAL MODE

STOP MODE

IDLE MODE

NORMAL MODE

OSCILLATION

STOPS

OSCILLATION RESUMES

CLOCK

SIGNAL

Figure 8-3. Timing When Stop Mode is Released by RESET

OSCILLATION

STABILIZATION

(BMOD SETTING)

STOP

INSTRUCTION

MODE

RELEASE

SIGNAL

INT ACK (IME = 1)

NORMAL MODE

STOP MODE

IDLE MODE

NORMAL MODE

OSCILLATION

STOPS

OSCILLATION RESUMES

CLOCK

SIGNAL

Figure 8-4. Timing When Stop Mode is Release by an Interrupt

8-4

S3C7414/P7414/C7424/P7424/C7434/P7434

POWER-DOWN

I/O PORT PIN CONFIGURATION FOR POWER-DOWN

The following method describes how to configure I/O port pins to reduce power consumption during power-down

modes (stop, idle):

Condition 1: If the microcontroller is not configured to an external device:

1. Connect unused port pins according to the information in Table 8–2.

2. Disable all pull-up resistors for output pins by making the appropriate modifications to the pull-up resistor

mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-

expected surges of current through the pull-up.

3. Disable pull-up resistors for input pins configured to V

DD

or V levels in order to check the current input

SS

option. Reason: If the input level of a port pin is set to V when a pull-up resistor is enabled, it will draw an

SS

unnecessarily large current.

Condition 2: If the microcontroller is configured to an external device and the external device's V_DDsource is

turned off in power-down mode.

1. Connect unused port pins according to the information in Table 8-2.

2. Disable the pull-up resistors of output pins by making the appropriate modifications to the pull-up resistor

mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-

expected surges of current through the pull-up.

3. Disable pull-up resistors for input pins configured to V_DDor V_SSlevels in order to check the current input

option. Reason: If the input level of a port pin is set to V_SSwhen a pull-up resistor is enabled, it will draw an

unnecessarily large current.

4. Disable the pull-up resistors of input pins connected to the external device by making the necessary modi-

fications to the PUMOD register.

5. Configure the output pins that are connected to the external device to low level. Reason: When the external

device's V_DDsource is turned off, and if the microcontroller's output pins are set to high level, V_DD– 0.7 V is

supplied to the V_DDof the external device through its input pin. This causes the device to operate at the level

V_DD– 0.7 V. In this case, total current consumption would not be reduced.

6. Determine the correct output pin state necessary to block current pass in according with the external tran-

sistors (PNP, NPN).

8-5

POWER-DOWN

S3C7414/P7414/C7424/P7424/C7434/P7434

RECOMMENDED CONNECTIONS FOR UNUSED PINS

To reduce overall power consumption, please configure unused pins according to the guidelines described in

Table 8-2.

Table 8-2. Unused Pin Connections for Reduced Power Consumption

Pin/Share Pin Names

P0.0/SCK

Recommended Connection

Input mode: Connect to V_DD

P0.1/SO

P0.2/SI

Output mode: No connection

P0.3/BUZ

Connect to V_DD

Connect to V_SS

P1.0/INT0–P1.2/INT2

P1.3/INT4

Input mode: Connect to V_DD

Output mode: No connection

P2.0/AD0

P2.1/AD1

P2.2/AD2

P2.3/AD3

P3.0/AD4

P3.1/AD5

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0–P4.3

P5.0–P5.3

P6.0/KS0–P6.3/KS3

P7.0–P7.3

P8.0/TCL0

P8.1/TCLO0

P8.2

Connect to V_SS

NC

TEST

8-6

S3C7414/P7414/C7424/P7424/C7434/P7434

RESET

9

RESET

OVERVIEW

When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is

initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms

(when a BCNT.5 is set) at 4.19 MHz has elapsed, normal system operation resumes.

Regardless of when the RESET occurs — during normal operating mode or during a power-down mode — most

hardware register values are set to the reset values described in Table 9-1 below. The current status of several

register values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs

during normal operating mode, their values are undefined. Current values that are retained in this case are as

follows:

— Carry flag

— General-purpose registers E, A, L, H, X, W, Z, and Y

— Serial I/O buffer register (SBUF)

OSCILLATOR

STABILIZATION WAIT TIME

(31.3 ms / 4.19 MHz)

RESET

INPUT

NORMAL MODE

IDLE MODE

OPERATING MODE

OR

POWER-DOWN

MODE

OPERATION

RESET

Figure 9-1. Timing for Oscillation Stabilization After RESET

HARDWARE RESET VALUES AFTER RESET

Table 9-1 gives you detailed information about hardware register values after a RESET occurs during power-

down mode or during normal operation.

9-1

RESET

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 9-1. Hardware Register Values After RESET

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

Normal Operation

Program counter (PC)

Lower six bits of address 0000H

are transferred to PC11–8, and

the contents of 0001H to PC7–0.

Lower six bits of address 0000H

are transferred to PC11–8, and

the contents of 0001H to PC7–0.

Program Status Word (PSW):

Carry flag (C)

Values retained

Undefined

Skip flag (SC0–SC2)

0

Interrupt status flags (IS0, IS1)

Bank enable flags (EMB, ERB)

Bit 6 of address 0000H in program Bit 6 of address 0000H in program

memory is transferred to the ERB memory is transferred to the ERB

flag, and bit 7 of the address to

the EMB flag.

flag, and bit 7 of the address to

the EMB flag.

Stack pointer (SP)

Undefined

Data Memory (RAM):

Registers E, A, L, H, X, W, Z, Y

General-purpose registers

Values retained

Undefined

0, 0

Values retained ^(NOTE)

Bank selection registers (SMB, SRB)

BSC register (BSC0–BSC3)

0, 0

0

Clocks:

Power control register (PCON)

0

Clock output mode register (CLMOD)

Interrupts:

Interrupt request flags (IRQx)

Interrupt enable flags (IEx)

Interrupt priority flag (IPR)

0

Interrupt master enable flag (IME)

INT0 mode register (IMOD0)

INT1 mode register (IMOD1)

INT2 mode register (IMOD2)

NOTE: The values of the 0F8H–0FDH are not retained when a RESET signal is input.

9-2

S3C7414/P7414/C7424/P7424/C7434/P7434

RESET

Table 9-1. Hardware Register Values After RESET (Continued)

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

Normal Operation

I/O Ports:

Output buffers

Off

0

Off

0

Output latches

Port mode flags (PM)

0

Pull-up resistor mode reg (PUMOD1/2)

N-channel open-drain mode reg (PNE)

0

Watchdog Timer:

WDT mode register (WDMOD)

WDT clear flag (WDTCF)

A5H

0

A5H

0

Basic Timer:

Count register (BCNT)

Mode register (BMOD)

Undefined

0

Undefined

0

Timer/Counters 0 and 1:

Count registers (TCNT0/1)

Reference registers (TREF0/1)

Mode registers (TMOD0/1)

Output enable flags (TOE0/1)

0

FFH

0

FFH

0

Watch Timer:

Watch timer mode register (WMOD)

Serial I/O Interface:

0

SIO mode register (SMOD)

SIO interface buffer (SBUF)

0

Values retained

Undefined

A/D Converter

A/D mode register (ADMOD)

A/D data register (ADATA)

A/D control register (AFLAG)

0

9-3

RESET

S3C7414/P7414/C7424/P7424/C7434/P7434

NOTES

9-4

S3C7414/P7414/C7424/P7424/C7434/P7434

I/O PORTS

10 I/O PORTS

OVERVIEW

The S3C7414/C7424/C7434 has one input port and eight I/O ports. Pin addresses for all I/O ports are mapped in

bank 15 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding

address using bit manipulation instructions.

There are total of four input pins and 31 configurable I/O pin for a maximum number of 35 I/O pins.

Port Mode Flags

Port mode flags (PM) are used to configure I/O ports 0, 4, and 5 (port mode group 1), ports 2 and 3 (port mode

group 2), port 6 (port mode group 3), and ports 7 and 8 (port mode group 4) to input or output mode by setting or

clearing the corresponding register bit. PM flags are grouped in four 8-bit registers, and are addressable by 8-bit

write instructions only.

PUMOD Control Register

The pull-up mode registers (PUMOD1 and 2) are 8-bit registers used to assign internal pull-up resistors by

software to specific I/O ports.

When configurable I/O port serves as an output pin, its assigned pull-up resistor is automatically disabled, even

though the pin's pull-up resistor is enabled by a corresponding bit setting in the pull-up resistor mode register

(PUMOD).

PUMOD1 and 2 are addressable by 8-bit write instructions only. RESET clears PUMOD register values to logic

zero, automatically disconnecting all software-assignable port pull-up resistors.

N-channel Open-drain Mode Register

N-channel open-drain mode register (PNE) is used to configure ports 4 and 5 to n-channel open-drain or push-

pull outputs by setting or clearing bits in the PNE register.

10-1

I/O PORTS

S3C7414/P7414/C7424/P7424/C7434/P7434

Function Description

Table 10-1. I/O Port Overview

Port

I/O

Pins

Pin Names

Address

0

I/O

4

P0.0–P0.3

FF0H

4-bit I/O port.

1-bit and 4-bit read/write and test is possible.

Individual pins are software configurable as in-

put or output. 4-bit pull-up resistors are

assignable by software.

1

2

I

4

P1.0–P1.3

P2.0–P2.3

FF1H

FF2H

4-bit input port.

1-bit and 4-bit read and test is possible.

3-bit pull-up resistors are software assignable

to pins P1.0, P1.1, and P1.2.

I/O

4-bit I/O port.

N-channel open-drain output.

1-bit or 4-bit read/write and test is possible.

Individual pins are software configurable as

input or output.

4-bit pull-up resistors are software assignable.

3

I/O

4

8

P3.0–P3.3

FF3H

Same as port 0.

4, 5

P4.0–P4.3

P5.0–P5.3

FF4H

FF5H

4-bit I/O ports.

Ports 4 and 5 can be configured individually

as n-channel open-drain or as CMOS push-

pull output by software.

1-bit and 4-bit read/write and test is possible.

Ports 4 and 5 can be paired to enable 8-bit

data transfer.

4-bit pull-up resistors are software assignable.

6

7

8

I/O

4

3

P6.0–P6.3

P7.0–P7.3

P8.0–P8.2

FF6H

FF7H

FF8H

Same as port 0.

Same as port 0 except port 8 is 3-bit I/O port

Table 10-2. Port Pin Status During Instruction Execution

Instruction Type

Example

Input Mode Status

Output Mode Status

1-bit test

BTST P0.1

Input or test data at each pin

Input or test data at output latch

1-bit input

4-bit input

8-bit input

LDB

LD

C,P1.3

A,P7

EA,P4

1-bit output

BITR P2.3

Output latch contents undefined

Output pin status is modified

4-bit output

8-bit output

LD

P2,A

P4,EA

Transfer accumulator data to the

output latch

Transfer accumulator data to the

output pin

10-2

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT MODE FLAGS (PM FLAGS)

I/O PORTS

Port mode flags (PM) are used to configure I/O ports 0 and 2–8 to input or output mode by setting or clearing the

corresponding I/O buffer.

For convenient program reference, PM flags are organized into four groups — PMG1, PMG2, PMG3, and PMG4

as shown in Table 10-3. They can be addressed by 8-bit write instructions only.

When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears

all port mode flags to logic zero, automatically configuring the corresponding I/O ports to input mode.

Table 10-3. Port Mode Group Flags

PM Group ID

Address

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

Bit 3

PM0.3

0

Bit 2

PM0.2

0

Bit 1

PM0.1

PM5

Bit 0

PM0.0

PM4

PMG1

PMG2

PMG3

PMG4

PM2.3

PM3.3

PM6.3

0

PM2.2

PM3.2

PM6.2

0

PM2.1

PM3.1

PM6.1

0

PM2.0

PM3.0

PM6.0

0

PM7.3

–

PM7.2

PM8.2

PM7.1

PM8.1

PM7.0

PM8.0

NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode: PM0.0 for

P0.0, PM4 for P4, etc. All flags are cleared to "0" following RESET.

+

PROGRAMMING TIP — Configuring I/O Ports to Input or Output

Configure P0.3 and P2 as an output port and the other ports as input ports:

BITS

SMB

LD

EMB

15

EA,#08H

PMG1,EA

EA,#0FH

PMG2,EA

EA,#00H

PMG3,EA

PMG4,EA

; P0.3 ¬ Output, P0.0–0.2, P4, P5 ¬ Input

; P2.0–2.3 ¬ Output, P3.0–3.3 ¬ Input

; P6 ¬ Input

; P7, P8 ¬ Input

10-3

I/O PORTS

S3C7414/P7414/C7424/P7424/C7434/P7434

PULL-UP RESISTOR MODE REGISTER (PUMOD)

The pull-up resistor mode registers (PUMOD1 and 2) are 8-bit registers used to assign internal pull-up resistors

by software to specific I/O ports.

When configurable I/O port is used as an output pin, its assigned pull-up resistor is automatically disabled, even

though the pin's pull-up is enabled by a corresponding PUMOD bit setting.

PUMOD1 and PUMOD2 are addressable by 8-bit write instructions only. RESET clears PUMOD register values

to logic zero, automatically disconnecting all software-assignable port pull-up resistors.

Table 10-4. Pull-up Resistor Mode Register (PUMOD) Organization

PUMOD ID

Address

FDCH

FDDH

FDEH

FDFH

Bit 3

PUR3

PUR7

"0"

Bit 2

PUR2

PUR6

"0"

Bit 1

PUR1

PUR5

"0"

Bit 0

PUR0

PUR4

PUR8

"0"

PUMOD1

PUMOD2

"0"

NOTE: When bit = "1", pull-up resistors are assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2, and

so on.

+

PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors

P6 and P7 enable pull-up resistors, P0–P5 disable pull-up resistors.

BITS

SMB

LD

EMB

15

EA,#0C0H

PUMOD1,EA

LD

; P6 and P7 enable

N-CHANNEL OPEN-DRAIN MODE REGISTER (PNE)

The n-channel open-drain mode register (PNE) is used to configure ports 4 and 5 to n-channel open-drain or

push-pull outputs. When a bit in the PNE register is set to 1, the corresponding output pin is configured to n-

channel open-drain, when set to 0, the output pin is configured to push-pull. The PNE register consists of two 4-

bit registers; PNE4, PNE5, and can be addressed 8-bit write instructions only.

PNE ID

Address

FFAH

Bit 3

Bit 2

Bit 1

Bit 0

PNE

PNE4.3

PNE5.3

PNE4.2

PNE5.2

PNE4.1

PNE5.1

PNE4.0

PNE5.0

PNE4

PNE5

FFBH

10-4

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 0 CIRCUIT DIAGRAM

I/O PORTS

P0.0

P0.1

P0.2

P0.3

LATCH

LATCH LATCH LATCH

SCK

SO

V

DD

SCK

SI

BUZ

PUR0

PM0.0

PM0.1

PM0.2

PM0.3

P0.3/BUZ

P0.2/SI

P0.1/SO

P0.0/

SCK

When a port pin acts as an output, its pull-up resistor is automatically disabled,

even though the port's pull-up resistor is enabled by bit settings to the pull-up

resistor mode register (PUMOD).

NOTE:

Figure 10-1. Port 0 Circuit Diagram

10-5

I/O PORTS

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 1 CIRCUIT DIAGRAM

V

DD

INT0 INT1

INT2

INT4

IMOD0

PUR1

N/R

CIRCUIT

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

N/R = NOISE REDUCTION

Figure 10-2. Port 1 Circuit Diagram

10-6

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 2 CIRCUIT DIAGRAM

I/O PORTS

V

DD

PUR2

PM2.3

PM2.2

PM2.1

PM2.0

P2.0/AD0

P2.1/AD1

P2.2/AD2

P2.3/AD3

OUTPUT

LATCH

1, 4

M

U

X

1, 4

AD0

AD1

AD2

AD3

ADMOD

NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though

the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

Figure 10-3. Port 2 Circuit Diagram

10-7

I/O PORTS

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 3 CIRCUIT DIAGRAM

V

DD

CLOCK OUTPUT

TC1 CLOCK OUTPUT

PUR3

PM3.3

PM3.2

PM3.1

PM3.0

P3.0/AD4

P3.1/AD5

OUTPUT

LATCH

1, 4

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

M

U

X

1, 4

AD4

AD5

TCL1

ADMOD

NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled,

even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor

mode register (PUMOD).

Figure 10-4. Port 3 Circuit Diagram

10-8

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 4, 5 CIRCUIT DIAGRAM

I/O PORTS

x = 4, 5

PNEx.3

V

DD

PNEx.2

PNEx.1

PURx

PNEx.0

PMx

Px.0

Px.1

Px.2

Px.3

OUTPUT

LATCH

1, 4, 8

CMOS PUSH -PULL,

N-CHANNEL

OPEN-DRAIN

M

U

X

1, 4, 8

When a port pin serves as an output, its pull-up resistor is automatically disabled, even

though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode

register (PUMOD).

NOTE:

Figure 10-5. Port 4 and 5 Circuit Diagram

10-9

I/O PORTS

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 6 CIRCUIT DIAGRAM

V

DD

PUR6

PM6.3

PM6.2

PM6.1

PM6.0

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

OUTPUT

1, 4

LATCH

M

1, 4

U

X

When a port pin serves as an output, its pull-up resistor is automatically disabled, even

though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode

register (PUMOD).

NOTE:

Figure 10-6. Port 6 Circuit Diagram

10-10

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 7 CIRCUIT DIAGRAM

I/O PORTS

V

DD

PUR7

PM7.3

PM7.2

PM7.1

PM7.0

P7.0

P7.1

P7.2

P7.3

OUTPUT

LATCH

1, 4

M

U

X

1, 4

When a port pin serves as an output, its pull-up resistor is automatically disabled, even

though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode

register (PUMOD).

NOTE:

Figure 10-7. Port 7 Circuit Diagram

10-11

I/O PORTS

S3C7414/P7414/C7424/P7424/C7434/P7434

PORT 8 CIRCUIT DIAGRAM

V

DD

PUR8.2

PUR8.1

PUR8.0

TC0 CLOCK OUTPUT

PM8.2

PM8.1

PM8.0

P8.0/TCL0

P8.1/TCLO0

P8.2

OUTPUT

1, 4

LATCH

M

1, 4

U

X

TCL0

When a port pin serves as an output, its pull-up resistor is automatically disabled, even

though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode

register (PUMOD).

NOTE:

Figure 10-8. Port 8 Circuit Diagram

10-12

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

11 TIMERS and TIMER/COUNTER

OVERVIEW

The S3C7414/C7424/C7434 microcontroller has four timer and timer/counter modules:

— 8-bit basic timer (BT)

— 8-bit timer/counter (TC0)

— 8-bit timer/counter (TC1)

— Watch timer (WT)

The 8-bit basic timer (BT) is the microcontroller's main interval timer. It generates an interrupt request at a fixed

time interval when the appropriate modification is made to its mode register. The basic timer also functions as a

'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an

interrupt and after a RESET.

The 8-bit timer/counter (TC0) are programmable timer/counters that are used primarily for event counting and for

clock frequency modification and output. In addition, TC0 generates a clock signal that can be used by the serial

I/O interface.

The 8-bit timer/counter (TC1) are programmable timer/counters that are used primarily for event counting and for

clock frequency modification and PWM output.

The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency

divider circuit. Watch timer functions include real-time and watch-time measurement, system clock interval

timing, buzzer output generation.

11-1

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

BASIC TIMER (BT)

OVERVIEW

The 8-bit basic timer (BT) has six functional components:

— Clock selector logic

— 4-bit mode register (BMOD)

— 8-bit counter register (BCNT)

— Watchdog timer control register (WDMOD)

— Watchdog timer clear flag (WDTCF)

— 3-bit watchdog counter register (WDCNT)

The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.

You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize

clock oscillation when stop mode is released by an interrupt or following RESET.

Use the basic timer mode register, BMOD, to enable/disable basic timer, to select input clock frequency, and to

control interrupt or stabilization intervals.

Interval Timer Function

The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT

clock pulses.

To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the

interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2–BMOD.0.

The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the

frequency selected by BMOD register. BCNT continues incrementing as it counts BT clocks until an overflow

occurs.

An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time

interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting

continues from 00H.

Watchdog Timer Function

The basic timer can also be used as a "watch-dog" timer to detects inadvertent program loop, that is, system or

program operation error. For this purpose, instruction that clear the watch-dog timer(BITS WDTCF) should be

executed at proper points in a program within a given period. If an instruction that clears the watch-dog timer is

not executed within the period and the watch-dog timer overflows, reset signal is generated and system is

restarted with reset status. An operation of watch-dog timer is as follows:

¾

Write some value(except #5AH) to Watch-Dog Timer Mode register, WDMOD.

If WDCNT overflows, system reset is generated.

Oscillation Stabilization Interval Control

Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also

determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when

power-down mode is released by an interrupt. When a RESET signal is generated, the standard stabilization

interval for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.

11-2

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

Table 11-1. Basic Timer Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

BMOD

Control Controls the clock frequency (mode)

of the basic timer; also, the oscillation

stabilization interval after power-down

F85H

4-bit

write-only;

BMOD.3: also

1-bit writeable

4-bit

"0"

mode release or RESET

U ^(note)

A5H

"0"

BCNT

Counter Counts clock pulses matching the

BMOD frequency setting

F86H–F87H 8-bit

read-only

8-bit

1-bit

F98HÄF99H

WDMOD Control Controls watch-dog timer operation.

8-bit

write-only

WDTCF Control Clear the watch-dog timer's counter.

F9AH.3

1-bit

write-only

NOTE: 'U' mans the value is undetermined after a RESET.

"CLEAR" SIGNAL

CLEAR

BCNT

CLEAR

IRQB

BITS

INSTRUCTION

BMOD.3

INTERRUPT

REQUEST

OVERFLOW

BMOD.2

CLOCK

4

IRQB

BCNT

SELECTOR

BMOD.1

1-BIT R/W

BMOD.0

CPU CLOCK

8

When

BCNT.5

is set

START SIGNAL

(POWER-DOWN

RELEASE)

CLOCK INPUT

8

1 pulse period=BT input clock 2 (1/2 duty)

RESET

GENERATION

WDCNT

RESET

WDMOD

8

WDTCF

BITS

DELAY

NOTE:

CLEAR

WAIT ^(NOTE)

STOP

WAIT means stabilization time after

RESET

or Stabilization time after

RESET

INSTRUCTION

STOP mode release

Figure 11-1. Basic Timer Circuit Diagram

11-3

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

BASIC TIMER MODE REGISTER (BMOD)

The basic timer mode register, BMOD, is a 4-bit write-only register located at RAM address F85H. Bit 3, the

basic timer start control bit, is also 1-bit addressable. All BMOD values are set to logic zero following RESET and

interrupt request signal generation is set to the longest interval. (BT counter operation cannot be stopped.)

BMOD settings have the following effects:

— Restart the basic timer,

— Control the frequency of clock signal input to the basic timer, and

— Determine time interval required for clock oscillation to stabilize following the release of stop modes by an

interrupt.

By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency

during program execution. Four BT frequencies, ranging from fx/2¹²(1.02 kHz) to fx/2⁵(131 kHz), are selectable.

12

Since BMOD's reset value is logic zero, the default clock frequency setting is fx/2 . (kHz frequencies assume a

system clock (fx) frequency of 4.19 MHz.)

The most significant bit of the BMOD register, BMOD.3, is used to start the basic timer again. When BMOD.3 is

set to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT

interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted.

The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 — determine

the clock input frequency and oscillation stabilization interval.

Table 11-2. Basic Timer Mode Register (BMOD) Organization

BMOD.3

Basic Timer Enable/Disable Control Bit

1

Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"

BMOD.2

BMOD.1

BMOD.0

Basic Timer Input Clock

Oscillation Stabilization

12

20

0

1

0

1

0

1

0

1

fx/2 (1.02 kHz)

2

/fx (250 ms)

/fx (31.3 ms)

/fx (7.82 ms)

/fx (1.95 ms)

9

17

15

13

fx/2 (8.18 kHz)

2

7

fx/2 (32.7 kHz)

5

fx/2 (131 kHz)

NOTES:

1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz.

2. fx = system clock frequency.

3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released.

4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.

11-4

S3C7414/P7414/C7424/P7424/C7434/P7434

BASIC TIMER COUNTER (BCNT)

TIMERS and TIMER/COUNTER

BCNT is an 8-bit counter register for the basic timer. It is mapped to RAM addresses F86H–F87H and can be

addressed by 8-bit read instructions.

RESET leaves the BCNT register value undetermined. BCNT is automatically cleared to logic zero whenever the

BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock

pulse of the frequency determined by the current BMOD bit settings is detected.

When BCNT has incremented to hexadecimal 'FFH' (256 clock pulses), it is cleared to '00H' and an overflow is

generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt

request is generated, BCNT immediately resumes counting incoming clock signals.

NOTE

Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while

the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the

latter value as valid data. Until the results of the consecutive reads match, however, the read operation

must be repeated until the validation condition is met.

BASIC TIMER OPERATION SEQUENCE

The basic timer's sequence of operations may be summarized as follows:

1. Set bit BMOD.3 to logic one to restart basic timer operation

2. BCNT is incremented by one after each clock pulse corresponding to BMOD selection

3. BCNT overflows if BCNT ³ 255 (FFH)

4. When an overflow occurs, the IRQB flag is set to logic one by hardware

5. The interrupt request is generated

6. BCNT is automatically cleared to logic zero (BCNT = 00H)

7. BCNT resumes counting basic timer clock pulse

11-5

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — Using the Basic Timer

1. To read the basic timer count register (BCNT):

BITS

SMB

LD

EMB

15

BCNTR

EA,BCNT

YZ,EA

EA,BCNT

EA,YZ

BCNTR

CPSE

JR

2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms:

BITS

SMB

LD

EMB

15

A,#0BH

BMOD,A

LD

; Wait time is 31.3 ms

STOP

NOP

; Set stop power-down mode

NORMAL

OPERATING MODE

NORMAL

OPERATING MODE

STOP MODE

IDLE MODE

(31.3 ms)

CPU

OPERATION

STOP

INSTRUCTION

STOP MODE IS

RELEASED BY

INTERRUPT

3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):

BITS

SMB

LD

EMB

15

A,#0FH

BMOD,A

LD

EI

BITS

IEB

; Basic timer interrupt enable flag is set to "1"

4. Clear BCNT and the IRQB flag and restart the basic timer:

BITS

SMB

BITS

EMB

15

BMOD.3

11-6

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

WATCH-DOG TIMER MODE REGISTER (WDMOD)

The watch-dog timer mode register, WDMOD, is a 8-bit write-only register located at RAM address F98H–F99H.

WDMOD register controls to enable or disable the watch-dog timer function. WDMOD values are set to logic

"A5H" following RESET and this value enable the watch-dog timer, and watch-dog timer's period is set to the

longest interval because basic timer overflow signal is generated with the longest interval. (Basic timer counter

operation cannot be stopped.)

WDMOD - Watch–Dog Timer Mode Control Register

F99H,F98H

Bit

7

.7

1

6

.6

0

5

.5

1

4

.4

0

3

.3

0

2

.2

1

.1

0

.0

1

Identifier

RESET Value

Read/Write

W

WDMOD

Watch-Dog Timer Enable/Disable Control

5AH

Disable Watch-dog timer function

Enable Watch-dog timer function

Any other Value

WATCH-DOG TIMER COUNTER (WDCNT)

WDCNT is an 3-bit counter. WDCNT is automatically cleared to logic zero whenever the WDTCF register control

bit (WDTCF) is set to "1" to restart the WDCNT. Reset, stop, and wait signal clear the WDCNT to logic zero also.

WDCNT is incremented each time a clock pulse of the overflow frequency determined by the current BMOD bit

settings. When WDCNT has incremented to hexadecimal '07H' (8 basic timer overflow pulses), it is cleared to

'00H' and an overflow is generated. The overflow causes the system reset. When the interrupt request is

generated, BCNT immediately resumes counting incoming clock signals.

WATCH-DOG TIMER'S COUNTER CLEAR FLAG(WDTCF)

WDTCF(F9AH.3) setting clear the WDT's counter to zero and restart the WDT's counter.

Table 11-3. Watch-Dog Timer Interval Time

BMOD

x000b

x011b

x101b

x111b

BT Input Clock

WDCNT input clock

12

WDT interval time

12

Main clock

2 sec

12

8

3

2

/fx

2

/fx ´ 2

2

/fx ´ 2 ´ 2

9

8

9

8

3

250 msec

62.5 msec

15.6 msec

2 /fx

2 /fx ´ 2

2 /fx ´ 2 ´ 2

7

8

2 /fx

2 /fx ´ 2

2 /fx ´ 2 ´ 2

5

8

2 /fx

2 /fx ´ 2

2 /fx ´ 2 ´ 2

NOTES:

1. Clock frequencies assume a system oscillator clock frequency (fx) of : Main clock 4.19MHz

2. fx = system clock frequency.

11-7

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

8-BIT TIMER/COUNTER 0 (TC0)

OVERVIEW

Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of

incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has

elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter

value with the reference register value, TC0 can be used to measure specific time intervals.

TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write

the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by

counter logic.

An 8-bit mode register, TMOD0, is used to activate the timer/counter 0 and to select the basic clock frequency to

be used for timer/counter 0 operations. To dynamically modify the basic frequency, new values can be loaded

into the TMOD0 register during program execution.

TC0 FUNCTION SUMMARY

8-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock

frequency.

Counts various system "events" based on edge detection of external clock

signals at the TC0 input pin, TCL0.

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC0 output pin, TCLO0.

Divides the frequency of an incoming external clock signal according to a

modifiable reference value (TREF0), and outputs the modified frequency to the

TCLO0 pin.

Serial I/O clock source

Outputs a modifiable clock signal for use as the SCK clock source.

11-8

S3C7414/P7414/C7424/P7424/C7434/P7434

TC0 COMPONENT SUMMARY

TIMERS and TIMER/COUNTER

Mode register (TMOD0)

Reference register (TREF0)

Counter register (TCNT0)

Clock selector circuit

Activates the timer/counter 0 and selects the internal clock frequency or the

external clock source at the TCL0 pin.

Stores the reference value for the desired number of clock pulses between

interrupt requests.

Counts internal or external clock pulses based on the bit settings in TMOD0

and TREF0.

Together with the mode register (TMOD0), lets you select one of four internal

clock frequencies or an external clock.

8-bit comparator

Determines when to generate an interrupt by comparing the current value of

the counter register (TCNT0) with the reference value previously programmed

into the reference register (TREF0).

Output latch (TOL0)

Where a TC0 interrupt request or clock pulse is stored pending output to the

serial I/O circuit or to the TC0 output pin, TCLO0.

When the contents 0 of the TCNT0 and TREF0 registers coincide, the

timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is

inverted, and an interrupt is generated.

Output enable flag (TOE0)

Must be set to logic one before the contents of the TOL0 latch can be output to

TCLO0.

Interrupt request flag (IRQT0) Cleared when TC0 operation starts and the TC0 interrupt service routine is

executed and set to 1 whenever the counter value and reference value

coincide.

Interrupt enable flag (IET0)

Must be set to logic one before the interrupt requests generated by

timer/counter 0 can be processed.

Table 11-4. TC0 Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

Controls TC0 enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and clock frequency

(bits 6–4)

8-bit

TMOD0

Control

8-bit F90H–F91H

"0"

write-only;

(TMOD0.3 is

also 1-bit

writeable)

Counts clock pulses matching

the TMOD0 frequency setting

8-bit

read-only

TCNT0

TREF0

TOE0

Counter

Reference

Flag

8-bit F94H–F95H

8-bit F96H–F97H

1-bit F92H.2

"0"

FFH

"0"

Stores reference value for the

timer/counter 0 interval setting

8-bit

write-only

Controls timer/counter 0 output

to the TCLO0 pin

1-bit or 4-bit

read/write-

only

11-9

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

CLOCKS

(fx/2 , fx/2 , fx/2 , fx)

10

6

4

P8.0/TCL0

8

TMOD0.7

TMOD0.6

TMOD0.5

8

8-BIT

TREF0

TCNT0

COMPARATOR

CLOCK

SELECTOR

8

TMOD0.4

CLEAR

TMOD0.3

TMOD0.2

TMOD0.1

TMOD0.0

INVERTED

CLEAR

SET

IRQT0

CLEAR

TOL0

SERIAL I/O

P8.1/TCLO0

PM8.1

P8.1 LATCH

TOE0

Figure 11-2. TC0 Circuit Diagram

TC0 ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 0

— Set TMOD0.2 to logic one

— Set the TC0 interrupt enable flag IET0 to logic one

— Set TMOD0.3 to logic one

TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 0

— Set TMOD0.2 to logic zero

Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read

if necessary.

11-10

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected

system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter 0 and to select

the clock frequency. The reference register TREF0 stores the value for the number of clock pulses to be

generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are

compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt

request is generated.

To program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock

frequencies (divisions of the system clock, fx) and load a counter reference value into the TREF0 register.

TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMOD0.4–TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag

(IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is output. The content of TCNT0 is

then cleared to 00H and TC0 continues counting. The interrupt request mechanism for TC0 includes an interrupt

enable flag (IET0) and an interrupt request flag (IRQT0).

TC0 OPERATION SEQUENCE

The general sequence of operations for using TC0 can be summarized as follows:

1. Set TMOD0.2 to "1" to enable TC0

2. Set TMOD0.6 to "1" to enable the system clock (fx) input

n

3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fx/2 )

4. Load a value to TREF0 to specify the interval between interrupt requests

5. Set the TC0 interrupt enable flag (IET0) to "1"

6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting

7. TCNT0 increments with each internal clock pulse

8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1"

9. Output latch (TOL0) logic toggles high or low

10. Interrupt request is generated

11. TCNT0 is cleared to 00H and counting resumes

12. Programmable timer/counter 0 operation continues until TMOD0.2 is cleared to "0".

11-11

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

TC0 EVENT COUNTER FUNCTION

Timer/counter 0 can monitor or detect system 'events' by using the external clock input at the TCL0 pin as the

counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals. The

counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMOD0.4–TMOD0.6 settings, the operation sequence for TC0's event counter

function is identical to its programmable timer/counter function. To activate the TC0 event counter function,

— Set TMOD0.2 to "1" to enable TC0;

— Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin;

— Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5

and TMOD0.4.

— P8.0 must be set to input mode.

Table 11-5. TMOD0 Settings for TCL0 Edge Detection

TMOD0.5

TMOD0.4

TCL0 Edge Detection

Rising edges

0

1

Falling edges

11-12

S3C7414/P7414/C7424/P7424/C7434/P7434

TC0 CLOCK FREQUENCY OUTPUT

TIMERS and TIMER/COUNTER

Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select

the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is

selected by loading the desired reference value into the reference register TREF0. To enable the output to the

TCLO0 pin at I/O port 8.1, the following conditions must be met:

1. Load a reference value to TREF0.

2. Set the internal clock frequency in TMOD0.

3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1").

4. Set P8.1 mode flag (PM8.1) to "1".

5. Set P8.1 output latch to "0".

6. Set TOE0 flag to "1".

Each time the contents of TCNTn and TREFn coincide and an interrupt request is generated, the state of the

output latch TOL0 is inverted and the TC0-generated clock signal is output to the TCLO0 pin.

+

PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin

Output a 30 ms pulse width signal to the TCLO0 pin:

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

EA,#20H

PMG4,EA

P8.1

; P8.1 ¬ output mode

; P8.1 clear

TOE0

11-13

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

TC0 SERIAL I/O CLOCK GENERATION

Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter

and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register,

SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface.

Use TMOD0 and TREF0 register settings to select the frequency and interval of the TC0 clock signals to be used

as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock

selector circuit — not through the port 8.1 latch and TCLO0 pin (the TOE0 flag may be disabled).

TC0 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you

can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the

TCLO0 pin. The sequence of operations used to divide external clock input can be summarized as follows:

1. Load a signal divider value to the TREF0 register

2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin

3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection

4. Set port 8.1 mode flag (PM8.1) to output ("1")

5. Set P8.1 output latch to "0"

6. Set TOE0 flag to "1" to enable output of the divided frequency to the TCLO0 pin

+

PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin

Output external TCL0 clock pulse to the TCLO0 pin (divide by four):

EXTERNAL (TCL0)

CLOCK PULSE

TCLO0

OUTPUT

PULSE

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#01H

TREF0,EA

EA,#0CH

TMOD0,EA

EA,#20H

PMG4,EA

P8.1

; P8.1 ¬ output mode

; P8.1 clear

TOE0

11-14

S3C7414/P7414/C7424/P7424/C7434/P7434

TC0 MODE REGISTER (TMOD0)

TIMERS and TIMER/COUNTER

TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit,

TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations.

F90H

F91H

TMOD0.3

"0"

TMOD0.2

TMOD0.6

"0"

TMOD0.5

TMOD0.4

TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0,

IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal

TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are

retained until TC0 is re-enabled.

The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This

selection involves two variables:

— Synchronization of timer/counter 0 operations with either the rising edge or the falling edge of the clock sig-

nal input at the TCL0 pin, and

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC0 operation.

Table 11-6. TC0 Mode Register (TMOD0) Organization

Bit Name

TMOD0.7

TMOD0.6

TMOD0.5

TMOD0.4

TMOD0.3

Setting

Resulting TC0 Function

Address

0

Always logic zero

F91H

0,1

Specify external input clock edge and internal frequency

1

Clear TCNT0, IRQT0, and TOL0 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes.)

F90H

TMOD0.2

0

1

0

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

TMOD0.1

TMOD0.0

Always logic zero

11-15

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 11-7. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings

TMOD0.6

TMOD0.5

TMOD0.4

Resulting Counter Source and Clock Frequency

External clock input (TCL0) on rising edges

0

1

0

1

0

1

0

1

0

1

External clock input (TCL0) on falling edges

10

fx/2 (4.09 kHz)

6

fx /2 (65.5 kHz)

4

fx/2 (262 kHz)

fx = 4.19 MHz

NOTE: 'fx' = system clock of 4.19 MHz.

+

PROGRAMMING TIP — Restarting TC0 Counting Operation

1. Set TC0 timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD0,EA

LD

EI

BITS

IET0

2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:

BITS

SMB

BITS

EMB

15

TMOD0.3

11-16

S3C7414/P7414/C7424/P7424/C7434/P7434

TC0 COUNTER REGISTER (TCNT0)

TIMERS and TIMER/COUNTER

The 8-bit counter register for timer/counter 0, TCNT0, is mapped to RAM addresses F94H–F95H. It is read-only

and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero

(00H).

Whenever TMOD0.3 is enabled, TCNT0 is cleared to logic zero and counting resumes. The TCNT0 register

value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency

setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4).

Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 refer-ence

register, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag,

IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter 0

interval has elapsed.

COUNT

CLOCK

TREF0

TCNT0

REFERENCE VALUE = n

0

1

2

n-1

n

0

1

2

n-1

n

0

1

2

3

MATCH

TOL0

INTERVAL TIME

TIMER START

INSTRUCTION

IRQT0 SET

Figure 11-3. TC0 Timing Diagram

11-17

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

TC0 REFERENCE REGISTER (TREF0)

The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control

instructions. RESET initializes the TREF0 value to 'FFH'.

TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify

an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used

to perform — as a programmable timer/counter 0, event counter, clock signal divider, or arbitrary frequency

output source.

During timer/counter 0 operation, the value loaded into the reference register is compared to the TCNT0 value.

When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal

the interval or event. The TREF0 value, together with the TMOD0 clock frequency selection, determines the

specific TC0 timer interval. Use the following formula to calculate the correct value to load to the TREF0

reference register:

1

TC0 timer interval = (TREF0 value + 1) ´

TMOD0 frequency setting

( assuming a TREF0 value ¹ 0 )

TC0 OUTPUT ENABLE FLAG (TOE0)

The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0

is addressable by 1-bit read and write instructions.

Bit 3

Bit 2

Bit 1

"0"

Bit 0

"0"

F92H

TOE1

TOE0

When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET

occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled,

timer/counter 0 can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock

selector circuit.

TC0 OUTPUT LATCH (TOL0)

TOL0 is the output latch for timer/counter 0. When the 8-bit comparator detects a correspondence between the

value of the counter register TCNT0 and the reference value stored in the TREF0 register, the TOL0 value is

inverted — the latch toggles high-to-low or low-to-high. Whenever the state of TOL0 is switched, the TC0 signal

is output. TC0 output may be directed to the TCLO0 pin at I/O port 8.1, or it can be output directly to the serial

I/O clock selector circuit as the SCK signal.

Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero,

along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately.

When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if

necessary.

11-18

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

+

PROGRAMMING TIP — Setting a TC0 Timer Interval

To set a 30 ms timer interval for TC0, given fx = 4.19 MHz, follow these steps.

1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter

10

clock = fx/2 , and TREF0 is set to FFH):

2. Calculate the TREF0 value:

TREF0 value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF0 + 1 =

= 122.9 = 7AH

TREF0 value = 7AH – 1 = 79H

3. Load the value 79H to the TREF0 register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

LD

11-19

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

8-BIT TIMER/COUNTER 1 (TC1)

OVERVIEW

Timer/counter 1 (TC1) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of

incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has

elapsed, TC1 generates an interrupt request. By counting signal transitions and comparing the current counter

value with the reference register value, TC1 can be used to measure specific time intervals.

TC1 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF1) into which you write

the counter reference value, and an 8-bit counter register (TCNT1) whose value is automatically incremented by

counter logic.

An 8-bit mode register, TMOD1, is used to activate the timer/counter or PWM function and to select the basic

clock frequency to be used for timer/counter operations. To dynamically modify the basic frequency, new values

can be loaded into the TMOD1 register during program execution.

TC1 FUNCTION SUMMARY

8-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock fre-

quency.

Counts various system "events" based on edge detection of external clock sig-

nals at the TC1 input pin, TCL1.

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC1 output pin, TCLO1.

Divides the frequency of an incoming external clock signal according to a

modifiable reference value (TREF1), and outputs the modified frequency to the

TCLO1 pin.

PWM function

PWM output can be generated.

11-20

S3C7414/P7414/C7424/P7424/C7434/P7434

TC1 COMPONENT SUMMARY

TIMERS and TIMER/COUNTER

Mode register (TMOD1)

Reference register (TREF1)

Counter register (TCNT1)

Clock selector circuit

Activates the timer/counter or PWM function and selects the internal clock

frequency or the external clock source at the TCL1 pin.

Stores the reference value for the desired number of clock pulses between in-

terrupt requests.

Counts internal or external clock pulses based on the bit settings in TMOD0

and TREF1.

Together with the mode register (TMOD1), lets you select one of four internal

clock frequencies or an external clock.

8-bit comparator

Determines when to generate an interrupt by comparing the current value of

the counter register (TCNT1) with the reference value previously programmed

into the reference register (TREF1).

Output latch (TOL1)

Where a TC1 interrupt request or clock pulse is stored pending output to the

TC1 output pin, TCLO1.

When the contents of the TCNT1 and TREF1 registers coincide, the

timer/counter interrupt request flag (IRQT1) is set to "1", the status of TOL1 is

inverted, and an interrupt is generated.

Output enable flag (TOE1)

Must be set to logic one before the contents of the TOL1 latch can be output to

TCLO1.

Interrupt request flag (IRQT1) Cleared when TC1 operation starts and the TC1 interrupt service routine is

executed and set to 1 whenever the counter value and reference value

coincide.

Interrupt enable flag (IET1)

Must be set to logic one before the interrupt requests generated by

timer/counter 1 can be processed.

Table 11-8. TC1 Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

Controls TC1 enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and clock frequency

(bits 6–4)

8-bit

TMOD1

Control

8-bit F90H–F91H

"0"

write-only;

(TMOD0.3 is

also 1-bit

writeable)

Counts clock pulses matching

the TMOD1 frequency setting

8-bit

read-only

TCNT1

TREF1

TOE1

Counter

Reference

Flag

8-bit F94H–F95H

8-bit F96H–F97H

1-bit F92H.2

"0"

FFH

"0"

Stores reference value for the

timer/counter 1 interval setting

8-bit

write-only

Controls timer/counter 1 output

to the TCLO1 pin

1-bit

write-only

11-21

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

8

CLOCKS

(fx/2 , fx/2 , fx/2 , fx)

10

6

4

TREF0

P3.2/TCL0

TMOD1.3

MATCH SIGNAL

TCNT1 OV

“0”

8

8-BIT

COMPARATOR

BUFFER

REG

TMOD1.6

TMOD1.5

TCNT0

CLOCK

SELECTOR

CLEAR

8

MARCH

TMOD1.4

TMOD1.3

TMOD1.2

“0”

TMOD1.0

CLEAR

SET

CLEAR

TOL1

“1” WHEN TCNT1<BUF

“0” WHEN TCNT1>=BUF

IRQT1

P3.3/PWM/TCLO1

PM3.3

P3.3 LATCH

TOE1

Figure 11-4. TC1 Circuit Diagram

TC1 ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 1

— Set TMOD1.2 to logic one

— Set the TC1 interrupt enable flag IET1 to logic one

— Set TMOD1.3 to logic one

TCNT1, IRQT1, and TOL1 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 1

— Set TMOD1.2 to logic zero

Clock signal input to the counter register TCNT1 is halted. The current TCNT1 value is retained and can be read

if necessary.

11-22

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

TC1 PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 1 can be programmed to generate interrupt requests at various intervals based on the selected

system clock frequency. Its 8-bit TC1 mode register TMOD1 is used to activate the timer/counter and to select

the clock frequency. The reference register TREF1 stores the value for the number of clock pulses to be

generated between interrupt requests. The counter register, TCNT1, counts the incoming clock pulses, which are

compared to the TREF1 value as TCNT1 is incremented. When there is a match (TREF1 = TCNT1), an interrupt

request is generated.

To program timer/counter 1 to generate interrupt requests at specific intervals, choose one of four internal clock

frequencies (divisions of the system clock, fx) and load a counter reference value into the TREF1 register.

TCNT1 is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMOD1.4–TMOD1.6 settings. To generate an interrupt request, the TC1 interrupt request flag

(IRQT1) is set to logic one, the status of TOL1 is inverted, and the interrupt is output. The content of TCNT1 is

then cleared to 00H and TC1 continues counting. The interrupt request mechanism for TC1 includes an interrupt

enable flag (IET1) and an interrupt request flag (IRQT1).

TC1 OPERATION SEQUENCE

The general sequence of operations for using TC1 can be summarized as follows:

1. Set TMOD1.2 to "1" to enable TC1

2. Set TMOD1.6 to "1" to enable the system clock (fx) input

n

3. Set TMOD1.5 and TMOD1.4 bits to desired internal frequency (fx/2 )

4. Load a value to TREF1 to specify the interval between interrupt requests

5. Set the TC1 interrupt enable flag (IET1) to "1"

6. Set TMOD1.3 bit to "1" to clear TCNT1, IRQT1, and TOL1, and start counting

7. TCNT1 increments with each internal clock pulse

8. When the comparator shows TCNT1 = TREF1, the IRQT1 flag is set to "1"

9. Output latch (TOL1) logic toggles high or low

10. Interrupt request is generated

11. TCNT1 is cleared to 00H and counting resumes

12. Programmable timer/counter operation continues until TMOD1.2 is cleared to "0".

11-23

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

TC1 EVENT COUNTER FUNCTION

Timer/counter 1 can monitor or detect system 'events' by using the external clock input at the TCL1 pin as the

counter source. The TC1 mode register selects rising or falling edge detection for incoming clock signals. The

counter register TCNT1 is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMOD1.4–TMOD1.6 settings, the operation sequence for TC1's event counter

function is identical to its programmable timer/counter function. To activate the TC1 event counter function,

— Set TMOD1.2 to "1" to enable TC1;

— Clear TMOD1.6 to "0" to select the external clock source at the TCL1 pin;

— Select TCL1 edge detection for rising or falling signal edges by loading the appropriate values to TMOD1.5

and TMOD1.4.

— P3.2 must be set to input mode.

Table 11-9. TMOD1 Settings for TCL1 Edge Detection

TMOD1.5

TMOD1.4

TCL1 Edge Detection

Rising edges

0

1

Falling edges

11-24

S3C7414/P7414/C7424/P7424/C7434/P7434

TC1 CLOCK FREQUENCY OUTPUT

TIMERS and TIMER/COUNTER

Using timer/counter 1, a modifiable clock frequency can be output to the TC1 clock output pin, TCLO1. To select

the clock frequency, load the appropriate values to the TC1 mode register, TMOD1. The clock interval is

selected by loading the desired reference value into the reference register TREF1. To enable the output to the

TCLO1 pin at I/O port 3.3, the following conditions must be met:

1. Load a reference value to TREF1.

2. Set the internal clock frequency in TMOD1.

3. Initiate TC1 clock output to TCLO1 (TMOD1.2 = "1").

4. Set P3.3 mode flag (PM3.3) to "1".

5. Set P3.3 output latch to "0".

6. Set TOE1 flag to "1".

Each time TCNT1 overflows and an interrupt request is generated, the state of the output latch TOL1 is inverted

and the TC1-generated clock signal is output to the TCLO1 pin.

+

PROGRAMMING TIP — TC1 Signal Output to the TCLO1 Pin

Output a 30 ms pulse width signal to the TCLO1 pin:

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#79H

TREF1,EA

EA,#4CH

TMOD1,EA

EA,#80H

PMG2,EA

P3.3

; P3.3 ¬ output mode

; P3.3 clear

TOE1

11-25

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

TC1 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC1 reference register, TREF1, you

can divide the incoming clock signal by the TREF1 value and then output this modified clock frequency to the

TCLO1 pin. The sequence of operations used to divide external clock input can be summarized as follows:

1. Load a signal divider value to the TREF1 register

2. Clear TMOD1.6 to "0" to enable external clock input at the TCL1 pin

3. Set TMOD1.5 and TMOD1.4 to desired TCL1 signal edge detection

4. Set port 3.3 mode flag (PM3.3) to output ("1")

5. Set P3.3 output latch to "0"

6. Set TOE1 flag to "1" to enable output of the divided frequency to the TCLO1 pin

+

PROGRAMMING TIP — External TCL1 Clock Output to the TCLO1 Pin

Output external TCL1 clock pulse to the TCLO1 pin (divide by four):

EXTERNAL (TCL1)

CLOCK PULSE

TLCO1

OUTPUT

PULSE

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#01H

TREF1,EA

EA,#0CH

TMOD1,EA

EA,#80H

PMG2,EA

P3.3

; P3.3 ¬ output mode

; P3.3 clear

TOE1

11-26

S3C7414/P7414/C7424/P7424/C7434/P7434

PWM FUNCTION DESCRIPTION

TIMERS and TIMER/COUNTER

The 8-bit counter counts modulus 256, that is, from 0–255, inclusive. The value of the 8-bit counter is compared

to the contents of the reference registers, TREF1. When the reference register value equals the counter value,

the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio

(duty) of the PWM output is TREF1/256.

All PWM outputs remain inactive during the first 256 input clock signals. Then, when the counter value changes

from FFH back to 00H, the PWM outputs are forced to high level. The pulse width ratio (duty cycle) is defined by

the contents of the reference register and is programmed in increments of 1:256. The 8-bit PWM data register

TREF1 is read and written using 8-bit RAM control instructions only.

PWM output can be held at low level by continuously loading the reference register with 00H. By continuously

loading the reference register with FFH, you can hold the PWM output to high level, except for the last pulse of

the clock source, which sends the output low (see Figure 11-5).

Table 11-10. PWM Reference Register Duty Values

Reference Register Value

(TREF1)

Duty

0000 0000

0000 0001

0/256 (0 %)

1/256 (0.39 %)

0000 0010

2/256 (0.78%)

.

1000 0000

128/256 (50 %)

1000 0001

129/256 (50.4 %)

.

1111 1110

1111 1111

254/256 (99.2 %)

255/256 (99.6 %)

. . . .

0

1

2

3

254 255

0

1

2

3

254 255

CLOCK

TREF1 = 00H

TREF1 = 01H

TREF1 = 80H

TREF1 = FFH

Figure 11-5. PWM Output Waveforms

11-27

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

TC1 MODE REGISTER (TMOD1)

TMOD1 is the 8-bit mode control register for timer/counter 1. It is addressable by 8-bit write instructions. One bit,

TMOD1.3, is also 1-bit writeable. RESET clears all TMOD1 bits to logic zero and disables TC1 operations.

F90H

F91H

TMOD1.3

"0"

TMOD1.2

TMOD1.6

"0"

TMOD 1.0

TMOD1.4

TMOD1.5

TMOD1.2 is the enable/disable bit for timer/counter 1. When TMOD1.3 is set to "1", the contents of TCNT1,

IRQT1, and TOL1 are cleared, counting starts from 00H, and TMOD1.3 is automatically reset to "0" for normal

TC1 operation. When TC1 operation stops (TMOD1.2 = "0"), the contents of the TC1 counter register TCNT1 are

retained until TC1 is re-enabled.

The TMOD1.6, TMOD1.5, and TMOD1.4 bit settings are used together to select the TC1 clock source. This

selection involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCL1 pin, and

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC1 operation.

Table 11-11. TC1 Mode Register (TMOD1) Organization

Bit Name

TMOD1.7

TMOD1.6

TMOD1.5

TMOD1.4

TMOD1.3

Setting

Resulting TC1 Function

Address

0

Always logic zero

F91H

0,1

Specify input clock edge and internal frequency

1

Clear TCNT1, IRQT1, and TOL1 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes.)

F90H

TMOD1.2

0

1

Disable timer/counter 1; retain TCNT1 contents

Enable timer/counter 1

TMOD1.1

TMOD1.0

0

Always logic zero

0, 1

0: Normal timer/counter mode

1: PWM mode

11-28

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

Table 11-12. TMOD1.6, TMOD1.5, and TMOD1.4 Bit Settings

TMOD1.6

TMOD1.5

TMOD1.4

Resulting Counter Source and Clock Frequency

External clock input (TCL1) on rising edges

0

1

0

1

0

1

0

1

0

1

External clock input (TCL1) on falling edges

10

fx/2 (4.09 kHz)

6

fx /2 (65.5 kHz)

4

fx/2 (262 kHz)

fx = 4.19 MHz

NOTE: 'fx' = system clock of 4.19 MHz.

+

PROGRAMMING TIP — Restarting TC1 Counting Operation

1. Set TC1 timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD1,EA

LD

EI

BITS

IET1

2. Clear TCNT1, IRQT1, and TOL1 and restart TC1 counting operation:

BITS

SMB

BITS

EMB

15

TMOD1.3

11-29

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

WATCH TIMER

OVERVIEW

The watch timer is a multi-purpose timer consisting of three basic components:

— 8-bit watch timer mode register (WMOD)

— Clock selector

— Frequency divider circuit

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. It

is also used as a clock source for generating buzzer output.

Real-Time and Watch-Time Measurement

To start watch timer operation, set bit 2 of the watch timer mode register, WMOD.2, to logic one. The watch timer

starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5-

second intervals.

Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be

cleared to logic zero by program software as soon as a requested interrupt service routine has been executed.

Using a System Clock Source

The watch timer can generate interrupts based on the system clock frequency. When WMOD.1 = 1, the watch

timer uses the system clock frequency directly as the watch timer clock source. When WMOD.1 = 0, the system

clock (fx) is used as the watch timer clock source, according to the following formula:

System clock (fx)

Watch timer clock (fw) =

= 32.768 kHz

128

(assuming fx = 4.19 MHz)

Buzzer Output Frequency Generator

If "fx/128" is used for the watch timer clock (fw) by setting WMOD.0 to 0 when the system clock is 4.19 MHz, the

watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the BUZ

frequency you want, load the appropriate value to the WMOD register. This output can then be used to actuate

an external buzzer sound. To generate a BUZ signal, three conditions must be met:

— The WMOD.7 register bit at F89H.3 is set to "1"

— The output latch for I/O port 0.3 is cleared to "0"

— The port 0.3 output mode flag (PM0.3) set to 'output' mode

Timing Tests in High-Speed Mode

When the watch timer clock frequency of 32.768 kHz is used as its source, by setting WMOD.1 (F88H.1) to "1",

the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. At its normal speed

(WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. High-speed mode is useful

for timing events for program debugging sequences.

11-30

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

P0.3 LATCH

PM0.3

WMOD.7

0

P0.3/BUZ

WMOD.5

MUX

8

WMOD.4

0

fw/16

fw/8

fw/4

fw/2

ENABLE / DISABLE

WMOD.2

WMOD.1

0

SELECTOR

CIRCUIT

IRQW

7

14

fw/2

FREQUENCY

DIVIDING

fw

(32.768 kHz)

CIRCUIT

fx = System clock

fw = Watch timer frequency = fx/128

Figure 11-6. Watch Timer Circuit Diagram

11-31

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

WATCH TIMER MODE REGISTER (WMOD)

The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only

addressable.

RESET sets all WMOD bits to logic zero.

F88H

F89H

"0"

WMOD.2

"0"

WMOD.1

WMOD.5

"0"

WMOD.7

WMOD.4

In brief, WMOD settings control the following watch timer functions:

— Watch timer speed control

— Enable/disable watch timer

— Buzzer frequency selection

(WMOD.1)

(WMOD.2)

(WMOD.4)

(WMOD.5)

(WMOD.7)

— Enable/disable buzzer output

Table 11-13. Watch Timer Mode Register (WMOD) Organization

Bit Name

Values

Function

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

Address

WMOD.7

0

1

F89H

WMOD.6

"0"

Always logic zero

WMOD.5 – .4

0

1

0

1

0

1

fw/16 buzzer (BUZ) signal output (2 kHz)

fw/8 buzzer (BUZ) signal output (4 kHz)

fw/4 buzzer (BUZ) signal output (8 kHz)

fw/2 buzzer (BUZ) signal output (16 kHz)

Always logic zero

WMOD.3

WMOD.2

"0"

0

F88H

Disable watch timer; clear frequency dividing circuits

Enable watch timer

1

WMOD.1

WMOD.0

0

Normal-speed mode; sets IRQW to 0.5 seconds at 4.19 MHz

High-speed mode; sets IRQW to 3.91 ms at 4.19 MHz

Must be set to zero

1

"0"

NOTE: A system clock frequency (fx) of 4.19 MHz and a watch timer clock (fw) of 32.768 kHz are assumed.

11-32

S3C7414/P7414/C7424/P7424/C7434/P7434

TIMERS and TIMER/COUNTER

+

PROGRAMMING TIP — Using the Watch Timer

1. Select a 0.5 second interrupt, and 2 kHz buzzer enable:

BITS

SMB

BITR

LD

EMB

15

P0.3

EA,#8H

PMG1,EA

EA,#84H

WMOD,EA

IEW

; Clear P0.3 output latch

; P0.3 ¬ Output mode

LD

BITS

2. Sample real-time clock processing method:

CLOCK

BTSTZ

RET

IRQW

; 0.5 second check

; No, return

•

; Yes, 0.5 second interrupt generation

; Increment HOUR, MINUTE, SECOND

11-33

TIMERS and TIMER/COUNTER

S3C7414/P7414/C7424/P7424/C7434/P7434

NOTES

11-34

S3C7414/P7414/C7424/P7424/C7434/P7434

A/D CONVERTER

12 A/D CONVERTER

OVERVIEW

The 8-bit analog-to-digital converter (ADC) has the following components:

— Digital-to-analog converter

— Comparator

— ADC data register (ADATA)

— ADC mode register (ADMOD)

— ADC control register (AFLAG)

— Successive approximation logic

To operate the A/D converter, one of the six analog input channels is selected by writing the appropriate value to

the A/D mode register. To start the converter, the ADSTR flag in the control register AFLAG must be set to "1".

Conversion speed is determined by the oscillator frequency and the CPU clock.

When the A/D operation is complete, the EOC flag must be tested in order to verify that the conversion was

successful. When the EOC value is "0", an interrupt request (INTAD) is issued. Then, when the interrupt request

has been enabled, the converted digital values stored in the data register ADATA can be read.

AD0/P2.0

AD1/P2.1

AD2/P2.2

A/D

CONVERTER

8

AD3/P2.3

AD4/P3.0

AD5/P3.1

Figure 12-1. A/D Converter Function Diagram

12-1

A/D CONVERTER

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 12-1. A/D Converter Component Overview

ADC Function

Mnemonic

Description

Digital-to-analog

converter

DAC

Uses successive approximation logic to convert digital input into

the reference analog voltage, V_DA. These V_DAvalues are input

to the comparator and then compared to the multiplexed external

analog source voltage, VA_IN.

Compares the applied external analog input voltage, VA_IN, to the

analog reference voltage (V_DA) that is generated by the DAC and

writes the corresponding digital value to the ADATA register.

Comparator

CMP

Digital data register

ADC mode register

ADC control register

ADATA

ADMOD

AFLAG

–

Stores digital values as analog-to-digital conversion is

completed.

Used to select one of six analog channels as the input source for

the analog data to be converted.

Contains the control flags used to start A/D converter operation

and to monitor operational status.

Successive approxima-

tion logic

Control blocks in the A/D converter contain the successive

approximation logic required to generate the analog reference

voltage.

DATA BUS

ADMOD

AFLAG

“0”

.3

.2

.1

.0

ADSTR EOC

“0”

ADATA

8

AD5

AD4

AD3

AD2

AD1

AD0

VA

IN

+

SUCCESSIVE

APPROXIMATION

LOGIC

MULTIPLEXER

CMP

-

V

DA

INTAD

DAC

AV

REF

RESISTOR STRING

DIGITAL-TO-ANALOG CONVERTER

8

SS

12-2

S3C7414/P7414/C7424/P7424/C7434/P7434

A/D CONVERTER

Figure 12-2. A/D Converter Circuit Diagram

tinit

tconv = 12x8/fx

ONE MACHINE CYCLE

ADSTR

EOC

INTAD

ADATA

VALID

DATA

VALUE REMAINS UNDETERMINED

Figure 12-3. A/D Converter Timing Diagram

ADC PROCEDURE DESCRIPTION

Use these steps as a general guideline for writing A/D converter programs:

1. Select one of the six analog channels, AD0–AD5, as the analog input source. To do this, write the appro-

priate value to the ADMOD register, bits ADMOD.3–ADMOD.0.

2. Start the A/D converter by setting the ADSTR flag of the AFLAG register to logic one.

3. When the converter starts, the EOC (End Of Conversion) flag in the AFLAG register is automatically set to

logic one, and the ADSTR flag is cleared to logic zero.

4. The analog-to-digital conversion speed is determined by the oscillator frequency and the CPU clock, as

follows:

1

fx

tconv =

´

96

For example, with a 4.19 MHz oscillator clock, the t

conv

the instruction type and the speed of the CPU clock.

value is 22.89 µs. The 'tinit' value is determined by

5. When conversion has been completed, the EOC flag is cleared automatically so that a check can be made to

verify that the conversion was successful.

6. Then, the interrupt request signal IRQAD is sent to the interrupt block to request interrupt service. (Before the

interrupt request can be generated, the interrupt enable flag IEAD must be set to logic one.)

7. Converted digital values that have been stored in the 8-bit ADATA register can now be read. Conversion

values are retained until the next A/D conversion operation starts.

12-3

A/D CONVERTER

S3C7414/P7414/C7424/P7424/C7434/P7434

ADC DIGITAL-TO-ANALOG CONVERTER (DAC)

The 8-bit digital-to-analog converter (DAC) generates analog voltage reference values for the comparator. The

DAC is a 256-step resistor string type digital-to-analog converter that uses successive approximation logic to

convert digital input into the reference analog voltage, V

.

DA

V

DA

values are input from the DAC to the comparator where they are compared to the multiplexed external

analog source voltage, VA . Since the DAC has 8-bit resolution, it generates the 256-step analog reference

in

voltage as follows:

n

256

1

512

±

V

DA

= V

´

REF

(

)

(1/2 LSB compensation)

(n = 0 – 256, as determined by successive approximation logic)

ADC DATA REGISTER (ADATA)

The A/D converter data register, ADATA, is an 8-bit register in which digital data values are stored as an A/D

conversion operation is completed. Digital values stored in ADATA are retained until another conversion

operation is initiated. ADATA is addressable by 8-bit read instructions only.

ADC MODE REGISTER (ADMOD)

The analog-to-digital converter mode register ADMOD is a 4-bit register that is used to select one of six analog

channels as the analog data input source. ADMOD is addressable by 1-bit or 4-bit read or write instructions.

FDAH

ADMOD.3 ADMOD.2 ADMOD.1 ADMOD.0

Input channels AD0–AD5 (corresponding to I/O port pins P2.0–P2.3, P3.0–P3.1) may be used either for analog

input to the A/D converter, or as output ports. Since only one of the six ports can be selected at one time as

external source of analog data, the five remaining I/O ports are always available for other function.

RESET clears the ADMOD register to logic zero. Table 12-2 shows ADMOD.3–ADMOD.0 bit settings for

selecting a channel for analog input:

Table 12-2. A/D Converter Mode Register Settings

ADMOD.3

ADMOD.2

ADMOD.1

ADMOD.0

Effect of ADMOD Bit Setting

Select input channel AD0 (pin P2.0)

Select input channel AD1 (pin P2.1)

Select input channel AD2 (pin P2.2)

Select input channel AD3 (pin P2.3)

Select input channel AD4 (pin P3.0)

Select input channel AD5 (pin P3.1)

–

0

1

0

1

0

1

0

1

0

1

12-4

S3C7414/P7414/C7424/P7424/C7434/P7434

ADC CONTROL REGISTER (AFLAG)

A/D CONVERTER

The A/D converter control register, AFLAG, is a 4-bit register that contains the control flags used to start the A/D

converter and to monitor its operational status.

FDBH

ADSTR

EOC

"0"

A conversion is started by setting ADSTR in the AFLAG register. ADSTR is write-only and is 1-bit and 4-bit

addressable. The EOC bit (End Of Conversion) is a flag that can be read to determine the current status of an

A/D conversion operation. When a conversion is completed, this bit is cleared so that an A/D conversion result is

ready to be read. EOC may be set by ADSTR setting. While this flag is set, the ADC cannot start a new

conversion. EOC is 1-bit or 4-bit read-only addressable.

+

PROGRAMMING TIP — Configuring A/D Converter Input Pins

In this A/D converter program sample, the AD0, AD1 and AD2 pins are used as A/D input pins and the P2.3 /

AD3 is used as output pin:

BITR

DI

EMB

IEAD

; Disable INTAD interrupt

; Disable all interrupts during A/D conversion

LD

A,#0H

LD

ADMOD,A

ADSTR

EOC

; AD0 pin select for A/D conversion

; A/D conversion start

; A/D conversion end check

; A/D conversion not completed

; A/D conversion end

BITS

BTSF

JR

LD

AD0CK

AD1CK

AD2CK

AD0CK

EA,ADATA

AD0BUF,EA

A,#1H

; AD0BUF ¬ AD0 conversion data

LD

ADMOD,A

ADSTR

EOC

; AD1 pin select for A/D conversion

; A/D conversion start

; A/D conversion end check

; A/D conversion not completed

; AD conversion end

BITS

BTSF

JR

LD

BITS

BTSF

JR

AD1CK

EA,ADATA

AD1BUF,EA

A,#02H

ADMOD,A

ADSTR

EOC

AD2CK

EA,ADATA

AD2BUF,EA

; AD1BUF ¬ AD1 conversion data

; AD2 pin select for A/D conversion

; AD conversion start

; AD conversion end check

; AD conversion not completed

; AD conversion end

LD

EI

; AD2BUF ¬ AD2 conversion data

; Interrupt enable

BITS

JPS

EMB

P2.3

AAA

; P2.3/AD3 pin output high

12-5

A/D CONVERTER

S3C7414/P7414/C7424/P7424/C7434/P7434

NOTES

12-6

S3C7414/P7414/C7424/P7424/C7434/P7434

SERIAL I/O INTERFACE

13 SERIAL I/O INTERFACE

OVERVIEW

The serial I/O interface (SIO) has the following functional components:

— 8-bit mode register (SMOD)

— Clock selector circuit

— 8-bit buffer register (SBUF)

— 3-bit serial clock counter

Using the serial I/O interface, 8-bit data can be exchanged with an external device. The transmission frequency

is controlled by making the appropriate bit settings to the SMOD register.

The serial interface can run off an internal or an external clock source, or the TOL0 signal that is generated by

the 8-bit timer/counter, TC0. If the TOL0 clock signal is used, you can modify its frequency to adjust the serial

data transmission rate.

SERIAL I/O OPERATION SEQUENCE

The general operation sequence of the serial I/O interface can be summarized as follows:

1. Set SIO mode to transmit-and-receive or to receive-only.

2. Select MSB-first or LSB-first transmission mode.

3. Set the SCK clock signal in the mode register, SMOD.

4. Set SIO interrupt enable flag (IES) to "1".

5. Initiate SIO transmission by setting bit 3 of the SMOD to "1".

6. When the SIO operation is complete, IRQS flag is set and an interrupt is generated.

13-1

SERIAL I/O INTERFACE

S3C7414/P7414/C7424/P7424/C7434/P7434

INTERNAL BUS

8

LSB / MSB

SO

SI

SBUF (8-BIT)

R

OVERFLOW

IRQS

Q

D

CK

P0.0/

SCK

TOL0

Q0

Q1 Q2

3-BIT COUNTER

CPU CLK

CLOCK

SELECTOR

R

S

10

fx/2

Q

CLEAR

fx/2⁴

SMOD.7 SMOD.6 SMOD.5

SMOD.3 SMOD.2 SMOD.1 SMOD.0

-

8

(note)

BITS

INTERNAL BUS

Instruction Execution

NOTE:

Figure 13-1. Serial I/O Interface Circuit Diagram

13-2

S3C7414/P7414/C7424/P7424/C7434/P7434

SERIAL I/O MODE REGISTER (SMOD)

SERIAL I/O INTERFACE

The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface.

Its reset value is logic zero. SMOD is organized in two 4-bit registers, as follows:

FE0H

FE1H

SMOD.3

SMOD.7

SMOD.2

SMOD.6

SMOD.1

SMOD.5

SMOD.0

0

SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in

transmit-and-receive mode or receive-only mode.

SMOD is a write-only register and can be addressed only by 8-bit RAM control instructions. One exception to this

is SMOD.3, which can be written by a 1-bit RAM control instruction. When SMOD.3 is set to 1, the contents of

the serial interface interrupt request flag, IRQS, and the 3-bit serial clock counter are cleared, and SIO

operations are initiated. When the SIO transmission starts, SMOD.3 is cleared to logic zero.

Table 13-1. SIO Mode Register (SMOD) Organization

SMOD.0

SMOD.1

SMOD.2

0

1

0

1

0

Most significant bit (MSB) is transmitted first

Least significant bit (LSB) is transmitted first

Receive-only mode; output buffer is off

Transmit-and-receive mode

Disable the data shifter and clock counter; retain contents of IRQS flag

when serial transmission is halted

1

0

Enable the data shifter and clock counter; set IRQS flag to "1" when serial

transmission is halted

SMOD.3

SMOD.4

Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then

reset this bit to logic zero

Bit not used; value is always "0"

SMOD.7

SMOD.6

SMOD.5

Clock Selection

R/W Status of SBUF

0

SBUF is enabled when SIO

operation is halted or when

External clock at SCK pin

SCK goes high.

0

1

0

1

0

1

x

0

Use TOL0 clock from TC0

CPU clock: fx/4, fx/8, fx/64

Enable SBUF read/write

10

SBUF is enabled when SIO

operation is halted or when

4.09 kHz clock: fx/2

SCK goes high.

4

1

262 kHz clock: fx/2

NOTES:

1. 'fx' = system clock; 'x' means 'don't care.'

2. kHz frequency ratings assume a system clock (fx) running at 4.19 MHz.

3. The SIO clock selector circuit cannot select a fx/2⁴clock if the CPU clock is fx/64.

13-3

SERIAL I/O INTERFACE

S3C7414/P7414/C7424/P7424/C7434/P7434

SERIAL I/O TIMING DIAGRAMS

SCK

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SI

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

SO

IRQS

TRANSMIT

COMPLETE

SET SMOD.3

Figure 13-2. SIO Timing in Transmit/Receive Mode

SCK

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SI

HIGH IMPEDANCE

SO

IRQS

TRANSMIT

COMPLETE

SET SMOD.3

Figure 13-3. SIO Timing in Receive-Only Mode

13-4

S3C7414/P7414/C7424/P7424/C7434/P7434

SERIAL I/O BUFFER REGISTER (SBUF)

SERIAL I/O INTERFACE

When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer

register are output to the SO pin (P0.1) at the rate of one bit for each falling edge of the SIO clock. Receive data

is simultaneously input from the SI pin (P0.2) to SBUF at the rate of one bit for each rising edge of the SIO clock.

When receive-only mode is used, incoming data is input to the SIO buffer at the rate of one bit for each rising

edge of the SIO clock. SBUF can be read or written using 8-bit RAM control instructions. Following a RESET, the

value of SBUF is undetermined.

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O

1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fx/24 and in

MSB-first mode:

BITS

SMB

LD

EMB

15

EA,#03H

LD

PMG1,EA

EA,#48H

SBUF,EA

EA,#0EEH

SMOD,EA

; P0.0 / SCK and P0.1 / SO ¬ Output

;

; SIO data transfer

SCK/P0.0

External

Device

SO/P0.1

[S3C7414/C7424/C7434]

2. Use CPU clock to transfer and receive serial data at high speed:

BITS

SMB

LD

EMB

15

EA,#03H

LD

PMG1,EA

EA,TDATA

SBUF,EA

EA,#4FH

SMOD,EA

IES

; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2 / SI ¬ Input

LD

; SIO start

BITR

BTSTZ

JR

STEST

IRQS

STEST

LD

SMB

LD

EA,SBUF

0

RDATA,EA

13-5

SERIAL I/O INTERFACE

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode:

BITS

SMB

LD

EMB

15

EA,#03H

LD

PMG1,EA

EA,TDATA

SBUF,EA

EA,#8FH

; P0.0/SCK and P0.1/SO ¬ Output, P0.2/SI ¬ Input

LD

SMOD,EA

; SIO start

EI

BITS

•

IES

•

INTS

PUSH

LD

SMB

XCH

SMB

LD

BITS

POP

IRET

SB

EA

EA,TDATA

15

EA,SBUF

0

RDATA,EA

SMOD.3

EA

; Store SMB, SRB

; Store EA

; EA ¬ Transmit data

; EA ¬ Receive data

; RDATA ¬ Receive data

; SIO start

SB

SCK/P0.0

SO/P0.1

SI/P0.2

External

Device

[S3C7414/C7424/C7434]

13-6

S3C7414/P7414/C7424/P7424/C7434/P7434

SERIAL I/O INTERFACE

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

4. Transmit and receive an external clock in LSB-first mode:

BITS

SMB

LD

EMB

15

EA,#02H

LD

PMG1,EA

EA,TDATA

SBUF,EA

EA,#0FH

; P0.1/SO ¬ Output, P0.0/SCK and P0.2 / SI ¬ Input

LD

SMOD,EA

; SIO start

EI

BITS

•

IES

•

INTS

PUSH

LD

SMB

XCH

SMB

LD

BITS

POP

IRET

SB

EA

EA,TDATA

15

EA,SBUF

0

RDATA,EA

SMOD.3

EA

; Store SMB, SRB

; Store EA

; EA ¬ Transmit data

; EA ¬ Receive data

; RDATA ¬ Receive data

; SIO start

SB

SCK/P0.0

SO/P0.1

SI/P0.2

External

Device

[S3C7414/C7424/C7434]

High Speed SIO Transmission

13-7

SERIAL I/O INTERFACE

S3C7414/P7414/C7424/P7424/C7434/P7434

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Concluded)

Use CPU clock to transfer and receive serial data at high speed:

BITS

SMB

LD

EMB

15

EA,#03H

LD

PMG1,EA

EA,TDATA

SBUF,EA

EA,#4FH

SMOD,EA

IES

; P0.0 / SCK and P0.1/SO ¬ Output, P0.2/SI ¬ Input

LD

; SIO start

BITR

BTSTZ

JR

STEST

IRQS

STEST

LD

SMB

LD

EA,SBUF

0

RDATA,EA

13-8

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7414/C7424/C7434 electrical characteristics is presented as tables and

graphics. The information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings

— D.C. electrical characteristics

— System clock oscillator characteristics

— Operating voltage range

— A.C. electrical characteristics

— A/D converter electrical characteristics

— I/O capacitance

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode

— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

Miscellaneous Timing Waveforms

— A.C timing measurement points (except for X_IN)

— Clock timing measurement at X_IN

— TCL0/1 timing

— Input timing for RESET signal

— Input timing for external interrupts and quasi-interrupts

— S3C7434 power-on RESET timing

— Serial data transfer timing

14-1

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-1. S3C7414/C7424 Absolute Maximum Ratings

°

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

Units

V

V_DD

Supply Voltage

Input Voltage

–

– 0.3 to + 6.5

V_I

– 0.3 to V_DD+ 0.3

All I/O ports

One pin

V

V_O

I_OH

Output Voltage

Output Current High

–

V

– 15

mA

All output pins

One pin

– 35

+ 30

peak value ^(note)

rms value

peak value ^(note)

rms value

–

I_OL

Output Current Low

mA

+ 15

+ 100

All pins

+ 60

T_A

°

C

Operating Temperature

Storage Temperature

– 40 to + 85

T_stg

°

C

–

– 65 to + 150

NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .

OL

14-2

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Input High

Symbol

Conditions

Min

Typ

Max

Units

V_IH1

0.7 V_DD

V_DD

All input pins except those specified

–

V

below for V –V

Voltage

IH2 IH3

V_IH2

V_IH3

V_IL1

0.8 V_DD

V_DD– 0.1

–

V_DD

Ports 0, 1, 3, 6 and RESET

X_IN,X_OUT

0.3 V_DD

Input Low

Voltage

All input pins except those specified

–

V

below for V –V

IL2 IL3

V_IL2

V_IL3

V_OH

0.2 V_DD

Ports 0, 1, 3, 6 and RESET

X_IN,X_OUT

0.1

–

V

DD

= 4.5 V to 5.5 V

V_DD– 1.0

Output High

Voltage

–

V

I_OH= – 1 mA

Ports 0, 2–8

V_OL

V

DD

= 4.5 V to 5.5 V

Output Low

Voltage

–

0.4

2

3

I_OL= 15 mA

Ports 4 and 5 only

I_OL= 4 mA

0.2

–

All output ports except ports 4 and 5

V_I= V_DD

I_LIH1

Input High

Leakage Current

–

µA

All input pins except those specified

below for I

LIH2

I_LIH2

I_LIL1

V_I= V_DD

X_INand X_OUTonly

20

V_I= 0 V

Input Low

–

– 3

Leakage Current

All input pins except X_INand X_OUT

,

RESET

I_LIL2

V_I= 0 V

– 20

X_INand X_OUTonly

I_LOH

I_LOL

R_L1

V_O= V_DD

Output High

Leakage Current

–

3

µA

kW

All output pins

V_O= 0 V

Output Low

Leakage Current

– 3

All output pins

Pull-up Resistor

25

50

100

200

400

800

V_I= 0 V; V_DD= 5 V except RESET

V_I= 0 V; V_DD= 3 V except RESET

V_I= 0 V; V_DD= 5 V; RESET

100

250

500

R_L2

Pull-up Resistor

100

200

kW

V_I= 0 V; V_DD= 3 V; RESET

14-3

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter Symbol

Conditions

= 5.0 V ± 10%

Min

Typ

3.0

2.3

1.4

1.1

1.0

0.5

0.4

0.1

Max

8.0

5.5

4.0

3.0

2.5

1.8

1.5

1.0

5.0

3.0

Units

mA

I

Supply

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

–

Run mode; V

DD

DD1

Current ⁽¹⁾

Crystal oscillator; C1=C2=22pF

= 3 V ± 10%

V

DD

mA

–

Idle mode; V

= 5.0 V ± 10%

DD2

DD

Crystal oscillator; C1=C2=22pF

= 3 V ± 10%

V

DD

Stop mode; V

= 5.0 V ± 10%

= 3.0 V ± 10%

mA

DD3

DD

NOTES:

1. D.C. electrical values for Supply current (I

to I

) do not include current drawn through internal pull-up registers,

DD3

DD1

output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

14-4

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

Table 14-3. S3C7414/C7424 System Clock Oscillator Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Oscillator

Clock

Parameter

Test Condition

Min Typ Max Units

Configuration

Oscillation frequency ⁽¹⁾

V

DD

= 2.7 V to 5.5 V

Ceramic

Oscillator

0.4

–

6.0

MHz

Xin

Xout

C1

C2

V

DD

V

DD

V

DD

V

DD

= 2.0 V to 5.5 V

= 1.8 V to 5.5 V

= 3.0 V

0.4

–

4.2

3.0

4

Stabilization time ⁽²⁾

ms

Oscillation frequency ⁽¹⁾

= 2.7 V to 5.5 V

Crystal

Oscillator

0.4

6.0

MHz

Xin

Xout

C1

C2

V

DD

V

DD

V

DD

V

DD

= 2.0 V to 5.5 V

= 1.8 V to 5.5 V

= 3.0 V

0.4

–

4.2

3.0

10

Stabilization time ⁽²⁾

ms

X_INinput frequency ⁽¹⁾

= 2.7 V to 5.5 V

External

Clock

0.4

6.0

MHz

Xin

Xout

V

= 2.0 V to 5.5 V

= 1.8 V to 5.5 V

–

0.4

–

4.2

3.0

DD

X_INinput high and low

83.3

1250

ns

level width (t , t

)

XH XL

V_DD= 5 V

RC

Oscillator

Oscillation frequency

limitation

–

4

–

MHz

Xin

Xout

R = 8.2 KW

R

NOTES:

1. Oscillation frequency and X_ininput frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is

terminated.

14-5

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

Main Oscillator Frequency

(Divided by 4)

CPU CLOCK

1.5 MHz

6 MHz

1.05 MHz

0.75 MHz

4.2 MHz

3 MHz

15.6 kHz

1

2

3

4

5

6

1.8

2.7

5.5

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 14-1. S3C7414/C7424 Standard Operating Voltage Range

Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics

°

(T = – 40 C to + 85 C, V

= 1.8 V to 5.5 V)

DD

A

Parameter

Instruction Cycle

Time

Symbol

Conditions

= 2.7 V to 5.5 V

= 1.8 V to 5.5 V

= 2.7 V to 5.5 V

= 1.8 V to 5.5 V

= 2.7 V to 5.5 V

= 1.8 V to 5.5 V

= 2.7 V to 5.5 V

Min

0.67

1.33

0

Typ

Max

Units

t

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

–

64

ms

CY

f

TCL0/1 Input

Frequency

–

1.5

0.75

–

MHz

ms

TI

t

, t

TCL0/1 Input High,

Low Width

0.48

1.8

TIH TIL

t

800

–

ns

KCY

SCK Cycle Time

External SCK source

Internal SCK source

670

V

DD

= 1.8 V to 5.5 V

3200

External SCK source

Internal SCK source

3800

14-6

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics (Continued)

°

(T = – 40 C to + 85 C, V

= 1.8 V to 5.5 V)

A

DD

Parameter

Symbol

Conditions

Min

Typ

Max

–

Units

t

, t

KH KL

V

DD

= 2.7 V to 5.5 V

335

–

ns

SCK High, Low

Width

External SCK source

Internal SCK source

t

/2 – 50

KCY

V

DD

= 1.8 V to 5.5 V

1600

External SCK source

Internal SCK source

t

_KCY/2 – 150

100

t

V

DD

= 2.7 V to 5.5 V

SI Setup Time to

–

ns

SIK

SCK High

External SCK source

Internal SCK source

150

V

DD

= 1.8 V to 5.5 V

External SCK source

Internal SCK source

500

400

t

V

DD

= 2.7 V to 5.5 V

SI Hold Time to

–

KSI

SCK High

External SCK source

Internal SCK source

400

600

V

DD

= 1.8 V to 5.5 V

External SCK source

Internal SCK source

500

–

(1)

V

DD

= 2.7 V to 5.5 V

Output Delay for

300

t

KSO

SCK to SO

External SCK source

Internal SCK source

250

V

DD

= 1.8 V to 5.5 V

1000

External SCK source

1000

–

Internal SCK source

(2)

t

,

Interrupt Input

High, Low Width

INT0

–

ms

INTH

INTL

INT1, INT2, INT4, KS0–KS3

Input

10

t

–

RSL

RESET Input

Low Width

NOTES:

1. R(1KW) and C (100pF) are the load resistance and load capacitance of the SO output line.

2. Minimum value for INT0 is based on a clock of 2t_CYor 128/fx as assigned by the IMOD0 register setting.

14-7

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-5. S3C7434 Absolute Maximum Ratings

°

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

Units

V

V_DD

Supply Voltage

Input Voltage

–

– 0.3 to + 6.5

V_I

– 0.3 to V_DD+ 0.3

All I/O ports

One pin

V

V_O

I_OH

Output Voltage

Output Current High

–

V

– 15

mA

All output pins

One pin

– 35

+ 30

peak value ^(note)

rms value

peak value ^(note)

rms value

–

I_OL

Output Current Low

mA

+ 15

+ 100

All pins

+ 60

T_A

°

C

Operating Temperature

Storage Temperature

– 40 to + 85

T_stg

°

C

–

– 65 to + 150

NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .

OL

14-8

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

Table 14-6. S3C7434 D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 2.5 V to 5.5 V)

°

Parameter

Input High

Symbol

Conditions

Min

Typ

Max

Units

V_IH1

0.7 V_DD

V_DD

All input pins except those specified

–

V

below for V –V

Voltage

IH2 IH3

V_IH2

V_IH3

V_IL1

0.8 V_DD

V_DD– 0.1

–

V_DD

Ports 0, 1, 3, 6 and RESET

X_IN,X_OUT

0.3 V_DD

Input Low

Voltage

All input pins except those specified

–

V

below for V –V

IL2 IL3

V_IL2

V_IL3

V_OH

0.2 V_DD

Ports 0, 1, 3, 6 and RESET

X_IN,X_OUT

0.1

–

V

DD

= 4.5 V to 5.5 V

V_DD– 1.0

Output High

Voltage

–

V

I_OH= – 1 mA

Ports 0, 2–8

V_OL

V

DD

= 3.5 V

Output Low

Voltage

–

0.4

2

3

I_OL= 15 mA

Ports 4 and 5 only

I_OL= 4 mA

0.2

–

All output ports except ports 4 and 5

V_I= V_DD

I_LIH1

Input High

Leakage Current

–

µA

All input pins except those specified

below for I

LIH2

I_LIH2

I_LIL1

V_I= V_DD

X_INand X_OUTonly

20

V_I= 0 V

Input Low

–

– 3

Leakage Current

All input pins except X_INand X_OUT,

RESET

I_LIL2

V_I= 0 V

– 20

X_INand X_OUTonly

I_LOH

I_LOL

R_L1

V_O= V_DD

Output High

Leakage Current

–

3

µA

kW

All output pins

V_O= 0 V

Output Low

Leakage Current

– 3

All output pins

Pull-Up Resistor

25

50

100

200

400

800

V_I= 0 V; V_DD= 5 V except RESET

V_I= 0 V; V_DD= 3 V except RESET

V_I= 0 V; V_DD= 5 V; RESET

100

250

500

R_L2

Pull-Up Resistor

100

200

kW

V_I= 0 V; V_DD= 3 V; RESET

14-9

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-6. S3C7434 D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 2.5 V to 5.5 V)

Parameter Symbol

Conditions

Min

Typ

3.1

2.4

1.5

1.2

1.1

0.6

0.5

120

100

Max

8.0

5.5

4.0

3.0

2.5

1.8

1.5

1.0

200

150

Units

mA

I

Supply

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

–

Run mode; V_DD= 5.0 V ± 10%

DD1

Current ⁽¹⁾

Crystal oscillator; C1 = C2 = 22pF

V

= 3 V ± 10%

DD

mA

–

Idle mode; V_DD= 5.0 V ± 10%

DD2

Crystal oscillator; C1 = C2 = 22pF

V

DD

= 3 V ± 10%

Stop mode; V_DD= 5.0 V ± 10%

Stop mode; V = 3.0 V ± 10%

mA

DD3

DD

NOTES:

1. D.C. electrical values for Supply current (I

to I

) do not include current drawn through internal pull-up registers,

DD3

DD1

output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

Table 14-7. S3C7434 Power-On Reset Circuit Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 2.5 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_DDH

Power-On Reset

Voltage High

2.5

5.5

V

V_DDL

t_r

Power-On Reset

Voltage Low

0

2.0

2.2

V

us

s

Power Supply

Voltage Rise Time

10

0.5

(1)

t_off

Power Supply

Voltage Off Time

I_DDPR

V_DD= 5 V ± 10%

V_DD= 3 V ± 10%

120

100

200

150

uA

Power-On Reset Circuit

Cunsumption Current ⁽²⁾

NOTES:

17

1.

2 /fx (= 31.3 ms at fx = 4.19 MHz)

2. Current consumed when power-on reset circuit is provided internally.

14-10

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

Table 14-8. S3C7434 System Clock Oscillator Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 2.5 V to 5.5 V)

Oscillator

Clock

Parameter

Test Condition

Min Typ Max Units

Configuration

Oscillation frequency ⁽¹⁾

V

DD

= 2.7 V to 5.5 V

Ceramic

Oscillator

0.4

–

6.0

MHz

Xin

Xout

C1

C2

V

DD

V

DD

V

DD

= 2.5 V to 5.5 V

= 3.0 V

0.4

–

4.2

4

Stabilization time ⁽²⁾

ms

Oscillation frequency ⁽¹⁾

= 2.7 V to 5.5 V

Crystal

Oscillator

0.4

6.0

MHz

Xin

Xout

C1

C2

V

DD

V

DD

V

DD

= 2.5 V to 5.5 V

= 3.0 V

0.4

–

4.2

10

Stabilization time ⁽²⁾

ms

X_INinput frequency ⁽¹⁾

= 2.7 V to 5.5 V

External

Clock

0.4

6.0

MHz

Xin

Xout

V

DD

= 2.5 V to 5.5 V

–

0.4

–

4.2

X_INinput high and low

83.3

1250

ns

level width (t , t

)

XH XL

Xin

Xout

V_DD= 5 V

RC

Oscillator

Oscillation frequency

limitation

–

4

–

MHz

R = 8.2 KW

R

NOTES:

1. Oscillation frequency and X_ininput frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is

terminated.

14-11

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

Main Oscillator Frequency

(Divided by 4)

CPU CLOCK

1.5 MHz

6 MHz

1.05 MHz

0.75 MHz

4.2 MHz

3 MHz

15.6 kHz

1

2

3

4

5

6

1.8

2.7

2.5

5.5

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 14-2. S3C7434 Standard Operating Voltage Range

14-12

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

Table 14-9. S3C7434 A.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 2.5 V to 5.5 V)

°

Parameter

Symbol

Conditions

Min

Typ

Max

Units

t_CY

V_DD= 2.7 V to 5.5 V

Instruction Cycle

Time

0.67

–

64

µs

f_TI0

V_DD= 2.7 V to 5.5 V

TCL0/1 Input

Frequency

0

–

1.5

–

MHz

µs

t_TIH0, t_TIL0V_DD= 2.7 V to 5.5 V

TCL0/1 Input

High, Low Width

0.48

800

t_KCY

t_KH, t_KL

t_SIK

V_DD= 2.7 V to 5.5 V

–

ns

SCK Cycle Time

External SCK source

670

325

Internal SCK source

V_DD= 2.7 V to 5.5 V

External SCK source

–

ns

SCK High, Low

Width

t_KCY/2 – 50

100

Internal SCK source

V_DD= 2.7 V to 5.5 V

External SCK source

SI Setup Time to

SCK High

150

400

Internal SCK source

V_DD= 2.7 V to 5.5 V

External SCK source

t_KSI

SI Hold Time to

–

SCK High

400

–

Internal SCK source

V_DD= 2.7 V to 5.5 V

External SCK source

t_KSO

Output Delay for

300

SCK to SO

250

–

Internal SCK source

t_INTH

t_INTL

t_RSL

,

Interrupt Input

INT0

–

µs

(NOTE)

10

High, Low Width

INT1, INT2, INT4, KS0–KS3

Input

10

–

RESET Input

Low Width

NOTE: Minimum value for INT0 is based on a clock of 2t_CYor 128/fx as assigned by the IMOD0 register setting.

14-13

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 14-10. A/D Converter Electrical Characteristics

°

(T_A= – 10 C to + 70 C, V_DD= 3.5 V to 5.5 V, V_SS= AV_SS= 0 V)

Parameter

Resolution

Symbol

Condition

Min

8

Typ

8

Max

8

Units

bit

–

Absolute accuracy ⁽¹⁾

Conversion time ⁽²⁾

2.5 V < AV_REF< V_DD

–

LSB

± 1.5

–

96/fx ⁽³⁾

–

t_CON

–

AV_SS

–

µs

V

V_IAN

R_AN

AV_REF

Analog input voltage

Analog input impedance

1000

–

MW

NOTES:

1. Absolute accuracy does not include the quantization error (± 1/2 LSB).

2. Conversion time is the time required from the moment a conversion operation starts until it ends (EOC = 0).

3. 'fx' is the abbreviation for system clock.

Table 14-11. Input/Output Capacitance

°

(T_A= 25 C, V_DD= 0 V )

Parameter

Input

Capacitance

Symbol

Condition

Min

Typ

Max

Units

C_IN

f = 1 MHz; Unmeasured pins

are returned to V_SS

–

15

pF

C_OUT

C_IO

Output

Capacitance

–

15

pF

I/O Capacitance

Table 14-12. RAM Data Retention Supply Voltage in Stop Mode

°

(T = – 40 C to + 85 C)

A

Parameter

Symbol

Conditions

Min

1.8

–

Typ

–

Max

Unit

V

V_DDDR

Data retention supply voltage

Data retention supply current

Release signal set time

–

5.5

10

–

I_DDDR

t_SREL

t_WAIT

0.1

–

µA

ms

0

Oscillation stabilization time ⁽¹⁾

2¹⁷/fx

When released by

–

RESET

(2)

When released by

interrupt

–

ms

NOTES:

1. During oscillation stabilization time, CPU operation must be stopped to avoid unstable operation upon oscillation start.

2. The basic timer causes a delay of 2¹⁷/fx after a reset.

14-14

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

TIMING WAVEFORMS

INTERNAL RESET

OPERATION

IDLE MODE

STOP MODE

OPERATING

MODE

DATA RETENTION MODE

V

DD

V_DDDR

EXECUTION OF

STOP INSTRUCTION

RESET

t_WAIT

t_SREL

Figure 14-3. Stop Mode Release Timing When Initiated By RESET

IDLE MODE

NORMAL

STOP MODE

OPERATING

MODE

DATA RETENTION

V

DD

V_DDDR

t_SREL

EXECUTION OF

STOP INSTRUCTION

t_WAIT

POWER-DOWN MODE TERMINATING

(INTERRUPT REQUEST)

Figure 14-4. Stop Mode Release Timing When Initiated By Interrupt Request

14-15

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

0.8 V

0.2 V

0.8 V

DD

MEASUREMENT

POINTS

0.2 V

DD

Figure 14-5. A.C. Timing Measurement Points (Except for X_IN)

1 / f

x

t

XH

XL

X

IN

V

– 0.5 V

DD

0.4 V

Figure 14-6. Clock Timing Measurement at X_IN

1 / f

TI0

t

TIH0

TIL0

TCL0

0.8 V

0.2 V

DD

Figure 14-7. TCL0/1 Timing

14-16

S3C7414/P7414/C7424/P7424/C7434/P7434

ELECTRICAL DATA

t

RSL

RESET

0.2 V

DD

Figure 14-8. Input Timing for RESET Signal

t

INTL

INTH

INT0, 1, 2, 4

KS0 to KS3

0.8 V

0.2 V

DD

Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts

14-17

ELECTRICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

t

r

off

V

DD

DDH

DDL

Figure 14-10. S3C7434 Power-On RESET Timing

t

KCY

t

KH

KL

0.8 V

0.2 V

DD

SCK

t

KSI

SIK

0.8 V

0.2 V

DD

SI

INPUT DATA

t

KSO

SO

OUTPUT DATA

Figure 14-11. Serial Data Transfer Timing

14-18

S3C7414/P7414/C7424/P7424/C7434/P7434

MECHANICAL DATA

15 MECHANICAL DATA

This section contains the following information about the device package:

— Package dimensions in millimeters

— Pad diagram

#42

#22

°

0-15

42-SDIP-600

#1

#21

39.50 MAX

39.10 ± 0.2

0.50 ± 0.1

1.00 ± 0.1

(1.77)

1.778

NOTE: Dimensions are in millimeters.

Figure 15-1. 42-SDIP-600 Package Dimensions

15-1

MECHANICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

13.20 ± 0.3

10.00 ± 0.2

0-8°

0.15 -⁺⁰0^..¹0⁰5

44-QFP-1010

0.10 MAX

#44

0.05 MIN

2.05 ± 0.10

2.30 MAX

+0.10

- 0.05

#1

0.35

(1.00)

0.80

NOTE: Dimensions are in millimeters.

Figure 15-2. 44-QFP-1010 Package Dimensions

15-2

S3C7414/P7414/C7424/P7424/C7434/P7434

MECHANICAL DATA

#30

#16

0-15

°

30-SDIP-400

#1

#15

27.88 MAX

27.48 ± 0.2

± 0.1

0.56

1.778

(1.30)

1.12 ± 0.1

NOTE: Dimensions are in millimeters.

Figure 15-3. 30-SDIP-400 Package Dimensions

15-3

MECHANICAL DATA

S3C7414/P7414/C7424/P7424/C7434/P7434

0-8°

#28

#15

28-SOP-375

+0.10

- 0.05

#1

#14

0.15

18.02 MAX

17.62 ± 0.2

0.10 MAX

1.27

± 0.1

0.41

(0.56)

NOTE: Dimensions are in millimeters.

Figure 15-4. 28-SOP-375 Package Dimensions

15-4

S3C7414/P7414/C7424/P7424/C7434/P7434

S3P7414/P7424/P7434 OTP

16 S3P7414/P7424/P7434 OTP

OVERVIEW

The S3P7414/P7424/P7434 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of

the S3C7414/C7424/C7434 microcontroller. It has an on-chip OTP ROM instead of masked ROM. Samsung¢s

own serial protocol used for OTP program pin information regarding OTP program can be referred OTP pin

description.

The S3P7414/P7424/P7434 is fully compatible with the S3C7414/C7424/C7434, in function, in D.C. electrical

characteristics and in pin configuration. Because of its simple programming requirements, the

S3P7414/P7424/P7434 is ideal for use as an evaluation chip for the S3C7414/C7424/C7434.

16-1

S3P7414/P7424/P7434 OTP

S3C7414/P7414/C7424/P7424/C7434/P7434

P8.2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

P2.0/AD0

P2.1/AD1

P2.2/AD2

P2.3/AD3

P3.0/AD4

1

2

3

4

5

6

7

8

P8.1/TCLO0

P8.0/TCL0

P7.3

P7.2

P7.1

P3.1/AD5

P7.0

AVREF

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

P0.1/SO

P0.0/SCK

P5.3

9

S3P7414

SCLK/P4.0

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1

10

11

12

13

14

15

16

17

18

19

20

21

(42-SDIP)

P4.2

RESET/RESET

P4.3

P5.0

P5.1

P5.2

NOTE:

The bolds indicate an OTP pin name.

Figure 16-1. S3P7414 Pin Assignments (42-SDIP)

16-2

S3C7414/P7414/C7424/P7424/C7434/P7434

S3P7414/P7424/P7434 OTP

P7.2

P7.1

P7.0

33

32

31

30

29

28

27

26

25

24

23

AVREF

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

1

2

3

4

5

6

7

8

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

SCLK/P4.0

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1

S3P7414

(44-QFP)

9

10

11

P4.2

NOTE:

The bolds indicate an OTP pin name.

Figure 16-2. S3P7414 Pin Assignments (44-QFP)

16-3

S3P7414/P7424/P7434 OTP

S3C7414/P7414/C7424/P7424/C7434/P7434

VDD/VDD

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VSS/VSS

1

2

3

4

5

6

7

8

P4.0/SCLK

P3.3/PWM/TCLO1/SDAT

P3.2/CLO/TCL1

AVREF

XOUT

XIN

VPP/TEST

P4.1

NC

P4.2

RESET/RESET

NC

S3P7424

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

P4.3

P5.0

P5.1

P5.2

9

(30-SDIP)

10

11

12

13

14

15

P5.3

P0.0/SCK

P0.1/SO

NOTE:

The bolds indicate an OTP pin name.

Figure 16-3. S3P7424 Pin Assignments (30-SDIP)

VDD/VDD

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1

1

2

3

4

5

6

7

8

P4.0/SCLK

P3.3/PWM/TCLO1/SDAT

P3.2/CLO/TCL1

AVREF

P2.3/AD3

P2.2/AD2

P2.1/AD1

P2.0/AD0

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P4.2

RESET/RESET

P4.3

S3P7424

P5.0

P5.1

P5.2

P5.3

9

(28-SOP)

10

11

12

13

14

P0.0/SCK

P0.1/SO

P0.2/SI

NOTE:

The bolds indicate an OTP pin name.

Figure 16-4. S3P7424 Pin Assignments (28-SOP)

16-4

S3C7414/P7414/C7424/P7424/C7434/P7434

S3P7414/P7424/P7434 OTP

P8.2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

P2.0/AD0

P2.1/AD1

P2.2/AD2

P2.3/AD3

P3.0/AD4

P3.1/AD5

AVREF

1

2

3

4

5

6

7

8

P8.1/TCLO0

P8.0/TCL0

P7.3

P7.2

P7.1

P7.0

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

SCLK/P4.0

VDD/VDD

9

S3P7434

10

11

12

13

14

15

16

17

18

19

20

21

VSS/VSS

(42-SDIP)

XOUT

XIN

VPP/TEST

P4.1

P4.2

RESET/RESET

P4.3

P0.1/SO

P0.0/SCK

P5.3

P5.0

P5.1

P5.2

NOTE:

The bolds indicate an OTP pin name.

Figure 16-5. S3P7434 Pin Assignments (42-SDIP)

16-5

S3P7414/P7424/P7434 OTP

S3C7414/P7414/C7424/P7424/C7434/P7434

P7.2

P7.1

P7.0

33

32

31

30

29

28

27

26

25

24

23

AVREF

P3.2/CLO/TCL1

SDAT/P3.3/PWM/TCLO1

1

2

3

4

5

6

7

8

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

SCLK/P4.0

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

P4.1

S3P7434

(44-QFP)

9

10

11

P4.2

NOTE:

The bolds indicate an OTP pin name.

Figure 16-6. S3P7434 Pin Assignments (44-QFP)

16-6

S3C7414/P7414/C7424/P7424/C7434/P7434

S3P7414/P7424/P7434 OTP

Table 16-1. Pin Descriptions of S3P7414/P7434 Used to Read/Write the EPROM

Main Chip

Pin Name

P3.3

During Programming

I/O

Pin Name

Pin No.

Function

SDAT

9 (3)

I/O

Serial data pin. Output port when reading and input

port when writing. Can be assigned as a Input /

push-pull output port.

P4.0

SCLK

10 (4)

15 (9)

I/O

I

Serial clock pin. Input only pin.

V_PP(TEST)

TEST

Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5

V is applied, OTP is in writing mode and when 5 V

is applied, OTP is in reading mode. (Option)

18 (12)

I

Chip initialization

RESET

V_DD/V_SS

Logic power supply pin. V_DDshould be tied to +5 V

during programming.

11/12 (5/6)

NOTE: Parentheses indicate 44-QFP pin number.

Table 16-2. Pin Descriptions of S3P7424 Used to Read/Write the EPROM

During Programming

Main Chip

Pin Name

P3.3

Pin Name

Pin No.

I/O

Function

SDAT

28 (26)

I/O

Serial data pin. Output port when reading and input

port when writing. Can be assigned as a Input /

push-pull output port.

P4.0

SCLK

29 (27)

4 (4)

I/O

I

Serial clock pin. Input only pin.

V_PP(TEST)

TEST

Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5

V is applied, OTP is in writing mode and when 5 V

is applied, OTP is in reading mode. (Option)

7 (7)

I

Chip initialization

RESET

V_DD/V_SS

Logic power supply pin. V_DDshould be tied to +5 V

during programming.

30/1 (28/1)

NOTE: Parentheses indicate 28-SOP pin number.

16-7

S3P7414/P7424/P7434 OTP

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 16-3. Comparison of S3P7414/P7424 and S3C7414/C7424 Features

Characteristic

Program Memory

Operating Voltage (V_DD

S3P7414/P7424

4 K byte EPROM

S3C7414/C7424

4 K byte mask ROM

1.8 V to 5.5 V

)

1.8 V to 5.5 V

V_DD= 5 V, V_PP(TEST)=12.5V

OTP Programming Mode

Pin Configuration

42 SDIP, 44 QFP, 30 SDIP, 28 SOP

User Program 1 time

42 SDIP, 44 QFP, 30 SDIP, 28 SOP

Programmed at the factory

EPROM Programmability

Table 16-4. Comparison of S3P7434 and S3C7434 Features

S3P7434

Characteristic

Program Memory

Operating Voltage (V_DD

S3C7434

4 K byte EPROM

2.5 V to 5.5 V

4 K byte mask ROM

2.5 V to 5.5 V

)

V_DD= 5 V, V_PP(TEST)=12.5V

OTP Programming Mode

Pin Configuration

42 SDIP, 44 QFP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V_PP(TEST) pin of the S3P7414/P7424/P7434, the EPROM programming mode is

entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins

listed in Table 16-4 below.

Table 16-5. Operating Mode Selection Criteria

V_DD

V_PP

(TEST)

REG/

MEM

Address

(A15-A0)

R/W

Mode

5 V

0

1

0000H

0E3FH

1

0

1

0

EPROM read

12.5 V

EPROM program

EPROM verify

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16-8

S3C7414/P7414/C7424/P7424/C7434/P7434

S3P7414/P7424/P7434 OTP

START

Address= First Location

V

=5V, V =12.5V

PP

DD

x = 0

Program One 1ms Pulse

Increment X

YES

x = 10

NO

FAIL

NO

Verify Byte

Verify 1 Byte

Last Address

Increment Address

V

= V = 5 V

PP

DD

FAIL

Compare All Byte

PASS

Device Failed

Device Passed

Figure 16-7. OTP Programming Algorithm

16-9

S3P7414/P7424/P7434 OTP

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 16-6. S3P7414/P7424 D.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter Symbol Conditions

Min

Typ

3.0

2.3

1.4

1.1

1.0

0.5

0.4

0.1

Max

8.0

5.5

4.0

3.0

2.5

1.8

1.5

1.0

5.0

3.0

Units

mA

I_DD1

I_DD2

I_DD3

Supply

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

–

Run mode; V_DD= 5.0 V ± 10%

Crystal oscillator; C1=C2=22pF

V_DD= 3 V ± 10%

Current ⁽¹⁾

mA

–

Idle mode; V

= 5.0 V ± 10%

DD

Crystal oscillator; C1=C2=22pF

= 3 V ± 10%

V

DD

Stop mode; V_DD= 5.0 V ± 10%

Stop mode; V_DD= 3.0 V ± 10%

mA

NOTES:

1. D.C. electrical values for Supply current (I

to I

) do not include current drawn through internal pull-up registers,

DD3

DD1

output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

Main Oscillator Frequency

(Divided by 4)

CPU CLOCK

1.5 MHz

6 MHz

1.05 MHz

0.75 MHz

4.2 MHz

3 MHz

15.6 kHz

1

2

3

4

5

6

1.8

2.7

5.5

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 16-8. S3P7414/P7424 Standard Operating Voltage Range

16-10

S3C7414/P7414/C7424/P7424/C7434/P7434

S3P7414/P7424/P7434 OTP

Table 16-7. S3P7434 D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 2.5 V to 5.5 V)

Parameter Symbol Conditions

= 5.0 V ± 10%

°

Min

Typ

3.1

2.4

1.5

1.2

1.1

0.6

0.5

120

100

Max

8.0

5.5

4.0

3.0

2.5

1.8

1.5

1.0

200

150

Units

mA

I

Supply

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

6.0MHz

4.19MHz

–

Run mode; V

DD

DD1

DD2

DD3

Current ⁽¹⁾

Crystal oscillator; C1=C2=22pF

= 3 V ± 10%

V

DD

mA

–

Idle mode; V

= 5.0 V ± 10%

DD

Crystal oscillator; C1=C2=22pF

= 3 V ± 10%

V

DD

Stop mode; V

= 5.0 V ± 10%

= 3.0 V ± 10%

mA

DD

NOTES:

1. D.C. electrical values for Supply current (I

to I

) do not include current drawn through internal pull-up registers,

DD3

DD1

output port drive currents and ADC.

2. The supply current assumes a CPU clock of fx/4.

Main Oscillator Frequency

(Divided by 4)

CPU CLOCK

1.5 MHz

6 MHz

1.05 MHz

15.6 kHz

4.2 MHz

1

2

3

4

5

6

2.5

5.5

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 16-9. S3P7434 Standard Operating Voltage Range

16-11

S3P7414/P7424/P7434 OTP

S3C7414/P7414/C7424/P7424/C7434/P7434

NOTES

16-12

S3C7414/P7414/C7424/P7424/C7434/P7434

DEVELOPMENT TOOLS

17 DEVELOPMENT TOOLS

OVERVIEW

Samsung or Samsung's tool maker provides a powerful and easy-to-use development support system. The

development support system is configured with a host system, debugging tools, and support software. For the

host system, any standard computer that operates with MS-DOS as its operating system can be used. One type

of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator,

SMDS2+, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of

SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting

options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked

help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be

sized, moved, scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates

object code in standard hexadecimal format. Assembled program code includes the object code that is used for

ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and

an auxiliary definition (DEF) file with device specific information.

SASM57

The SASM57 is an relocatable assembler for Samsung's S3C7-series microcontrollers. The SASM57 takes a

source file containing assembly language statements and translates into a corresponding source code, object

code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating

system. It produces the relocatable object code only, so the user should link object file. Object files can be linked

with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be

needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by

HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device

automatically.

17-1

DEVELOPMENT TOOLS

TARGET BOARDS

S3C7414/P7414/C7424/P7424/C7434/P7434

Target boards are available for all S3C7-series microcontrollers. All required target system cables and adapters

are included with the device-specific target board.

OTPs

One time programmable microcontroller (OTP) for the S3C7414/C7424/C7434 microcontroller and OTP

programmer (Gang) are now available.

IBM-PC AT or Compatible

RS-232C

SMDS2+

Target

Application

System

PROM/OTP Writer Unit

RAM Break/Display Unit

Trace/Timer Unit

Probe

Adapter

TB7414/424/434

POD

Target

Board

SAM4 Base Unit

Eva

Power Supply Unit

Chip

Figure 17-1. SMDS Product Configuration (SMDS2+)

17-2

S3C7414/P7414/C7424/P7424/C7434/P7434

TB7414/424/434 TARGET BOARD

DEVELOPMENT TOOLS

The TB7414/424/434 target board is used for the S3C7414/C7424/C7434 microcontroller. It is supported by the

SMDS2+ development system.

TB7414/424/434

To User_VCC

Off

On

RESET

Stop

+

Idle

+

25

J101

1

40

100 QFP

S3E7410

EVA Chip

CN1

1

XI

20

21

SM1257A

Figure 17-2. TB7414/424/434 Target Board Configuration

17-3

DEVELOPMENT TOOLS

S3C7414/P7414/C7424/P7424/C7434/P7434

Table 17-1. Power Selection Settings for TB7414/424/434

Operating Mode

'To User_Vcc' Settings

Comments

The SMDS2/SMDS2+

supplies V_CCto the target

To User_Vcc

TB7414/

424/434

Target

System

OFF

ON

VCC

VSS

board (evaluation chip) and

the target system.

VCC

SMDS2/SMDS2+

The SMDS2/SMDS2+

supplies V_CConly to the target

To User_Vcc

OFF ON

TB7414/

424/434

External

VCC

Target

System

board (evaluation chip). The

target system must have its

own power supply.

VSS

VCC

SMDS2/SMDS2+

Table 17-2. Main-Clock Selection Settings for TB7414/424/434

Operating Mode

Main Clock Setting

Comments

Set the X_INswitch to “MDS”

XI

EVA Chip

S3E7410

when the target board is

connected to the

MDS

XTAL

SMDS2/SMDS2+.

XOUT

XIN

No Connection

100 Pin Connector

SMDS2/SMDS2+

Set the X_INswitch to “XTAL”

XI

EVA Chip

S3E7410

when the target board is used

as a standalone unit, and is

not connected to the

MDS

XTAL

SMDS2/SMDS2+.

XOUT

XIN

XTAL

Target Board

17-4

S3C7414/P7414/C7424/P7424/C7434/P7434

DEVELOPMENT TOOLS

P2.0/AD0

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P8.2

P2.1/AD1

P2.2/AD2

P2.3/AD3

P3.0/AD4

P3.1/AD5

P8.1/TCLO0

P8.0/TCL0

P7.3

P7.2

P7.1

AV

P7.0

REF

P3.2/CLO/TCL1

P3.3/PWM/TCLO1

P4.0

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P0.3/BUZ

P0.2/SI

9

10

11

12

13

14

15

16

17

18

19

20

V

DD

V

SS

TEST

P4.1

P4.2

RESET

P4.3

P5.0

P5.1

P5.2

P0.1/SO

P0.0/

P5.3

SCK

Figure 17-3. 40-Pin Connector for TB7414/424/434

17-5

DEVELOPMENT TOOLS

S3C7414/P7414/C7424/P7424/C7434/P7434

TARGET BOARD

J101

40

TARGET SYSTEM

J101

1

42

1

40

Target Cable for 40-Pin Connector

Part Name: AP42SD-K

42 SDIP

CONVERSION

PCB

Order Code: SM6527

20 21

21

22

Figure 17-4. S3C7414/C7434 Probe Adapter Cable for 42 SDIP Package

TARGET BOARD

J101

TARGET SYSTEM

J101

30

1

40

1

40

30 SDIP

CONVERSION

PCB

Target Cable for 40-Pin Connector

Part Name: AP30SD-E

Order Code: SM6533

20 21

15

16

Figure 17-5. S3C7424 Probe Adapter Cable for 30 SDIP Package

17-6


型号：	S3P7434-QZ
厂家：	SAMSUNG
描述：	Microcontroller, 4-Bit, OTPROM, SAM47 CPU, 6MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44 可编程只读存储器时钟微控制器外围集成电路
文件：	总216页 (文件大小：1368K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3P7434-QZ [SAMSUNG]

相关型号：

S3P7434XX-AQ

S3P7434XX-QZ

S3P7515

S3P7515-AT

S3P7515-QT

S3P7528

S3P7528-AQ

S3P7538

S3P7538-AV

S3P7538-SO

S3P7544

S3P7544-AM