LC88F40F0PAU [SANYO]
For Car Audio Systems 16-bit ETR Microcontroller; 对于汽车音响系统的16位微控制器ETR
| 型号： | LC88F40F0PAU |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | For Car Audio Systems 16-bit ETR Microcontroller |
| 文件： | 总32页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1853A
LC88F40H0PA/PAU
LC88F40F0PA/PAU
LC88F40D0PA/PAU
CMOS LSI
For Car Audio Systems
16-bit ETR Microcontroller
(ALL FLASH)
Overview
The LC88F40H0PA/PAU, LC88F40F0PA/PAU and LC88F40D0PA/PAU are 16-bit microcontrollers which are
ideally suited as a system controller in car audio applications for the control of “MP3 and WMA and other compression
decoders through CD/USB,” “CD mechanisms and CD DSPs,” “displays,” and “DSP tuners.” They are configured
around a CPU that operates at a high speed, and incorporate an internal flash ROM (All Flash, onboard programmable)
and RAM. These 16-bit microcontrollers integrate on a single chip such principal functions as on-chip debugging,
16-bit timer/counter (may be divided into 8-bit timers/counters), synchronous SIO (also used as the I2C bus interface),
UART (full duplex), 12-bit PWM, 12-bit resolution (8-bit resolution selectable) × 13-channel A/D converter, and 16
vector interrupts.
Microcontroller model line-up (list of ROM and RAM sizes)
Type No.
Flash ROM (byte)
RAM (byte)
LC88F40H0PA/PAU
LC88F40F0PA/PAU
LC88F40D0PA/PAU
512K
30K
384K
20K
256K
12K
Features
■Power supply voltage
• Main power supply voltage (V CPU)
3.3V 0.3V
V CPU to 5.5V
DD
DD
• I/O power supply (V PORT)
DD
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.23
D1510HKPC 20101005-S00001, S00002, S00003, S00004, S00005, S00006 No.A1853-1/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Flash ROM (ALL FLASH)
• Single 3.3V power supply, on-board writeable
• Block erase in 512 byte units
■Minimum instruction cycle time (Tcyc)
• 83.3ns
■Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units :86 (P0n, P1n, P2n, P3n, P4n, P5n, P6n, P7n
PAn, PB0 to PB6, PC0, PD0 to PD5)
• Dedicated pin for low-pass filter connection
• Regulator pins
• Reset pins
• TEST pins
• Dedicated pins for crystal oscillator
• Power pins
: 1 (LPFO)
: 1 (VREG)
: 1 (RESB)
: 1 (TEST)
: 2 (XT1, XT2)
: 2 (V CPU, V 1: Main power, I/O power supply)
DD SS
: 4 (V PORT1 to 2, V 2 to 3: I/O power supply)
DD SS
: 2 (V PLL, V 4: PLLVCO power)
DD SS
■SIO: 6 channels (4 channels are also used as I2C bus.)
• SIO0: 8 bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (4 to 512 transfer clock cycle)
3) Automatic and continuous data transfer function to and from the RAM (max. 4096 bytes)
• SIO1: 8 bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (4 to 512 transfer clock cycle)
3) Automatic and continuous data transfer function to and from the RAM (max. 4096 bytes)
• SMIIC0: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• SMIIC1: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• SMIIC2: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• SMIIC3: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
■UART: 4 channels
1) Data length
2) Stop bits
: 8 bits (LSB first)
: 1 bit
3) Parity bits
4) Transfer rate
: None/even parity/odd parity
: 8 to 4096 cycle
5) Baudrate source clock : System clock/XT clock/VCO clock
5) Wakeup function
6) Full duplex communication
No.A1853-2/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Timers
• Timer 0: 16-bit timer that supports PWM/toggle outputs
1) 5-bit prescaler
2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, XT clock, VCO clock, and internal RC oscillator
• Timer 1: 16-bit timer with capture registers
1) 5-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, XT clock, VCO clock, and internal RC oscillator
• Timer 2: 16-bit timer with capture registers
1) 4-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, XT clock, VCO clock, and external events
• Timer 3: 16-bit timer that supports PWM/toggle outputs
1) 8-bit prescaler
2) 8-bit PWM × 2ch or 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, XT clock, VCO clock, and external events
• Timer 4: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Timer 5: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Timer 6: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 1
• Timer 7: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 1
* Prescaler 0 and 1 are consisted of 4 bits and can choose their clock source from XT clock or VCO clock.
• Timer 8
1) Clock source may be selected from XT clock (32.768kHz) and frequency-divided output of clock.
2) Interrupts can be generated in 8 timing schemes.
• Watch timer
1) Clock may be selected from XT clock (32.768kHz)
2) Interrupts can be generated in 4 timing schemes.
■Day, minute and second counters
1) Count-up of clocks output from watch timer
2) Configured with day counter, minute counter, second counter
3) Continues operation when in HOLDX mode.
■AD converter
1) 12/8 bits resolution selectable
2) Analog input: 13 channels
3) Comparator mode
4) Automatic reference voltage generation
No.A1853-3/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■PWM: Multifrequency 12-bit PWM × 4 channels
• PWM0: Multifrequency 12-bit PWM × 2 channels (PWM0A and PWM0B)
• PWM1: Multifrequency 12-bit PWM × 2 channels (PWM1A and PWM1B)
1) 2-channel pairs controlled independently of one another
2) Clock source selectable from system clock or VCO clock
3) 8-bit prescaler: TPWMR0 = (prescaler value + 1) × clock period
4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit
5) Fundamental wave PWM mode
Fundamental wave period : 16 TPWMR0 to 256 TPWR0
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
6) Fundamental wave + additional pulse mode
Fundamental wave period : 16 TPWR0 to 256 TPWR0
Overall period
High pulse width
: Fundamental wave period × 16
: 0 to (Overall period - TPWR0)
■Watchdog Timer: 1 channel
• Driven by the timer 8 + internal watchdog timer dedicated counter
• Interrupt or reset mode selectable
■Interrupts
• 63 sources, 16 vector addresses
1) Provides three levels of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the
current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
08000H
08004H
08008H
0800CH
08010H
08014H
08018H
0801CH
08020H
08024H
08028H
0802CH
08030H
08034H
08038H
0803CH
Interrupt Source
WDT (1)
2
Timer 8 (2)/Watch timer (1)
Timer 0 (2)
3
4
INT0 (1)
5
6
INT1 (1)
7
INT2 (1)/timer 1 (2)/UART 2 (3)
8
INT3 (1)/timer 2 (3)/SMIIC0 (1)
9
INT4 (1)/timer 3 (2)/SMIIC1 (1)/IR Remote control receive (4)
INT5 (1)/timer 4 (1)/SIO1 (2)
10
11
12
13
14
15
16
PWM0 (1)/PWM1 (1)/SMIIC2 (1)
ADC (1)/timer 5 (1)/SMIIC3 (1)
INT6 (1)/timer 6 (1)/UART 3 (3)
INT7 (1)/timer 7 (1)/SIO0 (2)/UART 4 (3)
Port 0 (3)/Port 5 (8)/UART 5 (3)
• 3 priority levels selectable.
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• A number enclosed in parentheses denotes the number of sources.
■Subroutine Stack: Entire maximum RAM space (The stack is allocated in RAM.)
• Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes
• Subroutine calls that do not automatically save PSW: 4 bytes
■High-speed Multiplication/division instructions
• 16 bits × 16 bits
• 16 bits ÷ 16 bits
• 32 bits ÷ 16 bits
No.A1853-4/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Infrared remote controller receive functions
1) Noise rejection function
2) PPM(Pulse Position Modulation), compatible with Manchester and other data encoding systems.
3) HOLDX mode release function
■Oscillation circuits
• RC oscillator circuit (internal):
• XT oscillator circuit:
For system clock
For system clock
• VCO oscillator circuit (internal): For system clock
■Low power consumption
• HALT mode:
Halts instruction execution while allowing the peripheral circuits to continue operation.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
• HOLDX mode: Suspends instruction execution and operation of all the peripheral circuits except the modules run
on the XT clock.
■System clock divider function
• Can run on low current.
• 1/1 to 1/128 of the system clock frequency can be set.
No.A1853-5/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
■Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Both the XT oscillator and internal RC oscillator retain the state established when the standby mode is entered.
2) Both the XT and VCO clocks retain the state established when the standby mode is entered.
3) There are the two ways of releasing the HALT mode.
(1) Generating a reset condition
(2) Generating an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) Both the XT oscillator and internal RC oscillator automatically stop operation.
2) XT clock and VCO clock oscillators automatically stop.
3) There are the six ways of releasing the HOLD mode.
(1) Generating a reset condition
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt request generated in UART2, UART3, UART4, or UART5
(6) Having an interrupt request generated in SIO0 or SIO1
• HOLDX mode: Suspends instruction execution and operation of all the peripheral circuits except the modules run
on the XT clock.
1) The internal RC oscillator automatically stops operation.
2) The XT clock retains the state established when the HOLDX mode is entered and the VCO clock automatically
stops.
3) There are nine ways of resetting the HOLDX mode.
(1) Generating a reset condition
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt request generated in UART2, UART3, UART4, or UART5
(6) Having an interrupt request generated in SIO0 or SIO1
(7) Having an interrupt source established in the timer 8 circuit
(8) Having an interrupt source established in the infrared remote controller receive circuit
(9) Having an interrupt source established in the clock timer circuit
■Reset
• External reset
• Voltage drop detection type of reset circuit (VDET circuit) incorporated
1) Normal mode detection voltage: 2.85V 0.15V
2) HOLD mode detection voltage: 1.42V 0.15V
■On-chip debugger function
• Supports software debugging with the IC mounted on the target board.
• Supports source line debugging and tracing functions, and breakpoint setting and real time monitor.
• Single-wire communication
■Shipping Form
• QIP100E (Lead free product)
No.A1853-6/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Package Dimensions
unit : mm (typ)
3151A
23.2
20.0
80
51
81
50
31
100
1
30
0.65
0.3
0.15
(0.58)
SANYO : QIP100E(14X20)
No.A1853-7/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P44/SIO1
PA0/SM1CK
PA1/SM1DA
PA2/SM1DO
PA3/SM2CK
PA4/SM2DA
PA5/SM2DO
PA6/U5RX
PA7/U5TX
PB0/PWM10
PB1/PWM11
PB2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P45/SCK1
P46/PWM00
P47/PWM01
V
V
2
SS
PORT1
DD
P27/RMIN
P26/T5O
P25/T4O
P24/SM0DO
P23/SM0DA
P22/SM0CK
P21/INT5
P20/INT4
PD5
LC88F40H0PA/PAU
LC88F40F0PA/PAU
LC88F40D0PA/PAU
PB3
PB4
PB5/INT7
PB6
PD4
V
PLL
4
DD
V
PD3
SS
PD2
LPFO
PD1/U4TX
PD0/U4RX
P50/P5INT0
P51/P5INT1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Top view
No.A1853-8/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
System Block Diagram
RC
Timer 8
X’tal
Watchdog timer
Watch timer
CPU
FLASH ROM
RAM
Day, minute and
second counter
On-chip debugger
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port A
Port B
Port C
Port D
SIO0
SIO1
SMIIC0
SMIIC1
SMIIC2
SMIIC3
PWM0
PWM1
UART2
UART3
UART4
UART5
ADC
Infrared remote
controller receive
INT0 to INT7
No.A1853-9/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Pin Description
Name
I/O
Description
V
V
V
V
V
V
V
V
CPU
-
+ Power sources 3.3V power supply (3.0 to 3.6V)
DD
DD
DD
DD
PORT1
PORT2
PLL
-
+ Power sources I/O power supply (V CPU to 5.5V)
DD
-
+ Power sources I/O power supply (V CPU to 5.5V)
DD
-
+ Power sources PLLVCO power supply (3.0 to 3.6V)
- Power sources
1
2
3
4
-
-
SS
SS
SS
SS
- Power sources
-
- Power sources
-
- Power sources
Port 0
I/O
• 8-bit I/O port
Supply voltage from
V PORT1 used
DD
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1 bit units
• Port 0 interrupt input (P00 to P05)
• HOLD release input (P00 to P05)
• Pin functions
(V CPU to 5.5V)
DD
P06: Timer 0L output
P07: Timer 0H output
Port 1
I/O
• 8-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
V
PORT2 used
DD
P10 to P17
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
(V CPU to 5.5V)
DD
P10: SIO0 data output
P11: SIO0 data input/output
P12: SIO0 clock input/output
P14: Timer 3L output
P15: Timer 3H output
P16: UART2 receive
P17: UART2 transmit
Port 2
I/O
• 8-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
V
PORT1 used
DD
P20 to P27
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
(V CPU to 5.5V)
DD
P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/
timer 2H capture input
P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/
timer 2H capture input
P22: SMIIC0 clock input/output
P23: SMIIC0 data bus input/output
P24: SMIIC0 data (used in 3-wire SIO mode)
P25: Timer 4 output
P26: Timer 5 output
P27: Remote control receive
• Interrupt acknowledge type
INT4, INT5: H level, L level, H edge, L edge, both edges
• 8-bit I/O port
Port 3
I/O
Supply voltage from
• I/O specifiable in 1-bit units
V
PORT2 used
DD
P30 to P37
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
(V CPU to 5.5V)
DD
P30: INT0 input/HOLD release input/timer 2L capture input
P31: INT1 input/HOLD release input/timer 2H capture input
P32: INT2 input/HOLD release input/timer 2 event input/timer 2L capture input
P33: INT3 input/HOLD release input/timer 2 event input/timer 2H capture input
P34: UART3 receive
P35: UART3 transmit
P36: Timer 6 output
P37: Timer 7 output
• Interrupt acknowledge type
INT0 to INT3: H level, L level, H edge, L edge, both edges
Continued on next page.
No.A1853-10/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Name
Port 4
I/O
I/O
Description
• 8-bit I/O port
Supply voltage from
V PORT1 used
DD
• I/O specifiable in 1-bit units
P40 to P47
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
(V CPU to 5.5V)
DD
P40: INT6 input/HOLD release input
P43: SIO1 data output
P44: SIO1 data input/output
P45: SIO1 clock input/output
P46: PWM00 output
P47: PWM01 output
• Interrupt acknowledge type
INT6: H level, L level, H edge, L edge, both edges
• 8-bit I/O port
Port 5
I/O
Supply voltage from V CPU
DD
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
used
P50 to P57
(3.0 to 3.6V)
• Port 5 interrupt function
• HOLD release input
Port 6
I/O
I/O
• 8-bit I/O port
Supply voltage from V CPU
DD
used
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P60 to P67
(3.0 to 3.6V)
AN0 (P60) to AN7 (P67): AD converter input port
• 8-bit I/O port
Port 7
Supply voltage from V CPU
DD
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
used
P70 to P77
(3.0 to 3.6V)
AN8 (P70) to AN12 (P74): AD converter input port
P75: SMIIC3 clock input/output
P76: SMIIC3 data bus input/output
P77: SMIIC3 data (used in 3-wire SIO mode)
• 8-bit I/O port
Supply voltage from
V
PORT1 used
DD
(V CPU to 5.5V)
DD
Supply voltage from
Port A
I/O
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
V
PORT2 used
DD
PA0 to PA7
(V CPU to 5.5V)
DD
PA0: SMIIC1 clock input/output
PA1: SMIIC1 data bus input/output
PA2: SMIIC1 data (used in 3-wire SIO mode)
PA3: SMIIC2 clock input/output
PA4: SMIIC2 data bus input/output
PA5: SMIIC2 data (used in 3-wire SIO mode)
PA6: UART5 receive
PA7: UART5 transmit
Port B
I/O
• 7-bit I/O port
Supply voltage from
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
V
PORT2 used
DD
PB0 to PB6
(V CPU to 5.5V)
DD
PB0: PWM10 output
PB1: PWM11 output
PB5: INT7 input/HOLD release input
• Interrupt acknowledge type
INT7: H level, L level, H edge, L edge, both edges
• 1-bit I/O port
Port C
PC0
I/O
I/O
Supply voltage from V CPU
DD
used
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• 6-bit I/O port
(3.0 to 3.6V)
Supply voltage from
Port D
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
V
PORT1 used
DD
PD0 to PD5
(V CPU to 5.5V)
DD
PD0: UART4 receive
PD1: UART4 transmit
Continued on next page.
No.A1853-11/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Name
I/O
Description
XT1
XT2
I
O
I
• Input terminal for 32.768kHz X'tal oscillation
• Output terminal for 32.768kHz X'tal oscillation
• Reset pin
RESB
• This must be set to low for 50μs or longer when the power is turned on and when a reset is required.
TEST
I/O
• TEST pin
• Used to communicate with on-chip debugger
• 100kΩ pull-down
LPFO
VREG
O
O
• LPF connection pin for PLLVCO
• Regulator output pin
Connect a bypass capacitor to this pin
No.A1853-12/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Port Output Types
The port output type and pull-up resistance must be set using the registers.
The pin data can be read regardless of the I/O setting of the port.
The port output type (CMOS output or N-channel open drain output) and use/disuse of the pull-up resistor can be
configured separately for each port.
* Make the following connection to minimize the noise input to the V CPU pin and prolong the backup time.
DD
Be sure to electrically short the V 1, V 2, V 3 and V 4 pins.
SS SS SS SS
Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the
backup capacitors. (V CPU = V PORT1 = V PORT2 = V PLL)
DD DD DD DD
LSI
V
DD
V
DD
V
DD
V
DD
CPU
Power
supply
LPFO
For
buckup
PORT1
PORT2
PLL
VREG
V
1 V 2 V 3 V
SS SS
4
SS
SS
Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is
unpredictable. (V CPU = V PORT1 = V PORT2 = V PLL)
DD DD DD DD
LSI
V
DD
V
DD
V
DD
V
DD
CPU
LPFO
Power
supply
For
buckup
PORT1
PORT2
PLL
VREG
V
1 V 2 V 3 V
SS SS
4
SS
SS
No.A1853-13/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = V 4 = 0V
SS SS SS SS
Specification
typ
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
min
max
+4.6
unit
Maximum Supply
voltage
V
V
max(1)
V
V
V
V
CPU
V
CPU=V PORT1
DD
DD
DD DD
-0.3
PLL
=V PORT2=V PLL
DD DD
DD
DD
DD
max(2)
PORT1
PORT2
V
PORT1=V PORT2
DD
DD DD
-0.3
-0.3
+6.5
Input voltage
V (1)
RESB, XT1
V
(1)+0.3
I
DD
Input/Output
voltage
V
(1)
Ports 5, 6
IO
V
P70 to 74
-0.3
-0.3
V
(1)+0.3
DD
Ports C
XT2
V
(2)
Ports 0, 1, 2, 3, 4
P75 to P77
Ports A, B, D
Ports 0, 1, 2, 3, 5
Ports 6, 7, A, C, D
P40 to P45
PB2 to PB6
P46, P47
IO
V
(2)+0.3
DD
Peak output
current
IOPH(1)
CMOS output selected
Per 1 application pin
-10
-20
IOPH(2)
IOMH(1)
Per 1 application pin
PB0, PB1
Average
Ports 0, 1, 2, 3, 5
Ports 6, 7, A, C, D
P40 to P45
PB2 to PB6
P46, P47
CMOS output selected
Per 1 application pin
output current
(Note 1-1)
-7.5
IOMH(2)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
Per 1 application pin
-10
-15
-15
PB0, PB1
Total output
current
Ports 5
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ports C
mA
Ports 6
P70 to P74
Ports 5, 6
P70 to P74
Ports C
-20
ΣIOAH(4)
Ports 2, D
P75 to P77
Ports 0, 4
Total of all applicable pins
-25
-25
-45
ΣIOAH(5)
ΣIOAH(6)
Total of all applicable pins
Total of all applicable pins
Ports 0, 2, 4, D
P75 to P77
Ports 1, 3
ΣIOAH(7)
ΣIOAH(8)
ΣIOAH(9)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
-25
-25
-45
Ports A, B
Ports 1, 3, A, B
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A1853-14/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Specification
typ
Applicable Pin
/Remarks
Parameter
Symbol
IOPL(1)
Conditions
min
max
unit
Peak output
current
Ports 0, 1, 3
Per 1 application pin.
Ports 4, 5, 6
Ports B, C, D
P20, P21
20
25
10
15
P24 to P27
P70 to P74, P77
PA2, PA5 to PA7
P22, P23
IOPL(2)
IOML(1)
Per 1 application pin.
Per 1 application pin.
P75, P76
PA0, PA1
PA3, PA4
Average
Ports 0, 1, 3
Ports 4, 5, 6
Ports B, C, D
P20, P21
output current
(Note 1-1)
P24 to P27
P70 to P74, P77
PA2, PA5 to PA7
P22, P23
IOML(2)
Per 1 application pin.
mA
P75, P76
PA0, PA1
PA3, PA4
Total output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
Ports 5
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
15
15
Ports C
Ports 6
P70 to P74
Ports 5, 6
P70 to P74
Ports C
20
ΣIOAL(4)
Ports 2, D
P75 to P77
Ports 0, 4
Total of all applicable pins
25
25
45
ΣIOAL(5)
ΣIOAL(6)
Total of all applicable pins
Total of all applicable pins
Ports 0, 2, 4, D
P75 to P77
Ports 1, 3
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
Pd max
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ta = -40 to +85°C
25
25
45
Ports A, B
Ports 1, 3, A, B
QIP100E
Allowable power
dissipation
400
+85
mW
°C
Operating
Topr
Tstg
-40
-45
temperature range
Storage
+125
°C
temperature range
Note 1-1: Average output current is average of current in 100ms interval.
No.A1853-15/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Allowable Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
min
typ
max
unit
Operating
V
V
(1)
V
CPU=V PLL
DD
3.0
(1)
3.6
5.5
DD
DD
supply voltage
(2)
V
V
V
PORT1
PORT2
DD
DD
DD
DD
V
DD
Memory sustaining
supply voltage
High level input
voltage
VHD
CPU=V PORT1
DD
RAM and register contents
in HOLD mode.
1.2
=V PORT2=V PLL
DD DD
V
(1)
Ports 0, 1, 2, 3, 4
P75 to P77
Ports A, B, D
Ports 5, 6, C
P70 to P74
RESB
V
PORT=V (2)
DD
IH
DD
0.3×V (2)
DD
V
(2)
(1)
DD
+0.7
V
(2)
V
CPU=V (1)
DD
0.3×V (1)
IH
DD
DD
V
V
DD
+0.7
V
V
(3)
(4)
V
V
CPU=V (1)
DD
0.75×V (1)
(1)
IH
DD
DD
DD
DD
V
P22, P23, P75, P76
PA0, PA1, PA3, PA4
I2C side
PORT=V (2)
DD
IH
DD
0.7×V (2)
V
(2)
DD
Low level input
voltage
V
(1)
Ports 0, 1, 2, 3, 4
P75 to P77
V
PORT=V (2)
DD
IL
IL
DD
0.1×V (2)
DD
V
SS
+0.4
Ports A, B, D
Ports 5, 6, C
P70 to P74
V
(2)
V
CPU=V (1)
DD
0.1×V (1)
DD
DD
V
SS
+0.4
V
V
(3)
(4)
RESB
V
V
CPU=V (1)
DD
V
0.25×V (1)
IL
DD
SS
DD
P22, P23, P75, P76
PA0, PA1, PA3, PA4
I2C side
PORT=V (2)
DD
IL
DD
V
0.3×V (2)
SS
DD
Instruction cycle
time
tCYC
Tpup
V
CPU=V (1)
DD
DD
83.3
μs
Supply voltage rise
time
V
CPU
DD
1
100
2.0
ms
MHz
kHz
Oscillation
FmRC
Internal RC oscillation
0.5
1.0
32.768
frequency range
FmX’tal
XT1, XT2
32.768kHz crystal
oscillation.
No.A1853-16/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
typ max
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
V
[V]
min
unit
DD
High level input
current
I
(1)
Ports 0, 1, 2, 3, 4
P75 to P77
Output disable
Pull-up resistor OFF
=V (2)
IH
V
PORT=
DD
Ports A, B, D
V
1
1
IN DD
V
(1) to 5.5
CPU=
DD
(including the off-leak current of
the output Tr.)
I
(2)
Ports 5, 6, C
P70 to P74
RESB
Output disable
IH
Pull-up resistor OFF
V
DD
V
=V (1)
IN DD
3.0 to 3.6
(including the off-leak current of
the output Tr.)
I
I
(3)
XT1
V
=V (1)
V
CPU=
IH
IN DD
DD
0.18
3.0 to 3.6
μA
Low level input
current
(1)
(2)
(3)
Ports 0, 1, 2, 3, 4
P75 to P77
Output disable
IL
IL
IL
Pull-up resistor OFF
V
PORT=
DD
Ports A, B, D
V
=V
-1
-1
IN SS
V
(1) to 5.5
DD
(including the off-leak current of
the output Tr.)
I
Ports 5, 6, C
P70 to P74
RESB
Output disable
Pull-up resistor OFF
V
CPU=
DD
V
=V
IN SS
3.0 to 3.6
(including the off-leak current of
the output Tr.)
I
XT1
V
=V
IN SS
V
CPU=
DD
-0.18
3.0 to 3.6
High level output
voltage
V
(1)
Ports 0, 1, 2, 3
P40 to P45
P75 to P77
Ports A, D
I
=-1.0mA, V (2)
V
PORT=
V
(2)
DD
-1.0
OH
OH
OH
DD
DD
4.5 to 5.5
V
(2)
I
=-0.4mA, V (2)
DD
OH
V
PORT=
V
(2)
DD
DD
V
(1) to 5.5
-0.4
DD
PB2 to PB6
Ports 5, 6, C
P70 to P74
V
V
V
V
V
V
(3)
(4)
(5)
(6)
I
I
I
I
I
I
=-1.0mA, V (1)
DD
V
CPU=
V
V
V
V
(1)
OH
OH
OH
OH
OH
OH
OH
OH
DD
DD
3.0 to 3.6
V CPU=
DD
-1.0
=-0.4mA, V (1)
DD
(1)
DD
3.0 to 3.6
-0.4
P46, P47
PB0, PB1
=-10mA, V (2)
DD
V
PORT=
DD
(2)
DD
4.5 to 5.5
-1.5
=-1.6mA, V (2)
DD
V
PORT=
(2)
DD
DD
V
V
(1) to 5.5
-0.4
DD
Low level output
voltage
(1)
Ports 0, 1, 3, 4
P20, P21
=10mA
V
PORT=
OL
OL
OL
OL
DD
1.5
0.4
4.5 to 5.5
P24 to P27,
P77
(2)
=1.6mA
V
PORT=
DD
PA2, PA5 to PA7
Ports B, D
V
(1) to 5.5
DD
V
V
V
(3)
(4)
(5)
Ports 5, 6, C
P70 to P74
P22, P23
I
I
I
=1.6mA
=11mA
=3.0mA
=0.9V
V
CPU=
DD
OL
OL
OL
OL
OL
OL
0.4
1.5
0.4
80
3.0 to 3.6
V
PORT=
DD
P75, P76
4.5 to 5.5
PA0, PA1
V
PORT=
DD
PA3, PA4
V
(1) to 5.5
DD
Pull-up resistor
Rpu(1)
Rpu(2)
Rpu(3)
VHYS
Ports 0, 1, 2, 3, 4
P75 to P77
Ports A, B, D
V
V
PORT=
DD
OH
DD
15
15
15
35
35
35
4.5 to 5.5
V
PORT=
DD
kΩ
150
150
V
(1) to 5.5
DD
Ports 5, 6, C
P70 to P74
V
CPU=
DD
3.0 to 3.6
Hysteresis
voltage
RESB
Ports 1, 2, 3, 4, 5
Ports 7, A, B, C, D
Ports 1 to 5, 7, A to D
PnFSAn=1
0.1V
DD
V
Continued on next page.
No.A1853-17/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
CP
Conditions
V
[V]
min
unit
pF
DD
Pin capacitance
All pins
• For pins other than that under
test: V =V
IN SS
10
• f=1MHz
• Ta=25°C
Low voltage
circuit
VDET(1)
VDET(2)
V
V
CPU
CPU
On low voltage detection circuit
Excluding the HOLD mode
On low voltage detection circuit
HOLD mode
DD
2.7
2.85
1.42
3.0
V
V
detection
voltage
DD
1.27
1.57
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS SS SS SS
1. SIO0, SIO1 Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1)
Specification
Applicable Pin
Parameter
Period
Symbol
tSCK(1)
Conditions
• See Fig. 1.
/Remarks
V
[V]
min
typ
max
unit
DD
SCK0(P12)
SCK1(P45)
4
2
2
6
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
V
PORT=
DD
• Automatic communication mode
• See Fig. 1.
V
(1) to 5.5
DD
tCYC
tSCKHBSY
(1a)
• Automatic communication mode
• See Fig. 1.
23
4
tSCKHBSY
(1b)
• Modes other than automatic
communication mode
• See Fig. 1.
Period
tSCK(2)
SCK0(P12)
SCK1(P45)
• CMOS output selected
• See Fig. 1.
4
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Automatic communication mode
• CMOS output selected
• See Fig. 1.
V
PORT=
DD
6
4
V
(1) to 5.5
DD
tSCKHBSY
(2a)
• Automatic communication mode
• CMOS output selected
• See Fig. 1.
tCYC
23
tSCKHBSY
(2b)
• Modes other than automatic
communication mode
• See Fig. 1.
4
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
SIO0(P11),
SIO1(P44)
• Specified with respect to rising
edge of SIOCLK
0.03
0.03
• See fig. 1.
V
PORT=
DD
V
(1) to 5.5
DD
Output
SO0(P10),
SO1(P43),
SIO0(P11),
SIO1(P44)
• (Note 4-1-2)
• (Note 4-1-2)
delay time
1tCYC
+0.05
μs
V
PORT=
DD
V
(1) to 5.5
tdD0(2)
DD
1tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Specified with respect to falling edge of SIOCLK. Specified as the time to the beginning of output state
change in open drain output mode. See Fig. 1.
No.A1853-18/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
2. SIO0, SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1)
Specification
Applicable Pin
/Remarks
Parameter
Period
Symbol
tSCK(3)
Conditions
• See Fig. 1.
V
[V]
min
typ
max
unit
DD
SCK0(P12)
SCK1(P45)
2
1
Low level
tSCKL(3)
tSCKH(3)
V
PORT=
DD
pulse width
High level
pulse width
tCYC
V
(1) to 5.5
DD
1
2
tSCKHBSY(3)
tsDI(2)
Data setup time
Data hold time
SIO0(P11),
SIO1(P44)
• Specified with respect to rising
edge of SIOCLK
0.03
0.03
• See fig. 1.
V
PORT=
DD
V
(1) to 5.5
thDI(2)
tdD0(3)
DD
μs
Output
SO0(P10),
SO1(P43),
SIO0(P11),
SIO1(P44)
• (Note 4-2-2)
delay time
V
PORT=
1tCYC
+0.05
DD
V
(1) to 5.5
DD
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-2-2: Specified with respect to falling edge of SIOCLK. Specified as the time to the beginning of output state
change in open drain output mode. See Fig. 1.
3. SMIIC0 to SMIIC3 Simple SIO Mode Input/Output Characteristics
Specification
Applicable Pin
/Remarks
Parameter
Period
Symbol
tSCK(4)
Conditions
• See Fig. 1.
V
[V]
min
typ
max
unit
DD
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
4
2
2
8
V
PORT=
Low level
tSCKL(4)
tSCKH(4)
tSCK(5)
tSCKL(5)
tSCKH(5)
tsDI(3)
DD
V
(1) to 5.5
pulse width
High level
pulse width
Period
DD
tCYC
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
• CMOS output selected
• See Fig. 1.
V
PORT=
Low level
pulse width
DD
1/2
1/2
V
(1) to 5.5
DD
tSCK
High level
pulse width
Data setup time
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• Specified with respect to rising
edge of SIOCLK
0.03
0.03
• See fig. 1.
V
DD
PORT=
V
(1) to 5.5
Data hold time
thDI(3)
tdD0(4)
DD
Output delay
time
SM0DO(P24)
SM0D1(PA2)
SM0D2(PA5)
SM0D3(P77)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• Specified with respect to falling
edge of SIOCLK
μs
• Specified as interval up to time
when output state starts changing.
• See Fig. 1.
V
PORT=
1tCYC
+0.05
DD
V
(1) to 5.5
DD
Note 4-5-1: These specifications are theoretical values. Add margin depending on its use.
No.A1853-19/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
tSCKHBSY
tSCKHBSY
RUN:
SIOCLK:
DATAIN:
DI0
DI1
DI6
DI7
DI8
DIx
DATAOUT:
DO0
DO1
DO6
DO7
DO8
DOx
Data transfer period
(SIO0 and SIO1 only)
tSCK
SIOCLK:
tSCKL
tSCKH
thDI
tsDI
DATAIN:
DATAOUT:
Data transfer period
(SIO0 and SIO1 only)
SIOCLK:
DATAIN:
tSCKL
tSCKHA
thDI
tsDI
tdDO
DATAOUT:
* Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768
Figure 1 Serial I/O Waveforms
No.A1853-20/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
4. SMIIC0 to SMIIC3 I2C Mode Input/Output Characteristics
Specification
Applicable Pin
/Remarks
Parameter
Period
Symbol
tSCL
Conditions
• See Fig. 2.
V
[V]
min
typ
max
unit
Tfilt
DD
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
5
V
PORT=
Low level
tSCLL
tSCLH
tSCLx
tSCLLx
tSCLHx
tsp
DD
2.5
2
V
(1) to 5.5
pulse width
High level
pulse width
Period
DD
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
• Specified as interval up to time
when output state starts changing.
10
V
PORT=
Low level
pulse width
DD
1/2
1/2
V
(1) to 5.5
DD
tSCL
High level
pulse width
SM0C and SM0DA
pins input spike
suppression time
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• See fig. 2.
1
Tfilt
Bus release
time between
start and stop
tBUF
• See fig. 2.
2.5
tBUFx
• Standard-mode
V
PORT=
DD
μs
• Specified as interval up to time
when output state starts changing.
• Fast-mode
5.5
1.6
2.0
2.5
4.1
1.0
1.0
5.5
1.6
1.0
4.9
1.1
V
(1) to 5.5
DD
• Specified as interval up to time
when output state starts changing.
• When SMIIC register control bit,
I2CSHDS=0
Start/restart
condition hold
time
tHD; STA
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• See fig. 2.
Tfilt
• When SMIIC register control bit,
I2CSHDS=1
• See fig. 2.
V
PORT=
DD
V
(1) to 5.5
tHD; STAx
• Standard-mode
DD
• Specified as interval up to time
when output state starts changing.
μs
Tfilt
μs
• Fast-mode
• Specified as interval up to time
when output state starts changing.
Restart
tSU; STA
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• See fig. 2.
condition setup
time
tSU; STAx
• Standard-mode
V
PORT=
DD
• Specified as interval up to time
when output state starts changing.
V
(1) to 5.5
DD
• Fast-mode
• Specified as interval up to time
when output state starts changing.
Stop condition
setup time
tSU; STO
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• See fig. 2.
Tfilt
μs
tSU; STOx
• Standard-mode
V
PORT=
DD
• Specified as interval up to time
when output state starts changing.
V
(1) to 5.5
DD
• Fast-mode
• Specified as interval up to time
when output state starts changing.
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Continued on next page.
No.A1853-21/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
Conditions
V
[V]
min
unit
Tfilt
DD
Data hold time
tHD; DAT
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
• See fig. 2.
0
1
1
V
PORT=
DD
tHD; DATx
• Specified as interval up to time
when output state starts changing.
V
(1) to 5.5
DD
1.5
Data setup time
tSU; DAT
• See fig. 2.
V
PORT=
DD
Tfilt
tSU; DATx
• Specified as interval up to time
when output state starts changing.
V
(1) to 5.5
PORT=
DD
1tSCL
-1.5Tfilt
Fall time
tF
tF
• See fig. 2.
V
DD
300
V
(1) to 5.5
DD
• When SMIIC register control bits,
PSLW=1, P5V=1
V
V
PORT=5 20+0.1Cb
PORT=3 20+0.1Cb
PORT=
250
250
DD
ns
• When SMIIC register control bits,
PSLW=1, P5V=0
DD
• When SMIIC register control bits,
PSLW=0
V
DD
(1) to 5.5
100
V
DD
• Cb ≤ 400pF
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-6-2: The value of Tfilt is determined by the values of the register SMICnBRG (n=0, 1, 2, 3), bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
1
1
0
1
0
1
tCYC × 1
tCYC × 2
tCYC × 3
tCYC × 4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns ≥ Tfilt > 140ns
Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF
Note 4-6-4: The standard-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The fast-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A1853-22/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
P
S
Sr
P
SDA
SCK
tBUF
tHD;STA tR
tF
tHD;STA
tsp
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2 I2C Timing
5. UART2 to UART5 Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
V
[V]
min
typ
max
unit
DD
Transfer rate
UBR
U2RX(P16),
U3RX(P34),
U4RX(PD0),
U5RX(PA6),
U2TX(P17),
U3TX(P35),
U4TX(PD1),
U5TX(PA7)
V
PORT=
DD
8
4096 tBGCYC
V
(1) to 5.5
DD
Note 4-7: tBGCYC denotes one cycle of the baudrate clock source.
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
typ max
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
V
[V]
min
unit
DD
High/low level
minimum pulse
width
tPIH(1)
tPIL(1)
INT0(P30),
INT1(P31),
INT2(P32),
INT3(P33),
INT4(P20),
INT5(P21),
INT6(P40),
INT7(PB5)
RESB
• Interrupt source flag can be set.
• Event inputs for timers 2 and 3
are enabled.
V
PORT=
DD
2
tCYC
V
(1) to 5.5
DD
tPIL(2)
tPIL(3)
Can be reset via the external
reset pin.
V
CPU=
DD
50
50
μs
μs
3.0 to 3.6
(Note 5-1)
V
CPU
Can be reset by the low voltage
detection circuit.
(Note 5-1)
DD
(Note 5-2)
Note 5-1: This parameter specifies the time required to ensure that the reset sequence is carried out without fail.
The reset may be applied even if this time specification is not satisfied.
Note 5-2: (V CPU voltage) ≤ (Low voltage circuit detection voltage)
DD
tPIL
tPIH
Figure 3 Pulse Input Timing Signal Waveform
No.A1853-23/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
AD Converter Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
1. 12-bit AD Conversion Mode
Specification
Applicable Pin
/Remarks
Parameter
Symbol
Conditions
V
CPU[V]
min
typ
12
max
unit
bit
DD
Resolution
NAD
AN0(P60)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
to AN7(P67),
AN8(P70)
Absolute accuracy
Conversion time
ETAD
(Note 6-1)
16
LSB
μs
TCAD12
VAIN
Conversion time calculated
102
to AN12(P74)
Analog input
voltage range
Analog port
input current
3.0 to 3.6
V
V
CPU
1
V
SS
DD
IAINH
IAINL
VAIN=V CPU
DD
3.0 to 3.6
3.0 to 3.6
μA
VAIN=V
SS
-1
Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC
2. 8-bit AD Conversion Mode
Specification
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
V
CPU[V]
min
typ
8
max
unit
bit
DD
Resolution
NAD
AN0(P60)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
to AN7(P67),
AN8(P70)
Absolute accuracy
Conversion time
ETAD
TCAD8
VAIN
(Note 6-1)
1.5
LSB
μs
Conversion time calculated
32
to AN12(P74)
Analog input
voltage range
Analog port
input current
3.0 to 3.6
V
V
CPU
1
V
SS
DD
IAINH
IAINL
VAIN=V CPU
DD
3.0 to 3.6
3.0 to 3.6
μA
VAIN=V
SS
-1
Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC
Note 6-1: The quantization error ( 1/2LSB) is excluded from the absolute accuracy.
Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital value against the analog input value is loaded in the result register.
The conversion time is twice the normal value when one of the following conditions occurs:
• The first AD conversion is executed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD
conversion mode.
No.A1853-24/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
V
[V]
min
typ max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
CPU
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (12MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (8MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (4MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
• FmX’tal=0kHz (oscillation stopped)
• System clock set to internal RC oscillation
• 1/1 frequency division mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
HALT mode
DD
=V PORT1
DD
=V PORT2
DD
=V PLL
DD
3.0 to 3.6
3.0 to 3.6
10
15
(Note 7-1)
IDDOP(2)
IDDOP(3)
8
12
mA
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
6
3.5
35
9
5
IDDOP(4)
IDDOP(5)
150
μA
HALT mode
consumption
current
IDDHALT(1)
IDDHALT(2)
IDDHALT(3)
V
CPU
DD
=V PORT1
DD
=V PORT2
DD
=V PLL
DD
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (12MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
HALT mode
3.0 to 3.6
3.0 to 3.6
3.5
2.5
5
4
(Note 7-1)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (8MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
HALT mode
mA
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to VCO (4MHz)
• Internal RC oscillation stopped
• 1/1 frequency division mode
HALT mode
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
1.5
0.2
15
3
1
IDDHALT(4)
IDDHALT(5)
• FmX’tal=0kHz (oscillation stopped)
• System clock set to internal RC oscillation
• 1/1 frequency division mode
HALT mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
HOLD mode
100
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
V
V
CPU
CPU
DD
μA
3.0 to 3.6
3.0 to 3.6
1
30
50
HOLDX mode
consumption
current
HOLDX mode
DD
• FmX’tal=32.768kHz crystal oscillation mode
15
Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal
pull-up resistors.
No.A1853-25/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
V
CPU[V]
min
typ max
unit
mA
DD
Onboard
programming
current
I
FW(1)
V
CPU
• Microcontroller erase consumption
current is excluded.
DD
DD
3.0 to 3.6
10
20
Onboard
programming
time
tFW(1)
tFW(2)
• 512-byte erase operation
3.0 to 3.6
3.0 to 3.6
20
40
30
60
ms
• 2-byte programming operation
μs
No.A1853-26/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Power Pin Treatment Condition 1 (V CPU, V 1)
DD SS
Connect capacitors that meet the following conditions between the V 1 and V 1 pins:
DD SS
• Connect among the V CPU and V 1 pins and the capacitors C1 and C2 with the shortest possible lead wires,
DD SS
of the same length (L1=L1’, L2=L2’) wherever possible.
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
• The capacitance of C2 should be approximately 0.1μF or larger.
• Please mount a suitable capacitor about C1.
• The V CPU and V 1 traces must be thicker than the other traces.
DD SS
L2
L1
V
V
CPU
DD
C2
C1
1
SS
L1’
L2’
Figure 4
Power Pin Treatment Condition 2 (V PORT1 to 2, V 2 to 3)
DD SS
Connect capacitors that meet the following conditions between the V PORT1 to V 2 and V PORT2 to V
DD SS DD
pins:
3
SS
• Connect among the V PORT1 to 2 and V 2 to 3 pins and the capacitor C3 with the shortest possible lead wires,
DD
SS
of the same length (L3=L3’) wherever possible.
• The capacitance of C3 should be approximately 0.1μF or larger.
• The V PORT1 to 2 and V 2 to 3 traces must be thicker than the other traces.
DD SS
L3
V
V
PORT1/
DD
PORT2
DD
C3
V
V
2/
3
SS
SS
L3’
Figure 5
No.A1853-27/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Power Pin Treatment Condition 3 (V PLL, V 4)
DD SS
Connect capacitors that meet the following conditions between the V PLL and V 4 pins:
DD SS
• Connect among the V PLL and V 4 pins and the capacitors C4 and C5 with the shortest possible lead wires,
DD SS
of the same length (L4=L4’, L5=L5’) wherever possible.
• Connect a large-capacity capacitor C4 and a small-capacity capacitor C5 in parallel.
• The capacitance of C4 should be approximately 10μF.
• The capacitance of C5 should be approximately 0.1μF.
• The V PLL and V 4 traces must be thicker than the other traces.
DD SS
L5
L4
V
V
PLL
DD
C5
C4
4
SS
L4’
L5’
Figure 6
Power Pin Treatment Condition 4 (VREG, V 1)
SS
Connect capacitors that meet the following conditions between the VREG and V 1 pins:
SS
• Connect among the VREG and V 1 pins and the capacitors C6 with the shortest possible lead wires,
SS
of the same length (L6=L6’) wherever possible.
• The capacitance of C6 should be approximately 1μF.
• The VREG and V 1 traces must be thicker than the other traces.
SS
L6
VREG
C6
V
1
SS
L6’
Figure 7
No.A1853-28/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
LPF Pin Treatment Condition (LPFO)
Insert a resistor and capacitors that meet the following conditions between the LPFO and V 4 pins.
SS
R1 = 3.3kΩ
C7 = 0.068μF
C8 = 0.0039μF
• Routing traces between the LPFO and V 4 pins and the resistor and capacitors, and between R1 and C7 must be as
SS
short as possible.
* After the PLL circuit is activated, 50ms or more is required for stabilizing oscillation.
LPFO
R1
C8
C7
V
4
SS
Figure 8
TEST Pin Treatment Condition (TEST)
Insert a resistor that meets the following condition between the TEST and V 1 pins.
SS
R
TEST
= 100kΩ
TEST
R
TEST
V
1
SS
Figure 9
No.A1853-29/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Example of Crystal Oscillator Circuit Characteristics
Given below are the characteristics of a sample crystal oscillator circuit that were measured using a SANYO-designated
oscillation characteristics evaluation board and external components with circuit constant values with which the
oscillator vendor confirmed normal and stable oscillation.
Table 1 Example of Crystal Oscillator Circuit Characteristics with a Crystal Resonator
Operating
Voltage
Range
[V]
Oscillator
Stabilization Time
tmsX'tal(typ)
[s]
Circuit Constant
Nominal
Vendor
Name
Oscillator Name
Remarks
C1
C2
Rd
Frequency
[pF]
[pF]
[Ω]
TFX-03
V
CPU=
DD
32.768kHz
RIVER ELETEC
15
15
680k
(CL=12.5pF)
3.0 to 3.6
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the XT oscillator circuit is executed plus the time interval that is required for the oscillation to get
stabilized after the HOLD mode is released (see Figure 11).
Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the
oscillation characteristics are affected by their trace pattern.
XT1
XT2
Rd
C1
C2
X’tal
Figure 10 XT Oscillator Circuit
No.A1853-30/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Power V PORT
DD
*1
V
CPU
DD
Operating V
lower limit
0V
DD
Power V CPU
DD
Reset time
tPIL(2)
RESB
Internal RC
oscillation
tmsX'tal
XT1, XT2
Initialization instruction
Unpredictable
Reset
User instruction execution
Operating
mode
execution
Figure 11 Reset Time and Oscillation Stabilization Time
*1: The voltage when the power is turned on and off must stand in the following relationship: V PORT ≥ V CPU.
DD DD
It should be noted that, while the V PORT power is supplied, the I/O pin remains in an undefined state until the
DD
V
CPU voltage reaches the allowable operation range.
DD
HOLD
release
No HOLD release signal
HOLD release signal valid
Interrupt operation
Internal RC
oscillation
tmsX'tal
XT1, XT2
State
HOLD
HALT
Instruction execution
Figure 12 HOLD Release and Oscillation Stabilization Time
No.A1853-31/32
LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Reset Pin Treatment Condition (RESB)
V
CPU
DD
(Note)
When the power is turned on, the RESB pin must be set to the
low level.
(A reset period of 50μs or longer is required after the power has
stabilized.)
R
C
RES
RESB
RES
Recommended value
R
RES
C
RES
: 100kΩ
: 0.033μF
Figure 13 Reset Circuit
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of December, 2010. Specifications and information herein are subject
to change without notice.
PS No.A1853-32/32
相关型号：
©2020 ICPDF网 联系我们和版权申明