S1C62M20F [SEIKO]
4-BIT, MROM, 0.032MHz, MICROCONTROLLER, PQFP80, PLASTIC, QFP5-80;
| 型号： | S1C62M20F |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | 4-BIT, MROM, 0.032MHz, MICROCONTROLLER, PQFP80, PLASTIC, QFP5-80 时钟 ISM频段 外围集成电路 |
| 文件： | 总105页 (文件大小：855K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MF1007 03
-
CMOS 4 BIT SINGLE CHIP MICROCOMPUTER
S1C62M20
Technical Manual
S1C62M20 Technical Hardware
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001 All rights reserved.
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
Devices
S1
C
60N01
F
0A01
00
00
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1
C
60R08 D1
1
Packing specification
2
Version (1: Version 1
)
1
)
Tool type (D1: Development Tool
Corresponding model number (60R08: for S1C60R08)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
2: Actual versions are not written in the manuals.
Comparison table between new and previous number
S1C60 Family processors
S1C62 Family processors
Previous No.
E0C6001
E0C6002
E0C6003
E0C6004
E0C6005
E0C6006
E0C6007
E0C6008
E0C6009
E0C6011
E0C6013
E0C6014
E0C60R08
New No.
S1C60N01
S1C60N02
S1C60N03
S1C60N04
S1C60N05
S1C60N06
S1C60N07
S1C60N08
S1C60N09
S1C60N11
S1C60N13
S1C60140
S1C60R08
Previous No.
E0C621A
E0C6215
E0C621C
E0C6S27
E0C6S37
E0C623A
E0C623E
E0C6S32
E0C6233
E0C6235
E0C623B
E0C6244
E0C624A
E0C6S46
New No.
S1C621A0
S1C62150
S1C621C0
S1C6S2N7
S1C6S3N7
S1C6N3A0
S1C6N3E0
S1C6S3N2
S1C62N33
S1C62N35
S1C6N3B0
S1C62440
S1C624A0
S1C6S460
Previous No.
E0C6247
E0C6248
E0C6S48
E0C624C
E0C6251
E0C6256
E0C6292
E0C6262
E0C6266
E0C6274
E0C6281
E0C6282
E0C62M2
E0C62T3
New No.
S1C62470
S1C62480
S1C6S480
S1C624C0
S1C62N51
S1C62560
S1C62920
S1C62N62
S1C62660
S1C62740
S1C62N81
S1C62N82
S1C62M20
S1C62T30
Comparison table between new and previous number of development tools
Development tools for the S1C60/62 Family
Previous No.
ASM62
New No.
Previous No.
DEV6262
DEV6266
DEV6274
DEV6292
DEV62M2
DEV6233
DEV6235
DEV6251
DEV6256
DEV6281
DEV6282
DEV6S27
DEV6S32
DEV6S37
EVA6008
EVA6011
EVA621AR
EVA621C
EVA6237
EVA623A
New No.
Previous No.
EVA623B
EVA623E
EVA6247
EVA6248
EVA6251R
EVA6256
EVA6262
EVA6266
EVA6274
EVA6281
EVA6282
EVA62M1
EVA62T3
EVA6S27
EVA6S32R
ICE62R
New No.
S5U1C62000A
S5U1C60N01D
S5U1C60N02D
S5U1C60N03D
S5U1C60N04D
S5U1C60N05D
S5U1C60N06D
S5U1C60N07D
S5U1C60N08D
S5U1C60N09D
S5U1C60N11D
S5U1C60R08D
S5U1C621A0D
S5U1C621C0D
S5U1C623B0D
S5U1C62440D
S5U1C624A0D
S5U1C624C0D
S5U1C62480D
S5U1C62470D
S5U1C62620D
S5U1C62660D
S5U1C62740D
S5U1C62920D
S5U1C62M20D
S5U1C62N33D
S5U1C62N35D
S5U1C62N51D
S5U1C62560D
S5U1C62N81D
S5U1C62N82D
S5U1C6S2N7D
S5U1C6S3N2D
S5U1C6S3N7D
S5U1C60N08E
S5U1C60N11E
S5U1C621A0E2
S5U1C621C0E
S5U1C62N37E
S5U1C623A0E
S5U1C623B0E
S5U1C623E0E
S5U1C62470E
S5U1C62480E
S5U1C62N51E1
S5U1C62N56E
S5U1C62620E
S5U1C62660E
S5U1C62740E
S5U1C62N81E
S5U1C62N82E
S5U1C62M10E
S5U1C62T30E
S5U1C6S2N7E
S5U1C6S3N2E2
S5U1C62000H
S5U1C60N03K
S5U1C60N04K
S5U1C60N07K
DEV6001
DEV6002
DEV6003
DEV6004
DEV6005
DEV6006
DEV6007
DEV6008
DEV6009
DEV6011
DEV60R08
DEV621A
DEV621C
DEV623B
DEV6244
DEV624A
DEV624C
DEV6248
DEV6247
KIT6003
KIT6004
KIT6007
CONTENTS
CONTENTS
CHAPTER 1 OVERVIEW _______________________________________________ 1
1.1 Features ........................................................................................................ 1
1.2 Block Diagram .............................................................................................. 2
1.3 Pin Layout Diagram...................................................................................... 3
1.4 Pin Description ............................................................................................. 5
CHAPTER 2 POWER SUPPLY AND INITIAL RESET ____________________________ 6
2.1 Power Supply ................................................................................................ 6
2.1.1 Boosted voltage <VSS2> for analog system ................................................ 7
2.1.2 Voltage <VL1, VL2 and VL3> for LCD driving ........................................... 7
2.1.3 Reference voltage <VRF1, VRF2> for A/D converter .................................. 7
2.2 Initial Reset ................................................................................................... 8
2.2.1 Reset terminal (RESET) .............................................................................. 8
2.2.2 Watchdog timer ........................................................................................... 9
2.2.3 Internal register at initial resetting ............................................................ 9
2.3 Test Terminal (TEST) .................................................................................... 9
CHAPTER 3 CPU, ROM, RAM________________________________________ 10
3.1 CPU.............................................................................................................. 10
3.2 ROM ............................................................................................................. 10
3.3 RAM ............................................................................................................. 10
CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION _________________________ 11
4.1 Memory Map ................................................................................................ 11
4.2 Resetting Watchdog Timer ........................................................................... 16
4.2.1 Configuration of watchdog timer ............................................................... 16
4.2.2 Control of watchdog timer ......................................................................... 16
4.2.3 Programming note ..................................................................................... 17
4.3 Oscillation Circuit........................................................................................ 18
4.3.1 Configuration of oscillation circuit ........................................................... 18
4.3.2 Crystal oscillation circuit .......................................................................... 18
4.3.3 Clock frequency and instruction execution time ........................................ 19
4.4 Input Ports (K00–K03, K10–K13) ............................................................... 20
4.4.1 Configuration of input ports ...................................................................... 20
4.4.2 Interrupt function ....................................................................................... 20
4.4.3 Mask option................................................................................................ 21
4.4.4 Control of input ports ................................................................................ 22
4.4.5 Programming notes.................................................................................... 23
4.5 Output Ports (R00–R03) .............................................................................. 24
4.5.1 Configuration of output ports .................................................................... 24
4.5.2 Mask option................................................................................................ 24
4.5.3 Control of output ports .............................................................................. 24
4.6 Buzzer Output Ports (BZ, BZ) ...................................................................... 25
4.6.1 Configuration of buzzer output ports ......................................................... 25
4.6.2 Buzzer output ............................................................................................. 25
4.6.3 Control of buzzer output ............................................................................ 27
S1C62M20 TECHNICAL MANUAL
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i
CONTENTS
4.7 I/O Ports (P00–P03) .................................................................................... 28
4.7.1 Configuration of I/O ports ......................................................................... 28
4.7.2 I/O control registers and input/output mode ............................................. 28
4.7.3 Pull down during input mode..................................................................... 28
4.7.4 Mask option................................................................................................ 29
4.7.5 Control of I/O ports ................................................................................... 29
4.7.6 Programming note ..................................................................................... 30
4.8 LCD Driver (COM0–COM3, SEG0–SEG15) .............................................. 31
4.8.1 Configuration of LCD driver ..................................................................... 31
4.8.2 LCD display control and duty switching ................................................... 34
4.8.3 Mask option (segment allocation).............................................................. 35
4.8.4 Control of LCD driver ............................................................................... 36
4.8.5 Programming notes.................................................................................... 37
4.9 Clock Timer .................................................................................................. 38
4.9.1 Configuration of clock timer ...................................................................... 38
4.9.2 Data reading and hold function ................................................................. 38
4.9.3 Interrupt function ....................................................................................... 39
4.9.4 Control of clock timer ................................................................................ 40
4.9.5 Programming notes.................................................................................... 41
4.10 Serial Interface (SIN, SOUT, SCLK, SRDY) ................................................ 42
4.10.1 Configuration of serial interface ............................................................. 42
4.10.2 Master mode and slave mode of serial interface ..................................... 43
4.10.3 Data input/output and interrupt function................................................. 44
4.10.4 Mask option.............................................................................................. 45
4.10.5 Control of serial interface........................................................................ 46
4.10.6 Programming notes.................................................................................. 48
4.11 A/D Converter .............................................................................................. 49
4.11.1 Configuration of A/D converter ............................................................... 49
4.11.2 Power supply and reference voltage generator for A/D converter ......... 50
4.11.3 Clock for A/D converter ........................................................................... 51
4.11.4 A/D converter control circuit (Dual slope A/D controller) ..................... 51
4.11.5 Operation of dual slope type A/D converter ............................................ 51
4.11.6 A/D conversion and interrupt .................................................................. 55
4.11.7 Control of A/D converter ......................................................................... 57
4.11.8 Programming notes.................................................................................. 59
4.12 Measurement Circuit and Measurement Procedure .................................... 60
4.12.1 Sort of measurement ................................................................................ 60
4.12.2 General AMP ........................................................................................... 62
4.12.3 Voltage measurement .............................................................................. 62
4.12.4 Current measurement .............................................................................. 63
4.12.5 Resistance measurement .......................................................................... 64
4.12.6 Continuity check ...................................................................................... 65
4.12.7 ADPT (adapter) ....................................................................................... 66
4.12.8 Control method ........................................................................................ 67
4.12.9 Programming notes.................................................................................. 68
4.13 VSS2 Booster ................................................................................................. 69
4.13.1 Configuration of VSS2 booster.................................................................. 69
4.13.2 Control of VSS2 booster ............................................................................ 69
4.13.3 Programming notes.................................................................................. 70
4.14 SVD (Supply Voltage Detection) Circuit ..................................................... 71
4.14.1 Configuration of SVD circuit ................................................................... 71
4.14.2 Operation of SVD circuit ......................................................................... 71
4.14.3 Control of SVD circuit ............................................................................. 71
4.14.4 Programming note ................................................................................... 72
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S1C62M20 TECHNICAL MANUAL
CONTENTS
4.15 Interrupt and HALT/SLEEP ......................................................................... 73
4.15.1 Interrupt factor ........................................................................................ 75
4.15.2 Interrupt mask .......................................................................................... 75
4.15.3 Interrupt vector ........................................................................................ 75
4.15.4 Control of interrupt .................................................................................. 76
4.15.5 Programming notes.................................................................................. 77
CHAPTER 5 SUMMARY OF NOTES _______________________________________ 78
5.1 Notes for Low Current Consumption ........................................................... 78
5.2 Summary of Notes by Function .................................................................... 79
CHAPTER 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS _____________________ 82
CHAPTER 7 ELECTRICAL CHARACTERISTICS ________________________________ 83
7.1 Absolute Maximum Rating ........................................................................... 83
7.2 Recommended Operating Conditions .......................................................... 83
7.3 DC Characteristics ...................................................................................... 84
7.4 Analog Characteristics and Current Consumption ..................................... 85
7.5 Oscillation Characteristics .......................................................................... 86
CHAPTER 8 PACKAGE ________________________________________________ 87
8.1 Plastic Package ............................................................................................ 87
8.2 Ceramic Package for Test Samples ............................................................. 89
CHAPTER 9 PAD LAYOUT _____________________________________________ 90
9.1 Diagram of Pad Layout................................................................................ 90
9.2 Pad Coordinates .......................................................................................... 91
REFERENCE DATA __________________________________________________ 92
1.
Electrical Specification ................................................................................ 92
1.1 DC Voltmeter ............................................................................................. 92
1.2 AC Voltmeter .............................................................................................. 92
1.3 DC Ammeter............................................................................................... 92
1.4 AC Ammeter ............................................................................................... 93
1.5 Resistance................................................................................................... 93
1.6 Continuity check......................................................................................... 93
2.
Notes............................................................................................................. 94
2.1 40 MΩ range during resistance measurement ........................................... 94
2.2 Frequency characteristic of AC voltage .................................................... 94
2.3 Reference voltage setting ........................................................................... 94
2.4 Connection of SGND .................................................................................. 94
S1C62M20 TECHNICAL MANUAL
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iii
CHAPTER 1: OVERVIEW
CHAPTER 1 OVERVIEW
The S1C62M20 is a CMOS 4-bit single-chip microcomputer made up of the 4-bit core CPU S1C6200A, ROM
(1,536 words, 12 bits to a word), RAM (128 words, 4 bits to a word), dual slope type A/ D converter,
attenuator circuit for various measurement modes, LCD driver, serial interface, and other circuits. It is
especially suitable for measurement and LCD display systems such as a digital multimeter.
1.1 Features
CMOS LSI 4-bit parallel processing
Clock ........................................ 32.768 kHz (Typ.)
Instruction set........................... 100 types
Instruction execution time ........ 153 µsec, 214 µsec, 366 µsec
ROM capacity........................... 1,536 words × 12 bits
RAM capacity ........................... 128 words × 4 bits
A/D converter ........................... Dual slope type
Resolution : Conversion time (2 stages)
4,370 counts : 400 msec
A/D conversion precision: ±0.1% (operating temperature range: 20°C to 40°C)
441 counts : 100 msec (High speed mode)
3 integral resistors can be connected
Current, voltage and resistance can be measured
AC voltage/AC current can be measured using an external rectifier circuit
Continuity check mode built-in (measurement value can be displayed)
Reference voltage generation circuit built-in
Input port .................................. 8 bits (pull down resistors can be supplemented by mask option)
Output port ............................... 4 bits
Buzzer output ........................... 2 ports (BZ, BZ) [1 system]
I/O port ..................................... 4 bits
Serial interface ......................... 1 port for data input
1 port for data output
These ports can be switched to general I/O port
1 port for clock input/output
LCD driver ................................ 16 segments × 3 or 4 commons (can be switched using software)
LCD drive voltage generation circuit built-in (VL1, VL2, VL3)
Compatible with 3 V LCD panel
Timer ........................................ Built-in
Watchdog timer ........................ Built-in
SVD circuit ............................... 2.3 ± 0.15 V
(supply voltage detection)
External interrupt...................... Input port interrupt:
2 systems
Internal interrupt ....................... A/D interrupt:
1 system
1 system
Timer interrupt:
Serial interface interrupt: 1 system
Supply voltage.......................... 3 V (2.15 V to 3.5 V)
Current consumption (Typ.) ..... During HALT:
During A/D operation:
3 µA
(3 V)
0.9 mA (3 V, in DC measurement)
1.1 mA (3 V, in AC measurement)
Package ................................... QFP5-80pin (plastic/ceramic), QFP14-80pin (plastic) or chip
S1C62M20 TECHNICAL MANUAL
EPSON
1
CHAPTER 1: OVERVIEW
1.2 Block Diagram
S1C62M20 BLOCK DIAGRAM
ROM
1,536 × 12
Core CPU S1C6200A
OSC1
OSC2
RESET
TEST
System Reset
Control
OSC and SLEEP
COM0~
COM3
SEG0~
SEG15
LCD Driver
Interrupt Control
16 × 4
V
DD
RAM
128 × 4
V
L1
L2
L3
V
Logic Power
Control
and SVD
V
V
SSD
C1
C2
Timer
V
SS2
V
DDA
K00~K03
K10~K13
V
V
V
RF1
RF2
ADJ
SSA
CH
CL
Input Port
Reference
Voltage
Control
V
R00~R03
BZ
BZ
Output Port
and Buzzer
SGND
BUF1
BUF2
BUF3
CAZ
CI
P00~P03
I/O Port
A/D Converter
OP-AMP
ADI
ADO
Serial Interface
AVX1
AVX2
CO
VI
R6
R5/VI2
R4/VI3
R3/VI4
R2/VI5
R1
IIL
Analog Switch Circuit
IIH
CFI
OVX
OVSG
Fig. 1.2.1 Block diagram
2
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S1C62M20 TECHNICAL MANUAL
CHAPTER 1: OVERVIEW
1.3 Pin Layout Diagram
QFP5-80pin
64
41
65
40
INDEX
25
80
1
24
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1
2
3
4
5
6
7
8
9
SEG15
COM0
COM1
COM2
COM3
VL1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VRF1
VRF2
CH
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
OVSG
R1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
BZ
P00/SIN
P01/SOUT
P02/SCLK
P03/SRDY
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
R2/VI5
R3/VI4
R4/VI3
R5/VI2
R6
K00
K01
K02
K03
K10
K11
K12
K13
R00
R01
R02
R03
CL
ADI
ADO
AVX1
AVX2
CO
CAZ
CI
BUF1
BUF2
BUF3
IIL
IIH
CFI
SGND
VI
OVX
VL2
VL3
VDD
10 OSC1
11 OSC2
12 RESET
13 TEST
14
15 C1
16 C2
17
18
19
20
VSSD
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
VSS2
VDDA
VSSA
VADJ
BZ
Fig. 1.3.1 Pin layout diagram (QFP5-80pin)
S1C62M20 TECHNICAL MANUAL
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3
CHAPTER 1: OVERVIEW
QFP14-80pin
60
41
61
40
INDEX
80
21
1
20
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1
2
3
4
5
6
7
8
9
COM2
COM3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CL
ADI
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
R3/VI4
R4/VI3
R5/VI2
R6
K00
K01
K02
K03
K10
K11
K12
K13
R00
R01
R02
R03
BZ
BZ
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P02/SCLK
P03/SRDY
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
VL1
VL2
VL3
VDD
ADO
AVX1
AVX2
CO
CAZ
CI
BUF1
BUF2
BUF3
IIL
OSC1
OSC2
RESET
10 TEST
11
12 C1
13 C2
14
15
16
17
18
19
SEG7
SEG8
SEG9
VSSD
IIH
CFI
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
COM1
V
V
V
V
V
V
SS2
DDA
SSA
ADJ
RF1
RF2
SGND
VI
OVX
OVSG
R1
P00/SIN
P01/SOUT
20 CH
R2/VI5
Fig. 1.3.2 Pin layout diagram (QFP14-80pin)
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S1C62M20 TECHNICAL MANUAL
CHAPTER 1: OVERVIEW
1.4 Pin Description
Table 1.4.1 Pin description
Pin name Pin No. (QFP5) Pin No. (QFP14) In/Out
Function
V
V
V
V
V
DD
9
18
6
15
(I) Digital system power supply pin (+)
DDA
SSD
SSA
SS2
(I) Analog system power supply pin (+)
14
11
(I) Digital system power supply pin (–)
19
16
(I) Analog system GND pin (same voltage with VSSD
)
17
14
(O) Analog system power supply pin (boosted voltage)
C1, C2
15, 16
10
12, 13
7
O
I
Booster capacitor connecting pins for analog system power supply (VSS2)
OSC1
Crystal oscillation input pin: 32.768 kHz
Crystal oscillation output pin
Input pins
OSC2
11
8
O
I
K00~K13
R00~R03
BZ, BZ
P00~P03
48~55
56~59
60, 61
62~65
6~8
2~5
66~80, 1
20
45~52
53~56
57, 58
59~62
3~5
79, 80, 1, 2
63~78
17
O
O
Output pins
Buzzer signal output pins
I/O I/O pins
VL1~VL3
O
O
O
–
–
–
I
LCD system voltage output pin
COM0~3
SEG0~15
LCD common output pins (1/3, 1/4 duty, programmable)
LCD segment output pin (DC output may be selected by mask option)
Reference voltage adjustment pin
VADJ
VRF1
VRF2
21
18
Reference voltage output pin
22
19
Reference voltage output pin
ADI
25
22
OP-AMP inverted input pin for AC-DC conversion
OP-AMP output pin for AC-DC conversion
AC-DC converted voltage input pin
ADO
AVX1
AVX2
IIL, IIH
VI
26
23
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
27
24
28
25
AC-DC converted voltage input pin
35, 36
39
32, 33
36
Input pins for current measurement
Input pin for voltage measurement
R1
42
39
Reference resistor connecting pin (100 Ω)
Reference resistor connecting pin (1 kΩ)
Reference resistor connecting pin (10 kΩ)
Reference resistor connecting pin (101 kΩ)
Reference resistor connecting pin (1.11 MΩ)
Reference resistor connecting pin (10 MΩ)
Reference resistor voltage input pin for resistance measurement
Reference resistor voltage input pin for resistance measurement
GND for measurement
R2/VI5
R3/VI4
R4/VI3
R5/VI2
R6
43
40
44
41
45
42
46
43
47
44
OVX
OVSG
SGND
CO
40
37
41
38
38
35
29
26
Dummy pad
CAZ
30
27
Capacitor connecting pin for offset voltage zero adjustment
Integral capacitor connecting pin
CI
31
28
BUF1~3
CFI
32~34
37
29~31
34
Buffer AMP output, integral resistor connecting pin
Noise rejection filter connecting pin
CH
23
20
Capacitor connecting pin for reference voltage control
Capacitor connecting pin for reference voltage control
Testing input pin
CL
24
21
TEST
RESET
13
10
12
9
I
Initial reset input pin
S1C62M20 TECHNICAL MANUAL
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5
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2 POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
With a single external power supply (3 V *1) supplied to VDD/ VDDA through VSSD/ VSSA, the S1C62M20
generates the necessary internal voltage with the regulated voltage circuit (<VL1, VL2, VL3> for LCD
driving), the voltage booster (<VSS2> for analog system) and the reference voltage generator (<VRF1> for
A/ D converter).
Figure 2.1.1 shows the configuration of power supply.
*1 Supply voltage: 2.15 to 3.5 V
Note: • External loads cannot be driven by the regulated voltage and voltage booster circuit’s output
voltage.
• See Chapter 7, "ELECTRICAL CHARACTERISTICS" for voltage values.
VDD
V
DDA
CH
CL
V
V
V
L1
L2
L3
V
REF
Reference voltage
control
LCD voltage
generator
V
RF1
RF2
ADJ
V
COM0~COM3
SEG0~SEG15
VMES
Reference voltage
generator
LCD circuit
V
VSSD
V
SSA
C1
C2
A/D converter
and
VSS2 booster
Analog switch
VSS2
VSS2
Fig. 2.1.1 Configuration of power supply
6
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S1C62M20 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.1 Boosted voltage <VSS2> for analog system
Making VDD the standard (GND), the S1C62M20 voltage booster doubles the supply voltage input from the
VDD–VSSD terminals to generate VSS2.
VSS2 is used to operate the analog circuits (A/ D converter, analog switch circuit, reference voltage genera-
tor and LCD power generator) in the S1C62M20. This voltage can be turned ON and OFF by programming.
The VSS2 booster circuit also supplies the clock to the A/ D converter and the LCD driver after dividing the
clock (32.768 kHz) from the crystal oscillation circuit. Therefore, the VSS2 booster should be turned ON
before starting the A/ D converter and/ or the LCD driver operations. See Section 4.13, "VSS2 Booster" for
details.
Figure 2.1.1.1 shows the configuration of the VSS2 circuit.
OSC1
10.923 kHz
X'tal
32.768 kHz
LCD circuit
OSC1 circuit
OSC2
32.768 kHz
LCD power
generator
V
SS2 divider
A/D converter
and
21.845 kHz
Switch circuit
V
SS2 booster circuit
Booster
C2
C1
V
DD
Reference voltage
generator
V
SS2
Fig. 2.1.1.1 Configuration of VSS2 circuit
2.1.2 Voltage <VL1, VL2 and VL3> for LCD driving
VL1, VL2 and VL3 are the voltages for LCD driving, and are generated by the internal LCD power generator
with VDD as the standard (GND). The LCD power generator operates with the VSS2 voltage as the power
supply, and can be turned ON and OFF by programming.
See Chapter 7, "ELECTRICAL CHARACTERISTICS" for the output voltage values.
2.1.3 Reference voltage <VRF1, VRF2> for A/D converter
VRF1 and VRF2 are reference voltage for the A/ D converter. The VRF1 voltage is generated by the reference
voltage generator in the S1C62M20, and the VRF2 voltage is generated by dividing using resisters outside of
the S1C62M20.
The reference voltage generator automatically starts to operate and outputs VRF1 and VRF2 by turning the
A/ D converter ON.
See Section 4.11, "A/ D Converter" for details of the circuit configuration and the operation.
S1C62M20 TECHNICAL MANUAL
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7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C62M20 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset using the RESET terminal
(2) Initial reset by the watchdog timer
Be sure to use reset function (1) when turning the power ON and be sure to initialize securely. In normal
operation, the circuits may be initialized by any of the above two types.
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
OSC1
circuit
Watchdog
timer
Timer
OSC2
Initial
reset
RESET
V
SSD
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a high level. After that, when the
reset terminal goes low, the initial reset is released. However, the clock is not supplied to the CPU until the
1 Hz signal from the timer goes high after an initial reset is released. When the 1 Hz signal goes high, the
CPU clock is supplied and the CPU starts to operate.
Maintain the reset terminal at a high level at least 2.0 msec to securely perform the initial reset after turning
the power ON.
Figure 2.2.1.1 shows the initial reset timing with the power ON.
VDD = GND
V
SSD
2.15 V
0.1VSS
2.0 msec
0.4VSS
RESET
1 Hz signal
CPU clock
Fig. 2.2.1.1 Initial reset at power ON
8
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S1C62M20 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.2 Watchdog timer
If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial
reset signal. See Section 4.2, "Resetting Watchdog Timer" for details.
However, do not perform an initial reset when turning the power ON by this function.
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in the table below.
Table 2.2.3.1 Initial values
CPU core
Name
Program counter step
Program counter page
New page pointer
Stack pointer
Symbol Number of bits Setting value
PCS
PCP
NPP
SP
IX
IY
RP
A
8
4
4
8
8
8
4
4
4
1
1
1
1
00H
1H
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
Index register IX
Index register IY
Register pointer
General-purpose register A
General-purpose register B
Interrupt flag
B
I
Decimal flag
D
0
Zero flag
Z
Undefined
Undefined
Carry flag
C
Peripheral circuits
Name
RAM
Number of bits Setting value
4
4
Undefined
Undefined
*1
Display memory
Other peripheral circuits
—
*1 See Section 4.1, "Memory Map".
2.3 Test Terminal (TEST)
This is the terminal that is used at the time of the factory inspection of the IC. During normal operation,
connect the TEST terminal to VSSD/ VSSA.
S1C62M20 TECHNICAL MANUAL
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9
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3 CPU, ROM, RAM
3.1 CPU
The S1C62M20 employs the 4-bit core CPU S1C6200A for the CPU, so that register configuration, instruc-
tions and so forth are virtually identical to those in other family processors using the S1C6200A.
Refer to "S1C6200/ 6200A Core CPU Manual" for details about the S1C6200A.
Note the following points with regard to the S1C62M20:
(1) Because the ROM capacity is 1,536 words, bank bits are unnecessary and PCB and NBP are not used.
(2) RAM is set up to one page only, so the page portion (XP, YP) of the index register that specifies ad-
dresses is invalid. (The four bits of XP and YP are ignored.)
3.2 ROM
The built-in ROM, a mask ROM for storing the program, has a capacity of 1,536 steps, 12 bits each. The
program area is 6 pages (0–5), each of 256 steps (00H–FFH). After initial reset, the program beginning
address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 02H–0FH.
Program start address
Step 00H
Step 01H
Step 02H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Interrupt
vector
area
Step 0FH
Step 10H
Step FFH
12 bits
Fig. 3.2.1 ROM configuration
3.3 RAM
The RAM, a data memory storing a variety of data, has a capacity of 128 words, each of four bits. When
programming, keep the following points in mind.
(1) Part of the data memory can be used as stack area when subroutine calls and saving registers, so be
careful not to overlap the data area and stack area.
(2) Subroutine calls and interrupts take up three words of the stack area.
(3) The data memory 000H–00FH is for the register pointers (RP), and is the addressable memory register
area.
10
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S1C62M20 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4
P
ERIPHERAL
C
IRCUITS AND
O
PERATION
Peripheral circuits (timer, I/ O, and so on) of the S1C62M20 are memory mapped, and interfaced with the
CPU. Thus, all the peripheral circuits can be controlled by using the memory operation command to access
the I/ O memory in the memory map.
The following sections describe how the peripheral circuits operation.
4.1 Memory Map
Data memory of the S1C62M20 has an address space of 180 words, of which 16 words are allocated to
display memory and 36 words to I/ O memory.
Figure 4.1.1 present the overall memory maps of the S1C62M20, and Tables 4.1.1(a)–(e) the peripheral
circuits’ (I/ O space) memory maps.
Table 4.1.2 shows the A/ D converter measurement function list and Table 4.1.3 shows the A/ D converter
measurement range list.
Address
Page
Low
High
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
RAM (128 words × 4 bits)
R/W
0
Unused area
Display memory (16 words × 4 bits) W
I/O memory
Unused area
Fig. 4.1.1 Memory map
Note: Memory is not mounted in unused area within the memory map and in memory area not indicated in
this chapter. For this reason, normal operation cannot be assured for programs that have been
prepared with access to these area.
S1C62M20 TECHNICAL MANUAL
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11
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1(a) I/O memory map (C0H–CAH)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SIK03
SIK02
SIK01
SIK00
K03
Init
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
1
Enable
Enable
Enable
Enable
High
High
High
High
Enable
Enable
Enable
Enable
High
High
High
High
High
High
High
High
Output
Output
Output
Output
Output
1
0
Disable Interrupt selection register (K03)
Disable Interrupt selection register (K02)
Disable Interrupt selection register (K01)
Disable Interrupt selection register (K00)
Low
SIK03
SIK02
SIK01
SIK00
C0H
C1H
C2H
C3H
C4H
R/W
R
*2
*2
*2
*2
K03
SIK13
K13
K02
SIK12
K12
K01
SIK11
K11
K00
SIK10
K10
Low
K02
Input port (K00–K03)
Low
K01
Low
K00
Disable Interrupt selection register (K13)
Disable Interrupt selection register (K12)
Disable Interrupt selection register (K11)
Disable Interrupt selection register (K10)
Low
SIK13
SIK12
SIK11
SIK10
K13
R/W
R
*2
*2
*2
*2
Low
K12
Input port (K10–K13)
Low
K11
Low
Low
K10
R03
R03
R02
R01
R00
Low
R02
Output port (R00–R03)
Low
R01
R/W
Low
R00
Input
IOC03
IOC02
IOC01
IOC00
IOC03
IOC03
IOC02
IOC01
IOC00
PUL03
PUL02
PUL01
PUL00
PUL03
PUL03
PUL02
PUL02
PUL01
PUL00
P03
IOC03
IOC02
IOC01
IOC00
Input
I/O control register (P00–P03)
Input
R/W
(ESIF = 0)
Input
When the serial I/F is used (ESIF = 1):
P00 = SIN (in), P01 = SOUT (out),
P02 = SCLK (master: out, slave: in),
P03 = SRDY (slave: out),
Input
0
Master mode: P03 I/O control register
Slave mode: General-purpose register
C8H
C9H
CAH
1
0
1
0
General-purpose register
P03 = I/O port (master: in/out)
1
0
On
Off
Off
Off
Off
Off
0
PUL03
PUL02
PUL01
PUL00
On
Pull down control register (P00–P03)
(ESIF = 0)
On
R/W
On
When the serial I/F is used (ESIF = 1):
P00 = SIN (in), P01 = SOUT (out),
P02 = SCLK (master: out, slave: in),
P03 = SRDY (slave: out),
On
Master mode: P03 pull down control register
Slave mode: General-purpose register
Master mode: General-purpose register
Slave mode: SCKL pull down control register
General-purpose register
1
1
0
On
Off
0
P03 = I/O port (master: in/out)
1
On
Off
Low
Low
Low
Low
Low
0
SIN pull down control register
*2
*2
*2
*2
*2
*2
*2
*2
*2
High
High
High
High
High
1
P03
P02
P01
P00
P02
I/O port (P00–P03)
(ESIF = 0)
P01
R/W
P00
When the serial I/F is used (ESIF = 1):
P00 = SIN (in), P01 = SOUT (out),
P02 = SCLK (master: out, slave: in),
P03 = SRDY (slave: out),
Master mode: I/O port P03
P03
Slave mode: General-purpose register
P03
1
0
P02
1
0
General-purpose register
P01
P03 = I/O port (master: in/out)
1
0
P00
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*3 Undefined
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S1C62M20 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1(b) I/O memory map (CCH–CFH)
Register
Address
CCH
Comment
*1
D3
0
D2
D1
D0
Name
Init
–
1
0
*5
*2
*2
*2
Unused
0
0
0
SCTRG
ESIF
*5
Unused
–
Trigger
Run
–
Serial interface clock trigger (writing)
Serial interface clock status (reading)
SCTRG(W)
SCTRG(R)
ESIF
–
Stop
0
R
R/W
SIF port I/O port P0 port function selection
LSB first MSB first Serial data input/output permutation
Serial interface clock phase selection
Serial interface clock mode selection
0: Slave, 1: CLK/2, 2: CLK, 3: CLK
MSB
0
SDP
0
SDP
SD3
SD7
SCPS
SD2
SCS1
SD1
SCS0
SD0
SCPS
SCS1
SCS0
SD3
0
CDH
CEH
CFH
0
R/W
R/W
R/W
0
*2
*2
*2
*2
*2
*2
*2
*2
–
SD2
–
Serial interface data (low-order 4 bits)
SD1
–
LSB
SD0
–
MSB
SD7
–
SD6
SD5
SD4
SD6
–
Serial interface data (high-order 4 bits)
LSB
SD5
–
SD4
–
Table 4.1.1(c) I/O memory map (D0H–D6H)
Register
Address
D0H
Comment
*1
D3
0
D2
D1
D0
R
Name
Init
–
–
0
0
–
–
0
0
–
–
–
–
–
–
–
–
–
–
–
–
1
0
*5
*2
*2
Unused
Unused
0
0
BZFQ
*5
0
BZFQ
R
2 kHz
1
4 kHz
0
Buzzer signal frequency selection
1 bit general-purpose register
Unused
R
R/W
R/W
*5
*2
*2
0
0
R
0
BSHOT
BZFNC
BZON
*5
BSHOT
One-shot
–
One-shot buzzer signal (31 msec) output trigger
D1H
D4H
D5H
D6H
Intermittent Continuous Continuous/intermittent output selection
BZFNC
BZON
W
0
On
Off
Buzzer signal output control
Unused
*5
*2
*2
*2
*2
*3
*3
*3
*3
*3
*3
*3
*3
0
0
WDRST TMRST
W
*5
*5
Unused
Reset
Reset
–
–
Watchdog timer reset
Clock timer and watchdog timer reset
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
WDRST
R
*5
TMRST
TM3
TM2
TM1
TM0
TM7
TM6
TM5
TM4
TM3
TM7
TM2
TM6
TM1
TM0
R
R
TM5
TM4
S1C62M20 TECHNICAL MANUAL
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13
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1(d) I/O memory map (E0H–EBH)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
Init
–
–
–
0
0
–
0
0
0
0
0
0
–
–
0
0
–
0
0
0
–
0
0
0
–
–
–
1
0
0
0
0
0
0
0
0
0
0
0
0
–
0
0
0
–
0
0
0
1
0
*3
*3
*3
Unused (Undefined when reading)
Unused (Undefined when reading)
Unused (Undefined when reading)
–
–
–
–
–
VSS2
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
–
R
0
R/W
On
Off
VSS2 booster control
VSS2
LOFF
All off
Normal LCD display all off / normal switch
LOFF
R/W
LDTY
LPWR
*5
*2
Unused
0
1/3
On
–
1/4
Off
–
LCD drive duty selection
LCD driver On/Off
LDTY
LPWR
BUFF
IIN
R
R/W
Fix at 0
BUFF
IIN
ADSPD
ADON
IIH
IIL
Current measurement terminal switching
100 mS 400 mS A/D conversion speed switching
ADSPD
ADON
R/W
On
Off
A/D converter On/Off
Unused
*5
*2
*2
0
0
0
0
R
SVDDT SVDON
R/W
*5
Unused
Low
On
Normal Supply voltage detection data
SVDDT
SVDON
Off
SVD circuit On/Off
Unused
*5
*2
*2
0
0
FNC2
FNC1
R/W
RNG1
R/W
0
FNC0
RNG0
ADP
FNC2
FNC1
FNC0
0
Measurement function selection
(See Table 4.1.2)
R
0
*5
Unused
RNG2
RNG2
RNG1
RNG0
Measurement range selection
(See Table 4.1.3)
R
0
*5
*2
*2
*2
Unused
Unused
Unused
0
0
0
*5
*5
0
R
R
R
R
R
R
Positive Negative A/D converter polarity judgment
ADP
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
DSC03
DSC02
DSC01
DSC00
DSC13
DSC12
DSC11
DSC10
DSC23
DSC22
DSC21
DSC20
DSC03
DSC13
DSC23
0
DSC02
DSC12
DSC22
DSC32
IDR
DSC01
DSC11
DSC21
DSC31
STS1
DSC00
DSC10
DSC20
DSC30
STS0
A/D conversion data (00–03)
A/D conversion data (10–13)
A/D conversion data (20–23)
*5
*2
*2
Unused
A/D conversion data (30–32)
0
1
1
1
0
0
0
DSC32
DSC31
DSC30
*5
Unused
Effective Read data status
A/D conversion status 0: auto zero adjustment,
1: input integral, 3: reverse integral
0
0
Invalid
IDR
STS1
STS0
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S1C62M20 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1(e) I/O memory map (F0H–F6H)
Register
Address
F0H
Comment
*1
D3
D2
D1
D0
Name
EIK1
Init
0
0
0
0
0
0
0
0
–
–
–
0
–
–
–
0
–
–
–
0
0
0
0
0
–
–
–
0
1
0
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Interrupt mask register (K10–K13)
Interrupt mask register (K00–K03)
Interrupt mask register (Serial interface)
Interrupt mask register (A/D converter)
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 16 Hz)
Interrupt mask register (Clock timer 32 Hz)
Unused
EIK1
EIK0
EIT2
0
EISIF
EIAD
EIK0
EISIF
EIAD
EIT1
R/W
R/W
R
EIT1
0
EIT16
EIT32
IK1
EIT2
F1H
F2H
F3H
F4H
F5H
F6H
EIT16
EIT32
*5
*2
*2
*2
0
0
0
0
*5
*5
*4
*5
*5
*5
*4
*5
*5
*5
*4
*4
*4
*4
*4
*5
*5
*5
*4
Unused
Unused
0
Yes
Yes
No
No
Interrupt factor flag (K10–K13)
Unused
IK1
0
*2
*2
*2
0
0
IK0
Unused
0
Unused
0
R
Interrupt factor flag (K00–K03)
Unused
IK0
0
*2
*2
*2
0
0
0
ISIF
IT32
IAD
Unused
0
Unused
0
R
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Interrupt factor flag (Serial interface)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 16 Hz)
Interrupt factor flag (Clock timer 32 Hz)
Unused
ISIF
IT1
IT2
IT16
IT32
0
IT1
0
IT2
0
IT16
0
R
*2
*2
*2
Unused
0
Unused
0
R
Yes
No
Interrupt factor flag (A/D converter)
IAD
Table 4.1.2 A/D converter measurement function list
D3
D2
FNC2
D1
D0
Measurement
function
Integral resistor
normal mode (400 ms) high speed mode (100 ms) amplifier parator
Integral resistor
General Com-
Address
FNC1 FNC0
–
–
–
–
–
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
DC voltmeter mode
AC voltmeter mode
DC ammeter mode
AC ammeter mode
Resistance
BUF1 terminal
BUF3 terminal
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
Input integral: BUF1 terminal
OFF
E4H
measurement mode
Continuity check
mode
–
1
0
1
Reverse integral: BUF1 and BUF2 terminals
parallel
OFF
ON
–
–
1
1
1
1
0
1
–
BUF1 terminal
BUF3 terminal
OFF
OFF
OFF
OFF
ADPT mode
* In the resistance measurement mode and continuity check mode, switching between input integral (BUF1
terminal) and reverse integral (BUF1 and BUF2 terminals parallel) is automatically done by the hardware.
Table 4.1.3 A/D converter measurement range list
D3
D2
D1
D0
Measurement function
Address
E5H
RNG2 RNG1 RNG0
DC voltmeter AC voltmeter
Resistance
400 Ω
4 kΩ
Continuity check
Current
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
400 mV
4 V
400 mV
4 V
50 Ω judgment Switching
100 Ω judgment outside of IC
40 V
400 V
1000 V
↑
40 V
400 V
750 V
↑
40 kΩ
400 kΩ
4 MΩ
40 MΩ
↑
500 Ω judgment
1 kΩ judgment
↑
↑
↑
↑
↑
↑
↑
↑
↑
* In the current measurement mode, the S1C62M20 performs an A/D conversion using a voltage value (within
±437 mV) input from the IIL terminal or IIH terminal. Consequently, it is not necessary to switch the range.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
4.2 Resetting Watchdog Timer
4.2.1 Configuration of watchdog timer
The S1C62M20 incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 1 Hz signal).
The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 seconds,
the initial reset signal is output automatically for the CPU.
Figure 4.2.1.1 is the block diagram of the watchdog timer.
1 Hz
Reset
signal
Timer
TM0–TM7
256 Hz from divider
Watchdog timer
Timer reset signal
SLEEP signal
Watchdog timer reset signal
Fig. 4.2.1.1 Watchdog timer block diagram
The watchdog timer, configured of a two-bit binary counter, generates the initial reset signal internally by
overflow of the counter.
Watchdog timer reset processing in the program’s main routine enables detection of program overrun,
such as when the main routine’s watchdog timer processing is bypassed. Ordinarily this routine is incorpo-
rated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer can also be reset by the resetting of the clock timer.
The watchdog timer operates in the HALT mode. If the watchdog timer is not reset within 3 or 4 seconds
including the HALT status, the IC reactivates from initial reset status.
When the S1C62M20 enters SLEEP status by the SLP instruction, the watchdog timer and the clock timer
are reset. Therefore, when SLEEP status is released, the watchdog timer and the clock timer operate the
same as that after releasing an initial reset.
4.2.2 Control of watchdog timer
Table 4.2.2.1 lists the watchdog timer’s control bits and their address.
Table 4.2.2.1 Control bits of watchdog timer
Register
Address
D4H
Comment
*1
D3
0
D2
D1
D0
Name
Init
–
1
0
*5
*2
*2
*2
*2
Unused
Unused
0
0
0
WDRST TMRST
*5
*5
–
Reset
Reset
–
–
Watchdog timer reset
WDRST
–
R
W
*5
TMRST
Clock timer and watchdog timer reset
–
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
WDRST: Watchdog timer reset (D4H•D1)
This is the bit for resetting the watchdog timer.
When "1" is written:
When "0" is written:
Reading:
Watchdog timer is reset
No operation
Always "0"
When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after
this. When "0" is written to WDRST, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
TMRST: Clock timer reset (D4H•D0)
This is the bit for resetting the clock timer and the watchdog timer.
When "1" is written:
When "0" is written:
Reading:
Clock timer and watchdog timer are reset
No operation
Always "0"
When "1" is written to TMRST, the clock timer and the watchdog timer are reset, and the operation restarts
immediately after this. When "0" is written to TMRST, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
4.2.3 Programming note
The watchdog timer must be reset within 3-second cycles.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3 Oscillation Circuit
4.3.1 Configuration of oscillation circuit
The S1C62M20 has a oscillation circuit (OSC1). OSC1 is a crystal oscillation circuit that supplies the operat-
ing clock to the CPU and peripheral circuits.
Figure 4.3.1.1 is the block diagram of this oscillation system.
10.9 kHz
LCD circuit
V
SS2 divider
Divider
A/D converter
Timer
21.8 kHz
256 Hz
OSC1 oscillator
32.768 kHz
1 Hz
CPU clock
control
CPU clock
32.768 kHz
SLEEP
K port interrupt
Fig. 4.3.1.1 Oscillation system
4.3.2 Crystal oscillation circuit
The S1C62M20 has a built-in crystal oscillation circuit. The OSC1 oscillation circuit generates the operating
clock for the CPU and peripheral circuitry by connecting the crystal oscillator (Typ. 32.768 kHz) as an
external element.
Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit.
Cg
OSC1
To CPU and divider
X'tal
Rf
Rd
Cd
OSC2
Fig. 4.3.2.1 OSC1 oscillation circuit
As Figure 4.3.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal
oscillator (X’tal) between terminals OSC1 and OSC2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
The OSC1 oscillation circuit starts to operate immediately after turning the power ON, so programming is
not necessary to control the circuit. However, be aware that the system clock is not supplied to the CPU
until the 1 Hz signal from the timer goes high after initial resetting.
In the S1C62M20, the OSC1 oscillation circuit does not stop even when the CPU enters SLEEP status.
However, SLEEP stops supplying the clock to the peripheral circuits (timer and watchdog timer).
4.3.3 Clock frequency and instruction execution time
Table 4.3.3.1 shows the instruction execution time according to the system clock from the OSC1 oscillation
circuit.
Table 4.3.3.1 Clock frequency and instruction execution time
Instruction execution time (µsec)
Clock frequency
5-clock instruction 7-clock instruction 12-clock instruction
OSC1: 32.768 kHz
152.6
213.6
366.2
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4 Input Ports (K00–K03, K10–K13)
4.4.1 Configuration of input ports
The S1C62M20 has eight bits general-purpose input ports. Each of the input port terminals (K00–K03, K10–
K13) provides internal pull down resistor. Pull down resistor can be selected for each bit with the mask
option.
Further, a Schmitt buffer is provided on each input line of all input terminals (K00–K03, K10–K13).
Figure 4.4.1.1 shows the configuration of input port.
Interrupt
request
Kxx
Address
Mask option
VSSD
Fig. 4.4.1.1 Configuration of input port
Selection of "With pull down resistor" with the mask option suits input from the push switch, key matrix,
and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing with
other LSIs.
Further, all the input port terminals (K00–K03, K10–K13) are used as the interrupt port for releasing the
SLEEP mode. See Section 4.15, "Interrupt and HALT/ SLEEP" for details.
4.4.2 Interrupt function
All eight bits of the input ports (K00–K03, K10–K13) provide the interrupt function. The conditions for
issuing an interrupt can be set by the software.
Figure 4.4.2.1 shows the configuration of input interrupt circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00
Address
Address
Interrupt selection
register (SIK00)
Interrupt factor
flag (IK0)
K0
interrupt
request
Address
Interrupt mask
register (EIK0)
K01
K02
K03
Address
K10
Address
Address
Interrupt selection
register (SIK10)
Interrupt factor
flag (IK1)
K1
interrupt
request
Address
Interrupt mask
register (EIK1)
K11
K12
K13
Address
Fig. 4.4.2.1 Input interrupt circuit configuration
The interrupt selection register (SIK) is individually set for the input ports (K00–K03, K10–K13) and can
specify the terminal for generating interrupt.
The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13 to
use for the interrupt. Writing "1" into an interrupt selection register incorporates that input port into the
interrupt generation conditions. The changing the input port where the interrupt selection register has been
set to "0" does not affect the generation of the interrupt.
The input interrupt is generated at the rising edge of the input.
The K00–K03 and K10–K13 interrupts are separated as two interrupt factors. Therefore, two interrupt factor
flags (IK0, IK1) and two interrupt mask registers (EIK0, EIK1) are provided. (IK0 and EIK0 correspond to
K00–K10. IK1 and EIK1 correspond to K10–K13.)
When the interrupt is generated, the interrupt factor flag (IK0, IK1) is set to "1".
Each interrupt request to the CPU by the interrupt factors can be masked using the interrupt mask registers
(EIK0, EIK1).
The K00–K03 and K10–K13 input interrupts are used to release the SLEEP mode.
4.4.3 Mask option
Internal pull down resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–K13)
with the input port mask option.
When "Gate direct" (without pull down resistor) is selected, take care that the floating status does not occur
for the input. Select "With pull down resistor" for input ports that are not being used.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.4 Control of input ports
Table 4.4.4.1 lists the input ports control bits and their addresses.
Table 4.4.4.1 Input port control bits
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SIK03
SIK02
SIK01
SIK00
K03
Init
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
0
–
–
–
0
1
0
Enable
Enable
Enable
Enable
High
Disable Interrupt selection register (K03)
Disable Interrupt selection register (K02)
Disable Interrupt selection register (K01)
Disable Interrupt selection register (K00)
Low
SIK03
SIK02
SIK01
SIK00
C0H
C1H
C2H
C3H
F0H
F2H
F3H
R/W
R
*2
*2
*2
*2
K03
SIK13
K13
EIK1
0
K02
SIK12
K12
EIK0
0
K01
SIK11
K11
EISIF
0
K00
SIK10
K10
High
Low
K02
Input port (K00–K03)
High
Low
K01
High
Low
K00
Enable
Enable
Enable
Enable
High
Disable Interrupt selection register (K13)
Disable Interrupt selection register (K12)
Disable Interrupt selection register (K11)
Disable Interrupt selection register (K10)
Low
SIK13
SIK12
SIK11
SIK10
K13
R/W
R
*2
*2
*2
*2
High
Low
K12
Input port (K10–K13)
High
Low
K11
High
Low
K10
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (K10–K13)
EIK1
EIK0
EISIF
EIAD
EIAD
IK1
Interrupt mask register (K00–K03)
Interrupt mask register (Serial interface)
R/W
R
Interrupt mask register (A/D converter)
*5
*2
*2
*2
Unused
0
0
*5
*5
*4
*5
*5
*5
*4
Unused
Unused
0
Yes
Yes
No
No
Interrupt factor flag (K10–K13)
IK1
0
*2
*2
*2
Unused
0
0
0
IK0
Unused
0
Unused
0
R
Interrupt factor flag (K00–K03)
IK0
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
K00–K03, K10–K13: Input port data (C1H, C3H)
Input data of the input port terminals can be read.
When "1" is read:
When "0" is read:
Writing:
High level
Low level
Invalid
The reading is "1" when the terminal voltage of the eight bits of the input ports (K00–K03, K10–K13) goes
high (VDD), and "0" when the voltage goes low (VSSD).
These bits are dedicated for reading, so writing cannot be done.
SIK00–SIK03, SIK10–SIK13: Interrupt selection register (C0H, C2H)
Selects the port to be used for the K00–K03 and K10–K13 input interrupts.
When "1" is written:
When "0" is written:
Reading:
Enable
Disable
Valid
Enables the interrupt for the input ports (K00–K03, K10–K13) for which "1" has been written into the
interrupt selection register (SIK00–SIK03, SIK10–SIK13). The input port set for "0" does not affect the
interrupt generation condition.
At initial reset, these registers are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
EIK0, EIK1: Interrupt mask registers (F0H•D2, D3)
Masking the interrupt of the input port can be selected with these registers.
When "1" is written:
When "0" is written:
Reading:
Enable
Mask
Valid
With these registers, masking of the input interrupt can be selected for each of the two systems (K00–K03,
K10–K13).
Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0").
At initial reset, these registers are set to "0".
IK0, IK1: Interrupt factor flags (F3H•D0, F2H•D0)
These flags indicate the occurrence of input interrupt.
When "1" is read:
When "0" is read:
Writing:
Interrupt has occurred
Interrupt has not occurred
Invalid
The interrupt factor flags IK0 and IK1 are associated with K00–K03 and K10–K13, respectively. From the
status of these flags, the software can decide whether an input interrupt has occurred.
Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be
generated.
These flags are reset when the software reads them.
At initial reset, these flags are set to "0".
4.4.5 Programming notes
(1) When input ports are changed from high to low by pull down resistor, the fall of the waveform is
delayed on account of the time constant of the pull down resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull down resistance 300 kΩ
(2) Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated.
(3) Write the interrupt mask register (EIK0, EIK1) only in the DI status (interrupt flag = "0"). Writing during
EI status (interrupt flag = "1") will cause malfunction.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.5 Output Ports (R00–R03)
4.5.1 Configuration of output ports
The S1C62M20 has four bits general output ports.
Output specifications of the output ports can be selected individually with the mask option. Two kinds of
output specifications are available: complementary output and Pch open drain output.
Figure 4.5.1.1 shows the configuration of the output port.
V
DD
Register
Rxx
Address
Complementary
Pch open drain
V
SSD
Mask option
Fig. 4.5.1.1 Configuration of output port
4.5.2 Mask option
Output specifications of the output ports can be selected with the mask option.
Output specifications for the output ports (R00–R03) enable selection of either complementary output or
Pch open drain output for each of the four bits.
However, even when Pch open drain output is selected, voltage exceeding source voltage must not be
applied to the output port.
4.5.3 Control of output ports
Table 4.5.3.1 lists the output ports’ control bits and their address.
Table 4.5.3.1 Control bits of output ports
Register
Address
C4H
Comment
*1
D3
D2
D1
D0
Name
R03
Init
0
1
0
High
High
High
High
Low
Low
Low
Low
R03
R02
R01
R00
R02
0
Output port (R00–R03)
R01
0
R/W
R00
0
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
R00–R03: Output port data (C4H)
Sets the output data for the output ports.
When "1" is written:
When "0" is written:
Reading:
High output
Low output
Valid
The output port terminals output the data written in the corresponding registers (R00–R03) without
changing it. When "1" is written in the register, the output port terminal goes high (VDD), and when "0" is
written, the output port terminal goes low (VSSD).
At initial reset, these registers are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Buzzer Output Ports)
4.6 Buzzer Output Ports (BZ, BZ)
4.6.1 Configuration of buzzer output ports
The S1C62M20 has two special output ports: a buzzer output (BZ terminal) and a buzzer inverted output
(BZ terminal). Output specification of the buzzer output ports is a complementary output.
Figure 4.6.1.1 shows the configuration of the buzzer output port.
VDD
BZ signal
BZ signal
BZ, BZ
VSSD
Fig. 4.6.1.1 Configuration of buzzer output port
4.6.2 Buzzer output
BZ and BZ are the buzzer signal outputs for driving the piezo-electric buzzer.
By setting the BZON register to "1", the BZ (buzzer signal output) terminal and the BZ (buzzer inverted
signal output) terminal output the buzzer signal.
The buzzer signal frequency can be selected as 2 kHz or 4 kHz by setting the BZFQ register.
The following four output modes are set in the buzzer output function.
• Continuous buzzer signal output
• Intermittent buzzer signal output
• One-shot buzzer signal output
• Buzzer signal output during the continuity check mode
(1) Continuous buzzer signal output
By setting the BZFNC register to "0" and the BZON register to "1", the buzzer signal is continuously
output from the BZ terminal and the BZ terminal.
Figure 4.6.2.1 shows the output waveform of a continuous buzzer signal.
BZON
BZFNC
BZ
0
1
0
0
BZ
Fig. 4.6.2.1 Continuous buzzer signal output waveform
The buzzer signal output stops by writing "0" to the BZON register. However, it may take up to 31 msec
for the buzzer signal output to actually stop depending on the status of the counter built into the buzzer
signal output control circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Buzzer Output Ports)
(2) Intermittent buzzer signal output
By setting the BZFNC register to "1" and the BZON register to "1", the buzzer signal is intermittently
output from the BZ terminal and the BZ terminal.
In this mode, the buzzer signal goes ON and OFF in 8 Hz cycles.
The buzzer signal output stops by writing "0" to the BZON register. However, it may take up to 31 msec
for the buzzer signal output to actually stop depending on the status of the counter built into the buzzer
signal output control circuit.
Figure 4.6.2.2 shows the output waveform of an intermittent buzzer signal.
BZON
BZFNC
BZ
0
0
1
0
1
125 msec
BZ
250 msec
Fig. 4.6.2.2 Intermittent buzzer signal output waveform
(3) One-shot buzzer signal output
By writing "1" to the BSHOT register, a buzzer signal is output for approximately 31 msec immediately
after writing.
Figure 4.6.2.3 shows the output waveform of one-shot buzzer signal.
BSHOT
BZ
BZ
31 msec
31 msec
Fig. 4.6.2.3 One-shot buzzer signal output waveform
When "1" is written to the BSHOT register again while the previous one-shot buzzer signal is being
output, the buzzer signal is output again for 31 msec from the time of rewriting "1".
This output is effective when the BZON register is set to "0".
(4) Buzzer signal output during the continuity check mode
If the measured resistance value is less than the judgment resistance setting value during measurement
in the continuity check mode of the S1C62M20 measurement function, a buzzer signal is output. The
continuity judgment and the buzzer signal output are automatically done by the hardware.
This auto buzzer signal output is done only in the continuity check mode. See Section 4.12, "Measure-
ment Circuit and Measurement Procedure" for details of the continuity check mode.
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4.6.3 Control of buzzer output
Table 4.6.3.1 lists the buzzer output control bits and their addresses.
Table 4.6.3.1 Control bits for buzzer output
Register
Address
Comment
*1
D3
0
D2
D1
D0
R
Name
Init
–
1
0
*5
*2
*2
Unused
Unused
0
0
BZFQ
*5
0
BZFQ
R
–
D0H
D1H
2 kHz
1
4 kHz
0
Buzzer signal frequency selection
1 bit general-purpose register
Unused
0
R
R/W
R/W
0
*5
*2
*2
0
–
0
BSHOT
W
BZFNC
BZON
*5
BSHOT
One-shot
–
One-shot buzzer signal (31 msec) output trigger
–
Intermittent Continuous Continuous/intermittent output selection
On Off
Buzzer signal output control
BZFNC
BZON
0
R
0
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
BZFQ: Buzzer signal frequency selection register (D0H•D1)
Selects the frequency of the buzzer signal.
When "1" is written:
When "0" is written:
Reading:
2 kHz
4 kHz
Valid
When "1" is written to this register, the frequency of the buzzer signal is set in 2 kHz, and in 4 kHz when "0"
is written. Buzzer signal output (ON/ OFF) is controlled using the BZON register.
At initial reset, this register is set to "0".
BSHOT: One-shot buzzer signal output trigger (D1H•D2)
Outputs a one-shot buzzer signal from the BZ and BZ terminals.
When "1" is written:
When "0" is written:
Reading:
Output
Invalid
Always "0"
When "1" is written to this trigger bit, a buzzer signal is output for approximately 31 msec immediately
after writing. When "1" is written again while the previous one-shot buzzer signal is being output, the
buzzer signal is output again for 31 msec from the time of rewriting "1".
This output is effective when the BZON register is set to "0".
BZFNC: Continuous/intermittent output selection register (D1H•D1)
Selects a buzzer signal output mode.
When "1" is written:
When "0" is written:
Reading:
Continuous buzzer signal output
Intermittent buzzer signal output
Valid
When "1" is written to this register, continuous buzzer signal output is selected as the output mode, and
when "0" is written, intermittent buzzer signal output is selected.
Buzzer signal output (ON/ OFF) is controlled using the BZON register.
In the intermittent buzzer signal output mode, the buzzer signal goes ON and OFF in 125 msec cycles while
the BZON register is set to ON.
At initial reset, this register is set to "0".
BZON: Buzzer signal output control (D1H•D0)
Controls turning buzzer signal output ON and OFF.
When "1" is written:
When "0" is written:
Reading:
ON
OFF
Valid
When "1" is written to this register, the buzzer signal is output in the output mode set by the BZFNC
register. After that, when "0" is written, the buzzer signal output stops.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.7 I/O Ports (P00–P03)
4.7.1 Configuration of I/O ports
The S1C62M20 has 4 bits general-purpose I/O ports. Figure 4.7.1.1 shows the configuration of the I/O port.
The four bits of the I/O ports P00–P03 can be set to either input mode or output mode. Modes can be set by
writing data to the I/O control register.
Moreover, pull down resistor which is turned ON during input mode can be controlled through the
software.
V
DD
Address
Data
register
Pxx
Address
Address
Address
I/O control
register
Pull down
control register
V
SSD
Fig. 4.7.1.1 Configuration of I/O port
The I/O ports P00–P03 are common used with the input/output ports of the serial interface, and function
of these ports can be selected through the software.
See Section 4.10, "Serial Interface", for details of the serial interface.
4.7.2 I/O control registers and input/output mode
Input or output mode can be set for the four bits of I/O ports P00–P03 by writing data into the correspond-
ing I/O control registers IOC00–IOC03.
To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it
becomes high impedance status and works as an input port.
However, when the pull down explained in the following section has been set by software, the input line is
pulled down only during this input mode.
The output mode is set when "1" is written to the I/O control register. When an I/O port set to output
mode works as an output port, it outputs a high level (VDD) when the port output data is "1", and a low
level (VSSD) when the port output data is "0".
If perform the read out in each mode; when output mode, the register value is read out, and when input
mode, the port value is read out.
At initial reset, the I/O control registers are set to "0", and the I/O port enters the input mode.
4.7.3 Pull down during input mode
A pull down resistor that operates during the input mode is built into the I/O ports of the S1C62M20.
Software can set the use or non-use of this pull down. The pull down resistor becomes effective by writing
"1" into the pull down control registers PUL00–PUL03 that correspond to each of P00–P03, and the input
line is pulled down during the input mode. When "0" has been written, no pull down is done.
At initial reset, the pull down control registers are set to "1".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.7.4 Mask option
Output specifications during the output mode (IOC = "1") can be selected with the mask option.
Output specifications for the I/O ports (P00–P03) enable selection of either complementary output or Pch
open drain output for each of the 4 bits.
However, even when Pch open drain output is selected, voltage exceeding source voltage must not be
applied to the output port.
4.7.5 Control of I/O ports
Table 4.7.5.1 lists the I/O ports’ control bits and their addresses.
Table 4.7.5.1 Control bits of I/O ports
Register
Address
Comment
*1
D3
D2
D1
D0
Name
IOC03
IOC02
IOC01
IOC00
IOC03
IOC03
IOC02
IOC01
IOC00
PUL03
PUL02
PUL01
PUL00
PUL03
PUL03
PUL02
PUL02
PUL01
PUL00
P03
Init
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
1
Output
Output
Output
Output
Output
1
0
Input
Input
Input
Input
Input
0
IOC03
IOC02
IOC01
IOC00
I/O control register (P00–P03)
(ESIF = 0)
R/W
When the serial I/F is used (ESIF = 1):
P00 = SIN (in), P01 = SOUT (out),
P02 = SCLK (master: out, slave: in),
P03 = SRDY (slave: out),
Master mode: P03 I/O control register
Slave mode: General-purpose register
C8H
1
0
1
0
General-purpose register
P03 = I/O port (master: in/out)
1
0
On
On
On
On
On
1
Off
Off
Off
Off
Off
0
PUL03
PUL02
PUL01
PUL00
Pull down control register (P00–P03)
(ESIF = 0)
R/W
When the serial I/F is used (ESIF = 1):
P00 = SIN (in), P01 = SOUT (out),
P02 = SCLK (master: out, slave: in),
P03 = SRDY (slave: out),
Master mode: P03 pull down control register
Slave mode: General-purpose register
Master mode: General-purpose register
Slave mode: SCKL pull down control register
General-purpose register
C9H
1
0
On
1
Off
0
P03 = I/O port (master: in/out)
On
High
High
High
High
High
1
Off
Low
Low
Low
Low
Low
0
SIN pull down control register
*2
*2
*2
*2
*2
*2
*2
*2
*2
P03
P02
P01
P00
P02
I/O port (P00–P03)
(ESIF = 0)
P01
R/W
P00
CAH
When the serial I/F is used (ESIF = 1):
P00 = SIN (in), P01 = SOUT (out),
P02 = SCLK (master: out, slave: in),
P03 = SRDY (slave: out),
Master mode: I/O port P03
P03
Slave mode: General-purpose register
P03
1
0
P02
1
0
General-purpose register
P01
P03 = I/O port (master: in/out)
1
0
P00
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
P00–P03: I/O port data (CAH)
I/O port data can be read and output data can be set through these ports.
• When writing data
When "1" is written:
When "0" is written:
High level
Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,
the level goes low (VSSD).
Port data can be written also in the input mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
• When reading data
When "1" is read:
When "0" is read:
High level
Low level
When the I/O port is in the input mode, the voltage level being input to the port terminal can be read out.
When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal
voltage is low (VSSD) the data is "0".
When the I/O port is in the output mode, the P00–P03 register value can be read.
When PUL register is set to "1", the built-in pull down resistor goes ON during input mode, so that the I/O
port terminal is pulled down.
When the serial input/output function is selected for P00–P03 ports, the registers P00–P03 in the slave mode
and the registers P00–P02 in the master mode can be used as a general register having both read and write
functions, and data of these registers exert no affect on input/output signal. In the master mode, since P03 is
not used for the serial interface and can be used as an I/O port, the P03 register becomes the I/O port data
register.
IOC00–IOC03: I/O control registers (C8H)
The input and output modes of the I/O ports can be set with these registers.
When "1" is written:
When "0" is written:
Reading:
Output mode
Input mode
Valid
The input and output modes of the I/O ports are set in one bit unit. IOC00, IOC01, IOC02 and IOC03 set
the mode for P00, P01, P02 and P03, respectively.
Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and
writing "0" induces the input mode.
At initial reset, these registers are set to "0", so the I/O ports are in the input mode.
When the serial input/output function is selected for P00–P03 ports, the registers IOC00–IOC03 in the slave
mode and the registers IOC00–IOC02 in the master mode can be used as a general register having both
read and write functions, and data of this registers exerts no affect on input/output control. In the master
mode, since P03 is not used for the serial interface and can be used as an I/O port, the IOC03 register
becomes the I/O control register.
PUL00–PUL03: Pull down control registers (C9H)
The pull down during the input mode can be set with these registers.
When "1" is written:
When "0" is written:
Reading:
Pull down ON
Pull down OFF
Valid
The built-in pull down resistor which is turned ON during input mode is set to enable in units of four bits.
PUL00, PUL01, PUL02 and PUL03 set the pull down for P00, P01, P02 and P03, respectively.
By writing "1" to the pull down control register, the corresponding I/O ports are pulled down (during
input mode), while writing "0" turns the pull down function OFF.
At initial reset, these registers are set to "1", so the pull down function is set to ON.
When the serial input/output function is selected for P00–P03 ports, the PUL01 register, the PUL02 register
in the master mode and the PUL03 register in the slave mode can be used as general registers having both
read and write functions, and data of this registers exerts no affect on pull down control. In the master
mode, since P03 is not used for the serial interface and can be used as an I/O port, the PUL03 register
becomes the pull down control register.
4.7.6 Programming note
When in the input mode, I/O ports are changed from high to low by pull down resistor, the fall of the
waveform is delayed on account of the time constant of the pull down resistor and input gate capacitance.
Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 10 pF + parasitic capacitance ? pF
R: pull down resistance 300 kΩ
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.8 LCD Driver (COM0–COM3, SEG0–SEG15)
4.8.1 Configuration of LCD driver
The S1C62M20 has four common terminals (COM0–COM3) and 16 segment terminals (SEG0–SEG15), so
that it can drive an LCD with a maximum of 64 (16 × 4) segments.
The power for driving the LCD is generated by the S1C62M20 internal circuit so that there is no need to
apply power especially from outside.
The driving method is 1/ 4 duty dynamic drive depending on the four types of potential, VDD, VL1, VL2 and
VL3. In addition to the 1/ 4 duty, 1/ 3 drive duty can be selected through the software. The frame frequency
is 42.7 Hz for 1/ 4 duty, and 56.9 Hz for 1/ 3 duty (fOSC1 = 32.768 kHz).
LCD display ON/ OFF can be controlled by the software.
Figures 4.8.1.1 and 4.8.1.2 show the drive waveform for 1/ 4 duty and 1/ 3 duty.
Note: "fOSC1" indicates the oscillation frequency of the OSC1 oscillation circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
LCD on condition
-VDD
-VL1
-VL2
-VL3
COM0
COM0
COM1
COM2
COM3
COM1
COM2
COM3
SEG0–15
Off
On
-VDD
-VL1
-VL2
-VL3
SEG
0–15
Frame frequency
Fig. 4.8.1.1 Drive waveform for 1/4 duty
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COM0
-VDD
-VL1
-VL2
-VL3
LCD on condition
COM0
COM1
COM2
COM1
COM2
COM3
SEG0–15
Off
On
-VDD
-VL1
-VL2
-VL3
SEG
0–15
Frame frequency
Fig. 4.8.1.2 Drive waveform for 1/3 duty
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.8.2 LCD display control and duty switching
(1) LCD drive power
The S1C62M20 has a built-in LCD power generator. The LCD power generator operates with the
boosted voltage VSS2 (VDD standard) and generates the LCD voltage (VL1, VL2, VL3). Therefore, turn the
VSS2 booster ON to generate boosted voltage VSS2 before displaying LCD.
See Section 4.13, "VSS2 Booster", for details of the VSS2 booster.
Figure 4.8.2.1 shows the configuration of the LCD drive power circuit.
VDD
LCD power
generator
LPWR
LPWR
VDD
VDD
VDD
VL1
VL2
VL3
C1
C2
+
–
VSS2
booster
circuit
+
–
VSS2
+
–
LCD
drive
circuit
COM0~COM3
SEG0~SEG15
VSS2
Fig. 4.8.2.1 Configuration of LCD drive power circuit
(2) Control of LCD driver
In the S1C62M20, turning ON/ OFF of the LCD display can be controlled using the LPWR register. At
initial reset, LPWR is set to "0", and the LCD display is set to the OFF status. In this time, the VL1, VL2,
VL3, COM and SEG (*) terminals goes to VDD level.
To set the LCD display ON, write "1" to the LPWR register.
* Except for the SEG terminals that have been set to DC output by the mask option.
(3) Switching of drive duty
By settings of LDTY register, the LCD drive duty can be selected either 1/ 4 or 1/ 3 duty. Table 4.8.2.1
shows the LCD drive duty setting.
Table 4.8.2.1 LCD drive duty setting
Terminals used Maximum number
LDTY
Duty
Frame frequency *
in common
of segments
0
1
1/4
1/3
COM0–COM3
COM0–COM2
64 (16 × 4)
48 (16 × 3)
f
OSC1/768 (42.7 Hz)
OSC1/576 (56.9 Hz)
f
* In case of fOSC1 = 32.768 kHz
Basically the LCD drive duty should be selected according to the LCD panel to be used. Select 1/ 3 duty
if the segment number is 48 segments or less or select 1/ 4 duty if it is 49 segments or more.
(4) LCD display all OFF
In the S1C62M20, switching from normal display to display all OFF can be controlled using the LOFF
register. By writing "1" to the LOFF register, all the LCD display can be turned OFF unless written to the
segment memory. It returns to the normal display when "0" is written to the LOFF register. This
operation does not affect the contents of the display memory.
(5) LCD driver in SLEEP status
When the S1C62M20 enters SLEEP status, it resets the LCD driver control registers (on the address
E1H) to the initial status. However, it does not change the data in the display memory.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.8.3 Mask option (segment allocation)
(1) Segment allocation
The LCD driver has a segment decoder built-in, and the data bit of the optional address in the display
memory area (A0H–AFH) can be allocated to the optional segment. This makes design easy by increas-
ing the degree of freedom with which the liquid crystal panel can be designed.
The allocated segment displays when the bit for the display memory is set to "1", and goes out when bit
is set to "0".
Figure 4.8.3.1 shows an example of the relationship between the LCD segments (on the panel) and the
display memory for the case of 1/ 3 duty.
Common 0
Common 1
Common 2
Data
Address
SEG10
SEG11
SEG12
AA, D0
(a)
AB, D1
(f)
AB, D0
(e)
D3
d
D2
c
D1
b
D0
a
AAH
ABH
ACH
ADH
AA, D1
(b)
AB, D2
(g)
AA, D3
(d)
p
g
f
e
d'
p'
c'
g'
b'
f'
a'
e'
AD, D1
(f')
AA, D2
(c)
AB, D3
(p)
Display memory allocation
Pin address allocation
a
a'
b'
b
f'
f
g'
g
c'
e
c
e'
p'
p
d'
d
SEG10 SEG11 SEG12
Common 0
Common 1
Common 2
Fig. 4.8.3.1 Segment allocation
(2) Output specification
➀ The segment terminals (SEG0–SEG15) are selected with the mask option in pairs for either segment
signal output or DC output (VDD and VSSD binary output).
When DC output is selected, the data corresponding to COM0 of each segment terminal is output.
➀ When DC output is selected, either complementary output or Pch open drain output can be selected for
each terminal with the mask option.
Note: The terminal pairs are the combination of SEG2 × n and SEG2 × n + 1 (where n is an integer from 0
to 7).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.8.4 Control of LCD driver
Table 4.8.4.1 shows the LCD driver’s control bits and their address. Figure 4.8.4.1 shows the display
memory map.
Table 4.8.4.1 LCD driver control bits
Register
Address
E1H
Comment
*1
*2
D3
D2
D1
D0
Name
LOFF
Init
0
1
0
All off
Normal LCD display all off / normal switch
LOFF
0
LDTY
LPWR
*5
Unused
0
–
1/3
On
1/4
Off
LCD drive duty selection
LCD driver On/Off
LDTY
LPWR
0
R/W
R
R/W
0
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
Address
Page
Low
High
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
A
Display memory (16 words × 4 bits)
Fig. 4.8.4.1 Display memory map
LPWR: LCD driver ON/OFF (E1H•D0)
Turns the LCD driver ON and OFF.
When "1" is written:
When "0" is written:
Reading:
LCD driver ON
LCD driver OFF
Valid
By writing "1" to LPWR, the LCD driver goes ON. The voltage (VL1, VL2, VL3) that is needed to drive the
LCD and the signals are generated and the LCD panel displays according to the display data set in the
display memory.
When "0" is written to LPWR, the LCD driver goes OFF and the terminals VL1, VL2, VL3, COM and SEG
(except for SEG terminals that are set to DC output by mask option) go to VDD level.
At initial reset and in SLEEP status, this register is set to "0".
LDTY: LCD drive duty selection (E1H•D1)
Sets the LCD drive duty as shown in Table 4.8.4.2.
Table 4.8.4.2 LCD drive duty setting
Terminals used Maximum number
LDTY
Duty
Frame frequency *
in common
of segments
0
1
1/4
1/3
COM0–COM3
COM0–COM2
64 (16 × 4)
48 (16 × 3)
f
OSC1/768 (42.7 Hz)
OSC1/576 (56.9 Hz)
f
* In case of fOSC1 = 32.768 kHz
The LDTY register can be read.
At initial reset and in SLEEP status, this register is set to "0".
Display memory (A0H–AFH)
The LCD segments are lit or turned off depending on this data.
When "1" is written:
When "0" is written:
Reading:
Lit
Not lit
Invalid
By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be
lit or put out.
At initial reset, the contents of the display memory for COM0 is set to "0", and COM1–COM3 are unde-
fined. Accordingly, when DC output is selected, the output level at initial reset is a low (VSSD) level.
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LOFF: LCD display all OFF (E1H•D3)
Turns LCD display all OFF.
When "1" is written:
When "0" is written:
Reading:
LCD display all OFF
Normal display (according to the Display memory)
Valid
When "1" is written to LOFF, all the LCD display goes OFF, and it returns to the normal display according
to the display memory when "0" is written.
This operation does not affect the contents of the display memory.
At initial reset and in SLEEP status, this register is set to "0".
4.8.5 Programming notes
(1) The contents of the display memory are undefined until the area is initialized (through, for instance,
memory clear processing by the CPU). Initialize the display memory by executing initial processing.
(2) Since the display memory area is write-only, display data cannot be rewritten by arithmetic operations
(such as AND, OR, ADD, SUB).
(3) The power source for the LCD power generator (VL1, VL2 and VL3 generation circuit) and the operating
clock for the LCD drive timing generator are supplied from the VSS2 booster. Therefore, be sure to turn
the VSS2 booster ON by setting the VSS2 register to "1" before turning the LCD driver ON (LPWR = "1").
(4) The control registers (LOFF, LDTY, LPWR) for the LCD driver are automatically set to the initial status
when the CPU enters SLEEP status using the SLP instruction. Therefore, after returning from SLEEP
status, set the registers’ value again.
In SLEEP status, the VSS2 booster turns OFF.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.9 Clock Timer
4.9.1 Configuration of clock timer
The S1C62M20 has a built-in clock timer as the source oscillator for OSC1 (crystal oscillator). The clock
timer is configured of a 8-bit binary counter that serves as the input clock, a 256 Hz signal output by the
OSC1 oscillation circuit. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software.
Figure 4.9.1.1 is the block diagram for the clock timer.
Data bus
Timer
Watchdog timer
1/2 Hz–1/4 Hz
OSC1
circuit
128 Hz–16 Hz
8 Hz–1 Hz
SLEEP
Timer reset
Watchdog
timer reset
32 Hz, 16 Hz
2 Hz, 1 Hz
Interrupt
control
INT (Interrupt request)
Fig. 4.9.1.1 Block diagram for the clock timer
Ordinarily, this clock timer is used for all types of timing functions such as clocks.
4.9.2 Data reading and hold function
The 8 bits timer data are allocated to the addresses D5H and D6H.
D5H D0: TM0 (128 Hz)
D6H D0: TM4 (8 Hz)
D1: TM1 (64 Hz)
D1: TM5 (4 Hz)
D2: TM2 (32 Hz)
D2: TM6 (2 Hz)
D3: TM3 (16 Hz)
D3: TM7 (1 Hz)
Since the clock timer data has been allocated to two addresses, a carry is generated from the low-order data
within the count (TM0–TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz). When this carry is
generated between the reading of the low-order data and the high-order data, a content combining the two
does not become the correct value (the low-order data is read as FFH and the high-order data becomes the
value that is counted up 1 from that point).
The high-order data hold function in the S1C62M20 is designed to operate to avoid this. This function
temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point
where the low-order data has been read and consequently the time during which the high-order data is
held is the shorter of the two indicated here following.
1. Period until it reads the high-order data.
2. 0.48–1.5 msec (varies due to the timing of the reading)
Note: When the high-order data has previously been read, since the low-order data is not held, you should
be sure to first read from the low-order data.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.9.3 Interrupt function
The clock timer can cause interrupts at the falling edge of 32 Hz, 16 Hz, 2 Hz and 1 Hz signals. Software
can set whether to mask any of these frequencies.
Figure 4.9.3.1 is the timing chart of the clock timer.
Address Register Frequency
Timer timing chart
D0
D1
128 Hz
64 Hz
D5H
D6H
D2
D3
32 Hz
16 Hz
8 Hz
D0
D1
D2
D3
4 Hz
2 Hz
1 Hz
32 Hz interrupt request
16 Hz interrupt request
2 Hz interrupt request
1 Hz interrupt request
Fig. 4.9.3.1 Timing chart of clock timer
As shown in Figure 4.9.3.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 16 Hz, 2 Hz,
1 Hz). At this time, the corresponding interrupt factor flag (IT32, IT16, IT2, IT1) is set to "1". Selection of
whether to mask the separate interrupts can be made with the interrupt mask registers (EIT32, EIT16, EIT2,
EIT1). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the
falling edge of the corresponding signal.
Note: • Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to
"1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt
request will not be generated. Be very careful when interrupt factor flags are in the same address.
• Write the interrupt mask register only in the DI status (interrupt flag = "0"). Writing during EI status
(interrupt flag = "1") will cause malfunction.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.9.4 Control of clock timer
Table 4.9.4.1 shows the clock timer control bits and their addresses.
Table 4.9.4.1 Control bits of clock timer
Register
Address
Comment
*1
D3
0
D2
D1
D0
Name
Init
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
1
0
*5
*2
*2
*2
*2
*3
*3
*3
*3
*3
*3
*3
*3
Unused
Unused
0
0
0
WDRST TMRST
*5
*5
D4H
D5H
D6H
F1H
F5H
Reset
Reset
–
–
Watchdog timer reset
WDRST
R
W
*5
Clock timer and watchdog timer reset
Clock timer data (16 Hz)
TMRST
TM3
TM3
TM7
EIT1
IT1
TM2
TM6
EIT2
IT2
TM1
TM5
TM0
TM4
EIT32
IT32
Clock timer data (32 Hz)
TM2
Clock timer data (64 Hz)
TM1
R
R
Clock timer data (128 Hz)
TM0
Clock timer data (1 Hz)
TM7
Clock timer data (2 Hz)
TM6
Clock timer data (4 Hz)
TM5
Clock timer data (8 Hz)
TM4
Enable
Enable
Enable
Enable
Yes
Mask
Mask
Mask
Mask
No
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 16 Hz)
Interrupt mask register (Clock timer 32 Hz)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 16 Hz)
Interrupt factor flag (Clock timer 32 Hz)
EIT1
EIT2
EIT16
EIT32
EIT16
IT16
R/W
*4
IT1
IT2
*4
*4
*4
Yes
No
Yes
No
IT16
IT32
R
Yes
No
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
TM0–TM7: Timer data (D5H, D6H)
The 128 Hz–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read
only, and writing operations are invalid.
By reading the low-order data (D5H), the high-order data (D6H) is held while the shorter of the two
indicated below.
1. Period until it reads the high-order data.
2. 0.48–1.5 msec (varies due to the timing of the reading)
At initial reset, the timer data is initialized to "00H".
EIT32, EIT16, EIT2, EIT1: Interrupt mask register (F1H)
These registers are used to select whether to mask the clock timer interrupt.
When "1" is written:
When "0" is written:
Reading:
Enabled
Masked
Valid
The interrupt mask registers (EIT32, EIT16, EIT2, EIT1) are used to select whether to mask the interrupt to
the separate frequencies (32 Hz, 16 Hz, 2 Hz, 1 Hz).
Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0").
At initial reset, these registers are all set to "0".
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IT32, IT16, IT2, IT1: Interrupt factor flag (F5H)
These flags indicate the status of the clock timer interrupt.
When "1" is read:
When "0" is read:
Writing:
Interrupt has occurred
Interrupt has not occurred
Invalid
The interrupt factor flags (IT32, IT16, IT2, IT1) correspond to the clock timer interrupts of the respective
frequencies (32 Hz, 16 Hz, 2 Hz, 1 Hz). The software can judge from these flags whether there is a clock
timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the
signal.
These flags can be reset through being read out by the software.
Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not
be generated. Be very careful when interrupt factor flags are in the same address.
At initial reset, these flags are set to "0".
TMRST: Clock timer reset (D4H•D0)
This bit resets the clock timer.
When "1" is written:
When "0" is written:
Reading:
Clock timer reset
No operation
Always "0"
The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No opera-
tion results when "0" is written to TMRST.
TMRST also resets the watchdog timer.
This bit is write-only, and so is always "0" at reading.
4.9.5 Programming notes
(1) Be sure to read data in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).
(2) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Conse-
quently, perform flag reading (reset the flag) as necessary at reset.
(3) The clock timer is reset when the CPU enters SLEEP status by the SLP instruction.
(4) When the clock timer has been reset, the watchdog timer is also reset.
(5) Write the interrupt mask register (EIT) only in the DI status (interrupt flag = "0"). Writing during EI
status (interrupt flag = "1") will cause malfunction.
(6) Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will
not be generated. Be very careful when interrupt factor flags are in the same address.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.10 Serial Interface (SIN, SOUT, SCLK, SRDY)
4.10.1 Configuration of serial interface
The S1C62M20 has a synchronous clock type 8-bit serial interface built-in.
The configuration of the serial interface is shown in Figure 4.10.1.1.
The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via the
same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/ output may be set by selecting by software any one of two
types of master mode (internal clock mode: when the S1C62M20 is to be the master for serial input/ output)
and a type of slave mode (external clock mode: when the S1C62M20 is to be the slave for serial input/
output).
Also, when the serial interface is used at slave mode, SRDY signal which indicates whether or not the serial
interface is available to transmit or receive can be output to the SRDY terminal.
SD0–SD7
SOUT
(P01)
Shift register (8-bit)
SCPS
SIN
(P00)
Output
latch
SCS0 SCS1
Serial clock
selector
Serial clock
counter
Serial interface
interrupt control circuit
ISIF
SCLK
(P02)
Serial clock
generator
System clock
EISIF
Serial interface
activating circuit
SRDY
(P03)
SCTRG
Fig. 4.10.1.1 Configuration of serial interface
The input/ output ports of the serial interface are common used with the I/ O ports P00–P03, and function
of these ports can be selected through the software.
P00–P03 terminals and serial input/ output correspondence are as follows:
Master mode
Slave mode
P00 = SIN (I)
P00 = SIN (I)
P01 = SOUT (O)
P02 = SCLK (O)
P03 = I/O port (I/O)
P01 = SOUT (O)
P02 = SCLK (I)
P03 = SRDY (O)
Note: At initial reset, P00–P03 are set to I/O ports.
When using the serial interface, switch the function (ESIF = "1") in the initial routine.
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4.10.2 Master mode and slave mode of serial interface
The serial interface of the S1C62M20 has two types of operation mode: master mode and slave mode.
In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates
this internal clock at the SCLK (P02) terminal and controls the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input from
the SCLK (P02) terminal and uses it as the synchronous clock to the built-in shift register.
The master mode and slave mode are selected by writing data to registers SCS0 and SCS1.
When the master mode is selected, a synchronous clock may be selected from among two types as shown
in Table 4.10.2.1.
Table 4.10.2.1 Synchronous clock selection
SCS1
SCS0
Mode
Synchronous clock
CLK
1
1
0
1
0
1
0
Master mode
Slave mode
CLK
CLK/2
0
External clock
CLK:
CPU system clock (32.768 kHz)
CLK/2: CPU system clock/2
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/ output of the 8-bit serial data, is controlled as
follows:
• At master mode, after output of 8 clocks from the SCLK (P02) terminal, clock output is automatically
suspended and SCLK (P02) terminal is fixed at low level.
• At slave mode, after input of 8 clocks to the SCLK (P02) terminal, subsequent clock inputs are masked.
A sample basic serial input/ output portion connection is shown in Figure 4.10.2.1.
S1C62M20
SCLK
S1C62M20
SCLK
External
External
serial device
serial device
CLK
CLK
SOUT
SOUT
SIN
SOUT
SIN
SOUT
SIN
SIN
Input terminal
READY
SRDY
Input terminal
(a) Master mode
(b) Slave mode
Fig. 4.10.2.1 Sample basic connection of serial input/output section
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.10.3 Data input/output and interrupt function
The serial interface of S1C62M20 can input/ output data via the internal 8-bit shift register. The shift
register operates by synchronizing with either the synchronous clock output from SCLK (P02) terminal
(master mode), or the synchronous clock input to SCLK (P02) terminal (slave mode).
The serial interface generates interrupt on completion of the 8-bit serial data input/ output. Detection of
serial data input/ output is done by the counting of the synchronous clock SCLK; the clock completes
input/ output operation when 8 counts (equivalent to 8 cycles) have been made and then generates inter-
rupt.
The serial data input/ output procedure data is explained below:
(1) Serial data output procedure and interrupt
The S1C62M20 serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to 4-bit registers SD0–SD3 (CEH) and SD4–SD7 (CFH) individually and
writing "1" to SCTRG bit (CCH• D1), it synchronizes with the synchronous clock and serial data is
output at the SOUT (P01) terminal. The synchronous clock used here is as follows: in the master mode,
internal clock which is output to the SCLK (P02) terminal while in the slave mode, external clock which
is input from the SCLK (P02) terminal. The serial output of the SOUT (P01) terminal changes with the
rising edge of the clock that is input or output from the SCLK (P02) terminal.
When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF (F4H• D0)
is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask
register EISIF (F0H• D1). Note, however, that regardless of the setting of the interrupt mask register, the
interrupt factor flag is set to "1" after output of the 8-bit data.
(2) Serial data input procedure and interrupt
The S1C62M20 serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN (P00) terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8-bit shift register. As in the above item (1), the synchronous clock used here is
as follows: in the master mode, internal clock which is output to the SCLK (P02) terminal while in the
slave mode, external clock which is input from the SCLK (P02) terminal.
The serial data to the built-in shift register is read with the rising edge of the SCLK signal when the
SCPS register is "1" and is read with the falling edge of the SCLK signal when the SCPS register is "0".
Moreover, the shift register is sequentially shifted as the data is fetched.
When the input of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to "1"
and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIF.
Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is
set to "1" after input of the 8-bit data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
(3) Serial data input/output permutation
S1C62M20 allows the input/ output permutation of serial data to be selected by register SDP (CDH• D3)
as to either LSB first or MSB first. The block diagram showing input/ output permutation in case of LSB
first and MSB first is provided in Figure 4.10.3.1.
Address [CFH]
Address [CEH]
Output
latch
SIN
SIN
SD7 SD6 SD5 SD4
SD3 SD2 SD1 SD0
SOUT
SOUT
(In case of LSB first)
Address [CFH]
Address [CEH]
Output
latch
SD0 SD1 SD2 SD3
SD4 SD5 SD6 SD7
(In case of MSB first)
Fig. 4.10.3.1 Serial data input/output permutation
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(4) SRDY signal
When the S1C62M20 serial interface is used in the slave mode (external clock mode), SRDY is used to
indicate whether the internal serial interface is available to transmit or receive data for the master side
(external) serial device. SRDY signal is output from the SRDY (P03) terminal.
SRDY signal becomes "1" (high: VDD level) when the S1C62M20 serial interface becomes available to
transmit or receive data; normally, it is at "0" (low: VSSD level).
SRDY signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to
"0" when "1" is input to the SCLK (P02) terminal (i.e., when the serial input/ output begins transmitting
or receiving data). Moreover, when data is read from or written to SD4–SD7, the SRDY signal returns to
"0".
(5) Timing chart
The S1C62M20 serial interface timing chart is shown in Figure 4.10.3.2.
SCTRG(W)
SCTRG(R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY(slave mode)
(a) When SCPS = "1"
SCTRG(W)
SCTRG(R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY(slave mode)
(b) When SCPS = "0"
Fig. 4.10.3.2 Serial interface timing chart
4.10.4 Mask option
Since the input/ output terminal of the serial interface is dual used with the I/ O ports (P00–P03), the mask
option that selects the output specification for the I/ O port is also applied to the serial interface.
The output specification of the terminals SOUT, SCLK (during the master mode) and SRDY (during the
slave mode) that are used as output in the input/ output port of the serial interface is respectively selected
by the mask options of P01, P02 and P03.
Either complementary output or P channel (Pch) open drain as output specification may be selected.
However, even if Pch open drain has been selected, application on the terminal of voltage exceeding power
source voltage is not permitted.
Select complementary output for the output specification of the SIN (P00) terminal.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.10.5 Control of serial interface
Table 4.10.5.1 list the serial interface control bits and their addresses.
Table 4.10.5.1 Control bits of serial interface
Register
Address
Comment
*1
D3
0
D2
D1
D0
Name
Init
–
–
–
0
0
0
0
0
0
–
–
–
–
–
–
–
–
1
1
1
1
1
1
0
0
0
0
–
–
–
0
1
0
*5
*2
*2
*2
Unused
Unused
0
0
0
SCTRG
ESIF
*5
Trigger
Run
–
Serial interface clock trigger (writing)
Serial interface clock status (reading)
SCTRG(W)
SCTRG(R)
ESIF
CCH
Stop
R
R/W
SIF port I/O port P0 port function selection
LSB first MSB first Serial data input/output permutation
Serial interface clock phase selection
Serial interface clock mode selection
0: Slave, 1: CLK/2, 2: CLK, 3: CLK
MSB
SDP
SDP
SD3
SD7
SCPS
SD2
SCS1
SD1
SCS0
SD0
SCPS
SCS1
SCS0
SD3
CDH
CEH
CFH
R/W
R/W
R/W
*2
*2
*2
*2
*2
*2
*2
*2
SD2
Serial interface data (low-order 4 bits)
SD1
LSB
SD0
MSB
SD7
SD6
SD5
SD4
SD6
Serial interface data (high-order 4 bits)
SD5
LSB
SD4
On
1
Off
0
Master mode: P03 pull down control register
Slave mode: General-purpose register
Master mode: General-purpose register
Slave mode: SCKL pull down control register
General-purpose register
PUL03
PUL03
PUL02
PUL02
PUL01
PUL00
EIK1
PUL03
PUL02
PUL01
EISIF
PUL00
1
0
C9H
On
Off
R/W
1
0
On
Off
SIN pull down control register
Interrupt mask register (K10–K13)
Interrupt mask register (K00–K03)
Interrupt mask register (Serial interface)
Interrupt mask register (A/D converter)
Unused
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
EIK1
0
EIK0
0
EIAD
ISIF
EIK0
F0H
F4H
EISIF
EIAD
R/W
*5
*2
*2
*2
0
0
*5
Unused
0
*5
Unused
0
R
*4
Yes
No
Interrupt factor flag (Serial interface)
ISIF
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
ESIF: P0 port function selection (CCH•D0)
Sets P00–P03 to the input/ output port for the serial interface.
When "1" is written:
When "0" is written:
Reading:
Serial interface
I/ O port
Valid
P00, P01, P02 and P03 will function as SIN, SOUT, SCLK, SRDY, respectively.
In the slave mode, the P03 terminal functions as the SRDY output terminal, and in the master mode, it
functions as the I/ O port terminal.
At initial reset, this register is set to "0".
PUL00, PUL02: Pull down control register (C9H•D0, D2)
Sets the pull down of SIN terminal and SCLK terminal (in the slave mode).
When "1" is written:
When "0" is written:
Reading:
Pull down ON
Pull down OFF
Valid
Sets the pull down resistor built into the SIN (P00) and SCLK (P02) ports to ON or OFF. SCLK pull down is
effective during the slave mode.
At initial reset, these registers are set to "1".
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SCS0, SCS1: Cock mode selection (CDH•D0, D1)
Selects the synchronous clock for the serial interface (SCLK).
Table 4.10.5.2 Synchronous clock selection
SCS1
SCS0
Mode
Synchronous clock
CLK
1
1
1
0
0
1
0
Master mode
Slave mode
CLK
CLK/2
0
External clock
CLK:
CPU system clock (32.768 kHz)
CLK/2: CPU system clock/2
Synchronous clock (SCLK) is selected from among the above 3 types: 2 types of internal clock and external clock.
At initial reset, external clock is selected.
SCPS: Shift clock phase selection (CDH•D2)
Selects the timing for reading in the serial data input from SIN (P00) terminal.
When "1" is written:
When "0" is written:
Reading:
Rising edge of SCLK
Falling edge of SCLK
Valid
Selects whether the fetching for the serial input data to the registers (SD0–SD7) at the rising edge (at "1"
writing) or falling edge (at "0" writing) of the SCLK signal.
The input data fetching timing may be selected but output timing for output data is fixed at SCLK rising edge.
When the internal clock is selected as the synchronous clock (SCLK), a hazard occurs in the synchronous
clock (SCLK) when data is written to the SCPS register.
At initial reset, this register is set to "0".
SDP: Data input/output permutation selection (CDH•D3)
Selects the serial data input/ output permutation.
When "1" is written:
When "0" is written:
Reading:
LSB first
MSB first
Valid
Select whether the data input/ output permutation will be MSB first or LSB first.
At initial reset, this register is set to "0".
SCTRG: Clock trigger/status (CCH•D1)
This is a trigger to start input/ output of synchronous clock (SCLK).
• When data is written
When "1" is written:
When "0" is written:
Trigger
No operation
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/
output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/
reading on data registers SD0–SD7.)
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from performing
trigger input multiple times, as leads to malfunctioning.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
• When data is read
When "1" is read:
When "0" is read:
RUN status
STOP status
When read out this bit, it indicates the status of serial interface clock.
After "1" is written to SCTRG, this value is latched till serial interface clock stops (8 clock counts). There-
fore, if "1" is read, it indicates that the synchronous clock is in input/ output operation.
When the synchronous clock input/ output is completed, this latch is reset to "0".
At initial reset, this bit is set to "0".
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SD0–SD3, SD4–SD7: Serial interface data register (CEH, CFH)
These registers are used for writing and reading serial data.
• When data is written
When "1" is written: High level
When "0" is written: Low level
Writes serial data will be output to SOUT (P01) terminal. From the SOUT (P01) terminal, the data converted
to serial data as high (VDD) level bit for bits set at "1" and as low (VSSD) level bit for bits set at "0".
• When data is read
When "1" is read:
When "0" is read:
High level
Low level
The serial data input from the SIN (P00) terminal can be read by this register.
The data converted to parallel data, as high (VDD) level bit "1" and as low (VSSD) level bit "0" input from
SIN (P00) terminal. Perform data reading only while the serial interface is halted (i.e., the synchronous
clock is neither being input or output).
At initial reset, these registers will be undefined.
EISIF: Interrupt mask register (F0H•D1)
This is the interrupt mask register of the serial interface.
When "1" is written:
When "0" is written:
Reading:
Enabled
Masked
Valid
With this register, masking of the serial interface interrupt can be selected.
At initial reset, this register is set to "0".
ISIF: Interrupt mask register (F4H•D0)
This is the interrupt factor flag of the serial interface.
When "1" is read:
When "0" is read:
Writing:
Interrupt has occurred
Interrupt has not occurred
Invalid
From the status of this flag, the software can decide whether the serial interface interrupt.
The interrupt factor flag is reset when it has been read out.
Note, however, that even if the interrupt is masked, this flag will be set to "1" after the 8-bit data input/
output.
Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not
be generated.
At initial reset, this flag is set to "0".
4.10.6 Programming notes
(1) Perform data writing/ reading to data registers SD0–SD7 only while the serial interface is halted (i.e.,
the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be per-
formed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through
data writing/ reading on data registers SD0–SD7.) Supply trigger only once every time the serial
interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock,
start to input the external clock after the trigger.
(3) Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will
not be generated.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
4.11 A/D Converter
4.11.1 Configuration of A/D converter
The S1C62M20 has a built-in dual slope type A/ D converter and an analog switch circuit. Combination of
the A/ D converter and the analog switch circuit make up the DMM (digital multimeter), and can measure
various items. See Section 4.12, "Measurement Circuit and Measurement Procedure", for measurement
when using these circuits as DMM.
Two types of resolution and conversion time are set in the S1C62M20 A/ D converter as follows:
Mode
Resolution (count)
Conversion time (msec)
Normal mode
High-speed mode
4,370
441
400
100
See Chapter 7, "ELECTRICAL CHARACTERISTICS", for the conversion precision.
Figure 4.11.1.1 shows the A/ D converter block diagram.
BUF1
BUF2
BUF3
S1C62M20 [A/D]
V
DD/VDDA
CH
–
+
CL
Reference voltage
controller
VRF1
VRF2
VADJ
Selector
Reference voltage
generator
CAZ
CI
+
–
V
SSD/VSSA
C1
+
–
CO
C2
V
SS2 booster
V
SS2
A/D clock
21.845 kHz
VI
R6
R5/VI2
R4/VI3
R3/VI4
R2/VI5
R1
Dual slope
A/D controller
Analog switch control
Analog switch
circuit
IIL
OP-AMP
IIH
OVX
OVSG
SGND
CFI
Dual slope
counter
Fig. 4.11.1.1 A/D converter block diagram
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4.11.2 Power supply and reference voltage generator for A/D converter
The A/ D converter operates with VSSA as the analog GND, VDDA as the positive power and VSS2 as the
negative power. VSS2 is the voltage generated by the voltage booster built into the S1C62M20. Therefore, be
sure to turn the VSS2 booster ON before operating the A/ D converter. See Section 4.13, "VSS2 Booster" for
details of the VSS2 booster.
Figure 4.11.2.1 shows the configuration of the A/ D converter power supply system.
VDD
VSSD
VDDA
VSSA
VDD–VSSD
+
Dual slope
counter
Analog GND
C1
C2
A/D
control
circuit
VSS2
booster
VSS2
VSS2
0 V
-3 V
-6 V
VDD, VDDA
A/D converter
OP-AMP
Analog switch
control circuit
Digital
VDD–VSS2
VSSD, VSSA
(Analog GND)
A/D
Reference
voltage
generator
Analog switch circuit
VSS2
VDDA–VSS2
Fig. 4.11.2.1 Configuration of A/D converter power supply system
The S1C62M20 generates the reference voltage VRF1 by turning the A/ D converter ON. Another reference
voltage VRF2 that is needed for A/ D conversion is generated by dividing with resistors connected to the
S1C62M20 externally.
Figure 4.11.2.2 shows the circuit diagram of the reference voltage generator.
VDDA
R1
V
RF2
A/D
R2/VI5
R3/VI4
R4/VI3
R5/VI2
R6
+
VRF1
–
r1
r2
r3
+
VADJ
Vref
–
r4
VSSA
VSS2
Fig. 4.11.2.2 Circuit diagram of reference voltage generator
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The reference voltage VRF2 (218.5 mV) after dividing with external resistors is supplied to inside of the
S1C62M20 from the VRF2 terminal and is used as the reference voltage for the A/ D converter. The VRF1 and
VRF2 voltage values can be adjusted using the variable resistor r4 shown in Figure 4.11.2.2. The VRF1 and
VRF2 voltage values should be set as below.
VRF1 = 1.0 to 1.2 V (VRF1–VSSA)
VRF2 ≈ 218.5 mV
The following shows the voltage values of r1 to r4 (shown in Figure 4.11.2.2) for reference.
r1 = 82 kΩ r2 = 22 kΩ r3 = 120 kΩ r4 = 75 k–412 kΩ
(VRF2–VSSA)
The VRF1 voltage is used as the reference voltage for generating the measurement voltage at the time of
resistance measurements. The VRF2 voltage is supplied to the A/ D converter as the positive reference
voltage (+VR) and the negative reference voltage (-VR) via the reference voltage controller.
4.11.3 Clock for A/D converter
The S1C62M20 uses a 21.845 kHz clock for the A/ D converter. This clock is generated by dividing the clock
from the OSC1 oscillation circuit (32.768 kHz).
[32.768 kHz × 2/3 = 21.845 kHz (A/D conversion clock) ]
The divider is built into the VSS2 booster, so be sure to turn the VSS2 booster ON before turning the A/ D
converter ON. See Section 4.13, "VSS2 Booster" for details.
4.11.4 A/D converter control circuit (Dual slope A/D controller)
The S1C62M20 has a built-in timing circuit (clock counter), that sets the time (period) of the auto zero
adjustment, the input integral and the reverse integral, within the A/ D converter control circuit (dual slope
A/ D controller). The A/ D converter is controlled with the signal from the timing circuit. The timing circuit
uses a 21.845 kHz clock from the VSS2 booster.
Table 4.11.4.1 shows the clock numbers that are taken for each period (auto zero adjustment, input integral
and reverse integral).
Table 4.11.4.1 Number of clocks for A/D conversion
Auto zero
adjustment
Input
integral
Reverse
integral
Mode
Total
High speed mode
Normal mode
1526
2185
218
441
2185
8740
2185
4370
1 clock: 1/21845 sec
4.11.5 Operation of dual slope type A/D converter
Figure 4.11.5.1 shows the circuit diagram of the A/ D converter built into the S1C62M20.
RB1
RB2
RB3
CAZ
CI
CI
BUF1 BUF2 BUF3
CAZ
S3
S5
S7
V
+VR
-VR
IN
S1
S4
S6
S8
+
A/D
control
circuit
+
+
–
–
–
GND
(SGND)
S2
GND
(SGND)
RB1 = 390 kΩ
RB2 ≈ 329 kΩ
RB3 = 39 kΩ
CAZ = 0.1 µF
CI = 0.1 µF
Fig. 4.11.5.1 Circuit diagram of A/D converter
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This A/ D converter performs A/ D conversion according to the following three sequences.
• Auto zero adjustment period
• Input integral period
• Reference voltage reverse integral period
The time of respective periods becomes as shown in Table 4.11.5.1 according to the high-speed mode and
normal mode (setting of ADSPD, E2H• D1 in the I/ O memory).
Table 4.11.5.1 A/D conversion time
Auto zero
adjustment
Input
integral
Reverse
integral
Total
time
ADSPS Resolution
0
1
4370
441
100 msec
70 msec
100 msec
10 msec
200 msec
20 msec
400 msec
100 msec
• When input voltage is positive pole (VSSA = GND)
Auto zero
adjustment
Input
integral
Reverse
integral
Auto zero
adjustment
Buffer AMP
output
GND
GND
Integral AMP
output
• When input voltage is negative pole (VSSA = GND)
Auto zero
adjustment
Input
integral
Reverse
integral
Auto zero
adjustment
Buffer AMP
output
GND
GND
Integral AMP
output
Fig. 4.11.5.2 Output waveform during A/D conversion
The following will explain the outline of A/ D operations in the respective period. However in the resist-
ance measurement mode, there are differences in the operation in the reverse integral period, operation in
the high-speed mode, and the reference voltage that is used during reverse integral. See Section 4.12,
"Measurement Circuit and Measurement Procedure", for details.
(1) A/D conversion in normal mode
1. Auto zero adjustment period
Auto zero adjustment is the sequence initially effected in order to compensate for error in the A/ D
conversion results, due to the offset voltage of the buffer AMP (BUF), integral AMP (INT) and compara-
tor (CMP).
The switch S1 in Figure 4.11.5.1 is connected to the GND at the beginning of this period and the
switches S2, S3, S4, S7 and S8 go ON to discharge the capacitor CI. At this time, the resistors (RB1 and
RB3) that are connected to the BUF1 and BUF3 terminals are used in parallel for discharge.
Then the switches S7 and S8 go OFF, and voltage is charged into CAZ to correct the offset.
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2. Input integral period
When the auto zero adjustment period terminates, the A/ D converter starts the integral of the input
voltage by connecting the switch S1 to the VIN side, turning the switch S2 OFF and turning the switches
S3 and S4 ON. The input voltage of the integral AMP changes according to the time constant of the
integral resistance RB1 and the capacitor CI, and the waveform indicated in Figure 4.11.5.2 is output
from the integral AMP. The slope of this integral output waveform changes in proportion to the input
voltage. The portion charged into the CAZ due to the previous auto zero adjustment is added to the
input voltage of the integral AMP and negates the offset voltage.
The time of the input integral period is obtained by counting the A/ D clock (21.845 kHz) 2,185 times.
(The A/ D clock is generated from the VSS2 booster in dividing the OSC1 clock by 1.5.)
1
tx = ——————— × 2185 ≈ 100 msec
(Equation 4.11.5.1)
32,768 × (2/3)
Relation between the integral AMP output voltage VINT and time t is indicated by the following
equation.
t
VINT = -VIN × —————
(Equation 4.11.5.2)
CI × RB
VIN: Input voltage
t:
Integral time
CI: Integral capacity
RB: Integral resistance
3. Reference voltage reverse integral period
When the input integral period is completed, the A/ D converter shifts into the reverse integral period
using the reference voltage. The switch S1 is connected to the +VR or -VR side and the switch S2 is kept
in OFF.
The side of opposite polarity to the input voltage that effected the integral in step 2 is selected for the
polarity of the reference voltage VR.
• When the input voltage VIN is positive: Switch S1 connects to the -VR side
• When the input voltage VIN is negative: Switch S1 connects to the +VR side
For this purpose, the polarity of the input voltage is checked by a comparator for the input integral
period, and which of the polarities to be used is selected in advance.
At the same time as it begins the reverse integral by the reference voltage, the dual slope counter begins
counting up using the 21.845 kHz clock. The content of this counter is reset to the input integral period
and hence counts up from "0".
Reverse integral continues until the comparator detects that the output of the integral AMP has become
"0" (GND) and at that point the dual slope counter stops, then shifts to the next A/ D conversion
sequence (auto zero adjustment period).
Since the slope of the reverse integral waveform is fixed (except for the resistance measurement mode),
the counter value according to the integral result of the input voltage in step 2 is obtained from the dual
slope counter. The counter value n at this time is indicated by the following equations.
Output voltage VX of the integral AMP when an input integral period has finished is
tx
VX = -VIN × —————
CI × RB
(Equation 4.11.5.3)
VIN: Input voltage
tx:
Integral time (1/21.845 kHz) × (2,185 counts)
CI: Integral capacity
RB: Integral resistance
The reverse integral is done using the reference voltage VR. If a counter value when the reverse integral
has completed is n, the voltage change VS during the reverse integral is
1/21,845 × n
VS = -VR × ————————
CI × RB
(Equation 4.11.5.4)
Since the output voltage VINT of the integral AMP when the reverse integral has completed becomes "0"
(GND),
VINT = VX - VS = 0
VX = VS
(Equation 4.11.5.5)
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According to Equations 4.11.5.3, 4.11.5.4 and 4.11.5.5,
VIN × 2185
n = ——————
VR
(Equation 4.11.5.6)
Since the reference voltage VR is set to 218.5 mV in the S1C62M20, n becomes as below.
n = VIN × 1000
The dual slope counter is a decimal counter. Consequently, if 120 mV is input to the VIN terminal, the
counter value becomes "1,200". (Actually it may not become "1,200" because a conversion error occurs.
See Chapter 7, "ELECTRICAL CHARACTERISTICS", for the conversion error.)
The counter data is loaded into the registers of addresses E7H to EAH when an A/ D conversion has
finished (when the reverse integral has finished) and is maintained until the next A/ D conversion is
finished. A/ D conversion results can be obtained by reading the addresses E7H to EAH.
(2) A/D conversion in high speed mode
1. Auto zero adjustment period
In the auto zero adjustment period during the high speed mode, the switch S1 in Figure 4.11.5.1 is
connected to the GND at the beginning of this period and the switches S2, S7 and S8 go ON. In this
status, the capacitor CI is discharged and the capacitor CAZ is charged to correct the offset.
This period in the high speed mode is 70 msec.
2. Input integral period
The input integral period in the high speed mode differs from the normal mode in the following two
points: one is the integral resistance RB3 that is connected to the BUF3 terminal is used, and another is it
takes 10 msec for an input integral period.
The time of the input integral period is obtained by counting the A/ D clock (21.845 kHz) 218 times.
(The A/ D clock is generated from the VSS2 booster in dividing the OSC1 clock by 1.5.)
1
tx = ——————— × 218 ≈ 10 msec
(Equation 4.11.5.7)
32,768 × (2/3)
The high speed mode uses the resistor RB3 connected to the BUF3 terminal for integration. The slope of
the integral waveform output from the integral AMP (Figure 4.11.5.2) steepens than that of the normal
mode because the RB3 is set smaller than the integral resistance RB1 used in the normal mode.
3. Reverse integral period
Output voltage VX of the integral AMP when an input integral period during the high speed mode has
finished is
tx
VX = -VIN × —————
CI × RB
(Equation 4.11.5.8)
VIN: Input voltage
tx:
Integral time (1/21.845 kHz) × (218 counts)
CI: Integral capacity
RB: Integral resistance
The value of the reference voltage VR that is used for the reverse integral in the high speed mode is the
same as the normal mode.
According to Equations 4.11.5.6 and 4.11.5.8, nH (counter value in the high speed mode) is calculated as
below.
VIN × 218
nH = ——————
(Equation 4.11.5.9)
VR
Since the value of the reference voltage VR is the same as the normal mode, conversion errors in the
high speed mode occurs more frequently than in the normal mode.
The counter data is loaded into the registers of addresses E7H to EAH even in the high speed mode.
However in the high speed mode, the register value of the address E7H is always "0", and the upper
three digits are effective for the conversion results.
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Table 4.11.5.2 Example of A/D conversion result
When the input voltage VIN = 234.2 [mV]
A/D data register
Maximum
count number
Mode
EAH
E9H
E8H
E7H
Normal mode
4370
441
2
2
3
3
4
4
2
0
High speed mode
* In the high speed mode, E7H is always "0".
* Data in the above table is for reference, and is not guaranteed.
4.11.6 A/D conversion and interrupt
This section explains about the control and interrupt of the A/ D conversion and reading of data.
(1) Turning A/D converter ON/OFF
The power supply to the circuit of the A/ D converter is normally kept OFF, in order to reduce current
consumption. The A/ D converter starts when "1" is written into the register ADON and continues to
operate until a "0" has been written. It terminates A/ D conversion when a "0"is written into the ADON
and the circuit also goes OFF.
The ADON can be read and is "1" while the circuit is operating and is "0" when it is stopped.
When "1" is written into the ADON, it resets the A/ D converter (resets the dual slope counter to "0")
and executes the A/ D conversion sequence from the auto zero adjustment. Writing "1" into ADON is
also effective during A/ D conversion and it terminates the sequence during the current execution and
starts a new A/ D conversion sequence.
1
1
0
ADON write signal
ADON register
0
1
0
A/D converter
OFF
ON
OFF
Buffer AMP output
Restart
Fig. 4.11.6.1 Control of A/D conversion by the ADON register
(2) A/D interrupt
When an input integral period has terminated and the reverse integral starts according to the reference
voltage, the dual slope counter is counted up from "0". At the point where the integral AMP output due
to the reverse integral has crossed "0", the count stops and the data of the dual slope counter is latched.
When the reverse integral period has terminated, the A/ D interrupt factor flag IAD is set to "1" and an
interrupt occurs.
The A/ D interrupt can also be masked by writing a "0" into the interrupt mask register EIAD. When
EIAD is set to "1", an interrupt occurs.
The interrupt factor flag IAD is set to "1" when the reverse integration period has terminated, regardless
of the setting of the interrupt mask register and is reset to "0" by reading.
Write the interrupt mask register only in the DI status (interrupt flag = "0"). Writing during EI status
(interrupt flag = "1") will cause a malfunction.
(3) Reading of A/D conversion result
The dual slope counter is a four-digit decimal counter and is configured with three 4-bit data corre-
sponding to E7H, E8H and E9H, and one 3-bit data corresponding to EAH. This counter counts up from
"0" in decimals during the reverse integration period. The result that has been counted is latched upon
completion of the reverse integral period and the data from that latch can be read. This data (DSC00–
DSC32) is allocated to the addresses E7H–EAH. The register ADP that indicates the polarity of inputs
during the input integral period is allocated to E6H. When an input is positive (+) the ADP becomes "1"
and when it is negative (-) it becomes "0".
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The latched data is effective until the next A/ D conversion is completed and it is necessary to read up
to that point. Basically the read processing should be done using the A/ D interrupt. Moreover, the data
should read in order of E7H → E8H → E9H → EAH from the lower side. This is because to the follow-
ing reason.
When the following A/ D conversion terminates during data reading, the latched data is just rewritten.
For this reason, the IDR bit is set into the address EBH, so that it can decide whether the data read is
effective or invalid, by reading the IDR bit following the reading of data. When the reading of the data
in the above sequence has been completed prior to the termination of the next A/ D conversion, the IDR
becomes "0", indicating that the data is effective. When the following A/ D conversion has been termi-
nated and the latch rewritten before the reading terminates, the IDR becomes "1", indicating that the
data is invalid.
The circuit that sets this IDR decides whether the data has been read and the reading terminated by the
above mentioned data read address. Consequently, data reading should be done in the above men-
tioned sequence and then decide whether the data is effective or invalid by reading the IDR.
Further, be sure to read the data while the A/ D converter is ON (ADON = "1"). Be aware that conver-
sion data may sometimes become invalid by turning the A/ D converter OFF. In addition, the latched
data is cleared when the CPU enters SLEEP mode.
Figure 4.11.6.2 shows a timing chart for the A/ D conversion.
Buffer AMP output
ADON register
A/D interrupt
Read F7H
Read F8H
Read F9H
Read FAH
Read IDR
IDR bit
OK
OK
NG
Fig. 4.11.6.2 A/D conversion timing chart
Note: The A/D converter automatically restarts from the auto zero adjustment period when writing is done
to the registers on the addresses listed below.
E2H ...A/D converter setting registers (ADON, ADSPD, IIN, BUFF)
E4H ...Measurement function selection registers (FNC0, FNC1, FNC2)
E5H ...Measurement range selection registers (RNG0, RNG1, RNG2)
The auto restart is done by writing with software only.
Furthermore, these registers are set to the initial status when the CPU enters SLEEP mode (A/D
converter is OFF status). Therefore, set the above registers again when the CPU reactivates from
SLEEP status.
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4.11.7 Control of A/D converter
Table 4.11.7.1 lists the A/ D converter’s control bits and their addresses.
Table 4.11.7.1 Control bits of A/D converter
Register
Address
Comment
*1
D3
D2
D1
D0
Name
BUFF
IIN
Init
0
0
0
0
–
–
–
1
0
0
0
0
0
0
0
0
0
0
0
0
–
0
0
0
–
0
0
0
0
0
0
0
–
–
–
0
1
–
0
–
Fix at 0
Current measurement terminal switching
BUFF
IIN
ADSPD
ADON
IIH
IIL
E2H
E6H
E7H
E8H
E9H
EAH
EBH
F0H
F6H
100 mS 400 mS A/D conversion speed switching
ADSPD
ADON
R/W
On
Off
A/D converter On/Off
Unused
*5
*2
*2
*2
0
0
0
DSC03
DSC13
DSC23
0
0
0
ADP
DSC00
DSC10
DSC20
DSC30
STS0
*5
*5
Unused
Unused
0
R
R
R
R
R
R
Positive Negative A/D converter polarity judgment
ADP
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
DSC03
DSC02
DSC01
DSC00
DSC13
DSC12
DSC11
DSC10
DSC23
DSC22
DSC21
DSC20
DSC02
DSC12
DSC22
DSC32
IDR
DSC01
DSC11
DSC21
DSC31
STS1
A/D conversion data (00–03)
A/D conversion data (10–13)
A/D conversion data (20–23)
*5
*2
*2
Unused
A/D conversion data (30–32)
0
1
1
1
0
0
0
DSC32
DSC31
DSC30
*5
Unused
Effective Read data status
A/D conversion status 0: auto zero adjustment,
0
0
Invalid
IDR
STS1
STS0
EIK1
EIK0
EISIF
EIAD
0
1: input integral, 3: reverse integral
Interrupt mask register (K10–K13)
Interrupt mask register (K00–K03)
Interrupt mask register (Serial interface)
Interrupt mask register (A/D converter)
Unused
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
EIK1
0
EIK0
EISIF
EIAD
R/W
R
*5
*5
*5
*4
*2
*2
*2
0
0
IAD
Unused
0
Unused
0
Yes
No
Interrupt factor flag (A/D converter)
IAD
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
ADON: A/D converter control (E2H•D0)
Turns the A/ D converter ON/ OFF and restarts it.
When "1" is written:
When "0" is written:
Reading:
ON and restart
OFF
Valid
When "1" is written to the ADON register while the A/ D converter is in the stop status, the A/ D converter
and the reference voltage generator start operating. If "1" is written to the ADON register during an A/ D
conversion, the A/ D conversion is interrupted and a new A/ D conversion cycle (from the auto zero
adjustment) starts.
When "0" is written to the ADON register, the A/ D conversion is terminated and the A/ D converter goes
OFF.
At initial reset and in SLEEP mode, this register is set to "0".
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ADSPD: A/D conversion speed switching (E2H•D1)
Switches the conversion mode of the A/ D converter.
When "1" is written:
When "0" is written:
Reading:
High speed mode (100 msec)
Normal mode (400 msec)
Valid
When "1" is written to the ADSPD register, the A/ D conversion mode is set to the high speed mode. If the
A/ D conversion mode is changed to the high speed mode during A/ D conversion in the normal mode by
writing "1" to this register, the A/ D conversion in the normal mode is interrupted and it restarts from the
auto zero adjustment in the high speed mode.
At initial reset and in SLEEP mode, this register is set to "0".
IIN: Current measurement terminal switching (E2H•D2)
BUFF: (E2H•D3)
...See Section 4.12, "Measurement Circuit and Measurement procedure".
ADP: A/D converter polarity judgment (E6H•D0)
Indicates the polarity of the input voltage.
When "1" is read:
When "0" is read:
Writing:
Positive pole
Negative pole
Invalid
By reading this register with software, the polarity of the input voltage that is input to the A/ D converter
during the input integral period can be checked. When the A/ D converter input voltage during the input
integral period is positive (+), the ADP becomes "1" and when it is negative (-), it becomes "0".
This data is rewritten at the same time with the A/ D conversion data (E7H–EAH)
At initial reset and in SLEEP mode, this register is set to "1".
DSC00–DSC32: A/D conversion data (E7H–EAH•D2)
Decimal data of an A/ D conversion result that is counted during the reverse integral period by the dual
slope counter.
This data is effective from the time when the reverse integral period has terminated until the next reverse
integral period is terminated. Read the data during this period in the order of the address
E7H→E8H→E9H→EAH.
At initial reset and in SLEEP mode, these registers are set to "0".
STS0, STS1: A/D conversion status (EBH•D0, D1)
Indicates the A/ D converter status.
Reading:
STS1 STS0
Status
0
0
1
0
1
1
During auto zero adjustment
During input integral execution
During reverse integral execution
There is no setting of (STS1, STS0) = (1, 0)
Invalid
Writing:
By reading these bits, the execution status of the A/ D converter can be checked as in the above table.When
the A/ D converter terminates a reverse integral period, the status indication becomes "during auto zero
adjustment".
At initial reset and in SLEEP mode, STS0 and STS1 are set to "0".
IDR: Read data status (EBH•D2)
Indicates whether the data that has been read is effective or invalid.
When "1" is read:
When "0" is read:
Writing:
Data invalid
Data effective
Invalid
It can decide whether the data that has been read is effective or invalid by reading the IDR after data has
been read.
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When the reading of the data has completed before the next A/ D conversion terminates, the IDR is set to
"0". When the next A/ D conversion terminates before the previous data is read, the IDR is set to "1" to
indicate data invalid, so that the data will be rewritten. The IDR that has been set to "1" is reset to "0" by
reading.
At initial reset and in SLEEP status, the IDR is set to "0".
EIAD: Interrupt mask register (F0H•D0)
Select whether to mask interrupt with the A/ D converter.
When "1" is written:
When "0" is written:
Reading:
Enable
Mask
Valid
The A/ D interrupt is permitted when "1" is written in the EIAD. When "0" is written, the interrupt is
masked.
At initial reset, this register is set to "0".
IAD: Interrupt factor flag (F6H•D0)
This flag indicates interrupt caused by the A/ D converter.
When "1" is read:
When "0" is read:
Writing:
Interrupt has occurred
Interrupt has not occurred
Invalid
From the status of this flag, the software can decide whether an A/ D interrupt has occurred.
This flag is reset when the software has read it.
Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be
generated.
The IAD is set to "1" when a reverse integral period has finished even if the interrupt has been masked.
The interrupt factor flag may be set when the A/ D conversion setting is changed or the CPU enters SLEEP
status. Therefore, read (clear) the flag if necessary.
See Section 4.12, "Measurement Circuit and Measurement Procedure", for details of E4H (A/ D conversion
function switching) and E5H (Range switching).
At initial reset, this flag is set to "0".
4.11.8 Programming notes
(1) Be sure to check whether the data is effective or invalid by reading the A/ D conversion data in the
order F7H → F8H → F9H → FAH and immediately thereafter reading the IDR.
(2) The interrupt factor flag may be set when the A/ D conversion setting is changed (writing to E2H, E4H
or E5H) or the CPU enters SLEEP status. Therefore, read (clear) the flag if necessary.
(3) The A/ D converter is automatically set to the auto zero adjustment period when writing is done to the
addresses E2H, E4H (function switching) and E5H (range switching). If the ADON register has been set
to "1" (A/ D converter is ON) at this time, the A/ D conversion restarts with the new settings from the
auto zero adjustment.
(4) The registers on the addresses E2H and E4H to EBH are set to initial status when the CPU enters SLEEP
mode. Therefore, set the registers again when the CPU reactivates from SLEEP status.
(5) Write the interrupt mask register (EIAD) only in the DI status (interrupt flag = "0"). Writing during EI
status (interrupt flag = "1") will cause a malfunction.
(6) Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Measurement Circuit and Measurement Procedure)
4.12 Measurement Circuit and Measurement Procedure
4.12.1 Sort of measurement
The S1C62M20 has a built-in dual slope type A/ D converter and an analog switch circuit. Combination of
the A/ D converter and the analog switch circuit make up the DMM (digital multimeter), and can measure
various items. The measurement mode can be set using the measurement function selection register
(FNC0–FNC2) on the address E4H. Table 4.12.1.1 shows the relationship of the measurement function
selection register and the measurement mode that are available in the S1C62M20.
Table 4.12.1.1 Measurement mode on S1C62M20
Address D3 D2 D1 D0
Measurement mode
DC voltmeter mode (DCV)
AC voltmeter mode (ACV)
DC ammeter mode (DCA)
AC ammeter mode (ACA)
Resistance measurement mode (Ω)
Continuity check mode (CONT)
–
Range
Remarks
*
*
*
*
*
*
*
*
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
5
–
–
6
4
400 mV range to 1000 V
400 mV range to 750 V
Measurement terminal 2 systems
Measurement terminal 2 systems
400 Ω range to 40 MΩ
E4H
50, 100, 500, 1 kΩ
Fixed Fixed at 4 V range
ADPT mode (ADPT)
Fixed Fixed at DCV 400 mV range
* Bit D3 is invalid
The S1C62M20 automatically controls the general amplifier (for AC-DC conversion), comparator (for
continuity check) and integral resistors (BUF1 to BUF3 terminals) according to the switching of the above
measurement modes.
Table 4.12.1.2 shows the relationship of the measurement modes and the peripheral circuits.
Table 4.12.1.2 Measurement modes and peripheral circuits
Integral resistor
Measurement
function
Input
terminal
General
amplifier
Polarity judgment
(ADP)
Comparator
Normal mode
BUF1 terminal
High speed mode
DCV
ACV
DCA
ACA
Ω
VI
VI
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
BUF3 terminal
Available
Fixed at (+)
Available
IIL or IIH
IIL or IIH
OVX, OVSG
OVX, OVSG
VI
OFF
ON
*1
Fixed at (+)
Fixed at (+)
Fixed at (+)
Fixed at (+)
Fixed at (+)
OFF
OFF
OFF
OFF
Input integral: BUF1
CONT
–
Reverse integral: BUF1+ BUF2
OFF
OFF
BUF1 terminal
BUF3 terminal
ADPT
VI
*1 See Section 4.12.4, "Current measurement".
The general AMP (amplifier) goes ON during the AC ammeter mode or AC voltmeter mode.
The comparator goes ON during the continuity check mode.
The polarity judgment register ADP is available only in the DC voltmeter mode or DC ammeter mode. In
the other modes, it is always fixed at "1" (positive pole).
In the DC/ AC ammeter mode, either the IIH terminal or IIL terminal can be selected as the input terminal
using the IIN register.
For the integral resistor in the resistance measurement mode, the resistor that connected to the BUF1
terminal is used during the input integral period, and the resisters that are connected to the BUF1 and
BUF2 terminals are used in parallel during the reverse integral period. It is the same with the normal mode
and high speed mode of the A/ D converter.
The continuity check mode measures resistance too. The settings of the integral resistors are the same as the
resistance measurement mode.
See each of the following sections for range settings.
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Figure 4.12.1.1 shows the measurement circuit for the S1C62M20.
E0C62M2
DCV/ACV
VI
ADO
SW13
OP-AMP
ACV
DCV
Ω
10M
ADI
CFI
SW14
SW15
OVX
SW16
CONT
Ω/CONT
R6
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
10M
Vref
generator
ACA
DCA
R5/VI2
CH
CL
Fuse
SW18
1.11M
R4/VI3
SW17
OPEN
Vref
control
SW9
SW19
SW20
SW21
101k
R3/VI4
900
90
9
SW10
SW11
SW12
10k
R2/VI5
PTC
1k
VDD
SW22
R1
100
4A, 10A
BUF1
BUF2
BUF3
CAZ
CI
OVSG
0.9
4A
SW23
10A
0.09
0.01
Vmsr
generator
ACV
DCV
A/D
converter
IIH
IIL
SW24
SW25
SW26
SGND
SW27
SW28
SW29
COM
AVX1
AVX2
SW
Fig. 4.12.1.1 Measurement circuit
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4.12.2 General AMP
The S1C62M20 has a built-in general AMP (amplifier). It is used for AC/ DC conversion in the AC voltme-
ter mode or AC ammeter mode. Turning the general AMP ON and OFF can be controlled using the
measurement function selection register on the address E4H. When the ACV or ACA mode is selected
using the register, the general AMP goes ON and when another mode is selected, it goes OFF.
The AC/ DC conversion can be done by connecting an external rectification circuit to the S1C62M20. The
AVX1 and AVX2 terminals are used for input to the A/ D converter after AC/ DC converting.
Figure 4.12.2.1 shows the configuration of the general AMP.
ACV, ACA
-437~437 mV
–
+
ADO
ADI
AC/DC
converter
SW28
AVX1
SW29
AVX2
S1C62M20
Fig. 4.12.2.1 Configuration of general AMP
4.12.3 Voltage measurement
Voltage measurement is done by A/ D converting the voltage divided with the external resistors, 10 MΩ
resistor that is connected to the VI terminal and the reference resistor that is connected to the R5/ VI2–R2/
VI5 terminal.
Figure 4.12.3.1 shows the circuit configuration for voltage measurements.
10 MΩ
SW13
DCV
ACV
VI
-437~437 mV
R5/VI2
SW2
SW3
SW4
SW5
1.11 MΩ
SW8
SW9
R4/VI3
R3/VI4
R2/VI5
101 kΩ
10 kΩ
1 kΩ
SW10
SW11
SGND
S1C62M20
Fig. 4.12.3.1 Circuit configuration for voltage measurements
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Table 4.12.3.1 shows the condition on the range settings during voltage measurement.
Table 4.12.3.1 Range settings during voltage measurement
E5H
Measurement
range
Switches
to be ON
Dividing
terminal
D2
D1
D0
Input to A/D converter
RNG2 RNG1 RNG0
400 mV
4 V
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
SW13
Direct input from VI terminal
–
SW2, SW8
SW3, SW9
SW4, SW10
SW5, SW11
VIN × {1.11 MΩ / (10 MΩ + 1.11 MΩ)}
VIN × {101 kΩ / (10 MΩ + 101 kΩ)}
VIN × {10 kΩ / (10 MΩ + 10 kΩ)}
VIN × {1 kΩ / (10 MΩ + 1 kΩ)}
R5/VI2
R4/VI3
R3/VI4
R2/VI5
40 V
400 V
1000 V
VIN: Voltage to be measured
In the voltmeter mode, voltage to be measured is input to the A/ D converter after dividing it with the
resistor on the VI terminal (10 kΩ) and one of the reference resistors on the R5/ VI2 through R2/ VI5
terminals as shown in the above table.
In the DC voltmeter mode, the divided voltage is directly input to the A/ D converter. In the AC voltmeter
mode, the divided voltage is input to the A/ D converter via the AVX1 and AVX2 terminals after inputting
it to the general AMP to convert from AC to DC.
The A/ D converter uses the input from the SGND terminal as the GND level input. Therefore, the input to
the SGND terminal should be directly connected to the COM port of the DMM (digital multimeter).
4.12.4 Current measurement
Current measurement is done by A/ D converting the voltage that is converted from the current on the
outside of the S1C62M20. Two analog input terminals, IIH terminal and IIL terminal, are provided for
current measurements and the terminal to be used can be selected by software.
Figure 4.12.4.1 shows the measurement circuit for current measurements.
DCA, ACA
OPEN
900 Ω
90 Ω
SW24
SW25
IIL
-437~437 mV
IIH
9 Ω
0.9 Ω
0.09 Ω
0.01 Ω
4A, 10A
SGND
S1C62M20
COM
Fig. 4.12.4.1 Measurement circuit for current measurements
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Table 4.12.4.1 shows the relationship of the register settings for the ammeter mode and A/ D conversion.
Table 4.12.4.1 Register for ammeter mode and A/D convertor settings
E2H
D2
IIN
0
A/D conversion
maximum input
voltage (mV)
Conversion
speed
(msec)
Maximum
count number
(count)
Input
terminal
Resolution
D3
D1
(µV)
BUFF
ADSPD
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
IIL
IIL
IIH
IIH
± 437
± 437
± 437
± 437
400
100
400
100
4370
441
100
100
100
100
0
1
4370
441
1
0
0
Cannot be used
1
1
Note: "BUFF" (bit D3 on address E2H) must be set to "0". If it is "1", A/D conversion will not be done
correctly.
4.12.5 Resistance measurement
Resistance measurement is done by A/ D converting the voltage of both sides of the external reference
resistor connected to the R1–R6 terminal and the resistor to be measured.
I
nput to the A/ D converter is switched in the input integral period and the reverse integral period as below.
Input integral period: Voltage of both sides of the resistor to be measured
Reverse integral period: Voltage of both sides of the reference resistor
The S1C62M20 generates the voltage needed for measurement and output to the R1–R6 terminals
according to the measurement range.
Figure 4.12.5.1 shows the circuit configuration for the resistance measurement mode.
Vmsr
generator
R6
R5/VI2
R4/VI3
R3/VI4
R2/VI5
R1
SW1
SW2
SW3
SW4
SW5
10 MΩ
1.11 MΩ
101 kΩ
10 kΩ
SW7
SW8
SW9
SW10
SW11
SW12
1 kΩ
VDD
SW23
100 Ω
PTC
OVSG
OVX
Rx
SGND
COM
S1C62M20
Fig. 4.12.5.1 Circuit configuration for resistance measurement mode
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Table 4.12.5.1 shows the condition on the range settings during resistance measurement.
Table 4.12.5.1 Range settings during resistance measurement
E5H
Measurement
D2
D1
D0
Reference resistor terminal
Reference resistance
range
RNG2 RNG1 RNG0
400 Ω
4 kΩ
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
R1
100 Ω
1 kΩ
R2/VI5
R3/VI4
R4/VI3, R6
R5/VI2, R6
R6
40 kΩ
400 kΩ
4 MΩ
40 MΩ
10 kΩ
(1/101 kΩ + 1/10 MΩ)-1
(1/1.11 MΩ + 1/10 MΩ)-1
10 MΩ
The A/ D converter changes the integral resistor setting in the input integral period and the reverse integral
period to perform A/ D conversion for resistance measurement. In each period, the following integral
resistor is used.
Input integral period:
Integral resistor on the BUF1 terminal
Reverse integral period: Parallel connected integral resistors on the BUF1 and BUF2 terminals
Usually a variable resistor should be used as the integral resistor on the BUF2 terminal and it should be
adjusted by actually measuring resistance. Further the resistance on the BUF2 terminal can be found with
the following equation.
RB1 × Rr/10-4
N - Rr/10-4
RB2 = ———————— [Ω]
(Equation 4.12.5.1)
RB1: Integral resistance on the BUF1 terminal (390 kΩ)
RB2: Integral resistance on the BUF2 terminal
Rr: Reference resistance on the R6 terminal (10 MΩ)
N:
Number of clocks during the input integral period (N = fixed at 2185)
The value that is obtained with the above equation is a theoretical value but actually an error is made.
The A/ D converter uses the input from the SGND terminal as the GND level input to integrate the voltage
of the measured resistor during the input integral period. Therefore, the input to the SGND terminal
should be directly connected to the COM port of the DMM (digital multimeter).
4.12.6 Continuity check
Continuity check is done with the same circuit configuration of the 400 Ω range and 4 kΩ range in the
resistance measurement mode. The difference from the resistance measurement mode is that the buzzer
signal is generated according to the measured resistance. The continuity judgment and buzzer signal
generation are automatically done by the internal hardware of the S1C62M20, so software control is not
necessary.
The S1C62M20 judges continuity by comparing both voltage on the measured resistor and reference
resistor using the comparator. The continuity judgment signal from the comparator is input to the buzzer
circuit and then the buzzer signal is generated.
The comparator for continuity judgment goes ON by setting the address E4H (FNC0–FNC2) to the continu-
ity check mode.
The measurement circuit is the same as the 400 Ω range and 4 kΩ range in the resistance measurement
mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Measurement Circuit and Measurement Procedure)
Figure 4.12.6.1 shows the circuit configuration of the continuity check mode.
Measured resistance can be displayed in this mode as the same as the resistance measurement mode.
Vmsr
generator
R2/VI5
R1
SW5
1 kΩ
V
DD
SW11
SW12
SW23
100 Ω
PTC
OVSG
OVX
Comparator
To Buzzer
SGND
COM
S1C62M20
Fig. 4.12.6.1 Circuit configuration of continuity check mode
Table 4.12.6.1 shows the range settings during continuity check mode.
Table 4.12.6.1 Range settings during continuity check mode
E5H
Judgment
resistance
Reference
resistor
Measurement
range
D2
D1
D0
RNG2 RNG1 RNG0
50 Ω
100 Ω
500 Ω
1 kΩ
0
0
0
0
0
0
1
1
0
1
0
1
R1 (100 Ω)
R1 (100 Ω)
400 Ω
4 kΩ
R2/VI5 (1 kΩ)
R2/VI5 (1 kΩ)
When the judgment resistance is 50 Ω or 100 Ω, the circuit configuration is the same as the 400 Ω range in
the resistance measurement mode, and when the judgment resistance is 500 kΩ or 1 kΩ, it is the same as
the 4 kΩ range in the resistance measurement mode.
4.12.7 ADPT (adapter)
This mode functions the same as the 400 mV range in the DC voltmeter mode and performs the A/ D
conversion of the voltage input from the VI terminal. However, ADPT mode does not judge polarity, and
the measurement range is fixed at 400 mV. Therefore, setting the address E5H (RNG0–RNG2) is invalid
and it does not affect the A/ D conversion results.
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4.12.8 Control method
Table 4.12.8.1 lists the A/ D converter’s control bits and their addresses.
Table 4.12.8.1 Control bits of A/D converter
Register
Address
E2H
Comment
*1
D3
D2
D1
D0
Name
BUFF
IIN
Init
0
1
–
0
–
Fix at 0
Current measurement terminal switching
BUFF
IIN
ADSPD
ADON
IIH
IIL
0
100 mS 400 mS A/D conversion speed switching
ADSPD
ADON
0
R/W
On
Off
A/D converter On/Off
Unused
0
*5
*2
*2
0
–
0
FNC2
RNG2
FNC1
R/W
FNC0
RNG0
FNC2
FNC1
FNC0
0
0
E4H
E5H
Measurement function selection *6
Unused
0
R
0
0
*5
–
RNG1
R/W
RNG2
RNG1
RNG0
0
Measurement range selection *6
0
R
0
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
BUFF: (E2H•D3)
This bit must be set to "0". If it is "1", A/ D conversion will not be done correctly.
IIN: Current measurement terminal switching (E2H•D2)
Selects the input terminal for current measurement.
When "1" is written:
When "0" is written:
Reading:
Input from IIH terminal
Input from IIL terminal
Valid
This register is effective only in the ammeter (current measurement) mode.
Either the IIL terminal or the IIH terminal can be selected as an analog input terminal for current measure-
ment. When "1" is written to this register, input from the IIH terminal is A/ D converted. When "0" is
written, input from the IIL terminal is A/ D converted.
By writing to this register, the A/ D converter restarts from the auto zero adjustment period.
At initial reset and in SLEEP mode, this register is set to "0".
FNC0–FNC2: Measurement function selection (E4H•D0–D2)
Switches the measurement function of the S1C62M20. Table 4.12.8.2 shows the measurement function and
the register setting.
Table 4.12.8.2 S1C62M20 measurement function
D3
0
–
D2
D1
D0
Address
Measurement mode
FNC2 FNC1 FNC0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DC voltmeter mode (DCV)
AC voltmeter mode (ACV)
DC ammeter mode (DCA)
AC ammeter mode (ACA)
Resistance measurement mode (Ω)
Continuity check mode (CONT)
–
–
–
–
E4H
–
–
–
–
ADPT mode (ADPT)
* Bit D3 is invalid
The measurement function can be switched by writing data to the registers FNC0–FNC2. These registers
can be read.
By writing to this address (E4H), the A/ D converter restarts from the auto zero adjustment period.
At initial reset and in SLEEP mode, these registers are set to "0".
When SLEEP mode is canceled, set these registers again.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Measurement Circuit and Measurement Procedure)
RNG0–RNG2: Measurement range selection (E5H•D0–D2)
Selects the measurement range as shown in Table 4.12.8.3.
Table 4.12.8.3 Measurement range selection
D3
0
D2
D1
D0
Continuity
Address
E5H
DCV
ACV
DCA
ACA Resistance
ADPT
RNG2 RNG1 RNG0
check
50 Ω
100 Ω
500 Ω
1 kΩ
↑
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
400 mV 400 mV Invalid Invalid
400 Ω
4 kΩ
40 kΩ
400 kΩ
4 MΩ
40 MΩ
↑
Fixed
4 V
40 V
400 V
1000 V
↑
4 V
40 V
400 V
750 V
↑
at DCV
400 mV
range
↑
↑
↑
↑
↑
↑
↑
↑
* Bit D3 is invalid
The measurement range can be switched by writing data to the registers RNG0–RNG2. These registers can
be read.
By writing to this address (E5H), the A/ D converter restarts from the auto zero adjustment period.
At initial reset and in SLEEP mode, these registers are set to "0".
When SLEEP mode is canceled, set these registers again.
4.12.9 Programming notes
(1) The interrupt factor flag may be set when the A/ D conversion setting is changed (writing to E2H, E4H
or E5H) or the CPU enters SLEEP status. Therefore, read (clear) the flag if necessary.
(2) The A/ D converter is automatically set to the auto zero adjustment period when writing is done to the
addresses E2H, E4H (function switching) and E5H (range switching). If the ADON register has been set
to "1" (A/ D converter is ON) at this time, the A/ D conversion restarts with the new settings from the
auto zero adjustment.
(3) The registers on the addresses E2H and E4H to EBH are set to the initial status when the CPU enters
SLEEP mode. Therefore, set the registers again when the CPU reactivates from SLEEP status.
(4) "BUFF" (bit D3 on address E2H) must be set to "0" (initial value). If it is "1", A/ D conversion will not be
done correctly.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (VSS2 Booster)
4.13 VSS2 Booster
4.13.1 Configuration of VSS2 booster
The S1C62M20 has a built-in voltage booster that doubles the supply voltage (VDD–VSSD). This booster
generates the boosted voltage VSS2 by connecting an external capacitor.
The boosted voltage VSS2 is used as the power source for the A/ D converter, analog switch circuit and LCD
driver. Therefore, turn the VSS2 booster ON before turning the A/ D converter or LCD driver ON.
Figure 4.13.1.1 shows the configuration of the VSS2 booster.
S1C62M20
V
DD
DDA
SSD
32.768 kHz
V
V
V
SS2 divider
21.845 kHz
V
SSA
C1
C2
2.2 µF
V
SS2 booster
V
SS2
2.2 µF
Fig. 4.13.1.1 VSS2 booster
The VSS2 booster uses the booster clock generated from the OSC1 oscillation clock (32.768 kHz) by dividing
it by 1/ 3. Besides the VSS2 booster, this divided clock (21.845 kHz) is also used in the A/ D converter and
LCD driver.
4.13.2 Control of VSS2 booster
Table 4.13.2.1 lists the VSS2 booster’s control bit and its address.
Table 4.13.2.1 Control bit of VSS2 booster
Register
Address
E0H
Comment
*1
D3
–
D2
D1
D0
Name
Init
–
1
0
*3
*3
*3
Unused (Undefined when reading)
Unused (Undefined when reading)
Unused (Undefined when reading)
–
–
–
–
VSS2
–
–
–
R
R/W
On
Off
VSS2 booster control
VSS2
0
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
VSS2: VSS2 booster control (E0H•D0)
Turns the VSS2 booster ON and OFF.
When "1" is written:
When "0" is written:
Reading:
VSS2 booster ON
VSS2 booster OFF
Valid
When "1" is written to the VSS2 register, the VSS2 booster starts operating and generates the boosted voltage
VSS2. When "0" is written, the VSS2 booster goes OFF.
At initial reset and in SLEEP mode, this register is set to "0". When SLEEP mode is canceled, set this register
again.
Be aware that the other bits (D1–D3) on the address E0H are undefined when they are read.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (VSS2 Booster)
4.13.3 Programming notes
(1) The A/ D converter and LCD driver use the boosted voltage VSS2. Therefore, turn the VSS2 booster ON
before turning the A/ D converter or LCD driver ON.
Further it is necessary to wait until the VSS2 voltage stabilizes after turning the VSS2 booster ON. Set at
least 30 msec of wait time before turning the A/ D converter or LCD driver ON after turning the VSS2
booster ON (VSS2 = "1").
(2) The bits other than VSS2 (D0) on the address E0H are undefined when reading. Take care when
programming.
(3) When the CPU enters SLEEP status by the SLP instruction, the VSS2 booster is reset to the initial status.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.14 SVD (Supply Voltage Detection) Circuit
4.14.1 Configuration of SVD circuit
The S1C62M20 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the
source voltage lowers. Turning the SVD circuit ON/ OFF can be controlled through the software.
Figure 4.14.1.1 shows the configuration of the SVD circuit.
SVDDT
SVDON
SVD circuit
Fig. 4.14.1.1 Configuration of the SVD circuit
4.14.2 Operation of SVD circuit
The SVD circuit compares the criteria voltage set in the S1C62M20 and the supply voltage (VDD–VSSD) and
sets its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be determined by
means of software whether the supply voltage is normal or has dropped.
The criteria voltage (VSVD) has been set to 2.3 V.
When SVDON is set to "1", source voltage detection by the SVD circuit is executed. As soon as SVDON is
reset to "0", the result is loaded to the SVDDT register and SVD circuit goes OFF.
To obtain a stable SVD detection result, the SVD circuit must be on for at least l00 µsec. However, the
S1C62M20 uses 32.768 kHz CPU system clock, the instruction cycles are long enough, so there is no need to
worry about maintaining 100 µsec.
When SVD is on, the IC draws a large current, so keep SVD off unless it is.
4.14.3 Control of SVD circuit
Table 4.14.3.1 shows the control bits and the address for the SVD circuit.
Table 4.14.3.1 Control bits for SVD circuit
Register
Address
E3H
Comment
*1
D3
0
D2
D1
D0
Name
Init
–
1
0
*5
*2
*2
Unused
Unused
0
0
0
SVDDT SVDON
*5
–
Low
On
Normal Supply voltage detection data
SVD circuit On/Off
SVDDT
SVDON
0
R
R/W
Off
0
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
SVDON: SVD circuit ON/OFF (E3H•D0)
Turns the SVD circuit ON and OFF.
When "1" is written:
When "0" is written:
Reading:
SVD circuit ON
SVD circuit OFF
Valid
When SVDON is set to "1", source voltage detection by the SVD circuit is executed. As soon as SVDON is
reset to "0", the result is loaded to the SVDDT register.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
SVDDT: SVD data (E3H•D1)
This is the result of supply voltage detection.
When "0" is read:
When "1" is read:
Writing:
Supply voltage ≥ Criteria voltage
Supply voltage < Criteria voltage
Invalid
The result of supply voltage detection at time of SVDON is set to "0" can be read from this register.
At initial reset, SVDDT is set to "0".
4.14.4 Programming note
The SVD circuit should normally be turned OFF as the current consumption of the IC becomes large when
it is ON. Turn the SVD circuit OFF when shifting to SLEEP mode in particular.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.15 Interrupt and HALT/SLEEP
<Interrupt types>
The S1C62M20 provides the following interrupt settings, each of which is maskable.
External interrupt:
Internal interrupt:
•Input interrupt (2 systems)
•Timer interrupt (4 systems)
•Serial interface interrupt (1 system)
•A/D converter interrupt (1 system)
To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable).
When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are
inhibited.
Figure 4.15.1 shows the configuration of the interrupt circuit.
<HALT and SLEEP>
The S1C62M20 has HALT and SLEEP functions that considerably reduce the current consumption when it
is not necessary.
The CPU enters HALT status when the HALT instruction is executed.
In HALT status, the operation of the CPU is stopped. However, the oscillation circuit and timer operate.
Reactivating the CPU from HALT status is done by generating an interrupt request. When it does not
reactivate upon an interrupt request, the watchdog timer will cause it to restart from the initial reset status.
When shifted into SLEEP as the result of the SLP instruction, the operation of the CPU is stopped, the same
as for HALT status, and timer also stops. However, the oscillation circuit operates.
Reactivation from SLEEP status can only be done by generation of K port input interrupt request. Conse-
quently, when it shifts to SLEEP status, you must invariably set the input interrupt (K00–K03, K10–K13) to
enable.
When SLEEP status is canceled by a K port input interrupt, the CPU starts operating.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
K00
SIK00
K01
SIK01
IK0
K02
SLEEP cancellation
EIK0
SIK02
K03
SIK03
K10
SIK10
Interrupt
Program counter
(low-order 4 bits)
vector
circuit
K11
SIK11
IK1
K12
EIK1
SIK12
K13
SIK13
INT
(interrupt request)
IAD
EIAD
Interrupt flag
ISIF
EISIF
IT1
Interrupt factor flag
EIT1
Interrupt mask register
IT2
Interrupt selection register
EIT2
IT16
EIT16
IT32
EIT32
Fig. 4.15.1 Configuration of the interrupt circuit
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.15.1 Interrupt factor
Table 4.15.1.1 shows the factors for generating interrupt requests.
The interrupt flags are set to "1" depending on the corresponding interrupt factors.
The CPU operation is interrupted when any of the conditions below set an interrupt factor flag to "1".
• The corresponding mask register is "1" (enabled)
• The interrupt flag is "1" (EI)
The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read out.
At initial reset, the interrupt factor flags are reset to "0".
Table 4.15.1.1 Interrupt factors
Interrupt factor
Clock timer 1 Hz (falling edge)
Interrupt factor flag
IT1
(F5H•D3)
(F5H•D2)
(F5H•D1)
(F5H•D0)
(F2H•D0)
(F3H•D0)
(F4H•D0)
(F6H•D0)
Clock timer 2 Hz (falling edge)
Clock timer 16 Hz (falling edge)
Clock timer 32 Hz (falling edge)
K10–K13 input (rising edge)
K00–K03 input (rising edge)
IT2
IT16
IT32
IK1
IK0
Serial interface (8-bit data input/output has completed) ISIF
A/D converter (reverse integral has completed) IAD
Note: Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1",
an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request
will not be generated. Be very careful when interrupt factor flags are in the same address.
4.15.2 Interrupt mask
The interrupt factor flags can be masked by the corresponding interrupt mask registers.
The interrupt mask registers are read/ write registers. They are enabled (interrupt authorized) when "1" is
written to them, and masked (interrupt inhibited) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.15.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.
Table 4.15.2.1 Interrupt mask registers and interrupt factor flags
Interrupt mask register
Interrupt factor flag
EIT1
(F1H•D3)
(F1H•D2)
(F1H•D1)
(F1H•D0)
(F0H•D3)
(F0H•D2)
(F0H•D1)
(F0H•D0)
IT1
(F5H•D3)
(F5H•D2)
(F5H•D1)
(F5H•D0)
(F2H•D0)
(F3H•D0)
(F4H•D0)
(F6H•D0)
EIT2
IT2
EIT16
EIT32
EIK1
EIK0
EISIF
EIAD
IT16
IT32
IK1
IK0
ISIF
IAD
Note: Write the interrupt mask register only in the DI status (interrupt flag = "0"). Writing during EI status
(interrupt flag = "1") will cause malfunction.
4.15.3 Interrupt vector
When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program
being executed is terminated, the interrupt processing is executed in the following order.
➀ The address data (value of program counter) of the program to be executed next is saved in the stack
area (RAM).
➀ The interrupt request causes the value of the interrupt vector (page 1, 02H–0AH) to be set in the
program counter.
➀
The program at the specified address is executed (execution of interrupt processing routine by software).
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Table 4.15.3.1 shows the correspondence of interrupt requests and interrupt vectors.
Note: The processing in ➀ and ➀ above take 12 cycles of the CPU system clock.
Table 4.15.3.1 Interrupt request and interrupt vectors
Interrupt vector
102H
Interrupt request
K10–K13 input
K00–K03 input
Serial interface
Clock timer
Priority
High
↑
104H
106H
108H
↓
10AH
A/D converter
Low
When multiple interrupts simultaneously occur, processing is done from the high priority interrupt.
The four low-order bits of the program counter are indirectly addressed through the interrupt request.
4.15.4 Control of interrupt
Tables 4.15.4.1 shows the interrupt control bits and their addresses.
Table 4.15.4.1 Control bits of interrupt
Register
Address
F0H
Comment
*1
D3
D2
D1
D0
Name
EIK1
Init
0
0
0
0
0
0
0
0
–
–
–
0
–
–
–
0
–
–
–
0
0
0
0
0
–
–
–
0
1
0
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Mask
Interrupt mask register (K10–K13)
Interrupt mask register (K00–K03)
Interrupt mask register (Serial interface)
Interrupt mask register (A/D converter)
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 16 Hz)
Interrupt mask register (Clock timer 32 Hz)
Unused
EIK1
EIK0
EISIF
EIAD
EIK0
EISIF
EIAD
EIT1
R/W
R/W
R
EIT1
0
EIT2
0
EIT16
EIT32
IK1
EIT2
F1H
F2H
F3H
F4H
F5H
F6H
EIT16
EIT32
*5
*2
*2
*2
0
0
0
0
*5
*5
*4
*5
*5
*5
*4
*5
*5
*5
*4
*4
*4
*4
*4
*5
*5
*5
*4
Unused
Unused
0
Yes
Yes
No
No
Interrupt factor flag (K10–K13)
Unused
IK1
0
*2
*2
*2
0
0
IK0
Unused
0
Unused
0
R
Interrupt factor flag (K00–K03)
Unused
IK0
0
*2
*2
*2
0
0
0
ISIF
IT32
IAD
Unused
0
Unused
0
R
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Interrupt factor flag (Serial interface)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 16 Hz)
Interrupt factor flag (Clock timer 32 Hz)
Unused
ISIF
IT1
IT2
IT16
IT32
0
IT1
0
IT2
0
IT16
0
R
*2
*2
*2
Unused
0
Unused
0
R
Yes
No
Interrupt factor flag (A/D converter)
IAD
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Resets (0) immediately after being read
*5 Constantly "0" when being read
*6 Refer to main manual
For control of the registers, see the following sections:
Section 4.4, "Input Ports"
Section 4.9, "Clock Timer"
Section 4.10, "Serial Interface"
Section 4.11, "A/ D Converter"
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.15.5 Programming notes
(1) When shifting to SLEEP status, at least either K00–K03 or K10–K13 interrupt must be set to enable
canceling SLEEP status.
(2) In the S1C62M20, the OSC1 oscillation circuit keeps operating even in SLEEP status.
(3) The interrupt factor flags are set when the timing condition is established, even if the interrupt mask
registers are set to "0".
(4) Write the interrupt mask register only in the DI status (interrupt flag = "0"). Writing during EI status
(interrupt flag = "1") will cause malfunction.
(5) Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will
not be generated. Be very careful when interrupt factor flags are in the same address.
(6) When the CPU enters SLEEP status, the following circuits are set to the initial status.
• Clock timer/ Watchdog timer
• VSS2 booster
• LCD driver
• A/ D converter
These circuits should be re-set after returning from SLEEP status.
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CHAPTER 5: SUMMARY OF NOTES
CHAPTER 5 SUMMARY OF NOTES
5.1 Notes for Low Current Consumption
The S1C62M20 contains control registers for each of the circuits so that current consumption can be low-
ered. These control registers lower the current consumption through programs that operate the circuits at
the minimum levels.
The following explains the circuits that can control operation and their control registers. Refer to these
when programming.
Table 5.1.1 Circuits and control registers
Circuit (and Item)
CPU
SS2 booster
Control register
SLP instruction, HALT instruction
V
VSS2
LCD driver
A/D converter
SVD circuit
LPWR
ADON
SVDON
See Chapter 7, "ELECTRICAL CHARACTERISTICS", for order of current consumption.
Below are the circuit statuses at initial reset.
CPU:
VSS2 booster:
LCD driver:
Operating status
OFF status
OFF status
A/ D converter: OFF status
SVD circuit: OFF status
When the CPU enters SLEEP status, the following circuits are set to the initial status.
• Clock timer/ Watchdog timer
• VSS2 booster
• LCD driver
• A/ D converter
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CHAPTER 5: SUMMARY OF NOTES
5.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mind when
programming.
Memory
Memory is not mounted in unused area within the memory map and in memory area not indicated in this
manual. For this reason, normal operation cannot be assured for programs that have been prepared with
access to these area.
Watchdog timer
The watchdog timer must be reset within 3-second cycles.
Oscillation circuit
In the S1C62M20, the OSC1 oscillation circuit does not stop even when the CPU enters SLEEP status.
However, SLEEP stops supplying the clock to the peripheral circuits (timer and watchdog timer).
Input ports
When input ports are changed from high to low by pull down resistor, the fall of the waveform is delayed
on account of the time constant of the pull down resistor and input gate capacitance. Hence, when fetching
input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull down resistance 300 kΩ
I/O ports
When in the input mode, I/ O ports are changed from high to low by pull down resistor, the fall of the
waveform is delayed on account of the time constant of the pull down resistor and input gate capacitance.
Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 10 pF + parasitic capacitance ? pF
R: pull down resistance 300 kΩ
LCD driver
(1) The contents of the display memory are undefined until the area is initialized (through, for instance,
memory clear processing by the CPU). Initialize the display memory by executing initial processing.
(2) Since the display memory area is write-only, display data cannot be rewritten by arithmetic operations
(such as AND, OR, ADD, SUB).
(3) The power source for the LCD power generator (VL1, VL2 and VL3 generation circuit) and the operating
clock for the LCD drive timing generator are supplied from the VSS2 booster. Therefore, be sure to turn
the VSS2 booster ON by setting the VSS2 register to "1" before turning the LCD driver ON (LPWR = "1").
(4) The control registers (LOFF, LDTY, LPWR) for the LCD driver are automatically set to the initial status
when the CPU enters SLEEP status using the SLP instruction. Therefore, after returning from SLEEP
status, set the registers’ value again.
In SLEEP status, the VSS2 booster turns OFF.
Clock timer
(1) Be sure to read data in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).
(2) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Conse-
quently, perform flag reading (reset the flag) as necessary at reset.
(3) The clock timer is reset when the CPU enters SLEEP status by the SLP instruction.
(4) When the clock timer has been reset, the watchdog timer is also reset.
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CHAPTER 5: SUMMARY OF NOTES
Serial interface
(1) Perform data writing/ reading to data registers SD0–SD7 only while the serial interface is halted (i.e.,
the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be per-
formed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through
data writing/ reading on data registers SD0–SD7.) Supply trigger only once every time the serial
interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock,
start to input the external clock after the trigger.
A/D converter
(1) Be sure to check whether the data is effective or invalid by reading the A/ D conversion data in the
order F7H → F8H → F9H → FAH and immediately thereafter reading the IDR.
(2) The interrupt factor flag may be set when the A/ D conversion setting is changed (writing to E2H, E4H
or E5H) or the CPU enters SLEEP status. Therefore, read (clear) the flag if necessary.
(3) The A/ D converter is automatically set to the auto zero adjustment period when writing is done to the
addresses E2H, E4H (function switching) and E5H (range switching). If the ADON register has been set
to "1" (A/ D converter is ON) at this time, the A/ D conversion restarts with the new settings from the
auto zero adjustment.
(4) The registers on the addresses E2H and E4H to EBH are set to initial status when the CPU enters SLEEP
mode. Therefore, set the registers again when the CPU reactivates from SLEEP status.
Measurment circuit and measurment procedure
(1) The interrupt factor flag may be set when the A/ D conversion setting is changed (writing to E2H, E4H
or E5H) or the CPU enters SLEEP status. Therefore, read (clear) the flag if necessary.
(2) The A/ D converter is automatically set to the auto zero adjustment period when writing is done to the
addresses E2H, E4H (function switching) and E5H (range switching). If the ADON register has been set
to "1" (A/ D converter is ON) at this time, the A/ D conversion restarts with the new settings from the
auto zero adjustment.
(3) The registers on the addresses E2H and E4H to EBH are set to the initial status when the CPU enters
SLEEP mode. Therefore, set the registers again when the CPU reactivates from SLEEP status.
VSS2 booster
(1) The A/ D converter and LCD driver use the boosted voltage VSS2. Therefore, turn the VSS2 booster ON
before turning the A/ D converter or LCD driver ON.
Further it is necessary to wait until the VSS2 voltage stabilizes after turning the VSS2 booster ON. Set at
least 30 msec of wait time before turning the A/ D converter or LCD driver ON after turning the VSS2
booster ON (VSS2 = "1").
(2) The bits other than VSS2 (D0) on the address E0H are undefined when reading. Take care when
programming.
(3) When the CPU enters SLEEP status by the SLP instruction, the VSS2 booster is reset to the initial status.
SVD circuit
The SVD circuit should normally be turned OFF as the current consumption of the IC becomes large when
it is ON. Turn the SVD circuit OFF when shifting to SLEEP mode in particular.
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CHAPTER 5: SUMMARY OF NOTES
Interrupt and HALT/SLEEP
(1) When shifting to SLEEP status, at least either K00–K03 or K10–K13 interrupt must be set to enable
canceling SLEEP status.
(2) In the S1C62M20, the OSC1 oscillation circuit keeps operating even in SLEEP status.
(3) The interrupt factor flags are set when the timing condition is established, even if the interrupt mask
registers are set to "0".
(4) Write the interrupt mask register only in the DI status (interrupt flag = "0"). Writing during EI status
(interrupt flag = "1") will cause malfunction.
(5) Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will
not be generated. Be very careful when interrupt factor flags are in the same address.
(6) When the CPU enters SLEEP status, the following circuits are set to the initial status.
• Clock timer/ Watchdog timer
• VSS2 booster
• LCD driver
• A/ D converter
These circuits should be re-set after returning from SLEEP status.
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CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS
CHAPTER 6 DIAGRAM OF BASIC EXTERNAL
CONNECTIONS
LCD Panel
Parts
Value
SR
80
75
70
65
60
SEG15
COM0
COM1
COM2
COM3
P02
P01
P00
BZ
1
CL1
0.047 µF
0.047 µF
0.047 µF
0.33 µF
2.2 µF
2.2 µF
0.22 µF
0.1 µF
2.2 µF
2.2 µF
0.22 µF
0.1 µF
0.1 µF
0.1 µF
0.01 µF
0.1 µF
82 kΩ 1.0 %
22 kΩ 1.0 %
120 kΩ 1.0 %
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
L2
R
BZ2
BZ1
L3
SR
B1
B2
R
BZ
Index
R
CL1
CL2
CL3
VL1
VL2
VL3
VDD
R03
R02
R01
R00
K13
K12
K11
K10
K03
K02
K01
K00
R6
5
AC1
AC2
AC3
AC4
AC5
AZ
1
CSR
OSC1
OSC2
RESET
TEST
55
50
X'tal
CPWR
3.6V
10
15
S1C62M20
Key scan
circuit
VSSD
+
C1
C2
FI
C
B1
I
C
B2
V
V
V
V
V
V
SS2
+
R1
R2
R3
R4
AC1
AC2
AC3
AC4
AC5
AC6
AC7
B1
B2
B3
VI
R
R
R
R
R
R
6
5
4
3
2
1
DDA
SSA
ADJ
RF1
RF2
R5/VI2
R4/VI3
R3/VI4
R2/VI5
R1
218.5 mV
1.00 V
45
40
75~412 kΩ
RR2 RR4
20
25
22 MΩ 1.0 %
21 kΩ 1.0 %
500 kΩ
22 kΩ 1.0 %
22 kΩ 1.0 %
330 kΩ 1.0 %
330 kΩ 1.0 %
390 kΩ 0.1 %
-329 kΩ
RR1 RR3
CH
CL
DCV
ACV
CR
OVSG
30
35
ROVSG
Ω
Cont
C1
RAC1
CAC5
39 kΩ 0.1 %
10 MΩ 0.1 %
1 MΩ
CAC1
PTC 1k
R
AC2
AC3
R
AC4
R
AC6
OVX
OVSG
1
CAC4
680 kΩ
R
RAC5
RAC7
100 Ω 0.1 %
1 kΩ 0.1 %
10 kΩ 0.1 %
101 kΩ 0.1 %
1.11 MΩ 0.1 %
10 MΩ 0.1 %
100 Ω
2
CAC2
CAC3
3
4
5
RI6
R
I5
R
I4
RI3
RI2
6
BZ1
BZ2
I1
R
I1
100 Ω
0.01 Ω 0.5 %
0.09 Ω 0.5 %
0.9 Ω 0.5 %
9 Ω 0.5 %
90 Ω 0.5 %
900 Ω 0.5 %
1 kΩ
I2
DCV
ACV
Ω
I3
I4
OPEN
CONT
I5
DCV
ACV
Cont
Ω
Fuse
I6
110V,0.3A
PTC
DCA, ACA
4A, 10A
COM
V
Ω
Cont
Note: The above table is simply an example, and is not guaranteed to work.
82
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S1C62M20 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
CHAPTER 7 ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Rating
(VDD/VDDA = 0 V)
Item
Symbol
Rated value
Unit
V
Power voltage
Input voltage
VDD/VDDA
0
V
V
V
V
SSD/VSSA
-3.5
V
SS2
I1
-7.0
V
V
SSD system
(VSSD/VSSA - 0.3) to (VDD/VDDA + 0.3)
V
VSS2 system
*1
I2
(VSS2 - 0.3) to (VDD/VDDA + 0.3)
V
Permissible total output current
Operating temperature (1)
ΣI
10
-20 to 70
mA
°C
°C
°C
–
Topr
Topr
Tstg
Tsol
1
*2
Operating temperature (2)
2
0 to 40
Strage temperature
-65 to 150
Soldering temperature / time
260°C, 10sec (lead section)
250
*3
Permissible disspation
PD
mW
*1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the
output pins (or is drawn in).
*2 The A/D converter is ON status.
*3 In case of plastic package (QFP5-80pin, QFP14-80pin).
7.2 Recommended Operating Conditions
Item
Power voltage
Symbol
Condition
Min.
-3.5
–
Typ.
-3.0
Max.
-2.15
–
Unit
V
VSSD/VSSA
VDD/VDDA = 0 V
Oscillation frequency
Measurement system
operating temperature
f
OSC1
32.768
25
kHz
°C
Tmes
During measurment by the A/D converter
15
35
S1C62M20 TECHNICAL MANUAL
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83
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.3 DC Characteristics
Unless otherwise specified:
VDD/VDDA = 0 V, VSSD/VSSA = -3.0 V, fOSC1 = 32.768 kHz, Ta = 25°C, VL1/VL2/VL3 are internal voltage
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
High level input voltage (1)
VIH1
K00–K03, K10–K13 0.1·VSSD
VDD
V
RESET, TEST
High level input voltage (2)
Low level input voltage (1)
VIH2
VIL1
P00–P03
0.1·VSSD
VDD
V
V
K00–K03, K10–K13
RESET, TEST
P00–P03
VSSD
0.9·VSSD
Low level input voltage (2)
High level input current (1)
VIL2
IIH1
VSSD
0.9·VSSD
V
VIH1 = VDD
K00–K03, K10–K13
P00–P03
0
0.5
µA
VSSD = -3.0 V
Without pull down resistor RESET, TEST
High level input current (2)
Low level input current
IIH2
IIL
VIH2 = VDD
K00–K03, K10–K13
P00–P03
5
10
20
0
µA
µA
VSSD = -3.0 V
With pull down resistor RESET, TEST
VIL = VSSD = -3.0 V
K00–K03, K10–K13
-0.5
P00–P03
RESET, TEST
R00–R03
P00–P03
High level output current (1) IOH1
High level output current (2) IOH2
VOH1 = 0.1·VSSD
VSSD = -3.0 V
-0.9
-1.2
mA
mA
mA
mA
VOH2 = 0.1·VSSD
VSSD = -3.0 V
BZ, BZ
Low level output current (1)
Low level output current (2)
Common output current
IOL1
IOL2
VOL1 = 0.9·VSSD
VSSD = -3.0 V
R00–R03
P00–P03
BZ, BZ
3.0
3.5
VOL2 = 0.9·VSSD
VSSD = -3.0 V
IOH3
IOL3
IOH4
IOL4
IOH5
IOL5
VOH3 = VDD - 0.05 V
VOL3 = VL3 + 0.05 V
VOH4 = VDD - 0.05 V
VOL4 = VL3 + 0.05 V
VOH5 = 0.1·VSSD
VOL5 = 0.9·VSSD
COM0–COM3
SEG0–SEG15
SEG0–SEG15
-3.0
-3.0
50
µA
µA
µA
µA
µA
µA
3.0
3.0
-70
Segment output current
(during LCD output)
Segment output current
(during DC output)
84
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S1C62M20 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.4 Analog Characteristics and Current Consumption
Unless otherwise specified:
VDD/VDDA = 0 V, VSSD/VSSA = -3.0 V, fOSC1 = 32.768 kHz, Ta = 25°C, VL1/VL2/VL3 are internal voltage
Item
Symbol
Condition
Connect 1 MΩ load resistor between VDD and VL1
CL1 = 0.047 µF
Min.
Typ.
Max.
Unit
LCD drive voltage
VL1
-1.15
-1.05
-0.95
V
VL2
VL3
Connect 1 MΩ load resistor between VDD and VL2
CL2 = 0.047 µF
-2.20
-3.25
-2.45
-2.10
-3.15
-2.30
-2.00
-3.05
V
V
Connect 1 MΩ load resistor between VDD and VL3
CL3 = 0.047 µF
SVD voltage
VSVD
tSVD
IOP
-2.15
100
4.0
V
SVD circuit response time
Power current consumption
µS
During SLEEP
VSSD/VSSA = -3.0 V
VSSD/VSSA = -3.0 V
VSSD/VSSA = -3.0 V
VSSD/VSSA = -3.0 V
1.5
3.0
0.9
1.1
µA
µA
mA
mA
During HALT
6.0
*1
*2
During A/D operation
During A/D operation
2.0
2.2
*1 DCV and DCA measurement mode.
*2 ACV and ACA measurement mode. (The general AMP is ON status.)
A/D converter (Characteristics of A/D converter unit only)
Unless otherwise specified:
VDD/VDDA = 0 V, VSSD/VSSA = -3.0 V, fOSC1 = 32.768 kHz, Ta = 25°C, VL1/VL2/VL3 are internal voltage
Item
Sampling time
Symbol
St1
Condition
Min.
Typ.
100
10
Max.
Unit
mS
mS
/S
A/D conversion in normal mode
A/D conversion in high speed mode
A/D conversion in normal mode
A/D conversion in high speed mode
A/D conversion in normal mode
A/D conversion in normal mode
A/D conversion in normal mode
St2
Sampling rate
Sr1
Sr2
LIN
EP
2.5
10
/S
Linearity error
Polarity error
Zero point error
Voltage range
-0.2
-2
0.2
+2
+2
%FS
dgt
dgt
V
ZOFF
-2
*1
VSSD/VSSA VDD = VDDA = 0 V
-3.5
VSVD
*1 VSVD: SVD judgment voltage
Reference voltage generator
Unless otherwise specified:
VDD/VDDA = 0 V, VSSD/VSSA = -3.0 V, fOSC1 = 32.768 kHz, Ta = 25°C, VL1/VL2/VL3 are internal voltage
Item
Symbol
Condition
Min.
-300
-0.1
400
Typ.
Max.
300
0.1
Unit
ppm/deg
%
Temperature characteristics
VrefT 0 to 40°C
0
Supply voltage characteristics VrefV VSSA (VSSD) = -2.15 to -3.5 V
Reference voltage output
Vref1 Short-circuit between VRF1 and VADJ terminals
780
mV
Voltage between VRF1 and VSSA
Connect 70 kΩ load resistor between VRF1 and VSSA
Output voltage during
resistance measurement
Vrmes VRF1 - VSSA = 1.0 V
400 Ω range
4 kΩ range
VDDA
0.7
V
V
V
V
V
V
(Output voltages are values
in case of VSSA standard)
40 kΩ range
400 kΩ range
4 MΩ range
40 MΩ range
0.47
0.47
0.47
0.47
S1C62M20 TECHNICAL MANUAL
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85
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.5 Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern, etc.).
Use the following characteristics as reference values.
Unless otherwise specified:
VDD/VDDA = 0 V, VSSD/VSSA = -3.0 V, Crystal: Q13MC146, CG = CD = built-in, fOSC1 = 32.768 kHz, Ta = 25°C
Item
Symbol
Vsta
Condition
Min.
Typ.
Max.
-2.15
-1.8
Unit
V
Oscillation start voltage
Oscillation stop voltage
t
t
sta ≤ 3 sec
Vstp
stp ≤ 10 sec
V
Built-in capacitance (gate)
Built-in capacitance (drain)
Harmonic oscillation start voltage
Permitted leak resistance
C
C
G
D
20
15
pF
pF
V
V
hho
-3.5
R
leak
200
MΩ
86
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S1C62M20 TECHNICAL MANUAL
CHAPTER 8: PACKAGE
CHAPTER 8 PACKAGE
8.1 Plastic Package
QFP5-80pin
(Unit: mm)
25.6±0.4
20±0.1
64
41
65
40
INDEX
25
80
1
24
0.8
0.35±0.1
0.15±0.05
0°
12°
1.5
2.8
S1C62M20 TECHNICAL MANUAL
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87
CHAPTER 8: PACKAGE
QFP14-80pin
(Unit: mm)
14±0.4
12±0.1
60
41
61
40
INDEX
80
21
1
20
+0.1
–0.05
0.5
0.18
0.125–+00..00255
0°
10°
0.5±0.2
1
88
EPSON
S1C62M20 TECHNICAL MANUAL
CHAPTER 8: PACKAGE
8.2 Ceramic Package for Test Samples
QFP5-80pin
(Unit: mm)
26.8 ± 0.15
20.0 ± 0.18
64
41
65
40
80
25
1
24
0.80 ± 0.05
0.35 ± 0.05
Grass
Note: The QFP14-80pin ceramic package is not available for test samples.
S1C62M20 TECHNICAL MANUAL
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89
CHAPTER 9: PAD LAYOUT
CHAPTER 9 PAD LAYOUT
9.1 Diagram of Pad Layout
80
75
20
15
10
5
1
25
Y
30
35
70
X
(0, 0)
65
60
40
45
50
55
4.32 mm
Chip thickness: 400 µm
Pad opening: 100 µm
An N channel silicon wafer is used, therefore the potential of the back of the IC should be the same as the
VDD when mounting the chip.
90
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S1C62M20 TECHNICAL MANUAL
CHAPTER 9: PAD LAYOUT
9.2 Pad Coordinates
(Unit: mm)
Pad
Coordinate
Pad
Coordinate
No.
1
2
3
4
5
6
7
8
Name
CH
CL
ADI
ADO
AVX1
AVX2
CO
CAZ
CI
BUF1
BUF2
BUF3
IIL
X
1.658
1.497
1.015
0.855
0.694
0.534
0.373
0.213
Y
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
X
Y
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
2.175
1.872
1.712
1.551
1.391
1.231
0.884
0.724
0.563
0.403
0.243
0.082
-0.078
-0.239
-0.465
-0.625
-0.786
-0.946
-1.106
-1.407
-1.567
P01/SOUT
P02/SCLK
P03/SRDY
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
COM1
COM2
COM3
VL1
-1.995
-1.995
-1.995
-0.703
-0.543
-0.382
-0.222
-0.061
0.099
0.259
0.420
0.580
0.741
0.901
1.061
1.222
1.437
1.670
1.831
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
1.995
-1.727
-1.887
-2.048
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-2.175
-1.585
-1.424
-1.264
-1.103
-0.934
-0.774
-0.613
-0.423
-0.235
-0.075
0.086
0.576
0.759
0.947
1.112
1.279
1.440
1.600
1.768
1.928
2.089
9
0.053
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
-0.108
-0.268
-0.429
-0.589
-0.749
-0.910
-1.070
-1.231
-1.391
-1.551
-1.712
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
-1.995
IIH
CFI
SGND
VI
OVX
OVSG
R1
R2/VI5
R3/VI4
R4/VI3
R5/VI2
R6
K00
K01
K02
K03
K10
K11
K12
K13
VL2
VL3
VDD
OSC1
OSC2
RESET
TEST
VSSD
C1
C2
VSS2
R00
R01
R02
R03
BZ
BZ
P00/SIN
VDDA
VSSA
VADJ
VRF1
VRF2
S1C62M20 TECHNICAL MANUAL
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91
REFERENCE DATA
REFERENCE DATA
This section presents an example of the DMM specification that can be realized by the S1C62M20. (Note
that data does not guaranty the characteristics.)
1. Electrical Specification
Temperature:
Humidity:
18°C to 35°C (except for 40 MΩ range in resistance measurement)
80%
Operating voltage: (VDD/ VDDA) - (VSSD/ VSSA) = VSVD to 3.5 [V]
Note: 1. Accuracy .... ± % of reading, ± number of least digits
2. This accuracy is an efficiency value for finished goods. (When reference resistors and
other parts which have precision reading shown in Chapter 6, "DIAGRAM OF BASIC
CONNECTIONS" are used.
3. VSVD .... SVD judgment voltage
1.1 DC Voltmeter
Reading
(Max. reading)
Resolution
Accuracy
399.9 mV
3.999 V
39.99 V
399.9 V
1000 V
100 µV
1 mV
± (0.5% + 1)
± (0.8% + 1)
± (0.8% + 1)
± (0.8% + 1)
± (0.8% + 1)
10 mV
100 mV
1 V
Input impedance:
Precision for reference resistor: 0.1%
10 MΩ
Response time:
Frequency (Hz)
2 seconds maximum
1.2 AC Voltmeter
Reading
(Max. reading)
Resolution
Accuracy
399.9 mV
3.999 V
39.99 V
399.9 V
750 V
100 µV
1 mV
± (1.5% + 3)
± (1.2% + 3)
± (1.2% + 3)
± (1.2% + 3)
± (1.2% + 3)
40–100
40–500
40–500
40–500
40–500
10 mV
100 mV
1 V
Input impedance:
10 MΩ
Precision for reference resistor:
Response time:
0.1%
2 seconds maximum
AC-DC conversion rectification method: Mean value detection, effective value indication
1.3 DC Ammeter
Reading
(Max. reading)
Resolution
Accuracy
Input resistor
399.9 µA
3.999 mA
39.99 mA
399.9 mA
3.999 A
100 nA
1 µA
± (1.0% + 2)
± (1.0% + 2)
± (1.0% + 2)
± (1.0% + 2)
± (1.5% + 2)
± (1.5% + 2)
1 kΩ
100 Ω
10 Ω
10 µA
100 µA
1 mA
1 Ω
0.1 Ω
0.01 Ω
10.00 A
10 mA
Maximum input current:
400 µA to 400 mA ... protected by fuse 0.5A
4 A, 10 A ................. Unfused
Precision for reference resistor: 0.5%
92
EPSON
S1C62M20 TECHNICAL MANUAL
REFERENCE DATA
1.4 AC Ammeter
Reading
(Max. reading)
Resolution
Accuracy
Input resistor
399.9 µA
3.999 mA
39.99 mA
399.9 mA
3.999 A
100 nA
1 µA
± (1.3% + 5)
± (1.3% + 5)
± (1.3% + 5)
± (1.3% + 5)
± (1.8% + 5)
± (1.8% + 5)
1 kΩ
100 Ω
10 Ω
10 µA
100 µA
1 mA
1 Ω
0.1 Ω
0.01 Ω
10.00 A
10 mA
Maximum input current:
400 µA to 400 mA ... protected by fuse 0.5A
4 A, 10 A ................. Unfused
0.5%
Precision for reference resistor:
AC-DC conversion rectification method: Mean value detection, effective value indication
1.5 Resistance
Reading
(Max. reading)
Measurement
voltage / current
Resolution
Accuracy
399.9 Ω
3.999 kΩ
39.99 kΩ
399.9 kΩ
3.999 MΩ
39.99 MΩ
100 mΩ
1 Ω
± (0.7% + 2)
± (0.7% + 2)
V
DDA 1.2 mA or less
0.7 V (TYP) 0.7 mA or less
10 Ω
± (0.7% + 2) 0.47 V (TYP) 0.7 mA or less
± (0.7% + 2) 0.47 V (TYP) 0.7 mA or less
± (1.0% + 2) 0.47 V (TYP) 0.7 mA or less
± (1.5% + 2) 0.47 V (TYP) 0.7 mA or less
100 Ω
1 kΩ
10 kΩ
Precision for reference resistor:
Response time:
0.1%
5 seconds maximum on 40 MΩ range
2 seconds maximum on all other ranges
Note: Temperature range for 40 MΩ is 18°C to 30°C.
1.6 Continuity check
Continuity check is done within the 400 Ω range or 4 kΩ range in the resistance measurement mode.
Buzzer control during the continuity check is done by the hardware. The hardware judges continu-
ity when the measured resistance is less than the threshold resistance for continuity sound genera-
tion, and generates continuity sound.
Reading
(Max. reading)
Continuity sound
generation resistance voltage
Release
Resolution
399.9 Ω
100 mΩ
50 Ω ± 30 Ω VDDA
Note: 50 Ω, 100 Ω, 500 Ω or 1 kΩ can be selected for the continuity sound generation resistance
by the software.
S1C62M20 TECHNICAL MANUAL
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93
REFERENCE DATA
2. Notes
The following shows the notes when using the S1C62M20 for DMM.
2.1 40 MΩ range during resistance measurement
When a resistance of about 40 MΩ is measured in the 40 MΩ range, the measurement error increases under
the influence of the diode leak inside of the S1C62M20 if the temperature becomes high. Therefore, the
measurable temperature range of the 40 MΩ range narrows on the high temperature side.
2.2 Frequency characteristic of AC voltage
In the 400 mV range during AC voltage measurement, the frequency characteristic is 40 Hz to 100 Hz. The
other ranges are 40 Hz to 500 Hz.
2.3 Reference voltage setting
The reference voltage should be set as follows: VRF1 = 1.0 V and VRF2 = 218.5 mV.
If the VRF1 voltage is too higher, measurement error increases during resistance measurement. If the VRF1
voltage is too low, measurement result does not stabilize during resistance measurement.
The VRF1 output voltage when the VRF1 terminal and VADJ terminal are shorted is 0.40 to 0.78 V.
2.4 Connection of SGND
The S1C62M20 uses the input from the SGND terminal as the GND level input to the A/ D converter. The
SGND terminal should be connected directly to the COM port of the DMM to increase the accuracy of A/ D
conversion. Measurement accuracy decreases if the COM port is connected to the SGND terminal via the
line in which the large current flows, particularly during current measurement.
4A
4A
i
i
SGND
r
COM
COM
SGND
94
EPSON
S1C62M20 TECHNICAL MANUAL
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
EPSON (CHINA) CO., LTD.
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Electronic Device Marketing Department
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In pursuit of “Saving”Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
assists in creating the products of our customers’ dreams.
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S1C62M20
Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
First issue September, 1997
M
Printed March, 2001 in Japan
A
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