SED1640D0B_技术文档

The information of the product number change

Starting April 1, 2001 the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

Configuration of product number

●DEVICES

S1

D

16006

D

00A0 00

Packing specification

Specifications

Shape (D:Chip, T:TCP)

Model number

Model name (D:LCD Driver)

Product classification (S1:Semiconductors)

Comparison table between new and previous number

Previous number

SED1606D0A

SED1606D0B

SED1606F0A

SED1606D1A

SED1606D1B

SED1640D0B

SED1651D0A

SED1670D0A

SED1670D1A

SED1670D0B

SED1670D1B

SED1672D0A

SED1672D1A

SED1672D0B

SED1672D1B

SED1672F0A

New number

S1D16006D00A

S1D16006D00B

S1D16006F00A

*

S1D16006D01A

*

S1D16006D01B

S1D16400D00B

S1D16501D00A

S1D16700D00A

S1D16700D01A

S1D16700D00B

S1D16700D01B

S1D16702D00A

S1D16702D01A

S1D16702D00B

S1D16702D01B

S1D16702F00A

*

CONTENTS

S1D 16000 series Selection Guide

S1D 16006...................................................... 1-1

S1D 16400...................................................... 2-1

S1D 16501...................................................... 3-1

S1D 16700...................................................... 4-1

S1D 16702...................................................... 5-1

Selection Guide

S1D16000 (SED1600) series

Á Segment drivers

Supply voltage LCD voltage

Part number

Duty

Data bus

Package

Outputs

range (V)

S1D16006D00A

(SED1606D0A)

S1D16006D00B

(SED1606D0B)

S1D16006F00A

*

Al pad chip (for COB)

Au bump chip

*

2.7 to 5.5

8 to 28

80

1/100 to 1/300

4-bit parallel

QFP5-100pin

(SED1606F^1A)

S1D16006D01A

(SED1606D1A)

S1D16006D01B

(SED1606D1B)

S1D16400D00B

(SED1640D^0B)

*

Al pad chip (DOFF type)

Au bump chip (DOFF type)

Au bump chip (slim chip)

1/100 to 1/300

80

2.7 to 5.5

8 to 28

Á Common drivers

Supply voltage

LCD voltage

range (V)

Duty

Package

Part number

Outputs

100

range (V)

S1D16501D00A

(SED1651D^0A)

S1D16700D00A

(SED1670D0A)

S1D16700D01A

(SED1670D1A)

S1D16700D00B

(SED1670D0B)

S1D16700D01B

(SED1670D1B)

S1D16702D00A

(SED1672D0A)

S1D16702D01A

(SED1672D1A)

S1D16702D00B

(SED1672D^0B)

S1D16702D01B

(SED1672D1B)

S1D16702F00A

*

Al pad chip (zigzag positioning)

Al pad chip (INH type)

2.7 to 5.5

8 to 28

1/64 to 1/300

Al pad chip (DOFF type)

Au bump chip (INH type)

Au bump chip (DOFF type)

Al pad chip (INH type)

100

1/64 to 1/300

2.7 to 5.5

8 to 28

Al pad chip (DOFF type)

Au bump chip (INH type)

Au bump chip (DOFF type)

QFP5-80pin (INH type)

1/64 to 1/300

68

2.7 to 5.5

8 to 28

*

(SED1672F0A)

S1D16006 Series

Rev.2.1

CONTENTS

1. DESCRIPTION ...............................................................................................................................................1-1

2. FEATURES ....................................................................................................................................................1-1

3. BLOCK DIAGRAM .........................................................................................................................................1-2

4. PIN DESCRIPTION ........................................................................................................................................1-3

5. PAD ................................................................................................................................................................1-4

6. PIN LAYOUT ..................................................................................................................................................1-6

7. FUNCTIONAL DESCRIPTION .......................................................................................................................1-7

8. TIMING CHART .............................................................................................................................................1-8

9. ABSOLUTE MAXIMUM RATINGS .................................................................................................................1-9

10. ELECTRICAL CHARACTERISTICS ............................................................................................................1-10

11. LCD DRIVE POWER ....................................................................................................................................1-13

12. TYPICAL CIRCUIT DIAGRAM .....................................................................................................................1-14

– i –

Rev. 2.1

S1D16006 Series

1. DESCRIPTION

The S1D16006 Series is an 80 output segment (column) driver which is suitable for driving a very high

capacity dot-matrix LCD panels. It is intended to be used in conjunction with the S1D16700/16702 as a pair.

The S1D16006 Series is featured in a high quality of picture in LCD display. It employs a high-speed enable

chain system which is favorable to a low-power driving. Allowed to be operated with a low voltage in the

logic system power supply, it can meet a wide range of applications.

2. FEATURES

• Number of LCD drive output segments: 80

• Low current consumption

• Low voltage operation: –2.7 V (Max.)

• Wide range of LCD drive voltages: –8 V to –28 V

• High-speed and low-power data transfer enabled by means of a 4-bit bus and chain enable support

Shift clock frequency: 6.5 MHZ (at –2.7 V)

10.0 MHZ (at –4.5 V)

• Selectable pin output shift direction (S1D16006D01A )

*

• Adjustable offset bias of LCD power to a VDD level

• Logic system power supply : –2.7 V to –5.5 V

• Non-bias display off function

• Chip packaging

S1D16006D00A (AL-pad die form)

*

S1D16006D00B (Au bump die form)

*

S1D16006D01A (AL-pad die form)

*

S1D16006D01B (Au bump die form)

*

PKG S1D16006F00A (QFP5-100 pin)

*

• No radial rays countermeasure taken in designing

Rev.2.1

EPSON

1–1

S1D16006 Series

3. BLOCK DIAGRAM

······································

LCD driver 80 bit

O 0

O79

V0

V5

V2

V3

VSS

V

DD

Level shifter 80 bit

Latch 80 bit

FR

DSPOFF

LP

*1

Data register 80 bit

Enable shift register

D3 to D0

SHL

EIO2

XSCL

EIO1

^{*1 Dummy terminal NC when S1D16006D00}**^{is used.}

^{DSPOFF terminal when S1D16006D01}**^{is used}

1–2

EPSON

Rev.2.1

S1D16006 Series

4. PIN DESCRIPTION

Number

of pins

Pin name

O0 ~ O79

I/O

O

Function

Segment (column) output for LCD driving

The output changes at the LP falling edge.

80

D0 ~ D3

XSCL

LP

I

Display data input

4

1

Display data shift clock input (Falling edge trigger)

Display data latch pulse input (Falling edge trigger)

Enable input/output

To be set to input or output according to the SHL input level.

The output is reset by the LP input. Upon the end of fetching of

80-bit data, the system starts up automatically to HIGH.

EIO1, EIO2

I/O

2

Shift direction selection and EIO pin I/O control input When data

is input to (D3, D2 ... D0 ) pins sequentially in order of (a3, a2,

a1, a0), (b3, b2, b1, b0) ... (t3, t2, t1, t0), the relationship

between the data and segment output becomes as shown in the

table below:

O Output

79 78 77

EIO

SHL

I

1

2

1

0

EIO1 EIO2

LOW a3 b2 c1 . . . t2 t1 t0 Output Input

HIGH t0 t1 t2 . . . a1 a2 a3 Input Output

(Note) The relationship between the data and segment output is

determined irrespective of the number of shift clock

inputs.

FR

I

LCD drive output AC converted signal input

1

Force input of blank

V0 level is forcibly set by entering LOW level (available with

DSPOFF

^S1D16006D01**^alone).

Logic power supply

VDD: 0 V VSS: –2.7 V to –5.5 V

VDD, VSS

Power supply

2

4

LCD drive circuit power supply

VDD: 0 V V5: –8 V to –28 V

VDD ≥ V0 ≥ V2 ≥ 6/9 V5

3/9 V5 ≥ V3 ≥ V5

V0, V2,

V3, V5

When used at a same potential, V0 and VDD are used by

grounding them close to the IC chip.

*1

*1 Be sure to connect V0 to V5 to their LCD power, respectively.

Total: 100

^S1D16006D00** ^{(including four NC’4)}

^S1D16006D01** ^{(including four NC’3)}

Rev.2.1

EPSON

1–3

S1D16006 Series

5. PAD

Á Pad Layout

75

70

50

80

65

60

55

Y

85

90

45

40

35

X

(0.0)

95

D1606D0B

30

25

5

20

100 1

15

10

Chip size: ........................... 5.59 mm × 3.50 mm

Pad pitch: ........................... 0.153 mm (Min.)

Chip thickness:................... 0.400 mm (AL-pad die form)

0.525 mm (Au-bump die form)

Au bump specifications [Reference values]

Bump size:

117µm × 109µm ± 20 um

Bump height:

17µm to 28µm (Details shall be stipulated in the delivery specification.)

AL-pad die form

Pad Opening

87×76µm

1–4

EPSON

Rev.2.1

S1D16006 Series

Á Pad center coordinate

Unit (µm)

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

NO.

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

X

Y

NO.

1

X

Y

NO.

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

X

Y

O68

O69

O70

O71

O72

O73

O74

O75

O76

O77

O78

O79

EIO2

D0

–537

1578

O0

–2227 –1578

–2073

–1920

–1766

–1612

–1459

–1305

–1152

–998

O34

O35

O36

O37

O38

O39

O40

O41

O42

O43

O44

O45

O46

O47

O48

O49

O50

O51

O52

O53

O51

O55

O56

O57

O58

O59

O60

O61

O62

O63

O64

O65

O66

O67

2622

–871

–713

–554

–396

–238

–79

–691

2

O1

–846

3

O2

–998

4

O3

–1152

–1305

–1459

–1613

–1766

–1920

–2073

–2227

–2381

–2622

5

O4

6

O5

7

O6

79

8

O7

238

9

O8

396

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

O9

–845

554

O10

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

O23

O24

O25

O26

O27

O28

O29

O30

O31

O32

O33

–691

713

–537

871

–384

1029

1188

1346

1578

1346

1192

1039

885

–230

D1

–76

D2

77

2381

2228

2074

1921

1767

1613

1460

1306

1152

999

D3

231

Dummy

*1

732

384

578

538

424

692

271

845

V^DD

V^SS

106

999

–58

1152

V0

–224

–389

–553

–718

–885

–1039

–1192

–1346

1306

V2

1460

V3

1613

845

V5

1767

692

SHL

XSCL

LP

–2611

1921

538

2074

384

2228

231

FR

2381

77

EIO1

–2381 –1578

2622 –1346

–1188

–1029

–76

–230

–384

^{*1: Pad No.89 is dummy when S1D16006D00}**^{is used.}

^{It will be DSPOFF with S1D16006D01}**^.

Rev.2.1

EPSON

1–5

S1D16006 Series

6. PIN LAYOUT

Package Type: QFP–5 100pin

80

51

81

50

S1D16006F

INDEX

1

30

PIN No. NAME PIN No. NAME PIN No. NAME PIN No. NAME PIN No. NAME

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

O0

O1

O2

O3

O4

O5

O6

O7

O8

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

O20

O21

O22

O23

O24

O25

O26

O27

O28

O29

O30

O31

O32

O33

O34

O35

O36

O37

O38

O39

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

O40

O41

O42

O43

O44

O45

O46

O47

O48

O49

O50

O51

O52

O53

O54

O55

O56

O57

O58

O59

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

O60

O61

O62

O63

O64

O65

O66

O67

O68

O69

O70

O71

O72

O73

O74

O75

O76

O77

O78

O79

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

EIO2

D0

D1

D2

D3

NC

*1

VDD

VSS

V0

V2

V3

V5

SHL

XSCL

LP

FR

EIO1

O9

O10

O11

O12

O13

O14

O15

O16

O17

O18

O19

^{*1: Pad No.89 is dummy when S1D16006D00}**^{is used.}

^{It will be DSPOFF with S1D16006D01}**^.

1–6

EPSON

Rev.2.1

S1D16006 Series

7. FUNCTIONAL DESCRIPTION

Enable shift register

This is a bidirectional shift register with which the shift direction is selected by SHL input. The output of this

shift register is used to store the data bus signals to data register.

When the enable signal is in the disable status, the internal clock signal and data bus are fixed to LOW and

the system is made into the power save mode.

When using two or more segment drivers, connect the EIO pin of each driver in a cascade arrangement and

the EIO pin of the leading driver to VDD.

Since the enable controller circuit automatically detects that the data for 80 bits have been fetched thoroughly

and then transfers the enable signal to the controller, it is not necessary to provide the control signal using the

control LSI.

Data register

This is a register used to convert the data bus signal into serial or parallel signal through the enable shift register

output. Consequently, the relationship between the serial display data and segment output is determined

irrespective of the number of shift clock inputs.

Latch

This latch is used to fetch the content of data register at the LP falling edge trigger and to send its output to

the level shifter.

Level shifter

This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive

level.

LCD driver

This driver outputs the LCD drive voltage.

The relationship among the data bus signal, AC converted signal FR and segment output voltage is as shown

in the table below:

^(S1D16006D00**⁾

Data bus

signal

FR

O output voltage

HIGH

LOW

HIGH

LOW

V0

V5

V2

V3

HIGH

LOW

^(S1D16006D01**⁾

Data bus

signal

DSPOFF

FR

O output voltage

HIGH

LOW

HIGH

LOW

—

V0

V5

V2

V3

V0

HIGH

LOW

—

Rev.2.1

EPSON

1–7

S1D16006 Series

8.TIMING CHART

When the duty is 1/200 (Reference Example)

200

1

2

3

4

199

200

1

2

199

200

1

LP

LATCH

DATA

FR

LP

XSCL

20

1

2

3

20

D0 to D3

1

2

3

1

2

3

1

2

3

EIO 1

EIO 2

EIO 3

1 to 3 stand for a cascaade No. of driver.

LP

LATCH

DATA

L

H

FR

L

H

DSPOFF

^S1D16006D00**

^S1D16006D01**

V0

V2

V3

V5

^{When S1D16006D01}**^{is used:}

The driver output is forcibly switched to

V0 output upon switching of DSPOFF

1–8

EPSON

Rev.2.1

S1D16006 Series

9. ABSOLUTE MAXIMUM RATINGS

VDD=0V

Parameter

Power voltage (1)

Power voltage (2)

Power voltage (3)

Input voltage

Symbol

VSS

Rating

–7.0 to +0.3

Unit

V

V5

–30.0 to +0.3

V5–0.3 to VDD+0.3

VSS–0.3 to VDD+0.3

20

V

V0, V2, V3

VI

V

Output voltage

VO

V

EIO output current

Operating temperature

Storing temperature 1

IO

mA

°C

Topr

Tstg 1

–40 to + 85

–65 to +150

Notes:

1. All the above voltage is based on VDD = 0V.

2. The storage temperature 1 stipulates the temperature by unit of a chip.

3. The voltage of V0, V2 and V3 must always satisfy the condition of VDD≥ V0≥ V2≥ V3 ≥ V5.

System side

V

DD

SS

V

DD

0

V_CC

–5V

5V

GND

2

–28V

V

3

V₅

4. Floating of the logic system power during while the LCD drive system power is applied, or exceeding VSS

= –2.6 V can cause permanent damage to the LSI. Functional operation under these conditions is not

implied.

Care should be taken to the power supply sequence especially in the system power ON or OFF.

Rev.2.1

EPSON

1–9

S1D16006 Series

10. ELECTRICAL CHARACTERISTICS

DC characteristics

Unless otherwise specified, V^DD= V0 = 0V, VSS = –5.0V±10% and Ta = –40 to 85°C.

Parameter

Symbol

V^SS

Condition

–

Min.

–5.5

Typ.

–5.0

Max.

–2.7

Unit

V

Applicable pin

V^SS

Supply voltage (1)

Recommended

operating voltage

V5

V^SS=–2.7 to –5.5V

–28.0

–

–12.0

V

V5

Operation enable voltage

Supply voltage (2)

Supply voltage (3)

Supply voltage (4)

V5

V0

V2

V3

Function

–

V^DD–2.5

3/9V⁵

V5

–

–8.0

V^DD

–

V

V5

V0

V2

V3

Recommended value

6/9V⁵

HIGH input voltage

LOW input voltage

VIH

VIL

0.2VSS

–

V

EIO1, EIO2, FR,

D0 to D3, XSCL,

SHL, LP

V^SS=–2.7 to –5.5V

0.8V^SS

I

OH=–0.6mA

V^DD–0.4

–

V

HIGH output voltage

LOW output voltage

VOH

VOL

–

VSS=–2.7 to –5.5V

EIO1, EIO2

IOL=0.6mA

VSS+0.4

Input leakage

current

D0 to D3, LP, FR

XSCL, SHL

V^SS≤ VIN ≤ VDD

VSS ≤ VIN ≤ VDD

ILI

–

2.0

5.0

25

µA

Input/output

leakage current

ILI/O

ISS

EIO1, EIO2

V^SS

V5=–28.0 to –14.0V

V^IH=VDD, VIL=VSS

Static current

∆VON=0.5V

V⁵=–20.0V V3=13/15·V5

V2=2/15·V5 V0=VDD

Ta=25°C

Output resistance

RSEG

–

1.2

1.6

0.2

kΩ

O0 to O79

V^SS=–5.0V, VIH=VDD

VIL=VSS, fXSCL=2.69MHz

fLP=16.8KHz, fFR=70Hz

Input data: Dice display at no

0.10

Average operating

current

consumption (1)

ISS

mA

V^SS

load

- - - - - - - - - - - - - - - - - - - - - - -

V^SS=–3.0V

- - - - - - - - - - - - - - - - - - - - - - - -

–

0.07

0.05

0.15

0.08

Other conditions are the

same as V^SS= -5 V

V^SS=–5.0V,

V⁰=0.0V, V2=–9.3V

V³=–18.6V, V5=–28.0V

Other conditions are the

same as in the item of I^SS.

Average operating

current

consumption (2)

mA

V5

I5

Input pin

capacitance

D0 to D3, LP, FR

XSCL, SHL

CI

–

pF

–

8

Freq.=1MHz

Ta=25°C

By unit of a chip

Input/output pin

capacitance

CI/O

15

EIO1, EIO2

1–10

EPSON

Rev.2.1

S1D16006 Series

AC Characteristics

Input timing characteristics

V

IH=0.2 × VSS

IL=0.8 × VSS

FR

t

WLH

t

DF

LP

t

LH

t

LD

t

C

XSCL

D3 to D0

t

DS

t

DH

t

WCH

t

WCL

SUE

t

EI01,2

(IN)

VSS=–5.0V±0.5V, Ta=–40 to 85°C

Parameter

XSCL period

XSCL HIGH pulsewidth

XSCL LOW pulsewidth

Data setup time

Symbol

tC

tWCH

tWCL

tDS

tDH

tLD

tLH

tWLH

tDF

Condition

Min.

100

30

Max.

Unit

ns

–

*3

–

30

20

–

Data hold time

10

0

–

XSCL-rise to LP-rise time

LP-fall to XSCL-fall time

LP HIGH pulsewidth

Allowable FR delay time

EIO setup time

40

–

–900

35

+900

–

tSUE

VSS=–4.5V to –2.7V, Ta=–40 to 85°C

Parameter

Symbol

tC

Condition

Min.

Max.

Unit

ns

VSS=–2.7V *1

153

133

50

–

XSCL period

VSS=–3.0V *2

XSCL HIGH pulsewidth

XSCL LOW pulsewidth

Data setup time

tWCH

tWCL

tDS

tDH

tLD

–

ns

–

50

–

30

–

Data hold time

XSCL-rise to LP-rise time

–

15

0

–

VSS=–2.7V

VSS=–3.0V

VSS=–2.7V *3

VSS=–3.0V *3

–

75

–

LP-fall to XSCL-fall time

tLH

ns

65

–

75

65

–

LP HIGH pulsewidth

Allowable FR delay time

EIO setup time

tWLH

tDF

ns

–900

60

+900

–

VSS=–2.7V

VSS=–3.0V

tSUE

51

–

*1 Equivalent to 6.5 MHz

*2 Equivalent to 7.5 MHz

*3 tWLH stipulates the time when LP is HIGH and XSCL is LOW.

*4 tr and tf of input signal are stipulated by unit of 20 ns.

*5 At a high-speed operation, tr and tf = {tC – (tDCL + tSUE)}/2

Rev.2.1

EPSON

1–11

S1D16006 Series

Output timing characteristics

V

IH=0.2 × VSS

IL=0.8 × VSS

FR

t

FRSD

LP

t

LSD

t

ER

XSCL

t

DCL

EIO1, 2

(OUT)

V

ON=0.2 × VSS

OL=0.8 × VSS

O n

(SEG)

Vn–0.5

Vn+0.5

VDD=–5.0±0.5V, V5=–12.0 to –28.0V

Parament

EIO reset time

Symbol

tER

Condition

Min.

–

Max.

90

Unit

ns

CL=15pF (EIO)

CL=100pF (On)

EIO output delay time

LP to SEG output delay time

FR to SEG output delay time

tDCL

–

55

ns

tLSD

–

200

400

ns

tFRSD

–

ns

VDD=–4.5V to 2.7V, V5=–12.0 to –28.0V

Parament

Symbol

tER

Condition

Min.

Max.

Unit

EIO reset time

–

150

88

ns

CL=15pF

(EIO)

VSS=–2.7V

VSS=–3.0V

EIO output delay time

tDCL

77

LP to SEG output delay time

FR to SEG output delay time

tLSD

400

800

CL=100pF (On)

tFRSD

*1 tr and tf of input signal are stipulated by unit of 20 ns.

*2 At a high-speed operation, tr and tf = {tC – (tDCL + tSUE)}/2

1–12

EPSON

Rev.2.1

S1D16006 Series

11. LCD DRIVE POWER

Each voltage level forming method

To obtain each voltage level for LCD driving, it is optimum to divide the resistance of potential between V5

and VDD to drive the LCD using the voltage follower with an operational amplifier. In taking into

consideration of such a case using the operational amplifier, the maximum potential level V0 for LCD driving

has been made a separate pin from VDD.

When the potential of V0 lowers than that of VDD and the potential difference between the two becomes larger,

however, the capacity of LCD drive output driver lowers. To avoid it, use the system with the potential

difference of 0 V to 2.5 V between V0 and VDD .

When no operational amplifier is used, connect V0 and VDD close to the IC chip.

When a series resistance exists in the power supply line of V5 and VDD , a voltage drop of V5 and VDD occurs

at the LSI power supply pin, the relationship with the LCD’s intermediate potential (VDD ≥ V0 ≥ V2 ≥ V3

≥ V5) cannot be met, this causing the LSI to be broken down in some cases. When a protection resistor is

inserted, it is necessary to stabilize the voltage by capacitance.

Note in power ON/OFF

Since this LSI is high in the voltage of LCD driving system, when a high voltage is applied to the LCD driving

system with the logic system power supply kept floating or above VSS = –2.6 V, and when the LCD driving

signal is output before the applied voltage to the LCD driving system is stabilized, an overcurrent flows and

LSI breaks down in some cases.

Be sure to follow the power ON/OFF sequence as shown below:

At power ON ... Logic system ON

At power OFF .. LCD driving system OFF

→LCD driving system ON or simultaneous ON of the both

→Logic system OFF or simultaneous OFF of the both

For a countermeasure to such overcurrent, it is effective to put a high-speed melting fuse or protection resistor

in series with the LCD power unit.

It is then required to select the optimum value in the protection resistance according to the capacitance of LC

cell.

Until the LCD driver voltage stabilizes. It is recommended to set the LCD driver output potential to V0 using

the display off function (DSPOFF).

^{Power ON/OFF sequence when S1D16006D01}**^{is used}

V

t1

t2

V

DD

SS

>

t1.t2.t3 0 sec

=

Power ON

Power OFF

V

5

t3

VDD

DSPOFF VSS

Rev.2.1

EPSON

1–13

S1D16006 Series

12.TYPICAL CIRCUIT DIAGRAM

Configuration Drawing of Large Screen LCD

V

SS

+

V

DD

V

0

r

+

–

1

+

–

2

3

R

r

+

–

+

–

V

4

5

r

V

5

1 0 0

S 1 D 1 6 7 0 0

1 0 0

S 1 D 1 6 7 0 0

1–14

EPSON

Rev.2.1

S1D16400

CONTENTS

1. DESCRIPTION ...............................................................................................................................................2-1

2. FEATURES ....................................................................................................................................................2-1

3. BLOCK DIAGRAM .........................................................................................................................................2-2

4. FUNCTIONS OF THE TERMINALS...............................................................................................................2-3

5. PAD LAYOUT.................................................................................................................................................2-4

6. PAD CENTER COORDINATES .....................................................................................................................2-5

7. FUNCTION DESCRIPTIONS .........................................................................................................................2-6

8. ABSOLUTE MAXIMUM RATING ...................................................................................................................2-7

9. ELECTRICAL CHARACTERISTICS ..............................................................................................................2-8

10. REGARDING THE LCD DRIVING POWER .................................................................................................2-12

11. AN EXAMPLE OF CONNECTION ...............................................................................................................2-13

– i –

S1D16400 Series

1. DESCRIPTION

The S1D16400 is an 80 output segment (column) driver for use in combination with an S1D16700/16702.

It is provided with high-vision measure of the LCD display and adopts high speed inable chain system for low

power operation and slim chip shape suitable for minimizing of the LCD panel. Also, low voltage operation

of the logic power source suits a wide range of applications.

2. FEATURES

• LCD driver output number : 80

• Ultra-slim chip

• Low current consumption

• Low voltage operation : –2.7V Max.

• Wide range of liquid crystal drive voltage : –8 to –28V

• High speed and low power data transfer is possible by adoption of the 4 bit bus inable chain system.

Shift clock frequency

6.5MHz (at –2.7V)

7.5MHz (at –3.0V)

• Non-bias display off function

• Pin selection of the output shift direction is available.

• Offset bias regulation of the liquid crystal power is possible depending on the VDD level.

• Logic system power source : –2.7V to –5.5V

• Product shapes

Chip : S1D16400D00B (Au bump article)

*

EPSON

2–1

S1D16400 Series

3. BLOCK DIAGRAM

······································

LCD driver 80 bit

O 0

O79

V0

V5

V2

V3

Level shifter 80 bit

Latch 80 bit

FR

DSPOFF

LP

VSS

V

DD

Data register 80 bit

Inable shift register

D0 to D3

SHL

EIO2

XSCL

EIO1

2–2

EPSON

S1D16400 Series

4. FUNCTIONS OF THE TERMINALS

Terminal

I/O

Numbers of

terminals

Functions

names

O0 ~ O79

O

LCD driving segment (column) output.

80

The output level varies by the trailing edge of the LP.

D0 ~ D3

XSCL

I

Display data input

4

1

2

Shift clock input of display data (trailing edge trigger)

Latch pulse input of display data (trailing edge trigger)

LP

I

EIO1, EIO2

I/O

Inable input and output.

Set to input or output depending on the SHL input level.

The output is reset by the LP input and, after receiving 80 bit

data, it automatically rises to HIGH.

SHL

I

Shifting direction choice and input/output controlling input to the

EIO terminal.

1

When data are input to (D3, D2 ...D0) terminals in the order of

(a,b,c,d,e,f,g,h).....(w,x,y,z), relations between data and segment

outputs are as follows:

O Output

EIO

SHL

79 78 77

2

x

c

1

y

b

0

z

a

EIO1 EIO2

Output Input

Input OUtput

LOW

HIGH

a

z

b

y

c

x

. . .

(Note) Relations between data and segment outputs are

determined independent from the shift clock number.

FR

I

Input of the alternating signal of the LCD drive output.

1

3

VDD, VSS

Power

source

Power supply for the logics

VDD : 0V

VSS : –2.7 ~ –5.5V

V0, V2,

V3, V5

Power

source

Power supply for the LCD driver circuit

VDD : 0V V5 : –8 ~ –28V

8

>

VDD V0 V2 6/9 V5

=

>

*1 3/9 V5 V3 V5

=

DSPOFF

I

Forced blank input

At the LOW level, it forces the output to V0 level.

1

* When using this function, the unit may be used in common

^{with S1D16700}*⁰¹**^.

*1 Be sure to connect pairs of V0 - V5 to respective LCD power sources.

Total 107

(including NC5)

EPSON

2–3

S1D16400 Series

5. PAD LAYOUT

95

90

85

80

75

70

65

60

55

50

45

40

100

105

35

30

(0,0)

1

5

10

15

20

25

Chip size ............................ 11.59mm x 1.40mm

Pad pitch ............................ 105µm (Min.)

Chip thickness .................... 625µm ±25µm

Au bump specification (S1D16400D00B_*) reference values

Bump size

A

B

C

D

160µm × 80µm ±4µm

86µm × 91µm ±4µm

86µm × 68µm ±4µm

82µm × 74µm ±4µm

22.5 ±5.5µm

(Pad No. 2 ~ 26)

(Pad No. 1, 27, 37 and 98)

(Pad No. 28 ~ 36 and 99 ~ 107)

(Pad No. 38 ~ 97)

Bump height A ~ D

(Pad No. 1 ~ 107)

2–4

EPSON

S1D16400 Series

6. PAD CENTER COORDINATES

X-axis of

coordinates coordinates

Y-axis of

X-axis of

coordinates coordinates

Y-axis of

X-axis of

coordinates coordinates

Y-axis of

PAD NO. PAD NAME

2

3

V0

V2

V3

V5

V^SS

–5345

–5164

–4984

–4594

–4091

–541

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

O10

O11

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

O23

O24

O25

O26

O27

O28

O29

O30

O31

O32

O33

O34

O35

O36

O37

O38

O39

O40

O41

O42

O43

O44

O45

5269

5090

4912

4733

4554

4376

4197

4019

3840

3661

3483

3304

3126

2947

2768

2590

2411

2233

2054

1875

1697

1518

1340

1161

982

553

74

75

O46

O47

O48

O49

O50

O51

O52

O53

O54

O55

O56

O57

O58

O59

O60

O61

O62

O63

O64

O65

O66

O67

O68

O69

O70

O71

O72

O73

O74

O75

O76

O77

O78

O79

EIO2

–1161

–1340

–1518

–1697

–1875

–2054

–2233

–2411

–2590

–2768

–2947

–3126

–3304

–3483

–3661

–3840

–4019

–4197

–4376

–4554

–4733

–4912

–5090

–5269

–5644

553

4

76

5

77

6

78

7

Dummy –3839

SHL –3587

79

8

80

9

Dummy –3065

Dummy –2828

81

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

82

V^DD

–2590

83

DSPOFF –2086

84

FR

–1583

–1079

1079

1583

2086

2590

3065

3587

3839

4091

4594

4984

5164

5345

5644

85

LP

86

XSCL

D0

87

88

D1

89

D2

90

Dummy

D3

91

92

Dummy

V^SS

V5

93

94

95

V3

96

V2

97

V0

98

546

418

EIO1

O0

–544

–426

–320

–215

–109

–4

804

99

625

100

101

102

103

104

105

106

107

1

313

O1

447

207

O2

268

102

O3

89

–4

O4

–89

–109

–215

–320

–426

–544

O5

102

–268

–447

–625

–804

–982

O6

207

O7

313

O8

418

O9

546

EPSON

2–5

S1D16400 Series

7. FUNCTION DESCRIPTIONS

Inable shift registor

The inable shift registor is a bidirectional shift registor wherewith the shift direction is determined by the SHL

inputs and outputs of such shift registor are used to store data bus signals to the data registor. When inable

signals are in the disable state, the internal clock signal and data bus are fixed to LOW to become the power

save mode.

When using multiple units of the segment driver, EIO terminals of each driver should be connected by the

cascade connection and the EIO terminals of the top end driver should be connected to “VDD”. (Refer to the

example of the connection) Since the inable control circuit automatically detects when all the 80 bit data are

taken in and automatically transfers the inable signal, control signals from a controlling LSI are not needed.

Data registor

This is a registor for serial and parallel conversion of data bus signals by means of the inable shift registor

output. Consequently, the relations between the serial display data and segment outputs are determined

independent from the shift clock input number.

Latch

It takes in the contents of the data registor by means of the trailing edge trigger of the LP to transmit the output

to the level shifter.

Level shifter

This is a level interface circuit to convert the voltage level of signals from logic level to LCD driving level.

LCD driver

It outputs the LCD drive voltage.

Relations among data bus signals, alternating signals FR and the segment output voltage are given below.

Data bus

signals

DSPOFF

FR

O Output Voltage

HIGH

LOW

HIGH

LOW

—

V0

V5

V2

V3

V0

HIGH

LOW

—

2–6

EPSON

S1D16400 Series

8. ABSOLUTE MAXIMUM RATING

Items

Symbols

VSS

Ratings

–7.0 ~ +0.3

Unit

V

Power voltage (1)

Power voltage (2)

Power voltage (3)

Input voltage

V5

–30.0 ~ +0.3

V5–0.3 ~ VDD+0.3

VSS–0.3 ~ VDD+0.3

20

V

V0, V2, V3

VI

V

Output voltage

VO

V

EIO output current

Working temperature

Storing temperature 1

Storing temperature 2

I01

mA

°C

Topr

Tstg 1

Tstg 2

–40 ~ +85

–65 ~ +150

–55 ~ +100

Note 1) All the above voltage is based on VDD = 0V.

Note 2) The storing temperature 1 specifies that of chips proper and the storing temperature 2 specifies that

of TAB packages.

>

Note 3) Voltage of V0, V2 and V3 should always be maintained under a condition of VDD V0 V2 V3

=

>

V5.

=

V

DD

–5V

0

VSS

2

–28V

V

3

5

V

Note 4) When logic power becomes floating state or if VSS = –2.6 or beyond while the LCD driver power

source is being applied, the LSI may be permanently damaged and avoid such circumstances.

Pay extra attention to the power sequence at times of turning on and turning off the power supply.

EPSON

2–7

S1D16400 Series

9. ELECTRICAL CHARACTERISTICS

DC characteristics

Unless otherwise designated, VDD = V0 = 0V, VSS = –5.0V±10% and Ta = –40 to 85°C.

Items

Symbols

V^SS

Conditions

Applicable terminals

Min.

–5.5

Typ.

–5.0

Max.

–2.7

Unit

V

Power voltage (1)

VSS

V5

Recommended

V⁵

VSS=–2.7 ~ –5.5V

–28.0

–12.0

V

operating voltage

Operatable voltage

Power voltage (2)

Power voltage (3)

Power voltage (4)

High level input voltage

V⁵

V⁰

V²

V³

VIH

Function

V5

V0

V2

V3

-8.0

V

Recommended value

VSS=–2.7 ~ –5.5V

VDD–2.5

3/9V5

V5

VDD

6/9V5

EIO1, EIO2, FR,

D0 ~ D3, XSCL,

SHL, LP, DSPOFF

0.2VSS

Low level input voltage

VIL

0.8VSS

V

High level output

V^OH

V^OL

VSS=–2.7 ~ –5.5V

I

OH=–0.6mA

EIO1, EIO2

VDD–0.4

V

Low level output

voltage

IOL=0.6mA

VSS+0.4

2.0

<

=

<

=

Input leak current

I^LI

VSS

V^IN

V^DD

D0 ~ D3, LP, FR

XSCL, SHL,

DSPOFF

µA

<

=

<

=

Input and output

leak current

I^LI/O

I^SS

V^IN

V^DD

EIO1, EIO2

5.0

25

µA

kΩ

Rest current

V5=–28.0 ~ –14.0V

V^IH=VDD, VIL=VSS

VSS

Output resistance

RSEG

∆VON=0.5V

O 0 ~ O 79

1.5

2.5

V⁵=–20.0V V3=13/15•V5

V²=2/15•V5 V0=VDD

Average operating

current

consumption (1)

ISS

VSS=–5.0V, VIH=VDD

V^IL=VSS, fXSCL=2.69MHz

fLP=16.8KHz, fFR=70Hz

VSS

0.10

0.2

mA

Input data: Diced display no-load

- - - - - - - - - - - - - - - - - - - - - - -

VSS=–3.0V

- - - - - - - - - - - - - - - -

0.07

0.15

Other conditions are the

same as with V^SS=–5V

Average operating

current

consumption (2)

I⁵

VSS=–5.0V, V0=0.0V,

V²=–9.3V, V3=–18.6V,

V⁵=–28.0V

V5

0.02

0.05

mA

Other conditions are the

same as with the item I^SS.

Input terminal

capacity

C^I

Freq.=1MHz

Ta=25°C

Chips proper

D0 ~ D3, LP, FR,

XSCL, SHL,

DSPOFF

8

pF

Input and output

terminal capacity

C^I/O

EIO1, EIO2

15

2–8

EPSON

S1D16400 Series

Timing Diagram

In case of 1/200 duty (an example)

200

1

2

3

4

199 200

1

2

3

199 200

1

LP

LATCH

DATA

FR

LP

*

XSCL

20

1

2

3

20

1

2

3

20

1

2

3

20

1

D0 to D3

EIO 1

1

2

EIO 2

EIO n

1 ~ n indicate the cascade numbers of drivers.

* In case of high speed data transfer, it is necessary to secure a longer XSCL cycle

in the timing of the LP pulse insertion in order to maintain the specified value

of LP → XSCL (tLH).

LP

LATCH

DATA

L

H

L

H

FR

H

DSPOFF

V0

V2

V3

V5

EPSON

2–9

S1D16400 Series

AC Characteristics

Input timing characteristics

FR

t

WLH

t

DF

LP

t

LH

t

LD

t

C

XSCL

t

DS

t

DH

t

WCH

t

WCL

D0 to D3

SUE

t

EI01,2

(IN)

VSS=–5.0V±0.5V, Ta=–40 ~ 85°C

Items

Symbols

tC

tWCH

tWCL

tDS

tDH

tLD

tLH

tWLH

tDF

Conditions

Min.

100

30

Max.

Unit

ns

XSCL cycle

XSCL HIGH level pulse duration

XSCL LOW level pulse duration

Data setup time

30

Data hold time

20

0

XSCL → LP rise time

LP → XSCL fall time

LP HIGH level pulse duration

FR delay permissible time

EIO setup time

40

*3

–900

35

+900

tSUE

VSS=–4.5V ~ 2.7V, Ta=–40 ~ 85°C

Items

Symbols

tC

Conditions

Min.

Max.

Unit

ns

*1

*2

VSS=–2.7V

VSS=–3.0V

153

133

50

XSCL cycle

XSCL HIGH level pulse duration

XSCL LOW level pulse duration

Data setup time

tWCH

tWCL

tDS

tDH

tLD

ns

50

Data hold time

30

XSCL → LP rise time

0

VSS=–2.7V

VSS=–3.0V

VSS=–2.7V

VSS=–3.0V

75

LP → XSCL fall time

tLH

ns

65

75

*3

LP HIGH level pulse duration

FR delay permissible time

EIO setup time

tWLH

tDF

ns

65

–900

50

+900

VSS=–2.7V

VSS=–3.0V

tSUE

40

*1 6.5MHz equivalence

*2 7.5MHz equivalence

*3 twLH specifies the time when LP is HIGH and, at the same time, XSCL is LOW.

2–10

EPSON

S1D16400 Series

Output timing characteristics

FR

t

FRSD

LP

t

LSD

t

ER

XSCL

t

DCL

EIO1, 2

(OUT)

SEG

VDD=–5.0±0.5V, V5=–12.0 ~ –28.0V

Items

EIO reset time

Symbols

tER

Conditions

Min.

Max.

90

Unit

ns

CL=15pF (EIO)

EIO output delay time

LP → SEG output delay time

FR → SEG output delay time

tDCL

55

ns

tLSD

200

400

ns

CL=100pF (0n)

tFRSD

ns

VDD=–4.5V ~ 2.7V, V5=–12.0 ~ –28.0V

Items

Symbols

tER

Conditions

Min.

Max.

Unit

EIO reset time

150

95

ns

CL=15pF

VSS=–2.7V

VSS=–3.0V

EIO output delay time

tDCL

(EIO)

85

LP → SEG output delay time

FR → SEG output delay time

tLSD

400

800

CL=100pF (0n)

tFRSD

EPSON

2–11

S1D16400 Series

10. REGARDING THE LCD DRIVING POWER

Methods to obtain necessary voltage levels

In order to obtain necessary voltage levels for driving of the LCD, it should be the best to divide the potential

between V5 VDD resistively to drive by means of the voltage follower by the operation amplifier. In

consideration of the case of using the operation amplifier, the maximum potential level V0 and VDD should

be separated to independent terminals.

Nevertheless, if V0 potential drops below the VDD potential increasing the potential difference, the capacity

of the LCD driver decreases and, therefore, it is suggested that the potential difference between V0 ~ VDD be

maintained within 0V ~ 2.5V. When the operation amplifier is not used, V0 and VDD should be connected.

As shown in the example of the connection, when using the resistive divider, set the resistance as low as the

power capacity of the system allows.

When a series resistance exist in the power line of V5 (VDD), voltage drop of V5 (VDD) at the LSI current end

occurs by I5 at times of signal changes and it becomes unable to maintain the relations of the LCD with

>

intermediate potentials (VDD V0 V2 V3 V5) leading to breakage of the LSI. When installing protective

=

resistors, it is necessary to stabilize the voltage by their capacity.

Cautions when turning the power on and off

Since the LCD drive system voltage with this LSI is comparatively high, when high voltage is applied to the

LCD drive system leaving the logic power floating or leaving VSS = –2.6V or over or if LCD drive signals

are output before the applied voltage to the LCD drive system is stabilized, excess current may flow to break

the LSI. It therefore is suggested to bring the potential of the LCD drive output to the V0 level until the LCD

drive system voltage gets stabilized using the display-off function (DSPOFF).

When turning the power on or off, follow the sequence below.

When turning on the power.....Logic systems ON →

LCD drive system ON

(or turn them on simultaneously).

When turning off the power.....LCD drive system OFF → Logic system OFF

(or turn them off simultaneously).

Insert quick melting fuse in series to the LCD power source for prevention of an excess current flow.

It is necessary to choose the optimum value for the protective resistance matching the capacity of the liquid

crystal cells.

2–12

EPSON

S1D16400 Series

11. AN EXAMPLE OF CONNECTION

Block diagram of a large sized LCD

V

SS

V

DD

V0

r

V1

V2

V3

V4

V5

r

R

r

V5

100

S1D16700

EPSON

2–13

S1D16501

Rev.1.0

CONTENTS

1. DESCRIPTION ...............................................................................................................................................3-1

2. FEATURES ....................................................................................................................................................3-1

3. BLOCK DIAGRAM .........................................................................................................................................3-2

4. PIN DESCRIPTION ........................................................................................................................................3-3

5. PAD ................................................................................................................................................................3-4

6. FUNCTIONAL DESCRIPTION .......................................................................................................................3-6

7. TIMING CHART .............................................................................................................................................3-7

8. ABSOLUTE MAXIMUM RATINGS .................................................................................................................3-8

9. ELECTRICAL CHARACTERISTICS ..............................................................................................................3-9

10. LCD DRIVE POWER ....................................................................................................................................3-12

11. TYPICAL CIRCUIT DIAGRAM .....................................................................................................................3-13

– i –

Rev.1.0

S1D16501 Series

1. DESCRIPTION

The S1D16501 is a 100 output low-power resistance common (row) driver which is suitable for driving a very

high capacity dotmatrix LCD panels. It is intended to be used in conjunction with the S1D16408 as a pair.

Since the S1D16501 is so designed to drive LCD’s over a wide range of voltages, and also the maximum

potential V0 of its LCD driving bias voltages is isolated from VDD to allow the LCD driving bias voltages to

be externally generated optionally with a high accuracy, it can cope with a wide range of LCD panels.

Owing to its pad layout which can minimize its PC boards mounting space in addition to its selectable

bidirectional driver output sequence and as many as 100 LCD output segments of high pressure resistance and

low output impedance, it is possible to obtain the highest driver working efficiency for the 1/200 duty panel.

2. FEATURES

• Number of LCD drive output segments: 100

• Super slim chip configuration

• Common output ON resistance: 750Ω (Typ.)

• Display capacity ... Possible to display 640 × 480 dots.

• Selectable pin output shift direction

• No bias display OFF function

• Adjustable offset bias of LCD power to VDD level

• Wide range of LCD drive voltages: –8 V to –28 V (Absolute maximum rated voltage: –30 V)

• Logic system power supply: –2.7 V to –5.5 V

• Chip packaging S1D16501D00A (AL-pad die form)

*

• No radial rays countermeasure taken in designing

Rev.1.0

EPSON

3–1

S1D16501 Series

3. BLOCK DIAGRAM

······································

O 0

O99

V0

V1

V4

LCD driver 100 bit

V5

FR

Level shifter 100 bit

V

SS

V

DD

DIO1

Bidirectional shift register

50 × 2 bit

YSCL

SHL

DSPOFF

SEL

DI3 DIO2

3–2

EPSON

Rev.1.0

S1D16501 Series

4. PIN DESCRIPTION

Number

of pins

Pin name

O0 to O99

I/O

O

Function

LCD drive common (row) output

80

2

The output changes at the YSCL falling edge.

50 × 2 bits bidirectional shift register serial data input/output

To be set to input or output according to the SHL input

The output changes at the YSCL falling edge.

DIO1

DIO2

I/O

I

This is the input pin of scanning pulse in the 50 × 2 bits

configuration.

DI3

1

When SEL = LOW, the DI3 pin to VSS or GND.

Selection input of bidirectional shift register operating mode

HIGH ... 50 × 2 (DI3 input) LOW ... 100

SEL

I

1

Serial data shift clock input

The scanning data is shifted at the falling edge.

YSCL

Shift direction selection and DIO pin I/O control input

SHL

O output shift direction

DIO1

Input

DIO2

Output

Input

LOW 0 → 49

HIGH 99 → 50

50 → 99

49 → 0

SHL

I

1

Ourput

When SEL = HIGH, the DI3 input is set to O50 (SHL = LOW) or

O49 (SHL = HIGH).

When SEL = LOW, the D13 input is ignored and the DIO inputs

are shifted continuously.

LCD display blanking control input

I

When LOW is input, the content of shift register is cleared and all

common outputs become the V0 level instantaneously.

1

DSPOFF

LCD drive output converted signal input

I

1

3

FR

Logic power supply

VDD: 0 V (GND) VSS: –2.7 V to –5.5 V

Power supply

VDD, VSS

LCD drive power supply V5: –8 V to –28 V

V0, V1,

V4, V5

Power supply

8

VDD ≥ V0 ≥ V1 ≥ V4 ≥ V5

Respectively

Total: 119

Rev.1.0

EPSON

3–3

S1D16501 Series

5. PAD

Á Pad layout

109

110

30

29

20

Y

X

119

1

19

Chip size: ........................... 13.43 mm × 1.76 mm

Chip thickness:................... 400 µm (Typ.)

AL pad specifications (S1D16501D00A )

*

Chip edge

130µm

153µm

(Min)

152µm-α

a

b

c

144µm

(Min)

170µm-α

b

(Min)

475µm

Chip edge

Pad a Opening (X, Y)

Pad b Opening (X, Y)

Pad c Opening (X, Y)

110 × 110µm

PAD No 30 to 109

PAD No 20 to 29, 110 to 119

PAD No 1 to 19

3–4

EPSON

Rev.1.0

S1D16501 Series

Á Pad center coordinates

Unit (µm)

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

NO.

1

X

Y

NO.

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

X

Y

NO.

85

X

Y

DIO2

V0

–5985

–5510

–5035

–4560

–4038

–3164

–2280

–1767

–1064

–181

770

–709

O23

O24

O25

O26

O27

O28

O29

O30

O31

O32

O33

O34

O35

O36

O37

O38

O39

O40

O41

O42

O43

O44

O45

O46

O47

O48

O49

O50

O51

O52

O53

O54

O55

O57

O58

O59

O60

O61

O62

O63

O64

4078

3924

3771

3617

3463

3309

3155

3001

2847

2693

2539

2385

2232

2078

1924

1770

1616

1462

1308

1154

1000

846

727

O65

O66

O67

O68

O69

O70

O71

O72

O73

O74

O78

O76

O77

O78

O79

O80

O81

O82

O83

O84

O85

O86

O87

O88

O89

O90

O91

O92

O93

O94

O95

O96

O97

O98

O99

–2385

–2539

–2693

–2847

–3001

–3155

–3309

–3463

–3617

–3771

–3924

–4078

–4232

–4386

–4540

–4694

–4848

–5002

–5156

–5310

–5463

–5617

–5771

–5925

–6079

–6430

–6560

–6430

–6560

–6430

–6560

–6430

–6560

–6430

–6560

727

2

86

3

V1

87

4

V4

88

5

V5

89

6

V^SS

SEL

SHL

DI3

YSCL

V^DD

DSPOFF

FR

90

7

91

8

92

9

93

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

94

95

1283

2176

2879

3753

4560

5035

5510

5985

6560

6430

6560

6430

6560

6430

6560

6430

6560

6430

6079

5925

5771

5617

5463

5310

5156

5002

4848

4694

4540

4386

4232

96

97

V^SS

V5

98

99

V4

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

V1

V0

DIO1

O0

–610

–466

–321

–177

–32

O1

O2

O3

693

O4

539

O5

112

385

O6

257

231

690

545

O7

401

77

O8

545

–77

401

O9

690

–231

–385

–539

–693

–846

–1000

–1154

–1308

–1462

–1616

–1770

–1924

–2078

–2232

257

O10

O11

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

727

112

–32

–177

–321

–466

–610

Rev.1.0

EPSON

3–5

S1D16501 Series

6. FUNCTIONAL DESCRIPTION

Shift register

This is a bidirectional shift register to transfer common data.

Being a 50 × 2 bits configuration, this register can select 50 × 2 bits or 100 bits according to the status of SEL.

When the 50 × 2 bits configuration is selected, the input of the 50-bit shift register becomes D13.

Level shifter

This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive

level.

LCD driver

This driver outputs the LCD drive voltage.

The relationship among the display blanking signal DSPOFF, contents of shift register, AC converted signal

FR and On output voltage is as shown in the table below:

Content of

shift register

DSPOFF

FR

O output voltage

HIGH

LOW

HIGH

LOW

–

V5

HIGH

(Select level)

V0

V1

V4

V0

HIGH

LOW

(Non-select

level)

LOW

–

3–6

EPSON

Rev.1.0

S1D16501 Series

7.TIMING CHART

SHL=LOW

1/200 Duty

1 frame

(200 lines)

DIO1

(DI3)

YSCL

FR

DSPOFF

Q0

Q1

Shift

register

Q2

100 lines

DIO2

( 50 lines when D13 is input where SEL = HIGH)

V

0

1

V

O0

O1

O2

V

4

5

V

0

1

V

4

5

V

0

1

V

4

5

V

Rev.1.0

EPSON

3–7

S1D16501 Series

8. ABSOLUTE MAXIMUM RATINGS

VDD=0V

Parameter

Supply voltage (1)

Supply voltage (2)

Supply voltage (3)

Input voltage

Symbol

VSS

Rating

–7.0 to +0.3

–30.0 to +0.3

V5–0.3 to +0.3

VSS–0.3 to +0.3

20

Unit

V

V5

V

V0, V1, V4

VI

V

Output voltage

VO

V

Output current (1)

Output current (2)

Operating temperature

Storing temperature 1

IO

mA

°C

IOCOM

Topr

Tstg 1

20

–40 to + 85

–65 to +150

Notes*

1. The voltage of V0, V1, V4 and V5 must always satisfy the condition of VDD ≥ V0 ≥ V1 ≥ V4 ≥ V5.

System side

V

DD

SS

V

DD

0

V_CC

–5V

5V

GND

1

–28V

V

4

V₅

2. Floating of the logic system power during while the LCD drive system power is applied, or exceeding VSS

= –2.6 V or less can cause permanent damage to the LSI. Functional operation under these conditions is

not implied.

Care should be taken to the power supply sequence especially in the system power ON or OFF.

3–8

EPSON

Rev.1.0

S1D16501 Series

9. ELECTRICAL CHARACTERISTICS

DC characteristics

Unless otherwise specified, VDD = V0 = 0V, VSS = –5.5V–2.7V, Ta = –40 to 85°C.

Parameter

Symbol

V^SS

Condition

–

Min.

–5.5

Typ.

–5.0

Max.

–2.7

Unit

V

Applicable pin

V^SS

Supply voltage (1)

Recommended

operating voltage

–

–28.0

–

–12.0

V

V5

Operation enable voltage

Supply voltage (2)

Supply voltage (3)

Supply voltage (4)

V5

V0

V1

V4

–

2.5

–

–8.0

0

V

V5

V0

V1

V4

Functional operation

–

2/9·V⁵

V5

V^DD

7/9·V5

0.2·VSS

–

V

DIO1, DIO2, FR,

YSCL, SHL, DI3

DSPOFF, SEL

HIGH input voltage

LOW input voltage

VIH

VIL

–

0.8·V^SS

I

OH=–0.3mA

HIGH output voltage

LOW output voltage

VOH

VOL

V^DD–0.4

–

V

DIO1, DIO2

IOL=0.3mA

VSS+0.4

Input leakage

current

YSCL, SHL, DI3

DSPOFF, FR, SEL

V^SS≤ VIN ≤ 0V

ILI

–

2.0

5.0

25

µA

Input/output

leakage current

V^SS≤ VIN ≤ 0V

ILI/O

IDDS

DIO1, DIO2

V^DD

V⁵=–12.0 ~ –28.0V

V^IH=VDD, VIL=VSS

Static current

∆VON=0.5V

V⁰=VDD, V1=–1.5V

V⁴=–18.5V V5=–20.0V

Output resistance

–

0.75

7

1.0

15

kΩ

µA

RCOM

O0~O99

V^SS=–5.0V, VIH=VDD

VIL=VSS, fYSCL=12KHz

Frame frequency=60Hz

Input data: 1/200 Ta=25°C

Average operating

current

consumption (1)

ISS1

V^SS

?

- - - - - - - - - - - - - - - - - - - - - - -

V^SS=–3.0V Other conditions

- - - - - - - - - - - - - - - - - - - - - - - -

are the same as V^SS= –5.0 V

–

5

10

V^SS=–5.0V, V0=0V,

V¹=1.5V, V4=18.5V,

V^EE=V5=–20.0V

Average operating

current

consumption (2)

–

7

15

V5

ISS2

Other conditions are the

same as in the item of ISS 1.

YSCL, SHL,

DSPOFF, FR,

DI3, SEL

Input pin

capacitance

–

8

pF

–

CI

Ta=25°C

Input/output pin

capacitance

15

CI/O

DIO1, DIO2

Rev.1.0

EPSON

3–9

S1D16501 Series

AC Characteristics

Input timing characteristics

V

IH=0.2 × VSS

IL=0.8 × VSS

FR

tr

t

DFR

t

f

t

WCLH

t

WCLL

YSCL

DIO1

t

CCL

t

DH

t

DS

DIO2

DI3

VSS=–5.0V±0.5V, Ta=–40 to 85°C

Parameter

Input signal rise time

Input signal fall time

YSCL period

Symbol

tr

Condition

Min.

–

Max.

50

–

Unit

ns

–

tf

–

500

70

330

100

10

tCCL

tWCLH

tWCLL

tDS

YSCL HIGH pulsewidth

YSCL LOW pulsewidth

Data setup time

–

Data hold time

tDH

Allowable FR delay time

tDFR

–300

300

VSS=–5.0V±0.5V, Ta=–40 to 85°C

Parameter

Input signal rise time

Input signal fall time

YSCL period

Symbol

tr

Condition

Min.

Max.

50

–

Unit

ns

–

tf

–

1000

160

330

200

10

tCCL

tWCLH

tWCLL

tDS

YSCL HIGH pulsewidth

YSCL LOW pulsewidth

Data setup time

–

Data hold time

tDH

Allowable FR delay time

tDFR

–500

500

3–10

EPSON

Rev.1.0

S1D16501 Series

Output timing characteristics

V

IH=0.2 × VSS

IL=0.8 × VSS

FR

V

YSCL

t

pdDOCL

V

OH=0.2 × VSS

OL=0.8 × VSS

DIO1

DIO2

V

t

pdCCL

DSPOFF

t

pdCFR

t

pdCDFF

Vn–0.5

Vn+0.5

On

VSS=–5.0±10%, Ta=–40 to +85°C

Parament

Symbol

tpdDOCL

tpdCCL

Condition

CL=15pF

V5=–12.0 to

–28.0V

Min.

–

Max.

350

Unit

ns

(YSCL - fall to DIO) delay time

(YSCL - fall to On output) delay time

(DSPOFF to On output) delay time

(FR to On Output) delay time

–

1.0

µs

tpdCDOFF

tpdCFR

CL=100pF

VSS=–4.5–2.7V, Ta=–40 to +85°C

Parament

Symbol

tpdDOCL

tpdCCL

Condition

CL=15pF

V5=–12.0 to

–28.0V

Min.

–

Max.

400

Unit

ns

(YSCL - fall to DIO) delay time

(YSCL - fall to On output) delay time

(DSPOFF to On output) delay time

(FR to On Output) delay time

–

2.0

µs

tpdCDOFF

tpdCFR

CL=100pF

Rev.1.0

EPSON

3–11

S1D16501 Series

10. LCD DRIVE POWER

Each voltage level forming method

To obtain each voltage level for LCD driving, it is optimum to divide the resistance of potential between VDDH

and GND to drive the LCD using the voltage follower with an operational amplifier.

In taking into consideration of such a case using the operational amplifier, the maximum potential level V0

for LCD driving has been made a separate pin from VDD.

When no operational amplifier is used in V0, set V0 = VDD.

When a resistive divider is used, set it to a resistance value as low as possible in the system power capacity.

When a series resistance exists in the power supply line of VDD, a voltage drop of VDD occurs at the LSI power

supply pin, the relationship with the LCD’s intermediate potential (VDD ≥ V0 ≥ V1 ≥ V4 ≥ V5) cannot be met,

this causing the LSI to be broken down in some cases. When a protection resistor is inserted, it is necessary

to stabilize the voltage by capacitance.

Note in power ON/OFF

Since this LSI is high in the voltage of LCD driving system, when a high voltage is applied to the LCD driving

system with the logic system power supply kept floating or above VSS = –2.5 V, an overcurrent flows and LSI

breaks down in some cases.

To avoid this, it is recommended to suppress the potential of LCD drive output to V0 level using the display

off function (DSPOFF) until the LCD driving system voltage is stabilized.

Be sure to follow the power ON/OFF sequence as shown below:

At power ON ... Logic system ON

→ LCD driving system ON or simultaneous ON of the both

At power OFF ... LCD driving system OFF → Logic system OFF or simultaneous OFF of the both

For a countermeasure to such overcurrent, it is effective to put a high-speed melting fuse or protection resistor

in series with the LCD power unit.

It is then required to select the optimum value in the protection resistance according to the capacitance of LC

cell.

1

t

V

t

2

V

DD

t

V

SS

>

3

1

t

2

t

0s

=

5

V

Powern ON

Power OFF

t

3

V

DD

SS

t

DSPOFF

3–12

EPSON

Rev.1.0

S1D16501 Series

11. TYPICAL CIRCUIT DIAGRAM

Configuration Drawing of Large Screen LCD

V

SS

+

V

DD

V

0

1

2

3

r

+

–

+

–

R

r

+

–

+

–

V

4

5

r

V5

1 0 0

S 1 D 1 6 5 0 1

1 0 0

S 1 D 1 6 5 0 1

Rev.1.0

EPSON

3–13

S1D16700

Rev.1.1

CONTENTS

1. DESCRIPTION ...............................................................................................................................................4-1

2. FEATURES ....................................................................................................................................................4-1

3. BLOCK DIAGRAM .........................................................................................................................................4-2

4. PIN DESCRIPTION ........................................................................................................................................4-3

5. PAD ................................................................................................................................................................4-4

6. FUNCTIONAL DESCRIPTION .......................................................................................................................4-6

7. TIMING CHART (S1D16700D01B ) ..............................................................................................................4-7

*

8. ABSOLUTE MAXIMUM RATINGS .................................................................................................................4-8

9. ELECTRICAL CHARACTERISTICS ..............................................................................................................4-9

10. LCD DRIVE POWER ....................................................................................................................................4-12

11. CONNECT EXAMPLE..................................................................................................................................4-13

– i –

Rev.1.1

S1D16700 Series

1. DESCRIPTION

The S1D16700 is a 100 output low-power resistance common (row) driver which is suitable for driving a very

high capacity dotmatrix LCD panels upto a duty ratio of 1/300. It is intended to be used in conjunction with

the S1D16400 or S1D16006 as a pair.

Since the S1D16700 is so designed to drive LCDs over a wide range of voltages, and also the maximum

potential V0 of its LCD drive bias voltages is isolated from VDD to allow the LCD driving bias voltages to

be externally generated optionally with a high accuracy, it can cope with a wide range of LCD panels.

Owing to its pad layout which can minimize its PC boards mounting space in addition to its selectable

bidirectional driver output sequence and as many as 100 LCD output segments of high pressure resistance and

low output impedance, it is possible to obtain the highest driver working efficiency for the 1/200 duty panel.

^{And the S1D16700}*⁰¹**^{can display 65 x 132 panel when used as a common driver of RAM buit-in driver,}

S1D15301.

2. FEATURES

• Number of LCD drive output segments: 100

• Common output ON resistance: 700 Ω (Typ.)

• Display duty ratio: 1/64 to 1/300 (Reference)

• Display capacity: Possible to display 640 × 480 dots when used in combination with S1D 16400D or

S1D16006D.

• Selectable pin output shift direction

^{• No-bias display OFF function (S1D16700}*⁰¹**⁾

^{• Instantaneous display blanking enabled by inhibit function (S1D16700}*⁰⁰**⁾

• Adjustable offset bias of LCD power to VDD level

• Wide range of LCD drive voltages: –7 V to –28 V (Absolute maximum rated voltage: –30 V)

• Logic system power supply: –2.7 V to –5.5 V

• Shipping pattern

S1D16700D00A (Al pad chip)

*

S1D16700D01A (Al pad chip)

*

S1D16700D00B (Au bump chip)

*

S1D16700D01B (Au bump chip)

*

S1D16700T00A (TCP)

*

S1D16700T01A (TCP)

*

• No radial rays countermeasure taken in designing

Rev.1.1

EPSON

4–1

S1D16700 Series

3. BLOCK DIAGRAM

COM0

COM99

COM1

············

COM2

V

DD

VSS

V1

V4

V0

LCD driver 100 bit

Voltage

control circuit

V5

FR

shift register 100 bit

DIO1

YSCL

SHL

DIO2

DOFF

INH

^{INH in S1D16700}*⁰⁰**

^{DOFF in S1D16700}*⁰¹**

4–2

EPSON

Rev. 1.1

S1D16700 Series

4. PIN DESCRIPTION

Number

of pins

Pin name

I/O

O

Function

LCD drive common (row) output

COM0 to

COM099

100

2

The output changes at the YS CL falling edge.

100-bit shift register serial data input/output

To be set to input or output according to the SHL input

The output changes at the YSCL falling edge.

DIO1,

DIO2

I/O

I

Serial data shift clock input

The scanning data is shifted at the falling edge.

YSCL

1

Shift direction selection and DIO pin I/O control input

SHL

LOW

HIGH

COM output shift direction

DIO1

Input

DIO2

Output

Input

SHL

I

1

0

→

99

0

99

Ourput

LCD display blanking control input

When LOW is input, the content of shift register is cleared and all

common outputs become the V0 level instantaneously

DOFF

(INH)

1

(S1D16700D01B ).

*

LCD drive display blanking control input

When LOW is input, the content of shift register is cleared and all

common outputs become the non-select level instantaneously.

Common output = V4 (when FR = LOW)

I

(1)

Common output = V1 (when FR = HIGH) (S1D16700D00B )

*

LCD drive output AC converted signal input

FR

1

2

VDD, VSS

Power supply Logic power supply

VDD: 0 V (GND) VSS: –5.0 V

LCD drive power supply V5: –7 V to –28 V

V0, V1,

V4, V5

Power supply

4

VDD ≥ V0 ≥ V1 > V4 ≥ V5

Total: 112

^{INH for S1D16700}*⁰⁰**

^{DOFF for S1D16700}*⁰¹**

Rev.1.1

EPSON

4–3

S1D16700 Series

5. PAD

Á Pad layout

92

57

56

93

Y

X

(0,0)

37

112

1

36

Chip size ............................ 5.49mm × 3.03mm

Chip thickness .................... 525µm (Au-bump die from)

400µm (Al-Pad die from)

1) Au bump specification reference values

Bump specific : High Quarity Au bump

Bump size :

Bump height :

90µm × 90µm

17µm 28µm

2) AL Pad specification reference values

Pad Opening : 100µm × 100µm

4–4

EPSON

Rev. 1.1

S1D16700 Series

Á Pad center coordinates

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

NO.

1

X

Y

NO.

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

X

Y

NO.

81

X

Y

COM5

6

-2187

-2058

-1929

-1799

-1670

-1541

-1412

-1283

-1153

-1024

-895

-766

-637

-507

-378

-249

-120

10

-1357

COM45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

2584

-711

-581

-452

-323

-194

-65

COM85

86

-803

1357

2

82

-932

3

7

83

87

-1062

-1191

-1320

-1449

-1578

-1708

-1837

-1966

-2095

-2224

-2473

4

8

84

88

5

9

85

89

6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

89

90

7

65

87

91

8

194

323

452

581

711

840

969

1098

1231

1357

88

92

9

89

93

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

90

94

91

95

92

96

1357

1334

1201

1071

941

93

97

94

98

95

99

2584

2298

2168

2039

1910

1781

1652

1522

1393

1264

1135

1006

876

96

DIO2

DOFF

(INH)

FR

YSCL

SHL

V^DD

V^SS

V0

97

715

(97)

98

139

585

455

268

99

397

100

101

102

103

104

105

106

107

108

109

110

111

112

325

526

185

656

46

785

-112

-252

-391

-531

-671

-810

-941

-1071

-1201

-1334

914

V1

1043

1172

1302

1431

1560

1689

1818

1948

2077

2206

2335

2584

V4

V5

DIO1

COM0

1

747

618

489

2

360

3

230

4

-2473

101

-28

-1357

-1231

-1094

-969

-157

-286

-416

-545

-674

-840

1357

^{PAD No. 97: INH for S1D16700}*⁰⁰**

^{DOFF for S1D16700}*⁰¹**

Rev.1.1

EPSON

4–5

S1D16700 Series

6. FUNCTIONAL DESCRIPTION

Shift register

This is a bidirectional shift register to transfer common data.

Level shifter

This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive

level.

LCD driver circuit

This driver outputs the LCD drive voltage.

The relationship among the display blanking signal DOFF, contents of shift register, AC converted signal FR

and common output voltage is as shown in the table below:

^(S1D16700*⁰¹**⁾

Contents of

shift register

DOFF

FR

COM output voltage

HIGH

LOW

HIGH

LOW

–

V5

HIGH

(Select level)

V0

HIGH

LOW

V1

(Non-select

level)

LOW

V4

Fixed to LOW

V0

–

The relationship among the display blanking signal INH, contents of the shift register, AC converted signal

FR and COM output voltage is as shown in the table below:

^(S1D16700*⁰⁰**⁾

Contents of

shift register

INH

FR

COM output voltage

HIGH

LOW

HIGH

LOW

HIGH

LOW

V5

HIGH

(Select level)

V0

HIGH

V1

(Non-select

level)

LOW

V4

V1

(Non-select

level)

LOW

Fixed to LOW

V4

4–6

EPSON

Rev. 1.1

S1D16700 Series

7.TIMING CHART (S1D16700D01B )

*

SHL=LOW

1/200 Duty

1 frame

(200 lines)

DIO1

YSCL

FR

DSPOFF

Q0

Q1

Shift

register

Q2

100 lines

DIO2

V

0

1

O0

O1

O2

V

4

5

V

0

1

V

4

5

V

0

1

V

4

5

The V1 or V4 non-select level is output corresponding to the FR in S1D16700D00B or INH=LOW,

*

respectively.

Rev.1.1

EPSON

4–7

S1D16700 Series

8. ABSOLUTE MAXIMUM RATINGS

VDD=0V

Parameter

Supply voltage (1)

Supply voltage (2)

Supply voltage (3)

Input voltage

Symbol

VSS

Rating

–7.0 to +0.3

–30.0 to +0.3

V5–0.3 to +0.3

VSS–0.3 to +0.3

20

Unit

V

V5

V

V0, V1, V4

VI

V

Output voltage

VO

V

Output current (1)

Output current (2)

Operating temperature

Storing temperature 1

IO

mA

°C

IOCOM

Topr

Tstg

20

–40 to + 85

–65 to +150

Notes:

1. The voltage of V0, V1 and V4 must always satisfy the condition of VDD ≥ V0 ≥ V1 ≥ V4 ≥ V5.

2. Floating of the logic system power during while the LCD drive system power is applied, or exceeding VSS

= –2.6 V or more can cause permanent damage to the LSI. Functional operation under these conditions

is not implied.

Care should be taken to the power supply sequence especially in the system power ON or OFF.

4–8

EPSON

Rev. 1.1

S1D16700 Series

9. ELECTRICAL CHARACTERISTICS

DC characteristics

Unless otherwise specified, VDD = V0 = 0V, VSS = –5.0V±10%, Ta = –40 to 85°C.

Parameter

Symbol

V^SS

Condition

–

Min.

–5.5

Typ.

–5.0

Max.

–2.7

Unit

V

Applicable pin

V^SS

Supply voltage (1)

Recommended

operating voltage

V

V5

–

–28.0

–

–7.0

V5

V0

V1

V4

Operation enable voltage

Supply voltage (2)

Supply voltage (3)

Supply voltage (4)

HIGH input voltage (1)

LOW input voltage (1)

HIGH input voltage (2)

LOW input voltage (2)

V5

V0

–

–7.0

0

V

Functional operation

Recommended value

–2.5

2/9·V⁵

V5

V^DD

V1

V4

7/9·V5

0

0.2VSS

VSS

VIH

VIL

VIHT

VILT

DIO1, DIO2,

YSCL, SHL, FR

V^SS=–2.7V to –5.5V

0.8V^SS

0

0.2VSS

VSS

DOFF, INH

0.85V^SS

I

OH=–0.3mA

OH=–0.2mA

–

0

V

HIGH output voltage

LOW output voltage

VOH

^–0.4

V^SS

(V^SS=–2.7 to –4.5V)

DIO1, DIO2

I

OL=+0.3mA

OL=+0.2mA

VOL

ILI

V^SS+0.4

(V^SS=–2.7 to –4.5V)

Input leakage

current

YSCL, SHL,

DOFF, INH, FR

VSS ≤ VIN ≤ 0V

–

2.0

5.0

25

µA

–

Input/output

leakage current

V^SS≤ VIN ≤ 0V

DIO1, DIO2

V^DD

ILI/O

IDDS

V⁵=–7.0 to –28.0V

V^IH=VDD, VIL=VSS

Static current

When the

V¹, V4, V0

or V5

∆VON

=0.5V

V5=

–20.0V

RCOM

Output resistance

0.70

1.40

15

kΩ

µA

COM0~COM99

–

level is

output

V^SS=–5.0V, VIH=VDD,

V^IL=VSS, fYSCL=12KHz,

Frame frequency=60Hz

Input data; “H” at no load

every 1/200 duty

Average operating

current

consumption (1)

7

V^SS

ISS1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Other conditions are the

–

5

10

same as V^SS= –3.0 V

V^SS=–5.0, V,=–2.0V,

Average operating

current

consumption (2)

V⁴=–18.0V, V5=–20.0V

Other conditions are the

same as in the item of I^SS1.

7

15

V5

–

ISS2

Input pin

capacitance

YSCL, SHL,

DOFF, INH, FR

–

8

pF

CI

Ta=25°C

Input/output pin

capacitance

DIO1, DIO2

15

CI/O

Rev.1.1

EPSON

4–9

S1D16700 Series

AC Characteristics

Input timing characteristics

VIH=0.2 × VSS

VIL=0.8 × VSS

FR

tDFR

t^r

tWCLH

tWCLL

tf

YSCL

tCCL

tDS

tDH

DIO1

DIO2

Unless otherwise specified VSS=–5.0V±10%, Ta=–40 to 85°C

Parameter

Input signal rise time

Input signal fall time

YSCL period

YSCL HIGH pulsewidth

YSCL LOW pulsewidth

Data setup time

Symbol

tr

Condition

Min.

–

Max.

50

–

Unit

ns

–

tf

tCCL

tWCLH

tWCLL

tDS

500

70

–

330

100

10

–

Data hold time

Allowable FR delay time

tDH

–

500

tDFR

–500

Unless otherwise specified VSS=–2.7V to –4.5V, Ta=–40 to 85°C

Parameter

Input signal rise time

Input signal fall time

YSCL period

YSCL HIGH pulsewidth

YSCL LOW pulsewidth

Data setup time

Symbol

tr

Condition

Min.

–

Max.

50

–

Unit

ns

–

tf

tCCL

tWCLH

tWCLL

tDS

1000

160

330

200

10

–

Data hold time

Allowable FR delay time

tDH

–

500

tDFR

–500

The standard applicable to tCCL, tWCLH, tWCLL and tDS when VSS = –2.4 V shall be 1.3 times of that

applies when VSS = –2.7V to –4.5V.

4–10

EPSON

Rev. 1.1

S1D16700 Series

Output timing characteristics

FR

V

IH=0.2 × VSS

IL=0.8 × VSS

YSCL

tpdDOCL

DIO1

DIO2

DOFF

INH

t

pdCCL

pdCDOFF

pdCFR

t

Vn–0.5V

Vn+0.5V

COM

Unless otherwise specified VSS=–5.0V±10%, Ta=–40 to 85°C

Parament

Symbol

tpdDOCL

tpdCCL

Condition

CL=15pF

Min.

30

Max.

300

Unit

ns

(YSCL - fall to DIO) delay time

(YSCL - fall to COM output) delay time

(DOFF to COM output) delay time

(INH to COM output) delay time

(FR to COM output) delay time

V5=–7.0 to

–28.0V

tpdCDOFF

tpdCINH

tpdCFR

–

3.0

µs

CL=100pF

Unless otherwise specified VSS=–2.7V to –4.5V, Ta=–40 to 85°C

Parament

Symbol

tpdDOCL

tpdCCL

Condition

CL=15pF

Min.

60

Max.

600

Unit

ns

(YSCL - fall to DIO) delay time

(YSCL - fall to COM output) delay time

(DOFF to COM output) delay time

(INH to COM output) delay time

(FR to COM output) delay time

V5=–7.0 to

–28.0V

tpdCDOFF

tpdCINH

tpdCFR

–

3.0

µs

CL=100pF

The standard applicable at VSS = –2.4V shall be the same as that employed when VSS = –2.7V to

–4.5V.

Rev.1.1

EPSON

4–11

S1D16700 Series

10. LCD DRIVE POWER

Each voltage level forming method

To obtain each voltage level for LCD driving, it is the most simple to divide the resistance of potential as shown

in the connection example. On the other hand, to obtain a high quality display, it is necessary to raise the

accuracy and constancy of each voltage level and to set the divided resistance value as low as possible in the

range of system power capacity.

Especially when a low-power LCD driving is required, set the divided resistance to a higher value and drive

the LCD with a voltage follower by means of operational amplifier instead. In taking into consideration of

a case where the operational amplifier is employed, the maximum potential level V0 for LCD driving has been

isolated from the VDD pin.

When the potential of V0 lowers than that of VDD and the potential difference between the two becomes larger,

however, the capacity of LCD drive output driver lowers. To avoid it, use the system with the potential

difference of 0 V to 2.5 V between V0 and VDD.

When no operational amplifier is used, connect V0 and VDD pins.

Note in power ON/OFF

Since this LSI is high in the voltage of LCD driving system, when a high voltage is applied to the LCD driving

system with the logic system power supply kept floating, an overcurrent flows and LSI breaks down in some

cases.

Be sure to follow the power ON/OFF sequence as shown below:

At power ON ... Logic system ON

→ LCD driving system ON or simultaneous ON of the both

At power OFF ... LCD driving system OFF → Logic system OFF or simultaneous OFF of the both

4–12

EPSON

Rev. 1.1

S1D16700 Series

11. CONNECT EXAMPLE

FR

LP

D0–3

XSCL

FR

LP

D0–3

XSCL

FR

LP

D0–3

XSCL

COM

99

S1D16006D

0

99

0

Note *1 It must be provided as the protective resister against overcurrent. Also,

the bypass capacitor (0.01 µF) for noise suppression must be provided

near to VSS and V5 terminals on each LSI.

Rev.1.1

EPSON

4–13

S1D16702

Rev.1.0

CONTENTS

1. DESCRIPTION ...............................................................................................................................................5-1

2. FEATURES ....................................................................................................................................................5-1

3. BLOCK DIAGRAM .........................................................................................................................................5-2

4. PIN DESCRIPTION ........................................................................................................................................5-3

5. PIN LAYOUT ..................................................................................................................................................5-4

6. PAD ................................................................................................................................................................5-5

7. FUNCTIONAL DESCRIPTION .......................................................................................................................5-6

8. TIMING CHART .............................................................................................................................................5-7

9. ABSOLUTE MAXIMUM RATINGS .................................................................................................................5-8

10. ELECTRICAL CHARACTERISTICS ..............................................................................................................5-9

11. LCD DRIVE POWER ....................................................................................................................................5-13

12. DIFFERENT POINTS FROM REPLACEMENT PRODUCT ........................................................................5-14

– i –

Rev.1.0

S1D16702 Series

1. DESCRIPTION

The S1D16702 is a 68 output low-power resistance common (row) driver which is suitable for driving a very

high capacity dotmatrix LCD panels up to a duty ratio of 1/300. It is intended to be used in conjunction with

the S1D16006 as a pair.

Since the S1D16006 is so designed to drive LCD’s over a wide range of voltages, and also the maximum

potential V0 of its LCD drive bias voltages is isolated from VDD to allow the LCD driving bias voltages to

be externally generated optionally with a high accuracy, it can cope with a wide range of LCD panels.

The S1D16702 is featured in its simple pad layout which is easy in mounting PC boards in addition to its

selectable bidirectional driver output sequence. It also has 68 LCD output segments of high pressure

resistance and low output impedance.

It can display the 65 × 132 panel when used as the expansion driver of S1D15301 being built in RAM

^(S1D16702*⁰¹**^).

2. FEATURES

• Number of LCD drive output segments: 68

• Common output ON resistance: 700 Ω (Typ.)

• Display duty ratio: 1/64 to 1/300 (Reference)

• Display capacity: Possible to display 640 × 480 dots when used in combination with S1D16006.

• Selectable pin output shift direction

^{• Instantaneous display blanking enabled by inhibit function (S1D16702}*⁰⁰**⁾

^{• Non-bias display off function (S1D16702}*⁰¹**⁾

• Adjustable offset bias of LCD power to VDD level

• Wide range of LCD drive voltages: –7 V to –28 V (Absolute maximum rated voltage: –30 V)

• Logic system power supply: –2.7 V to –5.5 V

• Shipping pattern

S1D16702D00A (Al pad chip)

*

S1D16702D01A (Al pad chip)

*

S1D16702F00A (80-pin QFP5)

*

• No radial rays countermeasure taken in designing

• Non-bias display off function

Rev.1.0

EPSON

5–1

S1D16702 Series

3. BLOCK DIAGRAM

COM0

COM67

COM1

············

COM2

V

DD

VSS

V1

V4

V0

LCD driver 68 bit

V5

FR

shift register 68 bit

DIO1

YSCL

SHL

DIO2

INH

* DOFF

^{* INH in S1D16702}*⁰⁰**

^{DOFF in S1D16702}*⁰¹**

5–2

EPSON

Rev.1.0

S1D16702 Series

4. PIN DESCRIPTION

Number

of pins

Pin name

I/O

O

Function

LCD drive common (row) output

COM0 to

COM67

68

2

The output changes at the YSCL falling edge.

100-bit shift register serial data input/output

To be set to input or output according to the SHL input

The output changes at the YSCL falling edge.

DIO1,

DIO2

I/O

I

Serial data shift clock input

The scanning data is shifted at the falling edge.

YSCL

1

Display data latch pulse input (Falling edge trigger)

Shift direction selection and DIO pin I/O control input

SHL

LOW

HIGH

COM output shift direction

DIO1

Input

DIO2

Output

Input

SHL

I

1

0

→

67

0

67

Ourput

LCD display blanking control input when LOW is input, the

content of shift register is cleared and all common outputs

DOFF

INH

^{become the non-select level instantaneously. (S1D16702}*⁰¹**⁾

LCD display blanking control input

When LOW is input, the content of shift register is cleared and all

common outputs become the non-select level instantaneously.

Common output = V4 (when FR = LOW)

I

(1)

^{Common output = V1 (when FR = HIGH) (S1D16702}*⁰⁰**⁾

FR

LCD drive output AC converted signal input

1

2

VDD, VSS

Power supply Logic power supply

VDD: 0 V (GND) VSS: –5.0 V

V0, V1,

V4, V5

LCD drive power supply V5: –7 V to –28 V

Power supply

4

VDD ≥ V0 ≥ V1 >V4 ≥ V5

^{INH in S1D16702}*⁰⁰**

^{DOFF in S1D16702}*⁰¹**

Rev.1.0

EPSON

5–3

S1D16702 Series

5. PIN LAYOUT

Package type: QFP–5 80pin

64

41

65

40

S1D16702F00A

INDEX

80

25

1

24

PIN No.

Pin Name

PIN No.

Pin Name

PIN No.

Pin Name

PIN No.

Pin Name

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

COM 3

COM 4

COM 5

COM 6

COM 7

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

COM 23

COM 24

COM 25

COM 26

COM 27

COM 28

COM 29

COM 30

COM 31

COM 32

COM 33

COM 34

COM 35

COM 36

COM 37

COM 38

COM 39

COM 40

COM 41

COM 42

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

COM 43

COM 44

COM 45

COM 46

COM 47

COM 48

COM 49

COM 50

COM 51

COM 52

COM 53

COM 54

COM 55

COM 56

COM 57

COM 58

COM 59

COM 60

COM 61

COM 62

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

COM 63

COM 64

COM 65

COM 66

COM 67

DIO2

INH

FR

YSCL

SHL

VDD

VSS

V0

V1

V4

V5

DIO1

COM 0

COM 1

COM 2

COM 8

COM 9

COM 10

COM 11

COM 12

COM 13

COM 14

COM 15

COM 16

COM 17

COM 18

COM 19

COM 20

COM 21

COM 22

5–4

EPSON

Rev.1.0

S1D16702 Series

6. PAD

Á Pad layout

72

46

73

45

Y

X

(0,0)

90

28

27

1

Chip size:

4.27 × 3.03 mm

Chip thickness: 400 µm (for AL pad product) and 525 µm (for BUMP product).

AL pad product: Pad opening is 100 × 100 µm.

BUMP product: Vertical Au bump.

Bump size is 90 × 90 µm.

Bump height is 17 to 25 µm.

Á Pad center coordinates

PAD

NO.

PAD

NO.

NAME

PAD

NO.

NAME

X

Y

X

Y

X

Y

NAME

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

DM

–1579

–1357

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

COM 29

COM 30

COM 31

COM 32

COM 33

COM 34

COM 35

COM 36

COM 37

COM 38

COM 39

COM 40

COM 41

COM 42

DM

1976

–711

–581

–452

–323

–194

–65

65

194

323

452

581

711

840

969

1098

1357

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

COM 56

COM 57

COM 58

COM 59

COM 60

COM 61

COM 62

COM 63 –1099

COM 64 –1229

COM 65 –1358

COM 66 –1487

–195

–324

–453

–583

–712

–841

–970

1357

COM 3 –1449

COM 4 –1320

COM 5 –1191

COM 6 –1062

COM 7

COM 8

COM 9

COM 10

COM 11

COM 12

COM 13

COM 14

COM 15

COM 16

COM 17

COM 18

COM 19

COM 20

COM 21

COM 22

COM 23

COM 24

COM 25

COM 26

DM

–933

–803

–674

–545

–416

–287

–154

–28

101

230

359

489

DM

COM 67

DIO2

–1616

–1865

1357

1201

1071

941

715

585

455

325

195

55

–112

–252

–391

–531

–671

–810

–941

–1071

–1201

1976

1743

1614

1485

1355

1226

1097

968

839

709

580

451

*1

DM

INH

FR

YSCL

SHL

V^DD

618

747

876

COM 43

COM 44

COM 45

COM 46

COM 47

COM 48

COM 49

COM 50

COM 51

COM 52

COM 53

COM 54

COM 55

1005

1135

1264

1393

1522

1651

1781

1976

V^SS

V⁰

V¹

V⁴

V⁵

DIO1

COM 0

COM 1

COM 2

DM

COM 27

COM 28

–1357

–1098

–969

322

193

63

–66

–840

1357

–1865

^{*1 PAD No. 76: INH for S1D16702}*⁰⁰**

^{DOFF for S1D16702}*⁰¹**

Rev.1.0

EPSON

5–5

S1D16702 Series

7. FUNCTIONAL DESCRIPTION

Shift register

This is a bidirectional shift register to transfer common data.

Level shifter

This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive

level.

LCD driver circuit

This driver outputs the LCD drive voltage.

The relationship among the display blanking signal INH, contents of shift register, AC converted signal FR

and common output voltage is as shown in the table below:

^(S1D16702*⁰⁰**⁾

Contents of

shift register

INH

FR

COM output voltage

HIGH

LOW

HIGH

LOW

HIGH

LOW

V5

HIGH

(Select level)

V0

HIGH

V1

V4

V1

V4

(Non-select

level)

LOW

(Non-select

level)

LOW

Fixed to LOW

The relationship among the display blanking signal INH, contents of shift register, AC converted signal FR

and common output voltage is as shown in the table below.

^(S1D16702*⁰¹**⁾

Contents of

shift register

DOFF

FR

COM output voltage

HIGH

LOW

HIGH

LOW

V5

HIGH

(Select level)

V0

HIGH

V1

V4

(Non-select

level)

LOW

(Non-select

level)

LOW

Fixed to LOW

—

V0

5–6

EPSON

Rev.1.0

S1D16702 Series

8.TIMING CHART

SHL=LOW

1/200 Duty

1 frame

(200 lines)

DIO1

YSCL

FR

INH

Q0

Q1

Shift

register

Q2

68 lines

DIO2

V

0

1

O0

O1

O2

V

4

5

V

0

1

V

4

5

V

0

1

V

4

5

Rev.1.0

EPSON

5–7

S1D16702 Series

9. ABSOLUTE MAXIMUM RATINGS

VDD=0V

Parameter

Supply voltage (1)

Supply voltage (2)

Supply voltage (3)

Input voltage

Symbol

VSS

Rating

–7.0 to +0.3

–30.0 to +0.3

V5–0.3 to +0.3

VSS–0.3 to +0.3

20

Unit

V

V5

V

V0, V1, V4

VI

V

Output voltage

VO

V

Output current (1)

Output current (2)

Operating temperature

Storing temperature

Soldering temperature and time

IO

mA

°C

–

IOCOM

Topr

Tstg

Tsol

20

–40 to + 85

–65 to +150

260°C · 10sec

Notes:

1. The voltage of V0, V1 and V4 must always satisfy the condition of VDD ≥ V0 ≥ V1 ≥ V4 ≥ V5.

2. Floating of the logic system power during while the LCD drive system power is applied, or exceeding VSS

= –2.6 V or more can cause permanent damage to the LSI. Functional operation under these conditions

is not implied.

Care should be taken to the power supply sequence especially in the system power ON or OFF.

3. All the above voltage is based on VDD = 0 V.

5–8

EPSON

Rev.1.0

S1D16702 Series

10. ELECTRICAL CHARACTERISTICS

DC characteristics

Unless otherwise specified, V^DD= V0 = 0V, VSS = –5.0V±10%, Ta = –40 to 85°C.

Parameter

Symbol

V^SS

Condition

–

Min.

–5.5

Typ.

–5.0

Max.

–2.7

Unit

V

Applicable pin

V^SS

Supply voltage (1)

Recommended

operating voltage

–

–28.0

–

–7.0

V

V5

Operation enable voltage

Supply voltage (2)

Supply voltage (3)

Supply voltage (4)

HIGH input voltage (1)

LOW input voltage (1)

HIGH input voltage (2)

LOW input voltage (2)

V5

V0

–

–7.0

0

V

V5

V0

V1

V4

Functional operation

Recommended value

–2.5

2/9·V⁵

V5

V1

V^DD

7/9·V5

0

V4

VIH

VIL

VIHT

VILT

0.2VSS

VSS

DIO1, DIO2,

YSCL, SHL, FR

V^SS=–2.7V to –5.5V

0.8V^SS

0

0.2VSS

VSS

INH

0.85V^SS

I

OH=–0.3mA

OH=–0.2mA

HIGH output voltage

LOW output voltage

VOH

^–0.4

V^SS

–

0

V

(V^SS=–2.7 to –4.5V)

DIO1, DIO2

I

OL=+0.3mA

OL=+0.2mA

V^SS+0.4

VOL

ILI

(V^SS=–2.7 to –4.5V)

YSCL, SHL,

INH, FR

Input leakage

current

VSS ≤ VIN ≤ 0V

–

2.0

5.0

25

µA

Input/output

leakage current

V^SS≤ VIN ≤ 0V

DIO1, DIO2

V^DD

ILI/O

IDDS

V⁵=–7.0 to –28.0V

V^IH=VDD, VIL=VSS

Static current

When the

V¹, V4, V0

or V5

∆VON

=0.5V

V5=

–20.0V

RCOM

COM0 to COM99

Output resistance

–

0.70

1.40

15

kΩ

µA

level is

output

V^SS=–5.0V, VIH=VDD,

V^IL=VSS, fYSCL=12KHz,

Frame frequency=60Hz

Input data; HIGH at no load

every 1/200 duy

Average operating

current

consumption (1)

7

V^SS

ISS1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Other conditions are the

–

5

10

same as V^SS= –3.0 V

V^SS=–5.0V, V1=–2.0V,

V⁴=–18.0V, V5=–20.0V

Other conditions are the

same as in the item of I^SS1.

Average operating

current

consumption (2)

V5

–

7

15

ISS2

Input pin

capacitance

YSCL, SHL,

INH, FR

–

8

pF

CI

Ta=25°C

Input/output pin

capacitance

15

DIO1, DIO2

CI/O

Rev.1.0

EPSON

5–9

S1D16702 Series

Operating Voltage Range VSS – V5

V5 voltage must be set within the following operating voltage range of VSS – V5.

–30

–28

–20

Operating Voltage Range

–10

–7

0

–2.0

–2.4

–3.0

–4.0

(V)

–5.0

–5.5

–6.

0

VSS

5–10

EPSON

Rev.1.0

S1D16702 Series

AC Characteristics

Input timing characteristics

VIH=0.2 × VSS

VIL=0.8 × VSS

FR

tDFR

t^r

tWCLH

tWCLL

tf

YSCL

tCCL

tDS

tDH

DIO1

DIO2

Unless otherwise specified VSS=–5.0V±10%, Ta=–40 to 85°C

Parameter

Input signal rise time

Input signal fall time

YSCL period

Symbol

tr

Condition

Min.

–

Max.

50

–

Unit

ns

–

tf

–

500

70

tCCL

tWCLH

tWCLL

tDS

YSCL HIGH pulsewidth

YSCL LOW pulsewidth

Data setup time

–

330

100

10

–

Data hold time

Allowable FR delay time

tDH

–

500

tDFR

–500

Unless otherwise specified VSS=–2.7V to –4.5V, Ta=–40 to 85°C

Parameter

Input signal rise time

Input signal fall time

YSCL period

Symbol

tr

Condition

Min.

–

Max.

50

–

Unit

ns

–

tf

–

tCCL

tWCLH

tWCLL

tDS

1000

160

330

200

10

YSCL HIGH pulsewidth

YSCL LOW pulsewidth

Data setup time

–

Data hold time

tDH

Allowable FR delay time

tDFR

–500

500

The standard applicable to tCCL, tWCLH, tWCLL, tDS and tDH when VSS = –2.4 V must be 1.3 times

of that applies when VSS = –2.7 V to –4.5 V.

Rev.1.0

EPSON

5–11

S1D16702 Series

Output timing characteristics

FR

V

IH=0.2 × VSS

IL=0.8 × VSS

YSCL

t

pdDOCL

DIO1

DIO2

INH

t

pdCCL

pdCINH

pdCFR

t

Vn–0.5V

Vn+0.5V

COM

Unless otherwise specified VSS=–5.0V±10%, Ta=–40 to 85°C

Parament

Symbol

tpdDOCL

tpdCCL

tpdCINH

tpdCFR

Condition

CL=15pF

V5=–7.0 to

–28.0V

Min.

30

Max.

300

Unit

ns

(YSCL - fall to DIO) delay time

(YSCL - fall to COM output) delay time

(INH to COM output) delay time

(FR to COM output) delay time

–

3.0

µs

CL=100pF

Unless otherwise specified VSS=–2.7V to –4.5V, Ta=–40 to 85°C

Parament

Symbol

tpdDOCL

tpdCCL

tpdCINH

tpdCFR

Condition

CL=15pF

V5=–7.0 to

–28.0V

Min.

60

Max.

600

Unit

ns

(YSCL - fall to DIO) delay time

(YSCL - fall to COM output) delay time

(INH to COM output) delay time

(FR to COM output) delay time

–

3.0

µs

CL=100pF

The standard applicable when VSS = –2.4 V must be 1.3 times of that applies when VSS = –2.7 V

to –4.5 V.

5–12

EPSON

Rev.1.0

S1D16702 Series

11. LCD DRIVE POWER

Each voltage level forming method

To obtain each voltage level for LCD driving, it is the most simple to divide the resistance of potential as shown

in the connection example.

On the other hand, to obtain a high quality display, it is necessary to raise the accuracy and constancy of each

voltage level and to set the divided resistance value as low as possible in the range of system power capacity.

Especially when a low-power LCD driving is required, set the divided resistance to a higher value and drive

the LCD with a voltage follower by means of operational amplifier instead. In taking into consideration of

a case where the operational amplifier is employed, the maximum potential level V0 for LCD driving has been

isolated from the VDD pin. When the potential of V0 lowers than that of VDD and the potential difference

between the two becomes larger, however, the capacity of LCD drive output driver lowers. To avoid it, use

the system with the potential difference of 0 V to 2.5 V between V0 and VDD.

When no operational amplifier is used, connect V0 and VDD pins.

Note in power ON/OFF

Since this LSI is high in the voltage of LCD driving system, when a high voltage is applied to the LCD driving

system with the logic system power supply kept floating, an overcurrent flows and LSI breaks down in some

cases.

Be sure to follow the power ON/OFF sequence as shown below:

At power ON ... Logic system ON

→ LCD driving system ON or simultaneous ON of the both

At power OFF ... LCD driving system OFF → Logic system OFF or simultaneous OFF of the both

Precautions:

Users of this development specification are reminded of the following precautions.

1. This development specification is subject to change without previous notice.

2. This specificatino does not warrant the user to exercise the industrial property right or other rights, nor does

this specification vest such rights to the user.

Application examples provided in this specification are solely intended to ensure better understanding of

the product. The manufacturer shall not be liable for any circuit related problem arising from using such

examples.

Numeric representation of measure or size provided in the characteristics table is one obtained from the

numeric line.

3. No part of this specification may be reproduced or duplicated in any form or by any means without the

written permission of the manufacturer.

4. As for use of semiconductor elements, users are required to pay attention to the following points.

[Precautions on the Product Handling in Light]

Characteristics of semiconductor elements are changed if they are exposed to light. Thus, exposing this

IC to light can result in its in malfunction. In order to prevent IC malfunctioning due to light, make sure

that the following measures are taken for the boards or products equipped with our IC.

(1) Design and mounting procedure employed do not allow light to IC.

(2) The inspection process is implemented in the environment that does not allow light to IC.

(3) Light shielding measures are established not only for surface of IC but also for rear face and side faces,

too.

Rev.1.0

EPSON

5–13

S1D16702 Series

12. DIFFERENT POINTS FROM REPLACEMENT PRODUCT

^S1D16702*⁰⁰**

^S1D16300*****

Function

Bidirectional shift register

INH

68 output segments

Output Tr configuration

PAD layout

Fig. 1

Fig. 2

Identical to the equivalent product

Different from the equivalent product

–

PAD coordinates

COM

V

0

V0

V1

V4

V5

V

1

V5

V4

Fig. 1

FIg. 2

5–14

EPSON

Rev.1.0

International Sales Operations

AMERICA

ASIA

EPSON ELECTRONICS AMERICA, INC.

HEADQUARTERS

150 River Oaks Parkway

EPSON (CHINA) CO., LTD.

28F, Beijing Silver Tower 2# North RD DongSanHuan

ChaoYang District, Beijing, CHINA

Phone : 64106655

Fax : 64107319

San Jose, CA 95134, U.S.A.

Phone : +1-408-922-0200

Fax : +1-408-922-0238

SHANGHAI BRANCH

4F, Bldg., 27, No. 69, Gui Jing Road

Caohejing, Shanghai, CHINA

SALES OFFICES

West

1960 E. Grand Avenue

Phone : 21-6485-5552

Fax : 21-6485-0775

El Segundo, CA 90245, U.S.A.

EPSON HONG KONG LTD.

20/F., Harbour Centre, 25 Harbour Road

Wanchai, Hong Kong

Phone : +1-310-955-5300

Fax : +1-310-955-5400

Central

Phone : +852-2585-4600

Telex : 65542 EPSCO HX

Fax : +852-2827-4346

101 Virginia Street, Suite 290

Crystal Lake, IL 60014, U.S.A.

Phone : +1-815-455-7630

Fax : +1-815-455-7633

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

10F, No. 287,Nanking East Road, Sec. 3

Taipei

Northeast

301 Edgewater Place, Suite 120

Wakefield, MA 01880, U.S.A.

Phone : +1-781-246-3600

Phone : 02-2717-7360

Fax : 02-2712-9164

Telex : 24444 EPSONTB

Fax : +1-781-246-5443

HSINCHU OFFICE

13F-3, No.295, Kuang-Fu Road, Sec. 2

HsinChu 300

Phone : 03-573-9900

Southeast

3010 Royal Blvd. South, Suite 170

Alpharetta, GA 30005, U.S.A.

Phone : +1-877-EEA-0020 Fax : +1-770-777-2637

Fax : 03-573-9169

EPSON SINGAPORE PTE., LTD.

No. 1 Temasek Avenue, #36-00

EUROPE

EPSON EUROPE ELECTRONICS GmbH

HEADQUARTERS

Millenia Tower, SINGAPORE 039192

Phone : +65-337-7911

Fax : +65-334-2716

Riesstrasse 15

SEIKO EPSON CORPORATION

80992 Munich, GERMANY

Phone : +49- (0) 89-14005-0

Fax : +49- (0) 89-14005-110

KOREA OFFICE

50F, KLI 63 Bldg., 60 Yoido-dong

SALES OFFICE

Altstadtstrasse 176

Youngdeungpo-Ku, Seoul, 150-763, KOREA

Phone : 02-784-6027

Fax : 02-767-3677

51379 Leverkusen, GERMANY

Phone : +49- (0) 2171-5045-0 Fax : +49- (0) 2171-5045-10

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

UK BRANCH OFFICE

Unit 2.4, Doncastle House, Doncastle Road

Bracknell, Berkshire RG12 8PE, ENGLAND

Phone : +44- (0) 1344-381700 Fax : +44- (0) 1344-381701

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5816

Fax: +81-(0)42-587-5624

FRENCH BRANCH OFFICE

1 Avenue de l’ Atlantique, LP 915 Les Conquerants

Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE

Phone : +33- (0) 1-64862350 Fax : +33- (0) 1-64862355

ED International Marketing Department

Europe & U.S.A.

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5812

Fax: +81-(0)42-587-5564

BARCELONA BRANCH OFFICE

Barcelona Design Center

Edificio Prima Sant Cugat

Avda. Alcalde Barrils num. 64-68

E-08190 Sant Cugat del Vallès, SPAIN

Phone : +34-93-544-2490

ED International Marketing Department

Asia

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5814

Fax: +81-(0)42-587-5110

Fax: +34-93-544-2491


型号：	SED1640D0B
厂家：	SEIKO EPSON CORPORATION
描述：	Liquid Crystal Driver, 80-Segment, CMOS 驱动接口集成电路
文件：	总86页 (文件大小：523K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SED1640D0B [SEIKO]

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