SC1154CSW.TRT [SEMTECH]
Switching Controller, 2A, PDSO28, SOIC-28;
| 型号： | SC1154CSW.TRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Switching Controller, 2A, PDSO28, SOIC-28 控制器 |
| 文件： | 总18页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
FEATURES
The SC1154 is a synchronous-buck switch-mode con-
troller designed for use in single ended power supply
applications where efficiency is the primary concern.
The controller is a hysteretic type, with a user se-
lectable hysteresis. The SC1154 is ideal for imple-
menting DC/DC converters needed to power advanced
microprocessors such as Pentium® ll, in both single
and multiple processor configurations. Inhibit, under-
voltage lockout and soft-start functions are included for
controlled power-up.
•
•
•
•
•
•
Programmable hysteresis
5 bit DAC programmable output (1.3V-3.5V)
On-chip power good and OVP functions
Designed to meet latest Intel specifications
Up to 95% efficiency
+1% tolerance over temperature
APPLICATIONS
•
•
•
•
Server Systems and Workstations
Pentium® II Core Supply
SC1154 features include an integrated 5 bit D/A con-
verter, temperature compensated voltage reference,
current limit comparator, over-current protection, and
an adaptive deadtime circuit to prevent shoot-through
of the power MOSFET during switching transitions.
Power good signaling, logic compatible shutdown, and
over-voltage protection are also provided. The inte-
grated D/A converter provides programmability of out-
put voltage from 2.0V to 3.5V in 100mV increments
and 1.3V to 2.05V in 50mV increments with no external
components.
Multiple Microprocessor Supplies
Voltage Regulator Modules
ORDERING INFORMATION
DEVICE(1)
PACKAGE
TEMP. RANGE (TJ)
SC1154CSW
SO-28
0 - 125°C
Note:
The SC1154 high side driver can be configured as ei-
ther a grounded reference or as a floating bootstrap
driver. High and low side drivers have a peak current
rating of 2 amps.
(1) Add suffix ‘TR’ for tape and reel.
PIN CONFIGURATION
SIMPLIFIED BLOCK DIAGRAM
Top View
(28-Pin SOIC)
1
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Maximum
Units
VIN12V
VINMAX
14
V
V
BOOT to DRVGND
25
15
BOOT to BOOTLO
V
Digital Inputs
-0.3 to +7.3
+0.5V
14
V
AGND to DRVGND
V
LOHIB to AGND
V
LOSENSE to AGND
14
V
IOUTLO to AGND
14
V
HISENSE to AGND
14
V
VSENSE to AGND
5
V
Continuous Power Dissipation, TA = 25°C
Continuous Power Dissipation, TC = 25°C
Operating Junction Temperature
Lead Temperature (Soldering) 10 seconds
Storage Temperature
PD
PD
1.2
W
W
°C
°C
°C
6.25
TJ
0 to +125
300
TL
TSTG
-65 to 150
2
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
PIN DESCRIPTION
Pin Pin Name Pin Function
1
2
3
4
IOUT
Current Out. The output voltage on this pin is proportional to the load current as measured
across the high side MOSFET, and is approximately equal to 2 x RDS(ON) x ILOAD
.
DROOP Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a
function of load current. The voltage is set by a resistor divider between IOUT and AGND.
OCP
Over Current Protection. This pin is used to set the trip point for over current protection by a
resistor divider between IOUT and AGND.
VHYST Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor
divider between VREFB and AGND.
5
6
VREFB Buffered Reference Voltage (from VID circuitry).
VSENSE Output Voltage Sense.
7
AGND
SOFTST Soft Start. Connecting a capacitor from this pin to AGND sets the time delay.
NC Not connected
Small Signal Analog and Digital Ground.
8
9
10
LODRV Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is
grounded, this pin can be used to control LOWDR.
11
12
13
14
15
16
17
18
19
LOHIB
Low Side Inhibit. This pin is used to eliminate shoot-thru current.
DRVGND Power Ground.
LOWDR Low Side Driver Output.
DRV
Drive Regulator for the MOSFET Drivers.
VIN12V 12V Supply.
BOOT
Bootstrap. This pin is used to generate a floating drive for the high side FET driver.
HIGHDR High Side Driver Output.
BOOTLO Bootstrap Low. In desktop applications, this pin connects to DRVGND.
HISENSE High Current Sense. Connected to the drain of the high side FET, or the input side of a current
sense resistor between the input and the high side FET.
20 LOSENSE Low Current Sense. Connected to the source of the high side FET, or the FET side of a current
sense resistor between the input and the high side FET.
21
IOUTLO This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin
when the high side FET is on.
22
INHIBIT Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V
through a pull-up resistor.
23
24
25
26
27
VID4(1)
VID3(1)
VID2(1)
VID1(1)
VID0(1)
Programming Input (MSB).
Programming Input.
Programming Input.
Programming Input.
Programming Input (LSB).
28 PWRGD(1) Power Good. This open collector logic output is high if the output voltage is within 5% of the set
point.
3
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
ELECTRICAL CHARACTERISTICS
Unless specified: 0 < TJ < 125°C, VIN = 12V
PARAMETER
SYMBOL
VIN12V
IINq
CONDITIONS
MIN TYP MAX UNITS
Supply Voltage Range
Supply Current (Quiescent)
11.4 12
15
13
V
INH = 5V, VID not 11111,
mA
VIN above UVLO threshold during start-up,
fSW = 200kHz, BOOTLO = 0V,
CDH = CDL = 50pF
High Side Driver Supply
Current (Quiescent)
I
BOOTq
INH = 0V or VID = 11111 or VIN below
UVLO threshold during start-up,
BOOT = 13V, BOOTLO = 0V
10
µA
INH = 5V, VID not 11111, VIN
above UVLO threshold during start-up,
fSW = 200kHz, BOOT = 13V, BOOTLO = 0V,
CDH = 50pF
5
mA
REFERENCE/VOLTAGE IDENTIFICATION
Reference Voltage Accuracy
VREF
VTH(H)
VTH(L)
11.4V < VIN12V < 12.6V, over full VID
range (see Output Voltage Table)
-1
1
1
%
V
VID0 - VID4 High Threshold
Voltage
2.25
VID0 - VID4 Low Threshold
Voltage
V
POWER GOOD
Undervoltage Threshold
Output Saturation Voltage
Hysteresis
VTH(PWRGD)
VSAT
90
0.5
10
95 % VREF
IO = 5mA
V
VHYS(PWRGD)
mV
OVER VOLTAGE PROTECTION
OVP Trip Point
Hysteresis(1)
VOVP
VHYS(OVP)
12
15
10
20
%VREF
mV
4
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
ELECTRICAL CHARACTERISTICS (cont.)
Unless specified: 0 < TJ < 125°C, VIN = 12V
PARAMETER
SOFT START
Charge Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ICHG
VSS = 0.5V, resistance from
VREFB pin to AGND = 20kΩ,
VREFB = 1.3V
10.4
13
15.6
µA
Note: ICHG = (IVREFB / 5)
Discharge Current
INHIBIT COMPARATOR
Start Threshold
Idischg
V(S/S) = 1V
1
mA
V
VstartINH
1
2.0
2.4
VIN12V UVLO
Start Threshold
VstartUVLO
VhysUVLO
9.25
1.8
10
2
10.75
2.2
V
V
Hysteresis
HYSTERETIC COMPARATOR
Input Offset Voltage
Input Bias Current
Hysteresis Accuracy
Hysteresis Setting
DROOP COMPENSATION
Initial Accuracy
VosHYSCMP VDROOP pin grounded
5
1
mV
µA
IbiasHYSCMP
VHYS_ACC
7
mV
mV
VHYS_SET
60
VDROOP_ACC VDROOP = 50mV
5
mV
OVERCURRENT PROTECTION
OCP Trip Point
VOCP
0.09
0.1
2
0.11
100
V
Input Bias Current
HIGH-SIDE VDS SENSING
Gain
IbiasOCP
nA
V/V
mV
µA
Initial Accuracy
VIOUT_ACC VHISENSE = 12V, VIOUTLO = 11.9V
6
IOUT Source
IsourceIOUT VIOUT = 0.5V, VHISENSE = 12V,
VIOUTLO = 11.5V
500
40
0
IOUT Sink Current
IsinkIOUT VIOUT = 0.05V, VHISENSE = 12V,
VIOUTLO = 12V
50
µA
V
Output Voltage Swing
VHISENSE = 11V,
RIOUT = 10k0hm
3.75
5
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
ELECTRICAL CHARACTERISTICS (cont.)
Unless specified: 0 < TJ < 125°C, VIN12V = 12V
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HIGH-SIDE VDS SENSING (cont.)
V
HISENSE = 4.5V,
0
2.0
1.0
V
RIOUT = 10kOhm
VHISENSE = 3V, RIOUT = 10kOhm
0
V
V
LOSENSE High Level Input
Voltage
VihLOSENSE VHISENSE = 4.5V (Note 1)
2.85
LOSENSE Low Level Input
Voltage
VilLOSENSE VHISENSE = 4.5V (Note 1)
1.8
80
V
Sample/Hold Resistance
RS/H
4.5V < = 13V
50
65
2
Ω
BUFFERED REFERENCE
VREFB Load Regulation
DEADTIME CIRCUIT
VldregREFB 10µA < IREFB < 500µA
mV
LOHIB High Level Voltage
VihLOHIB
VilLOHIB
2
2
V
V
LOHIB Low Level Input
Voltage
1.0
LOWDR High Level Input
Voltage
VihLOWDR (Note 1)
V
V
LOWDR Low Level Input
Voltage
VilLOWDR
(Note 1)
1.0
9
DRIVE REGULATOR
Output Voltage
VDRV
11.4 < VIN12V < 12.6V,
IDRV = 50mA
7
V
Load Regulation
VldregDRV 1mA < IDRV < 50mA
IshortDRV
100
mV
mA
Short Circuit Current
HIGH-SIDE OUTPUT DRIVER
Peak Output Current
100
2
IsrcHIGHDR’ duty cycle < 2%, tpw < 100us,
IsinkHIGHDR
A
TJ = 125°C
VBOOT - VBOOTLO = 6.5V, VHIGHDR
= 1.5V (src), or VHIGHDR = 5V
(sink) (Note 1)
6
652 MITCHELL ROAD NEWBURY PARK CA 91320
© 2000 SEMTECH CORP.
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
ELECTRICAL CHARACTERISTICS (cont.)
Unless specified: 0 < TJ < 125°C, VIN12V = 12V
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HIGH-SIDE OUTPUT DRIVER (cont.)
Output Resistance
RsrcHIGHDR’
45
TJ = 125°C
VBOOT - VBOOTLO = 6.5V,
VHIGHDR = 6V
Ω
RsinkHIGHDR
5
TJ = 125°C
VBOOT - VBOOTLO = 6.5V,
VHIGHDR = 0.5V
LOW-SIDE OUTPUT DRIVER
Peak Outout Current
IsrcLOWDR’ duty cycle < 2%, tpw < 100us,
2
IsinkLOWDR
TJ = 125°C
A
VDRV = 6.5V, VLOWDR = 1.5V
(src), or VLOWDR = 5V (sink)
(Note 1)
Output Resistance
RsrcLOWDR’
RsinkLOWDR
45
5
TJ = 125°C
VDRV = 6.5V, VLOWDR = 6V
Ω
TJ = 125°C
VDRV = 6.5V, VLOWDR = 0.5V
HYSTERETIC COMPARATORS(1)
Propagation Delay Time
from
tHCPROP
10mV overdrive,
1.3V < Vref < 3.5V
150
250
ns
VSENSE to HIGHDR or
LOWDR (excluding
deadtime)
OUTPUT DRIVERS
HIGHDR rise/fall time
trHIGHDR
Cl = 9nF, VBOOT = 6.5v,
60
60
ns
ns
,tfHIGHDR VBOOTLO = grounded,
TJ = 125 °C
LOWDR rise/fall time
trLOWDR ,
tfLOWDR
Cl = 9nF, VDRV = 6.5v,
TJ = 125 °C
OVERCURRENT PROTECTION(1)
Comparator Propagation
Delay Time
tOCPROP
1
1
µs
µs
Deglitch Time
tOCDGL
1
1
3
3
OVERVOLTAGE PROTECTION
Comparator Propagation
Delay Time
tOVPROP
tOVDGL
µs
µs
Deglitch Time
7
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
ELECTRICAL CHARACTERISTICS (cont.)
Unless specified: 0 < TJ < 125° C, VIN12V = 12V
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
HIGH-SIDE Vds SENSING(1)
Response Time
tVDSRESP
VHISENSE = 12v, VIOUTLO
2
µs
pulsed from 12v to 11.9v,
100ns rise and fall times
V
HISENSE = 4.5v, VIOUTLO
3
3
µs
µs
pulsed from 4.5v to 4.4v,
100ns rise and fall times
VHISENSE = 3v,
VIOUTLO
pulsed from 3.0v to 2.9v,
100ns rise and fall times
Short Circuit Protection
Rising Edge Delay
tVDSRED
tSWXDLY
LOSENSE grounded
300
30
500
100
ns
ns
Sample/Hold Switch turn-
on/turn-off Delay
3v < VHISENSE < 11v
VLOSENSE = VHISENSE
POWER GOOD
Comparator Propagation
Delay
tPWRGD
1
µs
ns
ns
SOFTSTART
Comparator Propagation
Delay
tSLST
overdrive = 10mv
560
900
100
DEADTIME
Driver Nonoverlap Time
tNUL
30
Note 1: Guaranteed, but not tested
8
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
BLOCK DIAGRAM
9
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
OUTPUT VOLTAGE TABLE
0 = GND; 1 = Floating or +5V pull-up
VID4
VID3
VID2
VID1
VID0
VDC
(V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
NO CPU
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
NOTE:
(1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, and the con-
troller will be set to a low-Iq state.
10
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
FUNCTIONAL DESCRIPTION
Reference/Voltage Identification
nal bootstrap diode, connected between the DRV and
BOOT pins, is a Schottky for improved drive efficiency.
The maximum voltage that can be applied between the
BOOT pin and ground is 25V. The driver can be refer-
enced to ground by connecting BOOTLO to PGND,
and connecting +12V to the BOOT pin.
The reference/voltage identification (VID) section con-
sists of a temperature compensated bandgap refer-
ence and a 5-bit voltage selection network. The 5 VID
pins are TTL compatable inputs to the VID selection
network. They are internally pulled up to +5V gener-
ated from the +12V supply by a resistor divider, and
provide programmability of output voltage from 2.0V to
3.5V in 100mV increments and 1.3V to 2.05V in 50mV
increments.
Refer to the Output Voltage Table for the VID code
settings. The output voltage of the VID network, VREF
is within 1% of the nominal setting over the full input
and output voltage range and junction temperature
range. The output of the reference/VID network is indi-
rectly brought out through a buffer to the REFB pin.
The voltage on this pin will be within 3mV of VREF. It
is not recommended to drive loads with REFB other
than setting the hysteresis of the hysteretic compara-
tor, because the current drawn from REFB sets the
charging current for the soft start capacitor. Refer to
the soft start section for additional information.
Deadtime Control
Deadtime control prevents shoot-through current from
flowing through the main power FETs during switching
transitions by actively controlling the turn-on times of
the FET drivers. The high side driver is not allowed to
turn on until the gate drive voltage to the low-side FET
is below 2 volts, and the low side driver is not allowed
to turn on until the voltage at the junction of the 2 FETs
(VPHASE) is below 2 volts. An internal low-pass filter
with an 11MHz pole is located between the output of
the low-side driver (DL) and the input of the deadtime
circuit that controls the high-side driver, to filter out
noise that could appear on DL when the high-side
driver turns on.
Current Sensing
Current sensing is achieved by sampling and holding
the voltage across the high side FET while it is turned
on. The sampling network consists of an internal 50Ω
switch and an external 0.1µF hold capacitor. Internal
logic controls the turn-on and turn-off of the sample/
hold switch such that the switch does not turn on until
VPHASE transitions high and turns off when the input
to the high side driver goes low. Thus sampling will
occur only when the high side FET is conducting cur-
rent. The voltage at the IO pin equals 2 times the
sensed voltage. In applications where a higher accu-
racy in current sensing is required, a sense resistor
can be placed in series with the high side FET and the
voltage across the sense resistor can be sampled by
the current sensing circuit.
Hysteretic Comparator
The hysteretic comparator regulates the output voltage
of the synchronous-buck converter. The hysteresis is
set by connecting the center point of a resistor divider
from REFB to AGND to the HYST pin. The hysteresis
of the comparator will be equal to twice the voltage dif-
ference between REFB and HYST, and has a maxi-
mum value of 60mV. The maximum propagation delay
from the comparator inputs to the driver outputs is
250ns.
Low Side Driver
The low side driver is designed to drive a low RDS(ON) N-
channel MOSFET, and is rated for 2 amps source and
sink. The bias for the low side driver is provided inter-
nally from VDRV.
Droop Compensation
The droop compensation network reduces the load
transient overshoot/undershoot at VOUT, relative to
VREF. VOUT is programmed to a voltage greater than
VREF (equal to VREF x (1+R5/R6)) by an external re-
sistor divider from VOUT to the VSENSE pin to reduce
the undershoot on VOUT during a low to high load
current transient. The overshoot during a high to low
load current transient is reduced by subtracting the
voltage that is on the DROOP pin from VREF. The
voltage on the IO pin is divided down with an external
High Side Driver
The high side driver is designed to drive a low RDS(ON)
N-channel MOSFET, and is rated for 2 amps source
and sink. It can be configured either as a ground refer-
enced driver or as a floating bootstrap driver. When
configured as a floating driver, the bias voltage to the
driver is developed from the DRV regulator. The inter-
11
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
Thus these resistor values will determine the soft start
charging current. The maximum current that can be
sourced by REFB is 500µA.
FUNCTIONAL DESCRIPTION (cont.)
resistor divider, and connected to the DROOP pin.
Thus, under loaded conditions, VOUT is regulated to
Vout = Vref • (1+R7/R8) - IOUT • R2/(R1+R2).
Power Good
The power good circuit monitors for an undervoltage
condition on VOUT. If VSENSE is 7% (nominal) below
VREF, then the power good pin is pulled low. The
PWRGD pin is an open drain output.
Inhibit
The inhibit pin is a TTL compatible digital pin that is
used to enable the controller. When INH is low, the
output drivers are low, the soft start capacitor is dis-
charged, the soft start current source is disabled, and
the controller is in a low IQ state. When INH goes high,
the short across the soft start capacitor is removed, the
soft start current source is enabled, and normal con-
verter operation begins. When the system logic supply
is connected to INH, it controls power sequencing by
locking out controller operation until the system logic
supply exceeds the input threshold voltage of the INH
circuit; thus the +12V supply and the system logic sup-
ply (either +5V or 3.3V) must be above UVLO thresh-
olds before the controller is allowed to start up.
Overvoltage Protection
The overvoltage protection circuit monitors VOUT for
an overvoltage condition. If VSENSE is 15% above
VREF, than a fault latch is set and both output drivers
are turned off. The latch will remain set until VIN goes
below the undervoltage lockout value. A 1ms deglitch
timer is included for noise immunity.
Overcurrent Protection
The overcurrent protection circuit monitors the current
through the high side FET. The overcurrent threshold
is adjustable with an external resistor divider between
IO and AGND, with the divider voltage connected to
the OCP pin. If the voltage on the OCP pin exceeds
100mV, then a fault latch is set and the output drivers
are turned off. The latch will remain set until VIN goes
below the undervoltage lockout value. A 1ms deglitch
timer is included for noise immunity. The OCP circuit
is also designed to protect the high side FET against a
short-to-ground fault on the terminal common to both
power FETs (VPHASE).
VIN
The VIN undervoltage lockout circuit disables the con-
troller while the +12V supply is below the 10V start
threshold during power-up. While the controller is dis-
abled, the output drivers will be low, the soft start ca-
pacitor will be shorted and the soft start current is dis-
abled and the controller will be in a low IQ state. When
VIN exceeds the start threshold, the short across the
soft start capacitor is removed, the soft start current
source is enabled and normal converter operation be-
gins. There is a 2V hysteresis in the undervoltage
lockout circuit for noise immunity.
Drive Regulator
The drive regulator provides drive voltage to the low
side driver, and to the high side driver when the high
side driver is configured as a floating driver. The mini-
mum drive voltage is 7V. The minimum short circuit
current is 100mA.
Soft Start
The soft start circuit controls the rate at which VOUT
powers up. A capacitor is connected between SS and
AGND and is charged by an internal current source.
The value of the current source is proportional to the
reference voltage so the charging rate of CSS is also
proportional to the reference voltage. By making the
charging current proportional to VREF, the power-up
time for VOUT will be independent of VREF. Thus, CSS
can remain the same value for all VID settings. The
soft start charging current is determined by the follow-
ing equation: ISS = IREFB/5. Where IREFB is the current
flowing out of the REFB pin. It is recommended that
no additional loads be connected to REFB, other than
the resistor divider for setting the hysteresis voltage.
12
652 MITCHELL ROAD NEWBURY PARK CA 91320
© 2000 SEMTECH CORP.
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
APPLICATION CIRCUIT
13
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
MATERIALS LIST
Quantity
Reference
Part/Description
Vendor
Notes
1
6
3
7
2
6
2
1
1
1
1
1
2
C5
0.001µF
0.01µF
C1-C4, C8, C11
C17-C19
150µF, 16V (TPS)
AVX
AVX
C6,C7,C9,C12,C16,C20, C27
0.1µF
C13,C14
C21-C26
C10,C15
D1
0.33µF
470µF, 6.3V (TPS)
2.2µF, 16V
MBRD1035
MOT
L1
1µH, DO5022P-102
Coilcraft
Coilcraft
L2
1.5µH, DO5022P-152HC
Q1
IRL3103NS, D2PAK
Int. Rect.
Int. Rect.
Q2
IRL2203NS, D2PAK
RA,RB
0Ω
1
2
1
1
1
1
3
1
1
1
R1
2K
R2,R4
R3
1K
2.7K
R5
100
R6
20K
R7
150
R8,R9,R10
R11
R12
U1
10K
2.2
3.9
SC1154, SO-28
SEMTECH
Layout guidelines
1. Locate R8 and C5 close to pins 6 and 7.
2. Locate C6 close to pins 5 and 7.
3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be refer-
enced to AGND.
4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND.
5. Locate bootstrap capacitor C13 close to the IC.
6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective.
7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise.
8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin.
9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple cur-
rent flow in this pass.
10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower
Vout settings, it needs to be placed next to the aforementioned FET in very close proximity.
11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be
achieved by connecting the AGND to the ground side of the bulk output capacitors.
12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple
vias.
13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the
chip with the cathode connected to BOOTLO and anode connected to DRVGND.
14
652 MITCHELL ROAD NEWBURY PARK CA 91320
© 2000 SEMTECH CORP.
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
EVALUATION BOARD ARTWORK
TOP LAYER
BOTTOM LAYER
15
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
EVALUATION BOARD LAYOUT
TOP VIEW
BOTTOM VIEW
16
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
TEST DATA
SC1154 Efficiency
100.0
95.0
90.0
85.0
Vin =
3.5
2.8
2.0
1.5
%
80.0
75.0
70.0
65.0
60.0
0
5
10
15
20
Output Current, A
SC1154 Voltage Regulation
5.00
4.00
3.00
2.00
1.00
3.5
2.8
2
% 0.00
-1.00
-2.00
-3.00
-4.00
-5.00
0
2
4
6
8
10
12
14
1.5
Output Current, A
17
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS
SC1154
PRELIMINARY - March 1, 2000
OUTLINE - SO-28
ECN00-904
18
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
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