SC1185ACSW.TRT [SEMTECH]
Programmable Synchronous DC/DC; 可编程同步DC / DC
| 型号： | SC1185ACSW.TRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Programmable Synchronous DC/DC |
| 文件： | 总14页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1185 & SC1185A
Programmable Synchronous DC/DC
Converter, Dual LDO Controller
POWER MANAGEMENT
Features
Description
The SC1185 combines a synchronous voltage mode con-
troller with two low-dropout linear regulators providing
most of the circuitry necessary to implement three DC/
DC converters for powering advanced microprocessors
such as Pentium® II .
ꢀSynchronous design, enables no heatsink solution
ꢀ95% efficiency (switching section)
ꢀ5 bit DAC for output programmability
ꢀOn chip power good function
ꢀDesigned for Intel Pentium® ll requirements
ꢀ1.5V, 2.5V @ 1.25% for linear section
ꢀ1.265V ± 1.5% Reference available
ꢀ 24-lead SO package. Lead free option available.
Lead free product is fully WEEE and RoHS
compliant.
The SC1185 switching section features an integrated 5
bit D/A converter, pulse by pulse current limiting, inte-
grated power good signaling, and logic compatible shut-
down. The SC1185 switching section operates at a fixed
frequency of 140kHz, providing an optimum compromise
between size, efficiency and cost in the intended appli-
cation areas. The integrated D/A converter provides pro-
grammability of output voltage from 2.0V to 3.5V in
100mV increments and 1.30V to 2.05V in 50mV incre-
ments with no external components.
Applications
ꢀ
ꢀ
ꢀ
ꢀ
Pentium® ll microprocessor supplies
Flexible motherboards
1.3V to 3.5V microprocessor supplies
Programmable triple power supplies
The SC1185 linear sections are low dropout regulators
supplying 1.5V for GTL bus and 2.5V for non-GTL I/O.
The Reference voltage is made available for external lin-
ear regulators.
Typical Application Circuit
12V
5V
+
4.7uF
10
+
0.1uF
1500uF
x4
0.1uF
5
7
9
VCC
CS+
CS-
0.1uF
PWRGOOD
8
PWRGOOD
VID0
22
21
20
19
18
16
1
17
15
11
14
13
10
12
6
IRLR3103N
1.00k
2.32k
VID0
VID1
VID2
VID3
VID4
EN
VOSENSE
VID1
BSTH
DH
5mOhm
2R2
VCC_CORE
VID2
1.9uH
IRLR3103N
VID3
BSTL
DL
VID4
+
2R2
0.1uF
EN
PGNDH
PGNDL
REF
AGND
LDOV
GATE2
LDOS2
SC1185CS
1k
23
24
4
1500uF
x6
12V
3.3V
2
GATE1
LDOS1
3
8
3.3V
3
2
+
1
IRLR024N
VLIN3
-
LM358
+
4
1.5V
2.5V
330uF
IRLR024N
+
IRLR024N
330uF
+
+
330uF
330uF
1
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Revision: July 28, 2005
SC1185 & SC1185A
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum
Units
VCC to GND
VIN
-0.3 to +7
+1
V
V
PGND to GND
BST to GND
-0.3 to +15
0 to +70
0 to +125
-65 to +150
300
V
Operating Temperature Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering) 10 Sec.
Thermal Impedance Junction to Ambient
Thermal Impedance Junction to Case
TA
TJ
°C
°C
TSTG
TL
°C
°C
80
°C/W
°C/W
θJA
θJC
25
Electrical Characteristics
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
Switching Section
Output Voltage
IO = 2A in Application Circuit
VCC
See Output Voltage Table
Supply Voltage
4.5
7
V
Supply Current
VCC = 5.0V
8
1
15
mA
%
Load Regulation
IO = 0.8A to 15A
Line Regulation
+0.15
70
%
Current Limit Voltage
Oscillator Frequency
Oscillator Max Duty Cycle
Peak DH Sink/Source Current
60
125
90
85
mV
kHz
%
140
95
160
BSTH - DH = 4.5V, DH - PGNDH = 3.1V
DH - PGNDH = 1.5v
1
A
100
mA
Peak DL Sink/Source Current
BSTL - DL = 4.5V, DL - PGNDL = 3.1V
DL - PGNDL = 1.5V
1
A
100
mA
Gain (AOL)
VOSENSE to VO
VIDx < 2.4V
VIDx < 2.4V
35
10
dB
µA
µA
%
VID Source Current
VID Leakage
1
10
Power good threshold voltage
Dead time
88
40
100
100
112
ns
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SC1185 & SC1185A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
Linear Sections
Quiescent current
Output Voltage LDO1
Output Voltage LDO2
Reference Voltage
Gain (AOL)
LDOV = 12V
Iref < 100µA
5
mA
V
2.469
1.481
1.246
2.500
1.500
1.265
90
2.531
1.519
1.284
V
V
LDOS (1, 2) to GATE (1, 2)
IO = 0 to 8A
dB
%
%
Ω
Load Regulation
0.3
0.3
1.5
750
Line Regulation
Output Impedance
Gate Pulldown Impedance
VOSENSE Impedance
NOTE:
VGATE = 6.5V
1
GATE (1,2)-AGND; VCC=LDOV=OV
80
10
300
kΩ
kΩ
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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2005 Semtech Corp.
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SC1185 & SC1185A
POWER MANAGEMENT
Pin Configuration
Ordering Information
TOP VIEW
Part Number
Package (1)
Linear
Temp
Voltage
Range (TJ)
AGND
GATE1
LDOS1
LDOS2
VCC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
GATE2
LDOV
VID0
VID1
VID2
SC1185CSW.TR
SC1185CSW.TRT(3)
SC1185ACSW.TR
SC1185ACSW.TRT(3)
SO-24
SO-24
1.5V2.5V 0° to 125°C
1.5V2.5V 0° to 125°C
REF
PWRGOOD
CS-
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
Notes:
CS+
PGNDH
DH
9
10
11
12
(1) Only available in tape and reel packaging. A reel contains
1000 devices.
PGNDL
(2) SC1185A provides improved output tolerance. See Output
Voltage Table.
(24 Pin SOIC)
(3). Lead free product. This product is fully WEEE and RoHS
compliant.
Pin Descriptions
Pin #
Pin Name
Pin Function
1
2
3
4
5
AGND
GATE1
LDOS1
LSOS2
VCC
Small Signal Analog and Digital Ground
Gate Drive Output LDO1
Sense Input for LDO1
Sense Input for LDO2
Input Voltage
6
7
8
9
REF
Buffered Reference Voltge output
Open collector logic output, high if VO within 10% of setpoint
Current Sense Input (negative)
Current Sense Input (positive)
Power Ground for High Side Switch
High Side Driver Output
PWRGOOD(1)
CS-
CS+
PGNDH
DH
PGNDL
DL
BSTL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Power Ground for Low Side Swtch
Low side Driver Output
Supply for Low Side Driver
Supply for High Side Driver
Logic low shuts down the converter. High or open for normal operation.
Top end of internal feedback chain
Programming Input (MSB)
Programming Input
Programming Input
Programming Input
Programming Input (LSB)
BSTH
EN (1)
VOSENSE
VID4 (1)
VID3 (1)
VID2 (1)
VID1 (1)
VID0 (1)
LDOV
GATE2
+12V for LDO section
Gate Drive Output LDO2
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
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2005 Semtech Corp.
4
SC1185 & SC1185A
POWER MANAGEMENT
Block Diagram
CS- CS+
VCC
EN
CURRENT LIMIT
BSTH
REF
-
70mV
+
LEVEL SHIFT
AND HIGH SIDE
VID4
VID3
VID2
VID1
VID0
DH
MOSFET DRIVE
D/A
R
S
Q
OSCILLATOR
PGNDH
SHOOT-THRU
CONTROL
VOSENSE
-
OPEN
+
-
COLLECTORS
BSTL
+
+
PWRGOOD
-
ERROR
AMP
SYNCHRONOUS
MOSFET DRIVE
DL
+
-
AGND
PGNDL
LDOS1
2.5V FET
CONTROLLER
1.5V FET
1.265V
REF
CONTROLLER
GATE1
AGND
LDOV
REF
GATE2 LDOS2 AGND
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5
SC1185 & SC1185A
POWER MANAGEMENT
Output Voltage Table
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0°C < Tj < 85°C
Parameter
Standard
Typ
"A" Version
Typ
Vid
Min
Max
Min
Max
Units
43210
Output Voltage
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
1.277
1.326
1.375
1.424
1.478
1.527
1.576
1.625
1.675
1.724
1.782
1.832
1.881
1.931
1.980
2.030
1.970
2.069
2.167
2.266
2.364
2.463
2.561
2.660
2.758
2.842
2.940
3.038
3.136
3.234
3.332
3.430
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
1.323
1.374
1.425
1.476
1.523
1.573
1.624
1.675
1.726
1.818
1.869
1.919
1.970
2.020
2.020
2.071
2.030
2.132
2.233
2.335
2.436
2.538
2.639
2.741
2.842
58
1.287
1.337
1.386
1.436
1.485
1.535
1.584
1.634
1.683
1.733
1.782
1.832
1.881
1.931
1.980
2.030
1.970
2.069
2.167
2.266
2.364
2.463
2.561
2.660
2.758
2.842
2.940
3.038
3.136
3.234
3.332
3.430
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
1.313
1.364
1.414
1.465
1.515
1.566
1.616
1.667
1.717
1.768
1.818
1.869
1.919
1.970
2.020
2.071
2.030
2.132
2.233
2.335
2.436
2.538
2.639
2.741
2.842
2.958
3.060
3.162
3.264
3.366
3.468
3.570
V
3.060
3.162
3.264
3.366
3.468
3.570
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SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
Careful attention to layout requirements are necessary for transition switching. Connections should be as wide and
successful implementation of the SC1185 PWM control- as short as possible to minimize loop inductance. Mini-
ler. High currents switching at 140kHz are present in the mizing this loop area will a) reduce EMI, b) lower ground
application and their effect on ground plane voltage differ- injection currents, resulting in electrically “cleaner” grounds
entials must be understood and minimized.
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and 3). The connection between the junction of Q1, Q2 and
position of ground plane interruptions should be such as the output inductor should be a wide trace or copper re-
to not unnecessarily compromise ground plane integrity. gion. It should be as short as practical. Since this connec-
Isolated or semi-isolated areas of the ground plane may tion has fast voltage transitions, keeping this connection
be deliberately introduced to constrain ground currents to short will minimize EMI. The connection between the out-
particular areas, for example the input capacitor and bot- put inductor and the sense resistor should be a wide trace
tom FET ground.
or copper area, there are no fast voltage or current transi-
tions in this connection and length is not so important,
2). The loop formed by the Input Capacitor(s) (Cin), the Top however adding unnecessary impedance will reduce effi-
FET (Q1) and the Bottom FET (Q2) must be kept as small ciency.
as possible. This loop contains all the high current, fast
12V IN
5V
10
1
2
24
AGND
GATE1
LDOS1
LDOS2
VCC
GATE2
LDOV
VID0
23
22
21
20
19
18
17
16
15
14
13
2.32k
3
Cin
+
4
Q1
Q2
1.00k
VID1
0.1uF
0.1uF
5
5mOhm
VID2
Vout
6
REF
VID3
L
+
7
PWRGOOD
CS-
VID4
Cout
8
VOSENSE
EN
9
CS+
10
11
12
PGNDH
DH
BSTH
BSTL
DL
PGNDL
SC1185
Heavy lines indicate
high current paths.
3.3V
Vo Lin1
Q3
+
+
Cout Lin1
Cin Lin
Layout Diagram
SC1185(A)
Vo Lin2
Q4
+
Cout Lin2
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SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
4) The Output Capacitor(s) (Cout) should be located as supply through a 10Ω resistor, the Vcc pin should be
close to the load as possible, fast transient load cur- decoupled directly to AGND by a 0.1µF ceramic capacitor,
rents are supplied by Cout only, and connections between trace lengths should be as short as possible.
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
7) The Current Sense resistor and the divider across it
should form as small a loop as possible, the traces run-
5) The SC1185 is best placed over a quiet ground plane ning back to CS+ and CS- on the SC1185 should run
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing parallel and close to each other. The 0.1µF capacitor should
in this area. PGNDH and PGNDL should be returned to be mounted as close to the CS+ and CS- pins as possible.
the ground plane close to the package. The AGND pin
should be connected to the ground side of (one of) the 8) Ideally, the grounds for the two LDO sections should be
output capacitor(s). If this is not possible, the AGND pin returned to the ground side of (one of) the output
may be connected to the ground path between the Output capacitor(s).
Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum-
stances should AGND be returned to a ground inside the
Cin, Q1, Q2 loop.
6) Vcc for the SC1185 should be supplied from the 5V
5V
+
Vout
+
Currents in various parts of the power section
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SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
COMPONENT SELECTION
SWITCHING SECTION
The calculated maximum inductor value assumes 100%
and 0% duty cycle, so some allowance must be made.
OUTPUT CAPACITORS - Selection begins with the most Choosing an inductor value of 50 to 75% of the calculated
critical component. Because of fast transient load current maximum will guarantee that the inductor current will ramp
requirements in modern microprocessor core supplies, the fast enough to reduce the voltage dropped across the ESR
output capacitors must supply all transient load current at a faster rate than the capacitor sags, hence ensuring a
requirements until the current in the output inductor ramps good recovery from transient with no additional excursions.
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be We must also be concerned with ripple current in the out-
simply calculated from:
put inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
Vt
It
RESR
≤
Where
Vt = Maximum transient voltage excursion
It = Transient current step
V
IN
IL
=
RIPPLE
4 L fOSC
Ripple current allowance will define the minimum permit-
ted inductor value.
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three
available capacitor technologies.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power dis-
sipation and power handling capability.
Each Cap.
ESR
Total
ESR
Qty.
Technology
TOP FET - The power dissipation in the top FET is a combi-
nation of conduction losses, switching losses and bottom
FET body diode recovery losses.
C
C
Rqd.
(µF) (mΩ)
(µF) (mΩ)
Low ESR Tantalum
OS-CON
330
330
60
25
44
6
3
5
2000
990
10
8.3
8.3
a) Conduction losses are simply calculated as:
PCOND = IO2 RDS(on)
δ
Low ESR Aluminum
1500
7500
where
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
VO
δ = duty cycle ≈
V
IN
b) Switching losses can be estimated by assuming a switch-
ing time, if we assume 100ns then:
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
−2
PSW = IO
V
10
IN
or more generally,
IO
=
V
(tr + tf ) fOSC
4
IN
PSW
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to as-
sume that the stored charge on the bottom FET body di-
ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
The maximum inductor value may be calculated from:
RESR
It
C
L ≤
VA
PRR = QRR
V
fOSC
IN
where VA is thelesser of VO or V − VO
( )
IN
To a first order approximation, it is convenient to only con-
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9
SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
sider conduction losses to determine FET suitability. position, power dissipation will be approximately halved
For a 5V in; 2.8V out at 14.2A requirement, typical FET and temperature rise reduced by a factor of 4.
losses would be: Using 1.5X Room temp RDS(ON) to allow for
temperature rise.
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra out-
put capacitance or, more usually, additional input capaci-
tors. Choosing low ESR input capacitors will help maximize
ripple rating for a given size.
FET type
IRL34025
IRL2203
Si4410
RDS(on) (mΩ)
PD (W)
1.69
Package
D2Pak
D2Pak
S0-8
15
10.5
20
1.19
2.26
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:
PCOND = IO2 RDS(on) (1− δ)
For the example above:
FET type
IRL34025
IRL2203
Si4410
RDS(on) (mΩ)
PD (W)
1.33
Package
D2Pak
D2Pak
S0-8
15
10.5
20
0.93
1.77
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the sur-
face mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W for
the D2PAK and 80oC/W for the SO-8 are readily achiev-
able. The corresponding temperature rise is detailed be-
low:
Temperature rise (oC)
FET type
IRL34025
IRL2203
Si4410
Top FET
67.6
Bottom FET
53.2
47.6
37.2
180.8
141.6
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
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SC1185 & SC1185A
POWER MANAGEMENT
Typical Characteristics
Typical Efficiency at Vo=3.5V
Typical Efficiency at Vo=2.8V
95%
90%
85%
80%
75%
70%
95%
90%
85%
80%
75%
70%
3.5V Std
3.5V Sync
3.5V Sync Lo Rds
2.8V Std
2.8V Sync
2.8V Sync Lo Rds
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Io (Amps)
Io (Amps)
Typical Efficiency at Vo=2.5V
Typical Efficiency at Vo=2.0V
95%
90%
85%
80%
75%
70%
95%
90%
85%
80%
75%
70%
2.0V Std
2.0V Sync
2.0V Sync Lo Rds
2.5V Std
2.5V Sync
2.5V Sync Lo Rds
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Io (Amps)
Io (Amps)
Typical Ripple, Vo=2.8V, Io=10A
Transient Response Vo=2.8V, Io=300mA to 10A
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2005 Semtech Corp.
11
SC1185 & SC1185A
POWER MANAGEMENT
Typical Application Circuit
www.semtech.com
2005 Semtech Corp.
12
SC1185 & SC1185A
POWER MANAGEMENT
Materials List
Item
1
Qty.
5
Reference
Value
Notes
C1, C4, C5, C10, C13
0.1uF Ceramic
C2, C3, C6, C7, C8, C9, C18, C19, C20,
C21, C22, C23
2
12
1500uF
Sanyo MV-GX or equiv. Low ESR
3
4
8
1
C11, C12, C14, C15, C16, C17, C24, C25 330uF
C26
L1
4.7uF
1.9uH
6 Turns 16AWG on MICROMETALS
T50-52D core
5
1
6
4
3
1
1
1
1
4
1
2
1
1
2
1
1
Q1, Q2, Q3, Q4
IRLR3103N
IRLR024N
10
7
Q5, Q6, Q7
8
R1
9
R3
EMPTY
1.00k
10
11
12
13
14
15
16
17
18
19
R4
R5
2.32k
R6, R7, R9, R10
2R2
R8
5mOhm
See Table
1k
IRC OAR-1 Series
R15, R11
R12
R16
0
R17, R18
U2
See Table
LM358
SC1185CS
U3
SEMTECH
www.semtech.com
2005 Semtech Corp.
13
SC1185 & SC1185A
POWER MANAGEMENT
Outline Drawing - SO - 24
DIMENSIONS
A
D
E
INCHES
MILLIMETERS
e
DIM
A
N
MIN NOM MAX MIN NOM MAX
-
-
-
-
-
-
-
-
-
-
.093
.104 2.35
.012 0.10
.100 2.05
.020 0.31
.013 0.20
2.65
0.30
2.55
0.51
0.33
A1 .004
A2 .081
2X E/2
b
.012
.008
c
D
.602 .606 .610 15.30 15.40 15.50
E1 .291 .295 .299 7.40 7.50 7.60
E1
E
e
.406 BSC
10.30 BSC
1.27 BSC
R
.050 BSC
-
-
h
J
.010
.020
.016
.030 0.25
.030 0.50
.041 0.40
0.75
0.75
1.04
-
-
-
-
L
(.041)
(1.04)
L1
N
24
24
1
2
3
ccc
C
-
-
R
.024
0°
.035 0.60
0.90
8°
-
-
2X N/2 TIPS
01
8°
0°
e/2
aaa
.004
.010
.013
0.10
0.25
0.33
B
bbb
ccc
D
h
aaa
SEATING
C
A2
A
h
H
PLANE
bxN
bbb
A1
C
C
A-B D
c
GAGE
J
PLANE
0.25
L
(L1)
01
SEE DETAIL A
DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-013, VARIATION AD.
Land Pattern - SO - 24
X
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.362)
.276
.050
.024
.087
.449
(9.20)
7.00
C
G
P
X
Y
Z
(C)
G
Y
Z
1.27
0.60
2.20
11.40
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 307A.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012-8790
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2005 Semtech Corp.
14
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