SC1211STR [SEMTECH]

High Speed, Combi-SenseTM Synchronous MOSFET Driver; 高速，组合式SenseTM同步MOSFET驱动器


型号：	SC1211STR
厂家：	SEMTECH CORPORATION
描述：	High Speed, Combi-SenseTM Synchronous MOSFET Driver 高速，组合式SenseTM同步MOSFET驱动器驱动器
文件：	总11页 (文件大小：271K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC1211

High Speed, Combi-Sense^TM

Synchronous MOSFET Driver

POWER MANAGEMENT

Features

Description

The SC1211 is a high speed, Combi-Sense^TM, dual out- u High efficiency

put driver designed to drive high-side and low-side

MOSFETs in a synchronous Buck converter. These

drivers combined with Combi-Sense PWM controllers,

such as Semtech SC2643VX or SC2643, provide a

cost effective multi-phase voltage regulator for advanced

microprocessors

u +12V supply voltage with internal LDO for optimum

gate drive

u High peak drive current

u Adaptive non-overlapping gate drives provide

shoot-through protection

u Support Combi-Sense^TMand VID-on-fly operations

u Fast rise and fall times (15ns typical with 3000pf

load)

u Ultra-low (<30ns) propagation delay (BG going low)

u Floating top gate drive

u Crowbar function for over voltage protection

u High frequency (to 1.5 MHz) operation allows use

of small inductors and low cost ceramic capacitors

u Under-voltage-lockout

The Combi-Sense^TMis a technique to sense the inductor

current for peak current mode control of voltage regula-

tor without using sensing resistor. It provides the follow-

ing advantages:

- No costly precision sensing resistor

- Lossless current sensing

- High level noise free signal

- Fast response

- Suitable for wide range of duty cycle

- Only two small signal components (third optional)

The detailed explanation of the technique can be found

in the Applications Information section.

u Low quiescent current

Applications

A 30ns max propagation delay from input transition to

the gate of the power FET’s guarantees operation at high

u Intel Pentium^TMprocessor power supplies

switching frequencies. Internal overlap protection circuit u AMD Athlon^TMand K8^TMprocessor power supplies

prevents shoot-through from Vin to PGND in the main

and synchronous MOSFETs. The adaptive overlap pro-

tection circuit ensures the bottom FET does not turn on

until the top FET source has reached 1V, to prevent cross-

conduction.

u High current low voltage DC-DC converters

8.5V gate drive provides optimum enhancement of

MOSFETs at minimum driver and MOSFET switching loss.

High current drive capability allows fast switching, thus

reducing switching losses at high (up to 1.5MHz) frequen-

cies without causing thermal stress on the driver.

Under-voltage-lockout and over-temperature shutdown

features are included for proper and safe operation.

Timed latches and improved robustness are built into

the housekeeping functions such as the Under Voltage

Lockout and adaptive Shoot-through protection circuitry

to prevent false triggering and to assure safe operation.

The SC1211 is offered in a Power SOIC-8L package.

February 24, 2003

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SC1211

POWER MANAGEMENT

Typical Application Circuit

DRN

VREG

VIN

DRN

VREG

VIN

DRN

VREG

VIN

BST

VPN

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SC1211

POWER MANAGEMENT

Absolute Maximum Ratings

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified

in the Electrical Characteristics section is not implied.

Parameter

Symbol

Conditions

Maximum

Units

V_{I N}Supply Voltage

V_{I N}

V_BST-DRN

V_BST-PGND

V_BST-PULSE

V_DRN-PGND

V_DRN-PULSE

V_PN

BST to DRN

BST to PGND

BST to PGND Pulse

t_PULSE< 100ns

t_PULSE< 200ns

DRN to PGND

-2 to 30

-5 to 35

DRN to PGND Pulse

VPN to PGND

VPN to PGND Pulse

V_PN-PULSE

t_PULSE< 100ns

PWM Input

-0.3 to 8.5

2.56

Continuous Power Dissipation

Thermal Resistance Junction to Case

Operating Junction Temperature Range

Storage Temperature Range

Lead Temperature (Soldering) 10 Sec.

P_D

T_A= 25°C, T_J=125°C

°C/W

°C

q_JC

T_J

0 to +125

-65 to +150

300

T_STG

T_LEAD

Electrical Characteristics

Unless specified: T_A= 25°C; V_IN= 12V; V_REG= 8.5V

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Power Supply

Supply Voltage

V_{I N}

Quiescent Current, Operating

Under Voltage Lockout

Iq_op

3.0

Start Threshold of V_REGVoltage

Hysteresis

V_{REG_START}

Vhys_UVLO

4.3

160

Internal LDO

LDO Output

V_REG

V_{I N}= 9V to 16V

8.5

0.3

Drop Out Voltage

V_DROP

V_{I N}= 5V to 8.8V

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SC1211

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Unless specified: T_A= 25°C; V_IN= 12V; V_REG= 8.5V

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Logic High Input Voltage

Logic Low Input Voltage

Thermal Shutdown

Over Temperature Trip Point

Hysteresis

V_{CO_H}

V_{CO_L}

2.0

0.8

T_OTP

155

°C

T_HYST

High Side Driver (TG)

R_{SRC_TG}

1.5

3.0

2.0

Output Impedance

V_BST- V_DRN= 8.5V

R_{SINK_TG}

t_{R_TG}

1.0

Rise Time

CL = 3nF, V_BST- V_DRN= 8.5V

V_BST- V_DRN= 8.5V

Fall Time

t_{F_TG}

Propagation Delay, TG Going High

Propagation Delay, TG Going Low

Low-Side Driver (BG)

t_{PDH_TG}

t_{PDL_TG}

V_BST- V_DRN= 8.5V

R_{SRC_BG}

R_{SINK_BG}

t_{R_BG}

1.5

3.0

Output Impedance

V_BST- V_DRN= 8.5V

Rise Time

CL = 3nF, V_BST- V_DRN= 8.5V

V_BST- V_DRN= 8.5V

Fall Time

t_{F_BG}

Propagation Delay, BG Going High

Propagation Delay, BG Going Low

t_{PDH_BG}

t_{PDL_BG}

V_BST- V_DRN= 8.5V

Under-Voltage-Lockout Time Delay

V_REGramping up

t_{PDH_UVLO}

t_{PDL_UVLO}

µs

V_REGramping down

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SC1211

POWER MANAGEMENT

Timing Diagrams

DRN

1.0V

tPDL_TG tF_TG

tPDH_TG

tR_TG

1.4V

tPDL_BG

tF_BG

tPDH_BG

tR_BG

Rising Edge Transition

Falling Edge Transition

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SC1211

POWER MANAGEMENT

Pin Configuration

Ordering Information

Device ⁽¹⁾

Package

Temp Range (T_J)

Top View

SC1211STR

EDP SO-8

0° to 125°C

DRN

Note:

(1) Only available in tape and reel packaging. A reel

contains 2500 devices.

VREG

VIN

BST

VPN

EXPOSED PAD MUST BE SOLDERED

TO POWER GROUND PLANE

(Power SOIC-8)

Pin Descriptions

Pin # Pin Name

Pin Function

The power phase node (or switching node) of the synchronous buck converter. This pin can be

subjected to a negative spike up to -V_REGrelative to PGND without affecting operation.

DRN

Output gate drive for the switching (top) MOSFET.

Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating

bootstrap voltage for the high-side MOSFET. The capacitor value is typically 1µF (ceramic).

BST

Logic level PWM input signal to the SC1211 supplied by external controller. An internal 50kohm

resistor is connected from this pin to PGND.

Virtual Phase Node. Connect an RC between this pin and the output sense point to Enable

Combi-Sense ^TMoperation. See the Typical Application Circuit.

VPN

Supply power for LDO and the internal Combi-Sense ^TMcircuitry. Connect to input power rail of the

converter.

VIN

VREG

LDO output. Decouple with 1µF to 4.7µF (ceramic) with lead length no more than 0.2" (5mm).

Output gate drive for the synchronous (bottom) MOSFET.

PAD

PGND

Ground. Keep this pin close to the synchronous MOSFETs source.

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SC1211

POWER MANAGEMENT

Block Diagram

VIN

LDO

VREG

VPN

UVLO

LOGIC

BST

CONTROL

OVERLAP

PROTECTION

CIRCUIT

DRN

PGND

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SC1211

POWER MANAGEMENT

Applications Information

THEORY OF OPERATION

simultaneously or shoot-through.

The SC1211 is a high speed, Combi-Sense^TM, dual out-

put driver designed to drive top and bottom MOSFETs in

VID-on-Fly Operation

a synchronous Buck converter. It features adaptive de- Certain new processors have required to changing the

VID dynamically during the operation, or refered as VID-

lay for shoot-through protection and VID-on-Fly opera-

tion; internal LDO for optimum gate drive voltage; and on-Fly operation. A VID-on-Fly can occur under light load

Virtual Phase Node for Combi-Sense^TMsolution. These

drivers combined with PWM controller SC2643VX form

or heavy load conditions. At light load, it could force the

converter to sink current. Upon turn-off of the top FET,

a multi-phase voltage regulator for advanced micropro- the reversed inductor current has to be freewheeling

through the body diode of the top FET instead of the

60A output is shown in the Typical Application Circuit sec- bottom FET. As a result, the phase node voltage remains

cessors. A three-phase voltage regulator with 12V input

high. The SC1211 incorporates the ability by pulling the

bottom gate to high internally, which over rides the adap-

tive circuit and turns the bottom FET on. The delay time

from the PWM falling egde to the bottom gate turn-on is

tion.

Startup and UVLO

To startup the driver, a supply voltage is applied to VIN set at 200ns typically.

pin of the SC1211. The top and bottom gates are held

Virtual Phase Node for Combi-Sense^TM

low until VIN exceeds UVLO threshold of the driver, typi-

cally 4.0V. Then the top gate remains low and the bot-

tom gate is pulled high to turn on the bottom FET. Once

Peak-Current-Mode control is widely employed in multi-

VIN exceeds UVLO threshold of the PWM controller, typi- phase voltage regulators. It features phase current bal-

ance, fast transient response, and over current protec-

tion, etc. These are essential to low-voltage high-cur-

rent regulators designed for advanced microprocessors.

Usually, a costly current sensing resistor is required to

obtain the output inductor current information for the

peak current control. The Combi-Sense^TMtechnique fea-

tured by the SC1211 is an approach to sense inductor

cally 7.5V, the soft-start begins and the PWM signal takes

fully control of the gate transitions.

Gate Transition and Shoot through Protection

Refer to the Timing Diagrams section, the rising edge of

the PWM input initiates the bottom FET turn-off and the

top FET turn-on. After a short propagation delay (tPDL_BG), current without using sensing resistor.

the bottom gate begins to fall (tF_BG). An adaptive circuit

in the SC1211 monitors the bottom gate voltage to drop

below 1.4V. Then after a preset delay time (tPDH_TG) is

expired, the top gate turns on. The delay time is set to

be 20ns typically. This prevents the top FET from turning

on until the bottom FET is off. During the transition, the

inductor current is freewheeling through the body diode

of either bottom FET or top FET, upon the direction of

the inductor current. The phase node could be low

(ground) or high (VIN).

VIN

Qcst

Vout

VPN

DRN

Qcsb

PGND

The falling edge of the PWM input controls the top FET

turn-off and the bottom FET turn-on. After a short propa-

gation delay (tPDL_TG), the top gate begins to fall (tF_TG).

As the inductor current is commutated from the top FET

to the body diode of the bottom FET, the phase node

Rcs

Ccs

SC1211

Inductor Current Signal

begins to fall. The adaptive circuit in the SC1211 de- The above circuit shows the concept of Combi-Sense^TM

technique. An internal totem pole (Qcst, Qcsb) gener-

ates a VPN (Virtual Phase Node) signal. This VPN follows

tects the phase node voltage. It holds the bottom FET

off until the phase node voltage has dropped below 1.0V.

This prevents the top and bottom FETs from conducting

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SC1211

POWER MANAGEMENT

Applications Information (Cont.)

Thermal Shut Down

the DRN (or the Power Phase Node) with the same tim-

ing. A RC network (Rcs and Ccs) is connected between

VPN and Vout. During Q1 turn-on, Qcst turns on as well.

The voltage drop across Q1 and Lo charges Ccs. During

Q2 turn-on, Qcsb turns on as well. The voltage drop across

Q2 and Lo discharges Ccs. Both voltage drops are pro-

portional to the inductor current and a resistance equal

to FET’s Rdson plus ESR of the inductor. If the time con-

stant Rcs x Ccs is close to the Lo/Ro of the inductor,

where Ro is given by

The SC1211 will shut down by pulling both driver out-

puts low if its junction temperature, Tj, exceeds 155°C.

COMPONENT SELECTION

Switching Frequency, Inductor and MOSFETs

The SC1211 is capable of providing up to 3.5A peak

drive current, and operating up to 1.5MHz PWM frequency

without causing thermal stress on the driver. The selec-

tion of switching frequency, together with inductor and

Ro = R_inductor+ R_{dson _hs}*D + R_{dson _ls}*(1- D)

the signal developed across Ccs will be proportional to FETs is a trade-off between the cost, size, and thermal

the inductor current, where Ro is the equivalent current

sensing resistance. In the above equation, Rinductor is

ESR of the inductor, Rdson_hs and Rdson_ls are the top

and bottom FET’s Rdson, and D is the duty cycle of the

converter.

management of a multi-phase voltage regulator. In mod-

ern microprocessor applications, these parameters could

be in the range of:

Switching Frequency 100kHz to 500kHz per phase

Inductor Value

FETs

0.2uH to 2uH

4m-ohm to 20m-ohm Rdson

20nC to 100nC total gate charge

Since a perfect timing match down to the nanosecond is

impossible, the VPN totem pole is held in tri-state during

the communtations of DRN in the SC1211. This avoids

errors and offset on the current detection which can be Bootstrap Circuit

significant since the timing mismatch is multiplied by the

input voltage. An optional capacitor between VPN and

DRN allows these two nodes to be AC coupled during

the tri-state window, hence yields a perfect timing match.

The SC1211 uses an external bootstrap circuit to pro-

vide a voltage for the top FET drive. This voltage, refer-

ring to the Phase Node, is held up by a bootstrap capaci-

Refer to Semtech SC2643VX Combi-Sense^TMCurrent tor. The capacitor value can be calculated based on the

Mode Controller about the details of the Combi-Sense

total gate charge of the top FET, QTOP, and an allowed

technique.

voltage ripple on the capacitor, DVBST, in one PWM cycle:

Optimized Gate Drive Voltage

CBST >QTOP/DVBST

With the supply voltage in between 9V to 16V, an inter-

nal LDO is designed with the SC1211 to bring the volt-

age to a lower level for gate drive. An external Ceramic

capacitor(1uF to 4.7uF) connected in between Vreg to

Typically, it is recommended to use a 1uF ceramic ca-

pacitor with 25V rating and a commonly available diode

IN4148 for the bootstrap circuit. In addition, a small re-

sistor (one ohm) has to be added in between DRN of the

ground is needed to support the LDO. The LDO output is SC1211 and the Phase Node. The resistor is used to

connected to low gate drive internally, and has to be

connected to high gate drive through an external boot-

strap circuit. The LDO output voltage is set at 8.5V. The

manufacture data and bench tested results show that,

allievate the stress of the SC1211 from exposing to the

negative spike at the Phase node. A negative spike could

occur at the Phase Node during the top FET turn-off due

to parasitic inductance in the switching loop. The spike

for low Rdson FETs run at applied load current, the opti- could be minimized with a careful PCB layout. In those

mum gate drive voltage is around 8.5V, where the total

power losses of power FETs, including conduction loss

and switching loss, are minimized.

applications with TO-220 package FETs, it is recom-

mended to use a clamping diode on the DRN pin to miti-

gate the impact of the excessive phase node negative

spike.

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SC1211

POWER MANAGEMENT

Applications Information (Cont.)

Filters for Supply Power

return and thermal release of the driver. The pad must

be soldered to the ground plane that is further connected

to the system ground in the inner layer through multiple

vias. For better electrical and thermal performance, it is

recommended to use all copper available under the driver

as the ground plane, and place the vias as close as pos-

sible to the solder pad. Meanwhile, the vias have to be

masked out to prevent solder leakage during reflow. The

layout arrangement is detailed in the above figure, which

also can be found in the “Land Pattern – Power SOIC-8”

section.

For VREG pin of the SC1211, it is recommended to use

a 1uF to 4.7uF, 25V rating ceramic capacitor for

decoupling.

LAYOUT GUIDELINES

The switching regulator is a high di/dt power circuit. Its

Printed Circuit Board (PCB) layout is critical. A good lay-

out can achieve an optimum circuit performance while

minimized the component stress, resulting in better sys-

tem reliability. For a multi-phase voltage regulator, the

SC1211 driver, FETs, inductor, and supply decoupling

capacitors in each phase have to be considered as a

whole during PCB layout. Refer to Semtech SC2643VX/

SC1211 EVB Layout Guideline.

For the SC1211 driver, the following guidelines are typi-

cally recommended during PCB layout:

1. Place the SC1211 close to the FETs for shortest gate

drive traces and ground return paths.

2. Connect bypass capacitors as close as possible to

decoupling pins (VREG and VIN) and PGND. The trace

length of the decoupling capacitor on VREG pin should

be no more than 0.2” (5mm).

3. Locate the components of the bootstrap circuit close

to the SC1211.

SOLDERING CONSIDERATION

The exposed die pad of the SC1211 is used for ground

Solder Pad

Solder Mask

Copper

Vias

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SC1211

POWER MANAGEMENT

Outline Drawing - Power SOIC-8

Outline Drawing - Power SOIC-8L

Land Pattern - Power SOIC-8

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Rd., Camarillo, CA 93012

Phone: (805)498-2111 FAX (805)498-3804

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SC1211STR [SEMTECH]

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