SC4603IMSTRT [SEMTECH]
Very Low Input, MHz Operation, High Efficiency Synchronous Buck; 极低的输入，兆赫操作，高效率同步降压
| 型号： | SC4603IMSTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Very Low Input, MHz Operation, High Efficiency Synchronous Buck |
| 文件： | 总16页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4603
Very Low Input, MHz Operation,
High Efficiency Synchronous Buck
POWER MANAGEMENT
Description
Features
The SC4603 is a voltage mode step down (buck) regula-
tor controller that provides accurate high efficiency power
conversion from input supply range 2.25V to 5.5V. A high
level of integration reduces external component count
and makes it suitable for low voltage applications where
cost, size and efficiency are critical.
BICMOS voltage mode PWM controller
2.25V to 5.5V Input voltage range
Output voltages as low as 0.5V
Sleep mode (Icc = 10µA typ)
Lossless adjustable overcurrent protection
Combination pulse by pulse & hiccup mode current
limit
High efficiency synchronous switching
0% to 100% Duty cycle range
Synchronization to external clock
Asynchronous start-up
1MHz frequency of operation
10-Pin MSOP surface mount package
The SC4603 drives external complementary power
MOSFETs; P-channel on the high side and N-channel on
the low side. The use of high side P-channel MOSFETs
eliminates the need for an external charge pump and
simplifies the high side gate driver. Non-overlap protec-
tion is provided for the gate drive signals to prevent shoot
through of the MOSFET pair. The voltage drop across the
P-channel MOSFET during its conduction is sensed for
lossless short circuit current limiting.
Applications
Distributed power architecture
Servers/workstations
A low power sleep mode can be achieved by forcing the
SYNC/SLEEP pin below 0.8V. A synchronous mode of op-
eration is activated as the SYNC/SLEEP pin is driven by
an external clock. The quiescent supply current in sleep
mode is typically lower than 10µA. A 1.7ms soft start is
internally provided to prevent output voltage overshoot
during start-up. A 100% maximum duty cycle allows the
SC4603 to operate as a low dropout regulator in the
event of a low battery condition.
Local microprocessor core power supplies
DSP and I/O power supplies
Battery powered applications
Telecommunication equipment
Data processing applications
The SC4603 is an ideal choice for 3.3V, 5V or other low
input supply systems. It’s available in 10 pin MSOP
package.
Typical Application Circuit
R15
Vin = 2.25V ~ 5.5V
1
C14
C10
22u
C11
22u
C12
C13
R3
M1
RT
33n
22u
22u
U1
34.8k
5
1
2
3
4
6
FS
ISET
PDRV
PHASE
NDRV
GND
R6
1.0
4.7u
C3
10
7
VCC
L1
2.3u
Vout = 1.5V (as low as 0.5V * ) /6A
SYNC
COMP
VSENSE
9
C9
C1
150p
M2
C7
150u
C4
8
1.2n
R1
C2
1n
R5
1.0
22u
R7
14k
SC4603
R8
806
20k
R9
6.98k
* External components can be modified to provide a Vout as low as 0.5V.
Revision: May 5, 2004
1
www.semtech.com
SC4603
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Supply Voltage (VCC)
6
±0.25
V
A
Output Drivers (PDRV, NDRV) Currents Continuous
Inputs (VSENSE, COMP, SYNC/SLEEP, FS, ISET)
Phase
6
V
-0.3 to 5.5
-2 to 6
-40 to +85
-65 to +150
-55 to +150
41.9
V
Phase Pulse tpulse < 50ns
V
Operating Ambient Temperature Range
Storage Temperature Range
TA
TSTG
TJ
°C
°C
°C
°C/W
°C/W
°C
kV
Junction Temperature Range
Thermal Impedance Junction to Case
Thermal Impedance Junction to Ambient
Lead Temperature (Soldering) 10 Sec.
ESD Rating (Human Body Model)
θJC
113.1
θJA
TLEAD
ESD
300
2
All voltages are with respect to GND. Currents are positive into,
Electrical Characteristics
negative out of the specified terminal.
Unless otherwise specified, VCC = 3.3V, RT = 21Kohm, TA = -40°C to 85°C, TA = TJ.
Parameter
Test Conditions
Min
Typ
Max
Unit
Overall
Supply Voltage
2.25
5.5
15
V
Supply Current, Sleep
Supply Current, Operating
VCC Turn-on Threshold
VCC Turn-off Hysteresis
Error Amplifier
VSYNC/SLEEP = 0V
10
2
µA
mA
V
3
2
2.25
100
mV
Internal Reference
VCC = 3.3V, TA = 25°C
495
492
500
505
508
0.35
0
mV
mV
VCC = 3.3V, TA = -40°C to 85°C
VCC = 2.25V to 3.3V, TA = 25°C
VCC = 3.3V to 5.5V, TA = 25°C
Internal Reference Change
-0.15
-0.4
0.1
-0.2
200
90
%/V
%/V
nA
VSENSE Bias Current
Open Loop Gain (1)
VCOMP = 0.5V to 2.5V
80 (1)
dB
Unity Gain Bandwidth (1)
8
MHz
V/µs
Slew Rate (1)
2.4
2004 Semtech Corp.
2
www.semtech.com
SC4603
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, RT = 21Kohm, TA = -40°C to 85°C, TA = TJ.
Parameter
Test Conditions
Min
Typ
Max
Unit
Error Amplifier (Cont.)
VCOMP High
I
COMP = -5.5mA
VCC - 0.6 VCC - 0.4
0.35
V
V
VCOMP Low
I
COMP = 5.5mA
0.525
660
Oscillator
Initial Accuracy
TA = 25°C, VSYNC/SLEEP = HIGH
TA = 25°C, VCC = 2.25V to 5.5V
TA = -40°C to 85°C
540
600
1
kHz
%/V
%/°C
MHz
V
Voltage Stability
Temperature Coefficient
Synchronization Frequency
SYNC Low Threshold
SYNC High Threshold
Ramp Peak to Valley (1)
Ramp Peak Voltage (1)
Ramp Valley Voltage (1)
Sleep, Soft Start, Current Limit
Sleep Threshold
0.01
1
0.8
2.0
V
1
V
1.25
0.25
V
V
Measured at VSYNC/SLEEP
LOGIC LOW
0.8
-57
V
V
Measured at VSYNC/SLEEP
LOGIC HIGH
2.0
-43
Sleep Input Bias Current (2)
Soft Start Time (1)
Current Limit Threshold (2)
VSYNC/SLEEP = 0V
FSW = 600kHz
-50
1.7
nA
ms
Bias Current, TJ = 25°C
Temperature Coefficient
-50
µA
+0.3
150
%/°C
ns
Current Limit Blank Time(1)
N-Channel and P-Channel Driver Outputs
Pull Up Resistance (PDRV) (2)
Pull Down Resistance (PDRV) (2)
Pull Up Resistance (NDRV) (1)
Pull Down Resistance (NDRV) (2)
PDRV Output Rise Time (2)
Vcc = 3.3V, IOUT = -100mA (source)
3.4
3
ohms
ohms
ohms
ohms
ns
Vcc = 3.3V, IOUT = 100mA (sink)
Vcc = 3.3V, IOUT = -100mA (source)
Vcc = 3.3V, IOUT = 100mA (sink)
Vgs = 3.3V, COUT = 1.0nF
3.4
1.5
8
PDRV Output Fall Time (2)
Vgs = 3.3V, COUT = 1.0nF
7
ns
2004 Semtech Corp.
3
www.semtech.com
SC4603
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, RT = 21Kohm, TA = -40°C to 85°C, TA = TJ.
Parameter
Test Conditions
Min
Typ
Max
Unit
N-channel and P-Channel Driver Outputs (Cont.)
NDRV Output Rise Time (1)
NDRV Output Fall Time (2)
Vgs = 3.3V, CCOMP = 1nF
Vgs = 3.3V, CCOMP = 1nF
8
3
ns
ns
Deadtime Delay
adaptive
(PDRV high to NDRV high) (3)
Deadtime Delay
30
50
ns
(NDRV low to PDRV low) (1)
Notes:
(1). Guaranteed by design.
(2). Guaranteed by characterization.
(3). Dead time delay from PDRV high to NDRV high is adaptive. As the phase node voltage drops below 600mV due to PDRV
high, NDRV will start to turn high.
2004 Semtech Corp.
4
www.semtech.com
SC4603
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number(1)
SC4603IMSTRT(2)
Notes:
Device
MSOP-10
Top View
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product.
(10 Pin MSOP)
Pin Descriptions
VCC: Positive supply rail for the IC. Bypass this pin to PHASE, ISET: PHASE input is connected to the junction
GND with a 0.1 to 4.7µF low ESL/ESR ceramic capaci- between the two external power MOSFET transistors. The
tor.
voltage drop across the upper P-channel device is moni-
tored by PHASE and ISET during PFET conduction and
GND: All voltages are measured with respect to this pin. forms the current limit comparator and logic that sets
All bypass and timing capacitors connected to GND should the PWM latch and terminates the PFET output pulse
have leads as short and direct as possible.
once excessive voltage drop across the PFET is detected.
The controller stops switching and goes through a soft
FS: An external resistor connected with FS pin sets the start sequence once the converter output voltage drops
clock frequency.
below 70% its nominal voltage. This prevents excess
power dissipation in the PMOSFET during a short circuit.
SYNC/SLEEP: The oscillator frequency of SC4603 is The current limit threshold is set by the external resistor
set by FS when SYNC/SLEEP is pulled and held above between VCC and ISET. The internal 50µA current source
2V. Its synchronous mode operation is activated as the has a positive temperature coefficient that can compen-
SYNC/SLEEP is driven by an external clock. The oscilla- sate PMOSFET Rdson variation due to its junction tem-
tor and PWM are designed to provide practical operation perature change.
to 1MHz when synchronized. Sleep mode is invoked if
SYNC/SLEEP is pulled and held below 0.8V which can be PDRV, NDRV: The PWM circuitry provides complemen-
accomplished by an external gate or transistor. The tary drive signals to the output stages. The Cross con-
Sleepmode supply current is 10µA typical.
duction of the external MOSFETs is prevented by moni-
toring the voltage on the P-channel and N-channel driver
VSENSE: This pin is the inverting input of the voltage pins in conjunction with a time delay optimized for FET
amplifier and serves as the output voltage feedback point turn-off characteristics.
for the Buck converter. It senses the output voltage through
an external divider.
COMP: This is the output of the voltage amplifier. The
voltage at this output is connected to the inverting input
of the PWM comparator. A lead-lag network around the
voltage amplifier compensates for the two pole LC filter
characteristic inherent to voltage mode control and is
required in order to optimize the dynamic performance
of the voltage mode control loop.
2004 Semtech Corp.
5
www.semtech.com
SC4603
POWER MANAGEMENT
Typical Characteristics
Oscillator Internal Accuracy
Oscillator Internal Accuracy
vs
vs
Input Voltage
Temperature
602.0
600.0
598.0
596.0
594.0
592.0
600
595
590
585
580
Vcc = 3.3V
TA = 25°C
2.5
2
3
3.5
4
4.5
5
5
5
5.5
5.5
5.5
-40
-20
0
20
40
60
80
Vcc (V)
Temperature (°C)
Sense Voltage
vs
Temperature
Sense Voltage
vs
Input Voltage
501.0
500.5
500.0
499.5
499.0
498.5
501.0
500.5
500.0
499.5
499.0
498.5
498.0
497.5
Vcc = 3.3V
A
T
= 25°C
-40
-20
0
20
40
60
80
2
2.5
3
3.5
4
4.5
Temperature (°C)
Vcc (V)
Current Limit Bias Current
Current Limit Bias Current
vs
vs
Input Voltage
Temperature
53
52
52
51
51
50
60
58
56
54
52
50
48
46
44
42
40
38
Vcc = 3.3V
A
T
= 25°C
2
2.5
3
3.5
Vcc (V)
4
4.5
-40
-20
0
20
40
60
80
Temperature (°C)
2004 Semtech Corp.
6
www.semtech.com
SC4603
POWER MANAGEMENT
Block Diagram
Applications Information
Enable
126 • 108
fS =
RT
Pulling and holding the SYNC/SLEEP pin below 0.8V ini-
tializes the SLEEP mode of the SC4603 with its typical
SLEEP mode supply current of 10uA. During the SLEEP
mode, the high side and low side MOSFETs are turned
off and the internal soft start voltage is held low.
An external clock connected to the SYNC/SLEEP acti-
vates its synchronous mode and the frequency of the
clock can be up to 1MHz.
Oscillator
UVLO
The oscillator uses an external resistor to set the oscilla-
tion frequency when the SYNC/SLEEP pin is pulled and
held above 2V. The ramp waveform is a triangle at the
PWM frequency with a peak voltage of 1.25V and a val-
ley voltage of 0.25V. A 100% maximum duty cycle allows
the SC4603 to operate as a low dropout regulator in the
event of a low battery condition. The resistor tolerance
adds to the accuracy of the oscillator frequency. The ex-
ternal resistor connected to the FS pin, as shown below
determines the approximate operating frequency:
When the SYNC/SLEEP pin is pulled and held above 2V,
the voltage on the VCC pin determines the operation of
the SC4603. As VCC increases during start up, the UVLO
block senses VCC and keeps the high side and low side
MOSFETs off and the internal soft start voltage low until
VCC reaches 2.25V. If no faults are present, the SC4603
will initiate a soft start when VCC exceeds 2.25V. A
hysteresis (100mV) in the UVLO comparator provides
noise immunity during its start up.
2004 Semtech Corp.
7
www.semtech.com
SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
Soft Start
IMAX and the internal 50µA pull down current available on
the ISET pin based on the following expression:
The soft start function is required for step down control-
lers to prevent excess inrush current through the DC bus
during start up. Generally this can be done by sourcing a
controlled current into a timing capacitor and then using
the voltage across this capacitor to slowly ramp up the
error amp reference. The closed loop creates narrow
width driver pulses while the output voltage is low and
allows these pulses to increase to their steady state duty
cycle as the output voltage reaches its regulated value.
With this, the inrush current from the input side is con-
trolled. The duration of the soft start in the SC4603 is
controlled by an internal timing circuit which is used dur-
ing start up and over current to set the hiccup time. The
soft start time can be calculated by:
IMAX • RDS(ON)
RSET
=
50µA
Kelvin sensing connections should be used at the drain
and source of P-MOSFET.
The RDS(ON) sensing used in the SC4603 has an addi-
tional feature that enhances the performance of the over
current protection. Because the RDS(ON) has a positive
temperature coefficient, the 50µA current source has a
positive coefficient of about 0.3%/C° providing first or-
der correction for current sensing vs temperature. This
compensation depends on the high amount of thermal
transferring that typically exists between the high side P-
MOSFET and the SC4603 due to the compact layout of
the power supply.
1020
=
TSOFT _START
fS
When the converter detects an over current condition
(I > IMAX) as shown in Figure 1, the first action the SC4603
takes is to enter cycle by cycle protection mode (Point B
to Point C), which responds to minor over current cases.
Then the output voltage is monitored. If the over current
and low output voltage (set at 70% of nominal output
voltage) occur at the same time, the Hiccup mode op-
eration (Point C to Point D) of the SC4603 is invoked
and the internal soft start capacitor is discharged. This is
like a typical soft start cycle.
As can be seen here, the soft start time is switching
frequency dependant. For example, if fs = 600kHz,
TSOFT
TSOFT
_
= 1020/600k = 1.7ms. But if fs = 1MHz,
_
START = 1020/1M = 1.02ms.
START
The SC4603 implements its soft start by ramping up the
error amplifier reference voltage providing a controlled
slew rate of the output voltage, then preventing over-
shoot and limiting inrush current during its start up.
Over Current Protection
A
Over current protection for the SC4603 is implemented
by detecting the voltage drop of the high side P-MOSFET
during conduction, also known as high side RDS(ON) detec-
tion. This loss-less detection eliminates the sense resis-
tor and its loss. The overall efficiency is improved and
the number of components and cost of the converter
are reduced. RDS(ON) sensing is by default inaccurate and
is mainly used to protect the power supply during a fault
case. The over current trigger point will vary from unit to
unit as the RDS(ON) of P-MOSFET varies. Even for the same
unit, the over current trigger point will vary as the junc-
tion temperature of P-MOSFET varies. The SC4603 pro-
vides a built-in 50µA current source, which is combined
with RSET (connected between VCC and ISET) to determine
the current limit threshold. The value of RSET can be prop-
erly selected according to the desired current limit point
B
VO−nom
⋅V
0.7
C
O−nom
VO
IMA
D
IO
Figure 1. Over current protection characteristic of
SC4603
2004 Semtech Corp.
8
www.semtech.com
SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
Power MOSFET Drivers
ripple current to be within 15% to 30% of the maximum
output current.
The inductor value can be determined according to its
operating point and the switching frequency as follows:
The SC4603 has two drivers for external complemen-
tary power MOSFETs. The driver block consists of one
high side P-MOSFET driver, PDRV, and one low side N-
MOSFET driver, NDRV, which are optimized for driving
external power MOSFETs in a synchronous buck con-
verter. The output drivers also have gate drive non-over-
lap mechanism that gives a dead time between PDRV
and NDRV transitions to avoid potential shoot through
problems in the external MOSFETs. By using the proper
design and the appropriate MOSFETs, a 6A converter can
be achieved. As shown in Figure 2, td1, the delay from
the P-MOSFET off to the N-MOSFET on is adaptive by
detecting the voltage of the phase node. td2, the delay
from the N-MOSFET off to the P-MOSFET on is fixed, is
50ns for the SC4603. This control scheme guarantees
avoiding the cross conduction or shoot through between
two MOSFETs and minimizes the conduction loss in the
bottom diode for high efficiency applications.
Vout (V − Vout
)
in
L =
V
fs ∆I IOMAX
in
Where:
fs = switching frequency and
∆I = ratio of the peak to peak inductor current to the
maximum output load current.
The peak to peak inductor current is:
Ip−p = ∆I• IOMAX
After the required inductor value is selected, the proper
selection of the core material is based on the peak in-
ductor current and efficiency requirements. The core
must be able to handle the peak inductor current IPEAK
without saturation and produce low core loss during the
high frequency operation.
Ip−p
2
PMOSFET Gate Drive
NMOSFET Gate Drive
IPEAK = IOMAX
+
The power loss for the inductor includes its core loss and
copper loss. If possible, the winding resistance should
be minimized to reduce inductor’s copper loss. The core
loss can be found in the manufacturer’s datasheet. The
inductor’s copper loss can be estimated as follows:
Ground
Phase node
td2
td1
PCOPPER = I2
RWINDING
LRMS
Figure 2. Timing Waveforms for Gate Drives and Phase Node
Where:
ILRMS is the RMS current in the inductor. This current can
be calculated as follows:
Inductor Selection
The factors for selecting the inductor include its cost,
efficiency, size and EMI. For a typical SC4603 applica-
tion, the inductor selection is mainly based on its value,
saturation current and DC resistance. Increasing the in-
ductor value will decrease the ripple level of the output
voltage while the output transient response will be de-
graded. Low value inductors offer small size and fast tran-
sient responses while they cause large ripple currents,
poor efficiencies and more output capacitance to smooth
out the large ripple currents. The inductor should be able
to handle the peak current without saturating and its
copper resistance in the winding should be as low as
possible to minimize its resistive power loss. A good trade-
off among its size, loss and cost is to set the inductor
1
3
ILRMS = IOMAX 1+
∆I2
Output Capacitor Selection
Basically there are two major factors to consider in se-
lecting the type and quantity of the output capacitors.
The first one is the required ESR (Equivalent Series Re-
sistance) which should be low enough to reduce the volt-
age deviation from its nominal one during its load changes.
The second one is the required capacitance, which should
be high enough to hold up the output voltage. Before the
SC4603 regulates the inductor current to a new value
2004 Semtech Corp.
9
www.semtech.com
SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
during a load transient, the output capacitor delivers all
the additional current needed by the load. The ESR and
ESL of the output capacitor, the loop parasitic inductance
between the output capacitor and the load combined
with inductor ripple current are all major contributors to
the output voltage ripple. Surface mount speciality poly-
mer aluminum electrolytic chip capacitors in UE series
from Panasonic provide low ESR and reduce the total
capacitance required for a fast transient response.
POSCAP from Sanyo is a solid electrolytic chip capacitor
which has a low ESR and good performance for high fre-
quency with a low profile and high capacitance. Above
mentioned capacitors are recommended to use in
SC4603 applications.
Because the input capacitor is exposed to the large surge
current, attention is needed for the input capacitor. If
tantalum capacitors are used at the input side of the
converter, one needs to ensure that the RMS and surge
ratings are not exceeded. For generic tantalum capaci-
tors, it is wise to derate their voltage ratings at a ratio of
2 to protect these input capacitors.
Power MOSFET Selection
The SC4603 can drive a P-MOSFET at the high side and
an N-MOSFET synchronous rectifier at the low side. The
use of the high side P-MOSFET eliminates the need for
an external charge pump and simplifies the high side gate
driver circuit.
Input Capacitor Selection
For the top MOSFET, its total power loss includes its con-
duction loss, switching loss, gate charge loss, output ca-
pacitance loss and the loss related to the reverse
recovery of the bottom diode, shown as follows:
The input capacitor selection is based on its ripple cur-
rent level, required capacitance and voltage rating. This
capacitor must be able to provide the ripple current by
the switching actions. For the continuous conduction
mode, the RMS value of the input capacitor can be cal-
culated from:
ITOP _PEAK V fs
I
PTOP _TOTAL = I2
RTOP_ON
+
TOP _RMS
V
GATE RG
(QGD + QGS2 ) + QGT VGATE fs + (QOSS + Qrr ) V fs
I
Vout (V − Vout
)
in
ICIN
= IOMAX
(RMS)
2
V
in
Where:
RG = gate drive resistor,
QGD = the gate to drain charge of the top MOSFET,
QGS2 = the gate to source charge of the top MOSFET,
QGT = the total gate charge of the top MOSFET,
QOSS = the output charge of the top MOSFET, and
Qrr = the reverse recovery charge of the bottom diode.
This current gives the capacitor’s power loss as follows:
PCIN = I2
RCIN(ESR)
CIN(RMS)
This capacitor’s RMS loss can be a significant part of the
total loss in the converter and reduce the overall
converter efficiency. The input ripple voltage mainly de-
pends on the input capacitor’s ESR and its capacitance
for a given load, input voltage and output voltage. As-
suming that the input current of the converter is con-
stant, the required input capacitance for a given voltage
ripple can be calculated by:
For the top MOSFET, it experiences high current and high
voltage overlap during each on/off transition. But for the
bottom MOSFET, its switching voltage is the bottom
diode’s forward drop during its on/off transition. So the
switching loss for the bottom MOSFET is negligible. Its
total power loss can be determined by:
PBOT _TOTAL = I2
RBOT _ON + QGB VGATE fs +ID _AVG VF
D (1−D)
fs (∆V −IOMAX RCIN
BOT _RMS
CIN = IOMAX
)
I
(ESR)
Where:
Where:
D = VO/VI , duty ratio and
QGB = the total gate charge of the bottom MOSFET and
VF = the forward voltage drop of the bottom diode.
∆VI = the given input voltage ripple.
2004 Semtech Corp.
10
www.semtech.com
SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
For example, if
VCC = 2.25V,
the reference voltage,
Internal Reference
For a low voltage and high output current application such
as the 3.3V/1.5V@6A case, the conduction loss is often
dominant and selecting low RDS(ON) MOSFETs will notice-
ably improve the efficiency of the converter even though
they give higher switching losses.
VREF @2.25V =
Vref @3.3V
100
+
•
V
@ 3.3V
REF
The gate charge loss portion of the top/bottom MOSFET’s
total power loss is derived from the SC4603. This gate
charge loss is based on certain operating conditions
(fs, VGATE, and IO).
@2.25V • VCC − 3.3V =
Change
500
500 +
• 0.1• 2.25 − 3.3 = 500.5(mV)
100
The thermal estimations have to be done for both
MOSFETs to make sure that their junction temperatures
do not exceed their thermal ratings according to their
total power losses PTOTAL, ambient temperature TA and their
5
1
2
3
4
6
FS
ISET
PDRV
PHASE
NDRV
GND
10
7
VCC
L1
Vout
SYNC
COMP
VSENSE
9
C9
8
thermal resistances RθJA as follows:
C2
C4
R
C1
R7
SC4603
R8
R1
PTOTAL
TJ(max) < TA +
RθJA
R9
Loop Compensation Design:
For a DC/DC converter, it is usually required that the Figure 3. Compensation network provides 3 poles and
converter has a loop gain of a high cross-over frequency 2 zeros.
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for For voltage mode step down applications as shown in
its operating stability. Often one can not have all these Figure 3, the power stage transfer function is:
properties at the same time. The purpose of the loop
s
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
1+
1
RC C4
1+ s + s2L1C4
GVD(s) = V
IN
L1
R
The SC4603 has an internal error amplifier and requires
the compensation network to connect among the COMP Where:
pin and VSENSE pin, GND, and the output as shown in R = load resistance and
Figure 3. The compensation network includes C1, C2, RC = C4’s ESR.
R1, R7, R8 and C9. R9 is used to program the output
voltage according to:
The compensation network will have the characteristic
as follows:
R7
R9
s
ωZ1
s
s
ωZ2
s
VOUT = 0.5 (1+
)
1+
1+
1+
1+
ωI
GCOMP (s) =
s
As indicated in Internal Reference Change section, the
internal reference voltage (measured at VSENSE pin)
changes slightly if the input voltage of the SC4603 is
away from 3.3V.
ωP1
ωP2
2004 Semtech Corp.
11
www.semtech.com
SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
Where
The compensated loop gain will be as given in Figure 4:
1
ωI =
T
ω
Z1
R7 (C1 + C2 )
Loop gain T(s)
-20dB/dec
o
ω
ω
Z2
Gd
1
c
ω
ωZ1
=
0dB
R1 C2
p1
ω
ωp2
1
ωZ2
=
(R7 + R8 ) C9
C1 + C2
=
Power stage GVD(s)
ω
ESR
-40dB/dec
ωP1
R1 C1 C2
1
=
ωP2
R8 C9
Figure 4. Asymptotic diagrams of power stage and its
loop gain.
After the compensation, the converter will have the
following loop gain:
Layout Guidelines
T(s) = GPWM GCOMP(s) GVD(s) =
s
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special at-
tention must be paid to the PCB layouts. The goal of lay-
out optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
1+
1
s
ωZ1
s
s
ωZ2
s
1
ωI V 1+
1+
1+
IN
VM
RC C4
1+ s + s2LC
L
R
s
1+
ωP1
ωP2
Where:
GPWM = PWM gain and
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
3. The VCC bypass capacitor should be placed next to
the VCC and GND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
5. Minimize the traces between PDRV/NDRV and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
6. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
VM = 1.0V, ramp peak to valley voltage of SC4603.
The design guidelines for the SC4603 applications are
as following:
1. Set the loop gain crossover corner frequency
ωC for given switching corner frequency
ωS =2 πfs,
2. Place an integrator at the origin to increase DC
and low frequency gains.
3. Select ωZ1 and ωZ2 such that they are placed
near ωO to damp the peaking and the loop gain
has a -20dB/dec rate to go across the 0dB
line for obtaining a wide bandwidth.
4. Cancel the zero from C4’s ESR by a compensa-
tor pole ωP1 (ωP1 = ωESR = 1/( RCC4)),
5. Place a high frequency compensator pole ωp2
(ωp2 = πpfs) to get the maximum attenuation of
the switching ripple and high frequency noise
with the adequate phase lag at ωC.
7. ISET and PHASE connections to P-MOSFET for cur-
rent sensing must use Kelvin connections.
2004 Semtech Corp.
12
www.semtech.com
SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
Layout Guidelines (Cont.)
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4603 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible.
Design Example 1: 3.3V to 1.5V @ 5A application with
SC4603 (NH020 footprint).
R15
1
Vin = 3.3V
R3
C14
33n
C10
22u
C11
22u
M1
U1
FS
RT 21k
4.7u
5
1
2
3
4
6
ISET
PDRV
R6
1.0
C3
10
7
VCC
L1
1.1u
R2
Vo = 1.5V/5A
SYNC/SLEEPPHASE
3.32k
9
COMP
NDRV
GND
C9
820p
C1
150p
C2
M2
C7
150u
C4
8
VSENSE
R1
R5
22u
R7
13k
SC4603
R8
604
20k
820p
1.0
R9
6.49k
Figure 5. Schematic for 3.3V/1.5V @ 5A application
2004 Semtech Corp.
13
www.semtech.com
SC4603
POWER MANAGEMENT
Bill of Materials - 3.3V to 1.5V @ 5A
Item
1
Qty
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
2
1
1
1
1
Reference
Value
Part No./Manufacturer
C1
C2
C3
C7
C9
150pF
820pF
4.7uF
2
3
4
150uF
820pF
22uF, 1210
33nF
Panasonic. P/N: 6.3V, SP
5
6
C10,C11,C4
C14
L1
TDK P/N: C3225X5R0J226M
7
8
1.1uH
9
M1
MOSFET P, S0-8
Fairchild P/N: FDS 6375
Fairchild P/N: FDS 6680A
10
11
12
13
14
15
16
17
18
19
20
M2
MOSFET N, S0-8
RT
21k
R1
20k
R2
3.32k
13k
R7
R8
604
R5,R6
R15
R3
1
1
2.94k
6.49k
SC4603
R9
U1
Semtech P/N: SC4603IMSTRT
Key components:
U1: SC4603, Semtech
M1: FDS 6375, SO-8, Fairchild
M2: FDS 6680A, SO-8, Fairchild
L1: SMT power inductor, 1.1uH ETQP6F1R1H, Panasonic.
Unless specified, all resistors and capacitors are in SMD 0603 package.
Resistors are +/-1% and all capacitors are +/-20%
2004 Semtech Corp.
14
www.semtech.com
SC4603
POWER MANAGEMENT
PCB Layout - 3.3V to 1.5V @ 6A
Top
Bottom
Top
Bottom
15
2004 Semtech Corp.
www.semtech.com
SC4603
POWER MANAGEMENT
Outline Drawing - MSOP-10
Land Pattern - MSOP-10
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2004 Semtech Corp.
16
www.semtech.com
相关型号：
©2020 ICPDF网 联系我们和版权申明