SC4612HSTRT [SEMTECH]
40V Synchronous Buck Controller; 40V同步降压控制器
| 型号： | SC4612HSTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 40V Synchronous Buck Controller |
| 文件： | 总21页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4612H
40V Synchronous Buck Controller
POWER MANAGEMENT
Description
Features
SC4612H is a high performance synchronous buck
controller that can be configured for a wide range of
applications. The SC4612H utilizes synchronous rectified
buck topology where high efficiency is the primary
consideration. SC4612H can be used over a wide input
voltage range with output voltage adjustable within limits
set by the duty cycle boundaries.
u Wide input voltage range, 4.75V to 40V
u Internally regulated DRV
u 1.7A gate drive capability
u Low side RDS-ON sensing with hiccup OCP
u Programmable current limit
u Programmable frequency up to 1.2 MHz
u Overtemperature protected
u Pre-bias startup
SC4612H comes with a rich set of features such as
regulated DRV supply, programmable soft-start, high
current gate drivers, shoot through protection, RDS-ON
sensing with hiccup over current protection.
u Reference accuracy ±1%
u Available in MLPD-12 4 x 3 and SOIC-14 Pb-free
packages. This product is fully WEEE and RoHS
compliant
Applications
u Distributed power architectures
u Telecommunication equipment
u Servers/work stations
u Mixed signal applications
u Base station power management
u Point of use low voltage high current applications
Typical Application Circuit
U1
R1
adj
SC4612MLP
D1
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
DH
C1
C2
BST
DRV
DL
C3
R2
C8
Q1
Q2
L1
C7
C4
+
8
R3
opt
C10
C11
Vout
C9
7
+
VDD
GND
C5
_
Cin
Vin
R5
_
R4
R6
C6
Revision: August 14, 2008
1
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SC4612H
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Bias Supply Voltage to GND
VDD
VIN
-0.3 to 45
-2 to +55
-0.3 to 10
-0.3 to +5
100
V
V
PHASE to GND
DRV, ILIM, DL to GND, BST, DH to PHASE
EAO, SS/EN, FB, OSC to GND
V
V
DRV Source Current (peak)
mA
°C/W
°C/W
°C/W
°C/W
°C
Thermal Resistance Junction to Ambient (MLPD) (1)
Thermal Resistance Junction to Case (MLPD)
45.3
qJA
qJC
11
(1)
Thermal Resistance Junction to Ambient (SOIC)
115
qJA
Thermal Resistance Junction to Case (SOIC)
Storage Temperature Range
45
qJC
TSTG
-65 to +150
260
Peak IR Reflow Temperature (10-40s)
Lead Temperature (10s), (SOIC-14)
T
°C
IR Reflow
TLEAD
300
°C
All voltages with respect to GND. Positive currents are into, and negative currents are out of the specified terminal. Pulsed
is defined as a less than 10% duty cycle with a maximum duration of 500ns. Consult Packaging Section of Data sheet for
thermal limitations and considerations of packages.
Note:
(1). ThetaJA is calculated from a package in still air, mounted to a 3” x 4.5”, 4 layer FR4PCB with thermal vias (if applicable)
per JESD51 standards.
Recommended Operating Conditions
Performance is not guaranteed if the conditions below are exceeded.
Parameter
Symbol
VDD
TA
Conditions
Min
5
Typ
Max
40
Units
V
Supply Voltage Range
Ambient Temperature Range
Junction Temperature Range
-40
-40
105
125
oC
TJ
oC
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SC4612H
POWER MANAGEMENT
Electrical Characteristics
Unless otherwise specified:
VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = 25°C.
Parameter
Test Conditions
Min
Typ
Max
Units
Bias Supply
Quiescent Current
VDD Undervoltage Lockout
Start Threshold
UVLO Hysteresis
Drive Regulator
DRV
VDD = 40V, No load, SS/EN = 0
5
7
mA
4.20
7.3
4.50
400
4.75
V
mV
10V £ VDD £ 40V, IOUT £ 1mA
1mA £ IOUT £ 70mA
7.8
8.3
V
Load Regulation
Oscillator
100
mV
Operation Frequency Range
Initial Accuracy(1)
100
540
1200
660
kHz
kHz
COSC = 160pF (Ref only)
600
Maximum Duty Cycle
VDD = VDR = 8V; VOUT_NOM = 5V; IOUT = 0A
VIN adjust down to VOUT = 0.99 · VOUT _NOM
82
90
%
Ramp Peak to Valley (1)
Oscillator Charge Current
Current Limit (Low Side Rdson)
Current Limit Threshold Voltage
Error Amplifier
850
100
mV
µA
VOSC = 1V
110
See Pg. 12 & 13 on OCP
mV
Feedback Voltage
TJ = 0 to +70°C
TJ = -40 to +85°C
TJ = -40 to +125°C
FB = 0.5V
0.495
0.492
0.488
0.500
0.500
0.500
0.505
0.508
0.512
200
V
V
V
Input Bias Current
nA
dB
MHz
µA
µA
V/µs
(1)
Open Loop Gain
60
10
Unity Gain Bandwidth (1)
Output Sink Current
Output Source Current
Slew Rate (1)
7
Open Loop, FB = 0V
Open Loop, FB = 0.6V
900
1100
1
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SC4612H
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified:
VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = 25°C.
Parameter
Test Conditions
Min
Typ
Max
Units
SS/EN
Disable Threshold Voltage
Soft Start Charge Current
Soft Start Discharge Current (1)
Disable Low to Shut Down (1)
Hiccup
500
mV
µA
µA
ns
25
1
50
CSS = 0.1,
current limit condition
Hiccup duty cycle
1
%
Gate Drive
Gate Drive On-Resistance (H)(2)
Gate Drive On-Resistance (L)(2)
DL Source/Sink Peak Current(2)
DH Source/Sink Peak Current(2)
Output Rise Time(2)
ISOURCE = 100mA
ISINK = 100mA
3
4
4
W
W
A
3
COUT = 2000pF
COUT = 2000pF
COUT = 2000pF
COUT = 2000pF
1.4
1.4
1.7
1.7
20
20
30
A
ns
ns
ns
ns
Output Fall Time(2)
Minimum Non-Overlap (1)
Minimum On Time(2)
110
Thermal Shutdown
Shutdown Temperature (2)
Thermal Shutdown Hysteresis (2)
Notes:
165
15
°C
°C
(1) Guaranteed by design. Not production tested.
(2) Guaranteed by characterization.
(3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC4612H
POWER MANAGEMENT
Pin Configurations
Ordering Information
Part Number(3)
Package(2)
Temp. Range (TJ)
TOP VIEW
SC4612HMLTRT MLPD-12 4 x 3
-40°C to +125°C
1
2
3
4
5
6
ILIM
OSC
SS/EN
EAO
FB
12
11
10
9
PHASE
DH
SC4612HSTRT
SC4612HEVB(1)
SOIC-14
EVALUATION BOARD
BST
DRV
DL
Notes:
(1) When ordering please specify MLPD or SOIC
package.
(2) Only available in tape and reel packaging. A reel
contains 3000 devices for MLPD package and 2500 for
SOIC package..
8
VDD
7
GND
(12 Pin MLPD)
TOP VIEW
(3) Pb-free product. This product is fully WEEE and
RoHS compliant.
NC
ILIM
OSC
1
2
3
4
5
6
7
14
13
12
11
10
9
PHASE
DH
BST
DRV
DL
SS/EN
EAO
VDD
NC
GND
FB
8
(14 Pin SOIC)
Marking Information - MLPD
Marking Information - SOIC
Top Mark
Top Mark
4612H
yyww
xxxxx
SC4612H
yyww
xxxxxxxxx
nnnn = Part Number (Example: SC4612H)
yyww =Date Code (Example: 0752)
nnnn
= Part Number (Example: 1531)
yyww = Date Code (Example: 0012)
xxxxx = Semtech Lot No. (Example:A01E90101)
xxxxx = Semtech Lot No. (Example:E9010)
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SC4612H
POWER MANAGEMENT
Pin Descriptions
Pin #
Pin#
Pin Name Pin Function
MLPD
SOIC
1, 7
2
NC
No connection.
1
ILIM
The current limit programing resistor at this pin in conjunction with an internal current
source programs the current limit threshold for the low side MOSFET RDS-ON sensing.
Once the voltage drop across the bottom MOSFET is larger than the programmed value,
current limit condition occurs, and the hiccup current limit protection is activated.
2
3
3
4
OSC
Oscillator Frequency set pin. An external capacitor to GND will program the oscillator
frequency. See Table 1 "Frequency vs. COSC" to determine oscillator frequency.
SS/EN
Soft Start pin. Internal current source connected to a single external capacitor will
determine the soft-start duration for the output. Inhibits the chip if pulled down.
CSS X 1.2
TSS
»
ISS
4
5
5
8
EAO
FB
Error Amplifier Output. A compensation network is connected from this pin to FB.
The inverting input of the error amplifier. Feedback pin is used to sense the output
voltage via a resistive divider.
6
6
VDD
Bias supply. Also, VDD pin is internally used to provide the base drive to the internal
pass transistor regulating the DRV supply.
7
8
9
9
GND
DL
Ground.
10
11
Drive Low. Gate drive for bottom MOSFET.
DRV
DRV supplies the external MOSFETs gate drive and the chips internal circuitry. This pin
should be bypassed with a ceramic capacitor to GND. DRV is internally regulated from
the external supply connected to VDD. If VDD is below 10V, the supply should be directly
connected to the DRV pin.
10
12
BST
BST signal. Supply for high side driver; can be directly connected to an external supply
or to a bootstrap circuit.
11
12
13
14
DH
Drive High. Gate drive for top MOSFET.
PHASE
The return path for the high side gate drive, also used to sense the voltage at the phase
node for adaptive gate drive protection and the low-side RDS-ON current sensing.
THERMAL Pad for heatsinking purposes. Connect to ground plane using multiple vias.
PAD (GND)
X
N/A
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SC4612H
POWER MANAGEMENT
Block Diagram
CO_INT
S
R
Q
BST
EN
S
R
Q
DH
OTP
PHASE
DRV
S_MOD
DL
+
-
S
R
Q
GND
830mV
OSC
SPLSE
OSC
OSC
DRV
DRV
VDD
VREF
S
R
Q
+
-
V+
VDD
DRV
SS_3
REG
OUT
& BG
VREF
VREF
V-
EAO
12k
0.6V
VSS
OVP
-
FB
+
OC DETECT
OC
ILIM
SOFTSTART
S
R
Q
S
R
Q
S
R
Q
S
R
Q
SSDN
SSLO
d
d
SSINT
SS/EN
SS SSHI
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SC4612H
POWER MANAGEMENT
Typical Characteristics
Typical Soft Start Current vs Temperature
Typical Error Amp Output Current vs Temperature
1.5
1.0
25
24
23
22
Source; VEAO=0V; VFB=0V
0.5
0.0
-0.5
-1.0
-1.5
Sink; VEAO=1.5V; VFB=0.6V
-50
0
50
100
150
-50
0
50
100
150
Temperature (OC)
Temperature (OC)
Typical DRV Voltage vs Load Current
Typical UVLO vs Temperature
8
4.5
-40C
25C
VDD Rising
4.4
4.3
4.2
4.1
4.0
7
6
5
125C
VDD Falling
-50
0
50
100
150
0
20
40
60
80
100
120
140
IDRV (mA)
Temperature (OC)
Typical VFB vs Temperature
Typical Oscillator Charge Current vs Temperature
503
502
501
500
499
498
497
104
102
100
98
VDD=42V
VDD=5V
96
94
-50
0
50
100
150
-50
0
50
100
150
Temperature (OC)
Temperature (OC)
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SC4612H
POWER MANAGEMENT
Typical Characteristics (Cont.)
Start Up from VOUT = 0V
Typical VDD Quiescent current vs Temperature
5
VDD=42V
4
3
VDD=12V
2
1
0
-50
0
50
100
150
Temperature (OC)
Start Up from VOUT = 2.5V
First DH/DL Pulses
Start Up from VOUT = 2.5V
Short Circuit Applied
Steady State Waveforms
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SC4612H
POWER MANAGEMENT
Applications Information
INTRODUCTION
startup to discharge it, as a normal synchronous buck
controller would do. An external capacitor on the SS/EN
pin is used to set the Soft Start duration.
The SC4612H is a versatile voltage mode synchronous
rectified buck PWM convertor, with an input supply (VIN)
ranging from 4.5V to 40V designed to control and drive
N-channel MOSFETs.
0.5 · CSS
TSS
»
25 · 10- 6
Startup is inhibited until VDD input reaches the UVLO
threshold (typically 4.5V). Once VDD rises above UVLO,
the external soft start capacitor begins to charge from an
internal 25uA current source. When the SS/EN pin reaches
approximately 0.8V, top side switching is enabled.
However, a top side pulse will not occur until SS/EN has
charged up to the level appropriate for the existing output
voltage (a pre bias condition). Once the first top side gate
pulse actually occurs, the bottom side driver is enabled
and the remainder of the startup is fully synchronous.
In the event of an over current during startup, the SC4612H
behaves in the same manner as an over current in steady
state (see Over Current Protection).
The power dissipation is controlled by allowing high speed
and integration with the high drive currents to ensure low
MOSFET switching loss. The synchronous buck configu-
ration also allows converter sinking current from load with-
out losing output regulation.
The internal reference is trimmed to 500mV with ± 1%
accuracy, and the output voltage can be adjusted by an
external resistor divider.
A fixed oscillator frequency (up to 1.2MHz) can be
programmed by an external capacitor for design
optimization.
Other features of the SC4612H include:
Wide input power voltage range (from 4.5V to 40V), low
output voltages, externally programmable soft-start, hiccup
over current protection, wide duty cycle range, thermal
shutdown, and -40 to 125°C junction operating
temperature range.
Oscillator Frequency Selection
The internal oscillator sawtooth signal is generated by
charging an external capacitor with a current source of
100µA charge current.
See Table 1 “Frequency vs. COSC” to determine oscillator
frequency.
THEORY OF OPERATION
SUPPLIES
Frequency, vs. COSC
Two pins (VDD and DRV) are used to power up the
SC4612H. If input supply (Vin) is less than 10V, tie DRV
and VDD together.
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
This DRV supply should be bypassed with a low ESR 2.2uF
(or greater) ceramic capacitor directly at the DRV to GND
pins of the SC4612H.
The DRV supply also provides the bias for the low and the
high side MOSFET gate drive.
The maximum rating for DRV supply is 10V and for
applications where input supply is below 10V, it should be
connected directly to VDD.
The internal pass transistor will regulate the DRV from an
external supply connected to VDD to produce 7.8V typical
at the DRV pin.
0
100 200 300 400 500 600 700 800 900 1000 1100 1200
Frequency, (kHz)
Table 1
Soft Start / Shut down
The SC4612H performs a “pre-bias” type startup. This
ensures that a pre-charged output capacitor will not
cause the SC4612H to turn on the bottom FET during
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SC4612H
POWER MANAGEMENT
Applications Information (Cont.)
Under Voltage Lock Out
to regulate the output voltage. The power stage of the
synchronous rectified buck converter control-to-output
transfer function is as shown below.
Under Voltage Lock Out (UVLO) circuitry senses the VDD
through a voltage divider. If this signal falls below 4.5V
(typical) with a 400mV hysteresis (typical), the output driv-
ers are disabled. During the thermal shutdown, the out-
put drivers are disabled.
æ
ç
ö
÷
V
1+ sESR C
ç
ç
÷
÷
IN
C
G
(s) =
´
VD
L
V
2
ç
ç
è
÷
÷
ø
1+ s
+ s LC
S
R
L
OVERCURRENT PROTECTION
where,
VIN – Input voltage
L – Output inductance
The SC4612H features low side MOSFET RDS(ON) current
sensing and hiccup mode over current protection. The
voltage across the bottom FET is sampled approximately
150ns after it is turned on to prevent false tripping due to
ringing of the phase node.
ESRC – Output capacitor ESR
VS – Peak to peak ramp voltage
RL – Load resistance
The internally set over current threshold is 100mV typical.
This can be adjusted up or down by connecting a resistor
between ILIM and DRV or GND respectively. When
programming with an external resistor, threshold set point
accuracy will be degraded to 30%. The FET RDS(ON) at
temperature will typically be 150% or more of the room
temperature value. Allowance should be made for these
sources of error when programming a threshold value.
When an over current event occurs, the SC4612H
immediately disables both gate drives. The SS ramp
continues to its final value, if not already there. Once at
final value, the SS capacitor is discharged at approximately
1uA until SS low value is reached (approx 0.8V). The SS/
Hiccup cycle will then repeat until the fault condition is
removed and the SC4612H starts up normally on the next
SS cycle.
C – Output capacitance
The classical Type III compensation network can be built
around the error amplifier as shown below:
C3
C2
R3
R2
C1
R1
-
+
Vref
Gate Drive/Control
The SC4612H provides integrated high current drivers for
fast switching of large MOSFETs. The higher gate current
will reduce switching losses of the larger MOSFETs.
Figure 1. Voltage mode buck converter compensation
network. The transfer function of the compensation
network is as follows:
The low side gate drive is supplied directly from the DRV.
The high side gate drive is bootstraped from the DRV pin.
s
s
wZ2
s
(1+
)(1+
)(1+
)
)
w
wZ1
s
I
GCOMP(s) =
×
(1+
Cross conduction prevention circuitry ensures a non over-
lapping (30ns typical) gate drive between the top and bot-
tom MOSFETs. This prevents shoot through losses which
provides higher efficiency. Typical total minimum off time
for the SC4612H is about 30ns.
s
wP1
wP2
where,
1
1
1
wZ1
=
, wZ2
=
, wo =
R2C1
(R1 + R3 )C2
Lout ´ Cout
ERROR AMPLIFIER DESIGN
The SC4612H is a voltage mode buck controller that utilizes
an externally compensated high bandwidth error amplifier
1
1
1
w =
,
wP1
=
,
wP2
=
I
C1C3
2 C1 + C3
R1(C1 + C3 )
R3C2
R
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SC4612H
POWER MANAGEMENT
Applications Information (Cont.)
The design guidelines are as following:
1. Set the loop gain crossover frequency wC for given
switching frequency.
2. Place an integrator at the origin to increase DC and low
frequency gains.
3. Select wZ1 and wZ2 such that they are placed near wO to
dampen peaking; the loop gain should cross 0dB at a rate
of -20dB/dec.
4. Cancel wESR with compensation pole wP1 (wP1 = wESR ).
5. Place a high frequency compensation pole wP2 at half
the switching frequency to get the maximum attenuation
of the switching ripple and the high frequency noise with
adequate phase lag at wC.
T
wZ1
Loop gain T(s)
w o
wZ2
Gd
wc
0dB
w p1
w p2
w ESR
Figure 2. Simplified asymptotic diagram of buck power
stage and its compensated loop gain.
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SC4612H
POWER MANAGEMENT
Application Information (Cont.)
COMPONENT SELECTION:
The maximum inductor value may be calculated from:
R ESR
C
SWITCHING SECTION
L £
(
VIN - VO
)
It
OUTPUT CAPACITORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maximum
will guarantee that the inductor current will ramp fast
enough to reduce the voltage dropped across the ESR at a
faster rate than the capacitor sags, hence ensuring a good
recovery from transient with no additional excursions. We
must also be concerned with ripple current in the output
inductor and a general rule of thumb has been to allow
10% of maximum output current as ripple current. Note
that most of the output voltage ripple is produced by the
inductor ripple current flowing in the output capacitor ESR.
Ripple current can be calculated from:
Vt
RESR
£
It
Where
Vt = Maximum transient voltage excursion
It = Transient current step
VIN
IL
=
RIPPLE
4×L× fOSC
Ripple current allowance will define the minimum permitted
inductor value.
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mW. To meet this kind of ESR level, there are three
available capacitor technologies.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
Each
Total
Capacitor
Qty
Rqd.
TOP FET - The power dissipation in the top FET is a
combination of conduction losses, switching losses and
bottom FET body diode recovery losses.
Technology
C
ESR
C
(uF)
ESR
(uF) (mW)
(mW)
2-10
7.0
Ceramic
22
2-10
7
1
1
2
5
22
a) Conduction losses are simply calculated as:
SP Cap
220
680
220
PCOND = I2O ×RDS(on) ×D
POS-CAP
18
44
1360
7500
9.0
where
Low ESR Aluminum 1500
8.8
VO
D = duty cycle »
V
IN
The choice of which to use is simply a cost/performance
issue, with low ESR Aluminum being the cheapest, but
taking up the most space.
b) Switching losses can be estimated by assuming a
switching time, If we assume 100ns then:
100ns
PSW = IO × V ×
IN
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of
inductor can be calculated. Too large an inductor will
produce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
TSW
or more generally,
IO × V ×(tr + tf )× fOSC
IN
PSW
=
2
c) Body diode recovery losses are more difficult to estimate,
but to a first approximation, it is reasonable to assume
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SC4612H
POWER MANAGEMENT
Application Information (Cont.)
Low Side RDS_ON Current Limit
that the stored charge on the bottom FET body diode will
be moved through the top FET as it starts to turn on. The
resulting power dissipation in the top FET will be:
PRR = QRR × V ×fOSC
IN
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very little
voltage across it resulting in very low switching losses.
Conduction losses for the FET can be determined by:
PCOND = I2O ×RDS(on) ×(1- D)
INPUT CAPACITORS - Since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra output
capacitance or, more usually, additional input capacitors.
Choosing low ESR input capacitors will help maximize ripple
rating for a given size.
1. Programming resistors Ra and Rb - Not installed:
2.75V - 100mV 100mV - Vphase
=
R3
R2
solving for: VPHASE = -100mV, therefore the circuit will trip @
RDS_ON x ILOAD = 100mV
2. To increase trip voltage - install Ra.
- 772 - 20× VPHASE
Ra =
1+10× VPHASE
solving for double the current limit: VPHASE = -200mV.
Ra = 768kW.
3. To decrease trip voltage - install Rb
8 - 20× VPHASE
Rb =
1+10× VPHASE
solving for half the current limit: VPHASE = -50mV.
Rb = 18kW.
NOTE! Allow for tempco and RDS_ON variation of the MOS-
FET - see “overcurrent protection” information on page 11
in the datasheet.
ã 2008 Semtech Corp.
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SC4612H
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 1: Vin = 24V; Vout = 3.3V @ 20A, Fsw = 500kHz.
+
Vin=24V
C14
470/ 35 V
C15
470/ 35 V
R1
adj
_
U1
D1
MBR0530
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
C1
200 p
DH
BST
DRV
DL
C2
0.1
C8
0.1
C3
3.9n
R2
10k
L1
1.5uH
Q1
Q2
C7
2.2
C4
300 p
+
8
R3
Vout=3.3@20A
1 0
C9
7
C10
C11
C12
C13
VDD
GND
180/ 4V 180/ 4V 180/ 4V 10/ 6.3V
C5
1
_
R5
39.2 k
R4
6.98 k
Fsw=500kHz
C6
750 p
R6
887
Vin=24V, Vout_nom=3.3V, Fsw=500kHz
100%
95%
90%
85%
80%
75%
70%
65%
60%
0
2
4
6
8
10
12
14
16
18
20
Current, (A)
ã 2008 Semtech Corp.
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SC4612H
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 2: Vin = 12V; Vout = 3.3V @ 10A, Fsw = 1MHz
+
Vin=12V
C12
220/ 16 V
R1
adj
_
U1
D1
MBR0520
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
C1
82p
DH
BST
DRV
DL
C2
0.1
C8
0.1
C3
2.7n
R2
13.7 k
L1
1uH
Q1
Q2
C7
2.2
C4
1 n
+
8
R3
1 0
Vout=3.3@10A
C9
7
C10
680/ 4V
C11
1 0
VDD
GND
C5
1
_
R5
21.5 k
R4
3.83 k
Fsw=1000kHz
C6
1.2n
R6
267
Vin=12V, Vout_nom=3.3V, Fsw=1MHz
100%
95%
90%
85%
80%
75%
70%
65%
60%
0
1
2
3
4
5
6
7
8
9
10
Current, (A)
ã 2008 Semtech Corp.
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SC4612H
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 3: Vin = 5V; Vout = 1.25V @ 12A, Fsw = 1MHz.
+
C12
Vin=5V
100 / 6.3V
R1
adj
_
U1
D1
SD107WS
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
C1
82p
DH
BST
DRV
DL
C2
0.1
C8
0.1
C3
1 n
R2
10k
L1
0.47uH
Q1
Q2
C7
2.2
C4
33p
+
8
R3
0
Vout=1.25@12A
C9
7
C10
C11
1
VDD
GND
100/ 4V
C5
1
_
R5
13.3 k
R4
8.87 k
Fsw=1000kHz
C6
510 p
R6
649
Vin=5V, Vout_nom=1.25V, Fsw=1MHz
100%
95%
90%
85%
80%
75%
70%
65%
60%
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Current, (A)
ã 2008 Semtech Corp.
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SC4612H
POWER MANAGEMENT
Application Information (Cont.)
Evaluation Board:
Top layer and components view
Bottom Layer:
ã 2008 Semtech Corp.
18
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SC4612H
POWER MANAGEMENT
PCB Layout Guidelines
Careful attention to layout is necessary for successful
implementation of the SC4612H PWM controller. High
switching currents are present in the application and their
effect on ground plane voltage differentials must be
understood and minimized.
VIN
I (Input Capacitor)
Vout
Ids (Top Fet)
I (Inductor)
Vphase
1) The high power section of the circuit should be laid out
first. A ground plane should be used. The number and
position of ground plane interruptions should not
unnecessarily compromise ground plane integrity. Isolated
or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas; for example, the input capacitor and
bottom FET ground.
+
Vout
I (Output Capacitor)
+
2) The loop formed by the Input Capacitor(s) (Cin), the Top
FET (M1), and the Bottom FET (M2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance.
Minimizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically “cleaner” grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
Ids (Bottom Fet)
Voltage and current waveforms of buck power stage .
3) The connection between the junction of M1, M2 and
the output inductor should be a wide trace or copper region.
It should be as short as practical. Since this connection
has fast voltage transitions, keeping this connection short
will minimize EMI. Also keep the Phase connection to the
IC short. Top FET gate charge currents flow in this trace.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load currents
are supplied by Cout only, and therefore, connections
between Cout and the load must be short, wide copper
areas to minimize inductance and resistance.
5) The SC4612H is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin, M1, M2 loop flowing
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of (one
of) the output capacitor(s). If this is not possible, the GND
pin may be connected to the ground path between the
Output Capacitor(s) and the Cin, M1, M2 loop. Under no
circumstances should GND be returned to a ground inside
the Cin, M1, M2 loop.
6) Allow adequate heat sinking area for the power
components. If multiple layers will be used, provide
sufficent vias for heat transfer.
ã 2008 Semtech Corp.
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SC4612H
POWER MANAGEMENT
Outline Drawing - MLPD - 12
B
E
D
A
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
DIM
A
.031
.040
0.90 1.00
0.80
.035
.001
PIN1
INDICATOR
(LASER MARK)
0.02
0.05
A1 .000
.002 0.00
-
-
-
-
(.008)
(0.20)
A2
b
D
0.25 0.30
.007
.010 .012 0.18
.154 .157 .161 3.90 4.00 4.10
D1
E
.124 .130 .134 3.15
3.40
3.30
.114 .118 .122 2.90 3.00 3.10
1.70
E1
.061
1.80
.067 .071 1.55
A2
C
e
.020 BSC
0.50 BSC
L
N
aaa
0.40
12
.012 .016 .020 0.30
0.50
12
.003
.004
A
SEATING
PLANE
0.08
0.10
aaa C
bbb
A1
D1
D1/2
1 2
E1/2
bxN
E1
LxN
N
bbb
C A B
e
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPD - 12
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.114)
.087
.067
.138
.020
.012
.028
.142
(2.90)
2.20
1.70
3.50
0.50
0.30
0.70
3.60
C
G
H
K
P
X
Y
Z
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
ã 2008 Semtech Corp.
20
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SC4612H
POWER MANAGEMENT
Outline Drawing - SOIC - 14
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
A
DIM
A
D
E
e
-
-
-
-
-
-
-
-
-
-
.053
.069 1.35
.010 0.10
.065 1.25
.020 0.31
.010 0.17
1.75
0.25
1.65
0.51
0.25
N
A1 .004
A2 .049
2X
E/2
b
c
D
.012
.007
.337 .341 .344 8.55 8.65 8.75
E1 .150 .154 .157 3.80 3.90 4.00
E1
E
e
h
L
L1
N
01
aaa
.236 BSC
6.00 BSC
1.27 BSC
.050 BSC
-
-
.010
.020 0.25
0.50
1
2
3
ccc C
2X N/2 TIPS
.016 .028 .041 0.40 0.72 1.04
B
(.041)
14
-
.004
.010
.008
(1.04)
14
-
0.10
0.25
0.20
0°
8°
0°
8°
bbb
ccc
D
aaa C
h
A2 A
SEATING
PLANE
h
C
A1
A-B D
H
bxN
bbb
C
c
GAGE
PLANE
0.25
L
01
(L1)
SEE DETAIL A
DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AB.
Land Pattern - SOIC - 14
X
DIMENSIONS
DIM
INCHES
(.205)
.118
.050
.024
MILLIMETERS
(5.20)
3.00
1.27
0.60
2.20
7.40
C
G
P
X
Y
Z
(C)
G
Y
Z
.087
.291
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 302A.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
ã 2008 Semtech Corp.
21
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相关型号：
SC4620
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