SK10E016PJ [SEMTECH]
8-Bit Synchronous Binary Up Counter; 8位同步二进制计数器
| 型号： | SK10E016PJ |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 8-Bit Synchronous Binary Up Counter |
| 文件： | 总9页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SK10/100E016
8-Bit Synchronous
Binary Up Counter
HIGH-PERꢀORMANCE PRODUCTS
ꢀeatures
Description
The SK10/100E016 is a high-speed synchronous, • 700 MHz Min Count Frequency
presettable, cascadable 8-bit binary counter.
• 1000 ps CLK to Q, TC*
• Internal TC* Feedback (Gated)
The counter features internal feedback of TC*, gated by • 8-Bit
the TCLD (terminal count load) pin. When TCLD is LOW • Fully Synchronous Counting and TC* Generation
(or left open,in which case it is pulled LOW by the internal • Asynchronous Master Reset
pull-downs), the TC* feedback is disabled, and counting • Internal 75 kΩ Input Pulldown Resistors
proceeds continuously, with TC* going LOW to indicate • Extended 100E V Range of –4.2V to –5.46V
EE
an all-one state. When TCLD is HIGH, the TC* feedback • Fully Compatible with MC10/100E016
causes the counter to automatically reload upon TC* = • Available in 28-Pin PLCC Package
LOW, thus functioning as a programmable counter. The • ESD Protection of >4000V
Qn outputs do not need to be terminated for the count
function to operate properly. To minimize noise and
power, unused Q outputs should be left unterminated.
ꢀunctional Block Diagram
8 Bit Binary Counter - Logic Counter
Q0
Q1
Q7
PE
TCLD
QOM
CE*
Q0*
Q1*
SLAVE
CE*
CE*
PO
Q2*
Q3*
Q4*
Q5*
Q6*
MASTER
BIT 1
BIT 7
BIT 0
Q0*
QOM*
P1
P7
MR
CLK
BITS 2-6
TC*
5
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally without incurring a full gate delay.
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SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
PIN Description
Pinout
Function Table
CE* PE* TCLD
MR CLK
ꢀunction
25
24
23
22
21
20
19
MR
CLK
26
27
28
18
17
16
15
14
13
12
X
L
L
X
L
L
L
Z
Z
Load Parallel (P to Q )
n
Q
Q
n
7
H
Continuous Count
6
L
H
H
H
X
L
L
Z
Z
Count; Load Parallel on TC* = LOW
Hold
TCLD
V
CC
H
28 Lead PLCC
V
Masters Respond,
Slaves Hold
EE
1
2
3
4
Q
V
5
X
X
X
X
X
X
L
ZZ
X
(Top View)
NC
Reset (Qn: = LOW,
TC*: = HIGH)
CCO
H
P
0
Q
4
3
P
1
Q
5
6
7
8
9
10
11
Pin Names
Pin
P0 - P7
Q0 - Q7
CE*
ꢀunction
Parallel Data (Preset) Inputs
Data Outputs
Count Enable Control Input
PE*
Parallel Load Enable Control Input
Master Reset
MR
CLK
Clock
TC*
Terminal Count Output
TC-Load Control Input
TCLD
Revision 1/ꢀebruary 13, 2001
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SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
Application Information
Function Table
ꢀunction
PE*
CE*
MR
TCLD CLK P7-P4
P3
P2
P1
P0
Q7-Q4
Q3
Q2
Q1
Q0
TC
Load
L
X
L
L
L
L
X
H
H
L
L
L
L
L
L
L
L
L
L
X
L
L
L
L
X
X
X
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
H
X
H
X
X
X
H
H
X
X
L
H
X
L
X
X
X
L
L
X
X
H
L
X
X
X
L
L
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
L
L
L
L
H
L
H
H
H
L
Count
H
H
H
H
L
X
X
X
X
H
L
H
H
X
H
H
X
H
H
H
H
H
Load
Hold
L
H
H
H
L
X
X
L
Load On
TerminalH
Count
H
H
H
L
L
H
Z
H
L
H
H
L
H
H
H
L
H
H
H
H
H
X
L
L
L
L
X
L
L
L
L
H
H
H
H
H
X
Z
Z
Z
Z
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
X
H
L
H
H
H
L
H
H
H
L
H
L
L
H
H
H
G
L
H
L
H
L
Reset
L
L
L
Cascading Multiple E016 Devices
all of the lower order terminal count outputs must
be in the low state. The bit width of the counter can
be increased or decreased by simply adding or
subtracting E016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same
figure.
For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very
wide bit width counters. The active low terminal count
(TC*) output and count enable input (CE*) greatly
facilitate the cascading of E016 devices. Two E016s
can be cascaded without the need for external gating;
however, for counters wider than 16 bits, external OR
gates are necessary for cascade implementations.
The maximum frequency of operation for the
cascaded counter chain is set by the propagation
delay of the TC* output, the necessary setup time
of the CE* input, and the propagation delay through
the OR gate controlling it (for 16-bit counters the
limitation is only the TC* propagation delay and the
CE* setup time). Figure 3 shows EL01 gates used
to control the count enable inputs; however, if the
frequency of operation is lower, a lower ECL OR gate
can be used. Using the worst case guarantees for
these parameters, the maximum count frequency
for a greater than 16-bit counter is 500 MHz, and
for a 16-bit counter is 625 MHz. Note that this
assumes the trace delay between the TC* outputs
and the CE* inputs are negligible. If this is not the
case, estimates of these delays need to be added
to the calculations.
Figure 3 below illustrates the cascading of 4 E016s to
build a 32-bit high frequency counter. Note that the
E101 gates are used to OR the terminal count outputs
of the lower order E016s to control the counting
operation of the higher order bits. When the terminal
count of the preceding device (or devices) goes low
(the counter reaches an all 1s state), the more
significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition.
In addition, the preceding devices will also count one
bit, sending their terminal count outputs back to a high
state, disabling the count operation of the more
significant counters, and placing them back into hold
modes. Therefore, for an E016 in the chain to count,
Revision 1/ꢀebruary 13, 2001
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SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
Application Information (continued)
LOAD
Q0 Q7
Q0 Q7
Q0 Q7
Q0 Q7
CE*
PE*
CE*
PE*
CE*
PE*
CE*
PE*
E016
LSB
E016
E016
E016
MSB
CLK
TC*
CLK
TC*
CLK
TC*
CLK
TC*
EL01
EL01
P0 P7
P0 P7
P0 P7
P0 P7
CLOCK
Figure 3. 32-Bit Cascaded E016 Counter
Programmable Divider
Pn’s = 256 – 113 = 8F = 1000 1111
16
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider.
The TCLD pin (load on terminal count) when asserted
reloads the data present at the parallel input pin (Pn’s)
upon reaching terminal count (an all 1s state on the
outputs). Because this feedback is built internal to the
chip, the programmable division operation will run at very
nearly the same frequency as the maximum counting
frequency of the device. Figure 4 below illustrates the
input conditions necessary for utilizing the E016 as a
programmable divider set up to divide by 113.
where:
PO = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure
4 will result in the waveforms of Figure 5. Note that
the TC* output is used as the divide output and the
pulse duration is equal to a full clock period. For
even divide ratios, twice the desired divide ratio can
be loaded into the E016, and the TC* output can
feed the clock input of a toggle flip-flop to create a
signal divided as desired with a 50% duty cycle.
H
L
L
L
H
H
H
H
Preset Data Inputs
P7 P6 P5 P4 P3 P2 P1 P0
Divide
Ratio
P7 P6 P5 P4 P3 P2 P1 P0
PE*
CE*
H
L
2
3
H
H
H
H
l
l
H
H
H
l
l
L
H
H
H
H
l
l
L
H
H
H
H
l
l
L
H
H
H
H
l
l
H
L
H
H
H
H
l
l
L
H
H
H
L
H
L
L
H
L
TCLD
CLK
H
4
L
TC*
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
5
H
l
l
L
H
l
l
L
l
l
l
L
l
Figure 4. Mod 2 to 256 Programmable Divider
112
113
114
l
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
L
L
H
H
l
l
L
H
H
l
l
L
H
H
l
l
H
L
H
L
L
L
L
l
l
L
l
l
L
l
l
L
l
l
L
l
254
255
256
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
Revision 1/ꢀebruary 13, 2001
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SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
Application Information (continued)
A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256
are needed, multiple E016s can be cascaded in a
manner similar to that already discussed. When E016s
are cascaded to build larger dividers, the TCLD pin will
no longer provide a means for loading on terminal count.
Because one does not want to reload the counters until
all of the devices in the chain have reached terminal
count, external gating of the TC* pins must be used for
multiple E016 divider chains.
Maximizing E016 Count Frequency
The E016 device produces 9 fast transitioning single-
ended outputs, thus VCC noise can become significant
in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise
can negatively impact the maximum frequency of
operation of the device. Since the device does not
need to have the Q outputs terminated to count properly,
it is recommended that if the outputs are not going to
be used in the rest of the system, they should be
terminated. Not terminating the unused outputs will
not only cut down the VCC noise generated, but will
also save in total system power dissipation. Following
these guidelines will allow designers to either be more
aggressive in their designs or provide them with an
extra margin to the published databook specifications.
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again, to maximize the frequency of
operation, EL01 OR gates were used. For lower
frequency applications, a slower OR gate could replace
the EL01. Note that for a 16-bit divider, the OR function
feeding the PE* (program enable) input CANNOT be
placed by a wire OR tie as the TC* output of the least
significant E016 must also feed the CE* input of the
most significant E016. If the two TC* outputs were OR
tied, the cascaded count operation would not operate
properly. Because, in the cascaded form, the PE*
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
LOAD
1001 0000
1001 0001
1111 1100
1111 1101
1111 1110
1111 1111
LOAD
CLOCK
PE*
TC*
DIVIDE BY 113
Figure 5. Divide by 113 E016 Programmable Divider Waveforms
Revision 1/ꢀebruary 13, 2001
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SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
Application Information (continued)
EL01
Q0 ® Q7
Q0 ® Q7
Q0 ® Q7
Q0 ® Q7
CE*
PE*
CE*
PE*
CE*
PE*
CE*
PE*
E016
LSB
E016
E016
E016
MSB
CLK
TC*
CLK
TC*
CLK
TC*
CLK
TC*
EL01
EL01
P0 ® P7
P0 ® P7
P0 ® P7
P0 ® P7
CLOCK
Figure 6. 32-Bit Cascaded E016 Programmable Divider
Revision 1/ꢀebruary 13, 2001
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6
SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
Package Information
Y BRK
–N–
S
N
S
S
M
B
0.007 (0.180)
T
L - M
D
U
M
S
N
0.007 (0.180)
+
T
L - M
–L–
PIN Descriptions
– M –
Z
D
W
+
0.010 (0.250) T L - M
S
S
N
S
S
G1
X
V
28
1
0.007(0.180)
M
T
L – M
S
N
H
S
S
N
A
R
0.007 (0.180)
0.007 (0.180)
M
M
T
L – M
L – M
Z
S
S
N
T
C
K1
E
0.004 (0.100)
–T– SEATING PLANE
G
J
G1
K
VIEW S
S
S
S
N
0.010 (0.250)
T
L – M
S
0.007 (0.180)
M
T L – M
N
S
F
NOTES:
MILLIMETERS
INCHES
1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.
4. Dimensioning and tolerancing per ANSI Y14.5M,
1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs,
gate burrs and interlead flash, but including any
mismatch between the top and bottom of the plastic
body.
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension to be smaller than 0.025 (0.635).
DIM
A
MIN
MAX
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
0.485
0.485
0.165
0.090
0.013
0.495
0.495
0.180
0.110
0.019
B
C
E
2.29
2.79
ꢀ
0.33
0.48
G
0.050 BSC
0.032
1.27 BSC
H
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
--
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
--
0.81
--
J
--
K
--
--
R
0.456
0.456
0.048
0.048
0.056
0.020
10o
11.58
11.58
1.21
1.21
1.42
0.50
10o
U
V
W
X
Y
Z
2o
2o
G1
K1
0.410
0.040
0.430
--
10.42
1.02
10.92
--
Revision 1/ꢀebruary 13, 2001
7
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SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
DC Characteristics
SK10/100E016 DC Electrical Characteristics (Notes 1, 2)
(V
CC
– V
= 4.2V to 5.5V;V = V
; VOUT Loaded 50Ω to V
– 2.0V)
EE
CC
CCO
CC
TA = –40oC
TA = 0oC
TA = +25oC
TA = +85oC
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
Input HIGH Current
150
150
150
150
µA
IH
Power Supply Current
I
10E
151
151
174
185
151
151
174
185
151
151
174
185
151
151
174
185
mA
mA
EE
100E
AC Characteristics
SK10/100E016 AC Electrical Characteristics
(V
– V
= 4.2V to 5.5V;V = V
; VOUT Loaded 50Ω to V
– 2.0V)
CC
EE
CC
CCO
CC
TA = –40oC
TA = 0oC
TA = +25oC
TA = +85oC
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
Maximum Count ꢀrequency
700
900
700
900
700
900
700
900
MHz
COUNT
Propagation Delay to Output
CLK to Q
726
666
743
656
855
775
775
738
948
876
926
820
726
666
743
656
855
775
775
738
948
876
926
820
726
666
743
656
855
775
775
738
948
876
926
820
726
666
743
656
855
775
775
738
948
876
926
820
ps
ps
ps
ps
t
t
PLH
PHL
MR to Q
CLK to TC*
MR to TC*
Setup Time
Pn
150
600
600
500
-30
400
400
300
150
600
600
500
-30
400
400
300
150
600
600
500
-30
400
400
300
150
600
600
500
-30
400
400
300
ps
ps
ps
ps
t
t
CE*
s
h
PE*
TCLD
Hold Time
Pn
350
0
100
-400
-400
-300
350
0
100
-400
-400
-300
350
0
100
-400
-400
-300
350
0
100
-400
-400
-300
ps
ps
ps
ps
CE*
PE*
0
0
0
0
TCLD
100
100
100
100
t
t
Reset Recovery Time
900
700
900
700
900
700
900
700
ps
RR
Minimum Pulse Width
CLK, MR
PW
400
231
400
231
400
235
400
244
ps
ps
t , t
r
Rise/ꢀall Times (20 - 80%)
306
559
306
559
318
526
330
460
f
Notes:
1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.
2. The same DC parameter values apply across the full VEE range of –4.2 to –5.5V. 100E circuits are
designed to meet the DC specifications shown in the table where transverse airflow greater than 500 lfpm
is maintained.
3. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data Sheet.
4. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
Revision 1/ꢀebruary 13, 2001
www.semtech.com
8
SK10/100E016
HIGH-PERꢀORMANCE PRODUCTS
Ordering Information
Ordering Code
SK10E016PJ
Package ID
28-PLCC
28-PLCC
28-PLCC
28-PLCC
Temperature Range
Industrial
Industrial
Industrial
Industrial
SK10E016PJT
SK100E016PJ
SK100E016PJT
Contact Information
Semtech Corporation
High-Performance Products Division
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
Phone: (858) 695-1808
FAX:
(858) 695-2633
FAX: (408) 727-8994
Revision 1/ꢀebruary 13, 2001
9
www.semtech.com
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