SGM51652H8 [SGMICRO]
16-Bit, 500kSPS, 4- and 8-Channel, Single Supply, SAR ADC with Bipolar Input Ranges;
| 型号： | SGM51652H8 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 16-Bit, 500kSPS, 4- and 8-Channel, Single Supply, SAR ADC with Bipolar Input Ranges |
| 文件： | 总43页 (文件大小：1449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM51652H4/SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel,
Single Supply, SAR ADCs
with Bipolar Input Ranges
GENERAL DESCRIPTION
FEATURES
The SGM51652H4 and SGM51652H8 are 4-channel and
8-channel, 16-bit resolution, high-precision successive
approximation (SAR) analog-to-digital converters (ADCs).
● Supported Input Ranges:
Bipolar Single-Ended Ranges: ±10.24V, ±5.12V, and
±2.56V
Unipolar Single-Ended Ranges: 0V to 10.24V and
0V to 5.12V
These ADCs are powered by a single unipolar 5V, and
support true bipolar ±10.24V, ±5.12V, and ±2.56V inputs, as
well as unipolar input ranges of 0V to 10.24V and 0V to 5.12V.
The input range is configured by software.
Bipolar Differential Ranges: ±10.24V, ±5.12V, and
±2.56V
● Supply Voltage Ranges:
These chips provide over-voltage protection up to ±20V at the
input.
Analog Supply: 5V
I/O Supply: 1.65V to 5V
● On-Chip Reference: 4.096V
These chips have an on-chip high accuracy and low drift
10ppm reference.
● Differential Nonlinearity (DNL): -0.6/+0.9LSB (TYP)
● Integral Nonlinearity (INL): ±1.3LSB (TYP)
● Signal-to-Noise Ratio (SNR): 89.5dB (TYP)
● Total Harmonic Distortion (THD): -99dB (TYP)
● Alarm Features
The input impedance of these chips is ~1MΩ and it is
independent of input range selection.
The digital interface is compatible to the traditional SPI
protocol.
● Daisy-Chain Operation
● -40℃ to +125℃ Operating Temperature Range
● Available in a Green TSSOP-38 Package
APPLICATIONS
Power Automation
Protection Relays
PLC Analog Input Modules
Factory Automation
SG Micro Corp
DECEMBER 2022–REV. A
www.sg-micro.com
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM51652H4
XTS38
SGM51652H4XTS38G-S/TR
Tape and Reel, 500
Tape and Reel, 4000
Tape and Reel, 500
Tape and Reel, 4000
XXXXX
SGM51652H4
TSSOP-38
TSSOP-38
-40℃ to +125℃
-40℃ to +125℃
SGM51652H4
XTS38
SGM51652H4XTS38G/TR
SGM51652H8XTS38G-S/TR
SGM51652H8XTS38G/TR
XXXXX
SGM51652H8
XTS38
XXXXX
SGM51652H8
SGM51652H8
XTS38
XXXXX
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Analog Supply Voltage Range, AVDD
AIN_nP, AIN_nN to AGND (1).............................. -20V to 20V
AIN_nP, AIN_nN to AGND (2).............................. -11V to 11V
AVDD to AGND ................................................... -0.3V to 6V
AUX_INP to AGND............................. -0.3V to AVDD + 0.3V
AUX_INN to AGND............................. -0.3V to AVDD + 0.3V
AGND to DGND............................................. -0.3V to + 0.3V
REFCAP to REFGND or REFIO to REFGND... -0.3V to 5.7V
REFGND to AGND ........................................... -0.3V to 0.3V
DVDD to DGND..............................................-0.3V to AVDD
Digital Input Pins to DGND ................. -0.3V to DVDD + 0.3V
Digital Output Pins to DGND............... -0.3V to DVDD + 0.3V
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
...................................................... 4.75V to 5.25V, 5V (TYP)
Digital Supply Voltage Range, DVDD
...................................................1.65V to AVDD, 3.3V (TYP)
Operating Temperature Range.................... -40℃ to +125℃
OVERSTRESS CAUTION
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
ESD SENSITIVITY CAUTION
HBM (Analog Input Pins: AIN_nP, AIN_nN) ...............±7000V
HBM (Other Pins) ......................................................±2000V
CDM ............................................................................±500V
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
NOTES:
1. AVDD = 5V or offers a low impedance of < 30kΩ.
2. AVDD = floating with an impedance > 30kΩ.
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
2
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
PIN CONFIGURATIONS
SGM51652H4 (TOP VIEW)
SGM51652H8 (TOP VIEW)
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SDI
nCS
SDI
nRST/nPD
DAISY
nCS
2
nRST/nPD
SCLK
SDO
SCLK
3
3
DAISY
SDO
4
4
nREFSEL
DNC
nREFSEL
REFIO
DNC
5
5
REFIO
DVDD
DGND
AGND
AGND
AVDD
AGND
AGND
NC
DVDD
DGND
AGND
AGND
AVDD
AGND
AGND
AIN_5P
AIN_5N
AIN_4P
AIN_4N
AIN_3P
AIN_3N
AIN_2P
AIN_2N
6
6
REFGND
REFGND
REFCAP
AGND
7
7
REFCAP
8
8
AGND
9
9
AVDD
AVDD
10
AUX_INP
10
11
12
13
14
15
16
17
18
19
AUX_INP
AUX_INN
AIN_6P
AIN_6N
AIN_7P
AIN_7N
AIN_0P
AIN_0N
AIN_1P
AIN_1N
SGM51652H4
SGM51652H8
11
AUX_INN
12
NC
13
NC
NC
14
NC
NC
15
NC
NC
16
AIN_0P
AIN_3P
AIN_3N
AIN_2P
AIN_2N
17
AIN_0N
18
AIN_1P
19
AIN_1N
TSSOP-38
TSSOP-38
PIN DESCRIPTION
NAME
PIN
TYPE (1)
FUNCTION
SGM51652H4 SGM51652H8
1
2
SDI
DI
DI
DI
DI
AIO
AI
Serial Data Input.
nRST/nPD
DAISY
Dual-Function Pin: Reset/Power-Down the Device. Active low.
Chain the Serial Data Input in Daisy-Chain Mode.
Active Low. When it is enabled, the internal reference is on.
Internal Reference Output and External Reference Input Pin.
Reference Ground Pin.
3
4
nREFSEL
REFIO
5
6
REFGND
REFCAP
AGND
7
AO
P
ADC Reference Decoupling Capacitor Pin.
Analog Ground.
8
9
AVDD
P
Analog Power Supply.
10
11
AUX_INP
AUX_INN
AI
Positive Auxiliary Input Pin.
AI
Negative Auxiliary Input Pin.
SG Micro Corp
DECEMBER 2022
www.sg-micro.com
3
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
PIN DESCRIPTION (continued)
NAME
PIN
TYPE (1)
FUNCTION
Channel 6 Positive Analog Input.
SGM51652H4 SGM51652H8
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
NC
NC
NC
AIN_6P
AIN_6N
AIN_7P
AIN_7N
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
Channel 6 Negative Analog Input.
Channel 7 Positive Analog Input.
Channel 7 Negative Analog Input.
Channel 0 Positive Analog Input.
Channel 0 Negative Analog Input.
Channel 1 Positive Analog Input.
Channel 1 Negative Analog Input.
Channel 2 Negative Analog Input.
Channel 2 Positive Analog Input.
Channel 3 Negative Analog Input.
Channel 3 Positive Analog Input.
Channel 4 Negative Analog Input.
Channel 4 Positive Analog Input.
Channel 5 Negative Analog Input.
Channel 5 Positive Analog Input.
AIN_0P
AIN_0N
AIN_1P
AIN_1N
AIN_2N
AIN_2P
AIN_3N
AIN_3P
NC
NC
NC
NC
AIN_4N
AIN_4P
AIN_5N
AIN_5P
28, 29,
31, 32
AGND
P
Analog Ground.
30
33
34
35
36
37
38
AVDD
DGND
DVDD
DNC
P
P
Analog Power Supply.
Digital Ground.
P
Digital Power Supply.
‒
Do Not Connect This Pin. Keep it floating.
Serial Data Output.
SDO
DO
DI
DI
SCLK
nCS
Serial Clock Input.
Chip-Select Input Pin. Active low.
NOTE:
1. AI = Analog Input, AO = Analog Output, AIO = Analog Input and Output, DI = Digital Input, DO = Digital Output, DIO = Digital
Input and Output, P = Power Supply.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
4
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
ELECTRICAL CHARACTERISTICS
(AVDD = 5V, DVDD = 3V, VREF = 4.096V (internal), and fSAMPLE = 500kSPS, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Inputs
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
-10.24
-5.12
-2.56
0
10.24
5.12
AIN_nP-AGND Input range = ±0.625 × VREF
Input range = 0 to 2.5 × VREF
2.56
V
(2)
10.24
5.12
(2)
(2)
(2)
Input range = 0 to 1.25 × VREF
Input range = ±2.5 × VREF
0
Absolute Input Voltage Range
-10.24
-5.12
-2.56
10.24
5.12
Input range = ±1.25 × VREF
AIN_nN-AGND Input range = ±0.625 × VREF
2.56
V
V
(2)
Input range = 0 to 2.5 × VREF
Input range = 0 to 1.25 × VREF
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
0
0
-10.24
-5.12
-2.56
0
10.24
5.12
2.56
10.24
5.12
10.24
5.12
2.56
7.5
AIN_nP-AIN_nN
(AIN_nN = AGND)
Or
AIN_nP-AIN_nN
(AIN_nP = AGND)
Input Voltage Range (1)
(Single-Ended Input)
(2)
Input range = 0 to 2.5 × VREF
Input range = 0 to 1.25 × VREF
Input range = ±2.5 × VREF
0
-10.24
-5.12
-2.56
-5.0
AIN_nP-AIN_nN Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
V
V
Input Voltage Range (1)
(Bipolar Differential Input)
(3)
Input range = ±2.5 × VREF
Common Mode
Input Range
(3)
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
TA = +25℃, all input ranges
All input ranges
-2.5
5.0
(3)
-1.2
2.5
Input Impedance
RIN
1
MΩ
Input Impedance Drift
15
ppm/℃
V
IN = 10.24V
7.3
2.8
0.9
With voltage at the
AIN_nP pin = VIN
Input Current
IIN
VIN = 5.12V
VIN = 2.56V
µA
Input Over-Voltage Protection
AVDD = 5V or offers low impedance
< 30kΩ, all input ranges
-20
-11
+20
+11
V
V
Over-Voltage Protection
Voltage
VOVP
AVDD = floating with impedance
> 30kΩ, all input ranges
NOTES:
1. Ideal input range. It does not consider gain and offset error.
2. These two unipolar input ranges are only valid for unipolar single-ended input with AIN_nN = AGND.
3. These input common mode voltage range is guaranteed by design, and tested by limited samples, and not covered by
manufacture testing. When the input common mode voltage exceeds ±100mV, the critical DC and AC performance are not
guaranteed.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
5
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 5V, DVDD = 3V, VREF = 4.096V (internal), and fSAMPLE = 500kSPS, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
System Performance (If without otherwise noted, the following parameters are tested with single-ended input)
Resolution
16
16
Bits
Bits
LSB (4)
No Missing Codes
Differential Nonlinearity
NMC
DNL
-1
-3
-0.6/+0.9
±1.3
2.1
3
TA = +25℃
All bipolar range
Integral Nonlinearity (5)
INL
-5.7
±1.3
5.1
LSB
TA = -40℃ to +125℃
All unipolar range
-3.1/+1.2
TA = +25℃,
±0.07
±0.07
±0.2
±0.14
±0.34
±0.68
±0.16
±0.45
±0.15
±0.15
±0.3
input range = ±2.5 × VREF
TA = +25℃,
input range = ±1.25 × VREF
TA = +25℃,
input range = ±0.625 × VREF
Gain Error
EG
%FSR (6)
TA = +25℃,
input range = 0 to 2.5 × VREF
±0.07
±0.07
±0.05
±0.05
±0.1
TA = +25℃,
input range = 0 to 1.25 × VREF
TA = +25℃,
input range = ±2.5 × VREF
TA = +25℃,
input range = ±1.25 × VREF
Gain Error Matching
(Channel-to-Channel)
TA = +25℃,
input range = ±0.625 × VREF
%FSR
TA = +25℃,
±0.05
±0.05
±0.3
±0.15
±0.15
±2.8
input range = 0 to 2.5 × VREF
TA = +25℃,
input range = 0 to 1.25 × VREF
TA = +25℃,
input range = ±2.5 × VREF
TA = +25℃,
input range = ±1.25 × VREF
±0.3
±2.9
TA = +25℃,
input range = ±0.625 × VREF
Offset Error
EO
±0.3
±3.1
mV
TA = +25℃,
input range = 0 to 2.5 × VREF
±0.3
±2.9
TA = +25℃,
input range = 0 to 1.25 × VREF
±0.3
±2.6
TA = +25℃,
input range = ±2.5 × VREF
±0.5
±2.5
TA = +25℃,
input range = ±1.25 × VREF
±0.5
±2.5
Offset Error Matching
(Channel-to-Channel)
TA = +25℃,
input range = ±0.625 × VREF
±0.5
±2.5
mV
TA = +25℃,
input range = 0 to 2.5 × VREF
±0.5
±2.5
TA = +25℃,
input range = 0 to 1.25 × VREF
±0.5
±2.5
NOTES:
4. LSB = Least significant bit.
5. This is best-fit INL.
6. FSR = Full-scale range.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
6
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 5V, DVDD = 3V, VREF = 4.096V (internal), and fSAMPLE = 500kSPS, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Sampling Dynamics (If without otherwise noted, the following parameters are tested with single-ended input.)
Conversion Time
Acquisition Time
tCONV
tACQ
1000
ns
ns
1000
Maximum Throughput Rate without
Latency
fS
500
kSPS
Dynamic Characteristics (If without otherwise noted, the following parameters are tested with single-ended input.)
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 0 to 2.5 × VREF
Input range = 0 to 1.25 × VREF
84.6
84.4
83.7
80.2
79.7
89.5
89.3
88.4
84.4
84.1
Signal-to-Noise Ratio
(VIN - 0.5dBFS at 1kHz)
SNR
THD
dB
dB
dB
Total Harmonic Distortion (7)
(VIN - 0.5dBFS at 1kHz)
All input ranges
-99
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 0 to 2.5 × VREF
Input range = 0 to 1.25 × VREF
84.0
83.6
83.2
79.4
79.1
89.1
88.9
88
Signal-to-Noise Ratio
(VIN - 0.5dBFS at 1kHz)
SINAD
SFDR
84.2
83.9
Spurious-Free Dynamic Range
(VIN - 0.5dBFS at 1kHz)
All input ranges
101
120
dB
dB
Aggressor channel input is overdriven to
2 × maximum input voltage
Crosstalk Isolation (8)
Aggressor channel input is overdriven to
2 × maximum input voltage
Crosstalk Memory (9)
94
dB
-3dB
-0.1dB
BW-3dB
13
TA = +25℃, all input ranges
TA = +25℃, all input ranges
Small-Signal Bandwidth
kHz
BW-0.1dB
2.1
Auxiliary Channel
Resolution
16
Bits
V
VAUX_INP
VAUX_INN
-
Input Voltage Range
AUX_INP - AUX_INN
AUX_INP
-VREF
+VREF
2.5 -
0.5 × VREF
2.5 -
2.5 +
0.5 × VREF
2.5 +
Operating Input Range
V
AUX_INN
0.5 × VREF
0.5 × VREF
During sampling
75
5
Input Capacitance
CI
pF
During conversion
Input Leakage Current
Differential Nonlinearity
Integral Nonlinearity
Gain Error
IIKG(IN)
DNL
100
nA
LSB
LSB
% FSR
mV
-0.6/+0.9
±1.3
INL
EG(AUX)
EO(AUX)
SNR
±0.08
±0.3
±0.2
±2
TA = +25℃
Offset Error
TA = +25℃
Signal-to-Noise Ratio
Total Harmonic Distortion (7)
Signal-to-Noise + Distortion
VAUX_INP - VAUX_INN = -0.5dBFS at 1kHz
VAUX_INP - VAUX_INN = -0.5dBFS at 1kHz
VAUX_INP - VAUX_INN = -0.5dBFS at 1kHz
VAUX_INP - VAUX_INN = -0.5dBFS at 1kHz
83.2
83.0
88.1
dB
THD
-99.1
87.8
dB
SINAD
SFDR
dB
Spurious-Free Dynamic Range
100.7
dB
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
7
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 5V, DVDD = 3V, VREF = 4.096V (internal), and fSAMPLE = 500kSPS, Full = -40℃ to +125℃, typical values are at TA =
+25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal Reference Output
Decoupling Capacitor on REFIO
Initial Reference Voltage
COUT_REFIO
VREFCAP
100
nF
V
4.093
4.096
4.099
TA = +25℃
Reference Buffer Output
Impedance
Reference Buffer Temperature
Drift
0.5
9
Ω
ppm/℃
Decoupling Capacitor on REFCAP COUT_REFCAP
Turn-On Time
22
25
μF
COUT_REFCAP = 22µF, COUT_REFIO = 100nF
REFIO pin configured as an input
ms
External Reference Input
External Reference Voltage on
VREFIO_EXT
4.046
4.096
4.146
V
REFIO (10)
Power-Supply Requirements
Analog Power-Supply Voltage
AVDD
DVDD
Analog supply
4.75
1.65
2.7
5
3.3
3.3
14.5
11
5.25
AVDD
AVDD
19.5
15.5
15
V
V
Digital supply range
Digital Power-Supply Voltage
Digital supply range for specified performance
SGM51652H8
AVDD = 5V, fS = maximum
and internal reference
Dynamic, AVDD
IAVDD_DYN
IAVDD_STC
ISTDBY
mA
mA
mA
SGM51652H4
AVDD = 5V, device not
converting and internal
reference
AVDD = 5V, device in
STDBY mode and internal
reference
SGM51652H8
SGM51652H4
SGM51652H8
SGM51652H4
10
Static
Analog Supply
Current
5
10.5
12.5
8.5
8.5
4.5
4
Standby
Power-Down
IPWR_DOWN
IDVDD_DYN
AVDD = 5V, device in PWR_DOWN mode
DVDD = 3.3V, output = 0000h
20
μA
Digital Supply Current
0.5
mA
Digital Inputs
0.7 ×
DVDD
DVDD
VIH
VIL
VIH
VIL
Digital Input Logic Levels
Digital Input Logic Levels
DVDD > 2.1V
V
V
0.3 ×
DVDD
0
0.8 ×
DVDD
DVDD
DVDD ≤ 2.1V
0.15 ×
DVDD
0
Input Leakage Current
Input Pin Capacitance
Digital Outputs
100
5
nA
pF
0.8 ×
DVDD
DVDD
VOH
VOL
IO = 100μA source
Digital Output Logic Levels
V
0.2 ×
DVDD
IO = 100μA sink
0
Floating State Leakage Current
Internal Pin Capacitance
Only for SDO
1
5
µA
pF
NOTES:
7. Accumulated the first nine harmonics.
8. A full-scale sinusoidal 10kHz signal is applied to a channel which is not selected in conversion sequence, and measures its
effect on any selected channel.
9. A full-scale sinusoidal 10kHz signal is applied to a channel which is selected in conversion sequence, and measures its effect
on the next selected conversion channel.
10. Limits set by characterization at room temperature only.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
8
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TIMING REQUIREMENTS: SERIAL INTERFACE
(AVDD = 5V, DVDD = 3V, VREF = 4.096V (internal), SDO Load = 20pF, and fSAMPLE = 500kSPS, Full = -40℃ to +125℃, typical
values are at TA = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
500
17
UNITS
Timing Specifications
Sampling Frequency (fCLK = max)
ADC Cycle Time Period (fCLK = max)
Serial Clock Frequency (fS = max)
Serial Clock Time Period (fS = max)
Conversion Time
fS
tS
kSPS
µs
2
fSCLK
tSCLK
t1
MHz
ns
1/fSCLK
1000
13
ns
Delay Time: nCS Falling to Data Enable
Delay Time: Last SCLK Falling to nCS Rising
Delay Time: nCS Rising to SDO Going to 3-State
Timing Requirements
t9
ns
t8
10
15
ns
t12
ns
Acquisition Time
t2
t4
t5
t7
t3
1000
0.4
0.4
30
ns
tSCLK
tSCLK
ns
Clock High Time
0.6
0.6
Clock Low Time
nCS High Time
Setup Time: nCS Falling to SCLK Falling
30
ns
Hold Time: SCLK Falling to (Previous) Data Valid on
SDO
t10
5
ns
Setup Time: SDO Data Valid to SCLK Falling
Setup Time: SDI Data Valid to SCLK Falling
t11
t13
5
5
ns
ns
Hold Time: SCLK Falling to (Previous) Data Valid on
SDI
t14
5
ns
Sample
N+1
Sample N
ts
t2
t1
nCS
t7
t3
1
t4
t6
t8
SCLK
SDO
2
15
16
17
18
31
32
t5
t12
t11
t10
t9
DO15
XX
DO14
XX
DO12
DO1
DO0
t14
t13
DI14
DI1
DI0
XX
DI15
XX
SDI
Figure 1. Serial Interface Timing Diagram
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
9
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS
Input I-V Characteristic
I-V Curve for an Input OVP Circuit (AVDD = 5V)
10
8
20
15
10
5
6
4
2
0
0
-2
-4
-6
-8
-10
-12
-5
Range = ±2.5 × VREF
Range = ±2.5 × VREF
-10
-15
-20
-25
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
-10 -8 -6 -4 -2
0
2
4
6
8
10
-20 -15 -10
-5
0
5
10
15
20
Input Voltage (V)
Input Voltage (V)
Input Current vs. Temperature
Offset Error vs. Temperature across Input Ranges
10
8
0.8
0.6
0.4
0.2
0
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
6
4
2
0
-2
-4
-6
-8
-10
-12
-0.2
-0.4
-0.6
T = -40℃
T = +25℃
T = +125℃
-40 -25 -10
5
20 35 50 65 80 95 110 125
-10 -8 -6 -4 -2
0
2
4
6
8
10
Input Voltage (V)
Temperature (℃)
Typical Histogram for Offset Error Drift
Offset Error vs. Temperature across Channels
12
10
8
0.2
0.1
Range = ±2.5 × VREF
Range = ±2.5 × VREF
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
6
4
CH0, CH1, CH2,
CH3, CH4, CH5,
CH6, CH7
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Offset Drift (ppm/℃)
SG Micro Corp
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DECEMBER 2022
10
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Gain Error vs. Temperature across Input Ranges
Gain Error vs. Temperature across Channels
0.04
0.03
0.02
0.01
0
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0.000
Range = ±2.5 × VREF
Range = 0 to 2.5 × VREF
Range = ±2.5 × VREF
Range = to 1.25 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
CH0, CH1, CH2,
CH3, CH4, CH5,
CH6, CH7
-0.01
-0.02
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
Typical Histogram for Gain Error Drift
Gain Error vs. External Resistance (REXT)
24
20
16
12
8
0.5
0.0
Range = ±2.5 × VREF
-0.5
-1.0
-1.5
-2.0
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
4
0
0
4
8
12
External Resistance (kΩ)
SNR, SINAD, SFDR and THD vs. Temperature (AUX Channel)
16
20
Gain Drift (ppm/℃)
Offset and Gain vs. Temperature (AUX Channel)
108
104
100
96
-94
-0.055
-0.060
-0.065
-0.070
-0.075
-0.080
0.05
fIN = 1kHz
SFDR
-96
0.00
Gain Error
-98
-0.05
-0.10
-0.15
-0.20
-100
-102
-104
-106
THD
92
Offset Error
SNR
88
SINAD
84
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
11
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
SNR vs. Input Frequency
SNR vs. Temperature
90
89
88
87
86
85
84
83
82
81
80
90
89
88
87
86
85
84
83
82
fIN = 1kHz
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
Range = 0 to 1.25 × VREF
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
0
0
0
2000
4000
6000
8000
10000
Input Frequency (Hz)
SINAD vs. Input Frequency
Range = ±2.5 × VREF
SINAD vs. Temperature
90
89
88
87
86
85
84
83
82
81
80
89
88
87
86
85
84
83
82
81
fIN = 1kHz
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
-40 -25 -10
5
20 35 50 65 80 95 110 125
2000
4000
6000
8000
10000
Input Frequency (Hz)
Temperature (℃)
SFDR vs. Input Frequency
SFDR vs. Temperature
120
100
80
60
40
20
0
104
102
100
98
fIN = 1kHz
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
96
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
94
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
92
90
-40 -25 -10
5
20 35 50 65 80 95 110 125
2000
4000
6000
8000
10000
Input Frequency (Hz)
Temperature (℃)
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
12
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD vs. Input Frequency
THD vs. Temperature
-88
-90
-86
-88
fIN = 1kHz
-92
-90
-94
Range = ±2.5 × VREF
-92
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
-96
-98
-94
Range = ±2.5 × VREF
-100
-102
-104
-106
-108
-96
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
-98
-100
-102
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
2000
4000
6000
8000
10000
5000
5000
Input Frequency (Hz)
Temperature (℃)
Memory Crosstalk vs. Input Frequency
Memory Crosstalk vs. Input Frequency for Overrange Inputs
-80
-90
-80
Input = 2 × maximum
input voltage
-90
-100
-110
-120
-130
-140
-100
-110
-120
-130
-140
Range = ±2.5 × VREF
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
0.05
0.5
5
50
500
0.05
0.5
5
50
500
5000
Input Frequency (kHz)
Input Frequency (kHz)
Isolation Crosstalk vs. Input Frequency
Isolation Crosstalk vs. Input Frequency for Overrange Inputs
-80
-90
-80
Range = ±2.5 × VREF
Input = 2 × maximum
input voltage
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
-90
-100
-110
-120
-130
-140
-100
-110
-120
-130
-140
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Range = 0 to 2.5 × VREF
Range = 0 to 1.25 × VREF
0.05
0.5
5
50
500
0.05
0.5
5
50
500
5000
Input Frequency (kHz)
Input Frequency (kHz)
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
13
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
AVDD Current vs. Temperature (fS = 500kSPS)
SGM51652H8
AVDD Current vs. Temperature (fS = 500kSPS)
SGM51652H4
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
2
2
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
AVDD Current vs. Temperature (During Sampling)
SGM51652H8
AVDD Current vs. Temperature (During Sampling)
SGM51652H4
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
AVDD Current vs. Temperature (Standby Mode)
SGM51652H8
AVDD Current vs. Temperature (Standby Mode)
SGM51652H4
12
10
8
12
10
8
6
6
4
4
2
2
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
14
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
AVDD Current vs. Temperature (Power-Down Mode)
SGM51652H8
AVDD Current vs. Temperature (Power-Down Mode)
35
30
25
20
15
10
5
35
30
25
20
15
10
5
SGM51652H4
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
Variation of the Reference Buffer Output (REFCAP)
across Supply and Temperature
Reference Buffer Temperature Drift Histogram
4.102
10
8
AVDD = 5.25V
AVDD = 5V
4.101
4.100
4.099
4.098
4.097
4.096
4.095
4.094
AVDD = 4.75V
6
4
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
REFCAP Drift (ppm/℃)
Temperature (℃)
DC Histogram for Mid-Scale Inputs (±2.5 × VREF
)
DC Histogram for Mid-Scale Inputs (±1.25 × VREF)
25000
20000
15000
10000
5000
0
12000
10000
8000
6000
4000
2000
0
Output Codes
Output Codes
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
DC Histogram for Mid-Scale Inputs (±0.625 × VREF
)
DC Histogram for Mid-Scale Inputs (2.5 × VREF)
16000
14000
12000
10000
8000
6000
4000
2000
0
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
Output Codes
DC Histogram for Mid-Scale Inputs (1.25 × VREF
Output Codes
DC Histogram for Mid-Scale Inputs (AUX Channel)
)
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
25000
20000
15000
10000
5000
0
Output Codes
Typical FFT Plot (±2.5 × VREF
Output Codes
Typical FFT Plot (±1.25 × VREF
)
)
SG Micro Corp
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DECEMBER 2022
16
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Typical FFT Plot (±0.625 × VREF
)
Typical FFT Plot (2.5 × VREF)
Typical FFT Plot (1.25 × VREF
)
Typical INL for All Codes (±2.5× VREF)
Typical INL for All Codes (±1.25× VREF
)
Typical INL for All Codes (±0.625× VREF)
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
17
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Typical INL for All Codes (2.5 × VREF
)
Typical INL for All Codes (1.25 × VREF)
Typical DNL for All Codes (±2.5× VREF
)
Typical DNL for All Codes (±1.25× VREF)
Typical DNL for All Codes (±0.625× VREF
)
Typical DNL for All Codes (2.5× VREF)
SG Micro Corp
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DECEMBER 2022
18
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Typical DNL for All Codes (1.25 × VREF
)
REFCAP Solder Heat Shift Distribution Histogram
35
30
25
20
15
10
5
0
Error Voltage (mV)
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
19
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
Input Floating
Detection
Input block0
1MΩ
OVP
OVP
AIN_0P
AIN_0N
2nd-Order ADC
PGA
LPF
Driver
1MΩ
VBIAS
AIN_1P
AIN_1N
Input block1
Digital Logic
& Interface
nCS
AIN_2P
AIN_2N
Input block2
Input block3
SCLK
SDI
AIN_3P
AIN_3N
SDO
16-Bit
SAR ADC
DAISY
Input Floating
Detection
Input block4
nREFSEl
1MΩ
OVP
AIN_4P
AIN_4N
2nd-Order ADC
LPF
Driver
PGA
Oscillator
nRST/nPD
OVP
1MΩ
VBIAS
REFCAP
REFIO
Input block5
AIN_5P
AIN_5N
AIN_6P
AIN_6N
Input block6
Input block7
4.096V
Reference
AIN_7P
AIN_7N
REFGND
AUX_INP
AUX_INN
SGM51652H4
SGM51652H8
AGND
DGND
Figure 2. Block Diagram
SG Micro Corp
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DECEMBER 2022
20
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION
Overview
The input voltage range is configured by software, and it can
be bipolar ±2.5 × VREF, ±1.25 × VREF, and ±0.625 × VREF or
unipolar 0 to 2.5 × VREF, and 0 to 1.25 × VREF. If there is a
reference voltage of 4.096V (internal or external), then the
input ranges of the device can be configured to bipolar ranges
of ±10.24V, ±5.12V, and ±2.56V, or unipolar ranges of 0V to
10.24V and 0V to 5.12V.
The SGM51652H4 has 4 channels inputs. The SGM51652H8
has 8 channels inputs. They both have a 16-bit 500kSPS
SAR ADC core. The interface is SPI-compatible serial
interface and supports with daisy-chain (DAISY) features.
Analog Inputs
The chip supports bipolar single-ended input, bipolar
Analog Input Impedance
differential input, and unipolar single-ended input.
The input impedance of each channel is ≥ 1MΩ.
When it works in bipolar single-ended input, tie the AIN_nN to
AGND (system ground), the signal applied to AIN_nP can be
bipolar ±2.5 × VREF, ±1.25 × VREF, and ±0.625 × VREF. Another
selection is that tie the AIN_nP to AGNG (system ground), the
signal applied to AIN_nN can be bipolar ±2.5 × VREF, ±1.25 ×
Input Over-Voltage Protection Circuit
The chip has input over-voltage protection (OVP) circuit.
Table 1 shows these characteristics.
V
REF, and ±0.625 × VREF.
Table 1. Input Over-Voltage Protection Limits when AVDD
= 5V (1)
When it works in unipolar single-ended input, tie the AIN_nN
to AGND (system ground), the signal applied to AIN_nP can
Input Condition
(VOVP = ±20V)
ADC
Output
Comments
be unipolar 0 to 2.5 × VREF, and 0 to 1.25 × VREF
.
|VIN| < |VRANGE
|VRANGE| < |VIN| < |VOVP
|VIN| > |VOVP
|
Valid
Work normally.
ADC output is saturated, and
When it works in bipolar differential input, then AIN_nN and
AIN_nP are differential inputs referring to AGND. For each pin,
the absolute voltage referring to AGND must be within the
limited voltage specified in electrical characteristic table, at
the same time, the differential voltage of AIN_nP-AIN_nN
must be compatible with the according input ranges. The
common mode voltage of AIN_nP and AIN_nN are limited in
according input ranges. Please refer to electrical
characteristic table. When the chip works in bipolar
differential input, the valid input ranges are bipolar ±2.5 ×
|
Saturated the internal protection circuits
are on.
|
Saturated This may damage the chip.
NOTE: 1. AGND = 0V, |VRANGE| is the maximum input voltage
for any selected input range, and |VOVP| is the break-down
voltage for the internal OVP circuit. Assume that RS is
approximately 0Ω.
V
REF, ±1.25 × VREF, and ±0.625 × VREF. The illustrative input
In the following condition, the input signal is applied before
analog AVDD is powered on or the input signal is applied and
keep analog AVDD is floating, the input OVP circuits will be
on. And if the input voltage exceeds the |VOVP|, the chip will
be damaged.
signals are shown in Figure 3, as shown in this example, if
input common mode voltage is not 0V, there will be some
dynamic range (ADC conversion code) losing accordingly.
VP-P = -5.12V ~ +5.12V
VIN_P
VIN_MAX = 10.24V
VIN_P
V
P-P = -2.74V ~ +2.74V (MAX)
VCM = 7.5V (MAX)
VIN_P - VIN_N
VCM = AGND = 0V
AGND = 0V
VIN_P - VIN_N
VP-P = -10.24V ~ +10.24V
VCM = AGND = 0V
VP-P = -5.48V ~ +5.48V
VCM = AGND = 0V
OR
VIN_N
VIN_MAX = 10.24V
VIN_N
VCM = 7.5V (MAX)
VP-P = -2.74V ~ +2.74V (MAX)
VCM = AGND = 0V
AGND = 0V
V
P-P = -5.12V ~ +5.12V
NOTE: VCM means common mode voltage. VP-P means peak-to-peak voltage.
Figure 3. Examples of Bipolar Differential ±10.24V Input
SG Micro Corp
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DECEMBER 2022
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
Table 2. Input Range Selection Bits Details
Input Floating Detection Function
The device features an input floating detection function, when
this function is enabled by setting INPUT_FLOATING_
DETECTION_EN register corresponding bit (see Table 16).
Besides setting the INPUT_FLOATING_DETECTION_EN
register, it also needs a pull-down resistor 10MΩ connected
to system ground (AGND), please refer to typical connection
in Figure 4. After setting INPUT_FLOATING_DETECTION
_EN register (see Table 16), the host needs to send the
manual mode command to continuously convert the channel
that needs floating detection. When the detected input is
floating, the corresponding bit in the INPUT_FLOATING_
DETECTION_STATUS register is set to 1 (see Table 17).
After the floating detection is completed, the bit in the
INPUT_FLOATING_DETECTION_EN register is automatically
set to 0 (see Table 16). If the detected input is given an input
signal source later, please repeat the above floating detection
steps. Then the INPUT_FLOATING_ DETECTION_STATUS
register referred bit can be cleared.
RANGE_CHn[3:0]
Analog Input Range
Bit 3
Bit 2
Bit 1
Bit 0
±2.5 × VREF (default)
±1.25 × VREF
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
±0.625 × VREF
(1)
0 to 2.5 × VREF
(1)
0 to 1.25 × VREF
NOTE: 1. These two unipolar input ranges are only valid for
unipolar single-ended input with AIN_nN = AGND.
Multiplexer (MUX)
The maximum throughout data rate of scanning all channels
is 500kSPS. For the SGM51652H4, it means the maximum
data rate per channel is 125kSPS if all 4 channels are
enabled. For the SGM51652H8, it means the maximum data
rate per channel is 62.5kSPS if all 8 channels are enabled.
Please refer to Table 6 for details of auto-scan mode and
manual mode settings.
Note that, to perform a complete input floating detection,
there must be a consecutive 256 times conversions, which
cannot be interrupted by normal input sampling. At same time,
if there is still an input signal at input pin, the input floating
detection will report an untrusted result.
Reference
The chip can be operated with an internal reference or an
external voltage reference.
Programmable Gain Amplifier (PGA)
The chip has a programmable gain amplifier (PGA), and the
PGA gain can be adjusted by setting the RANGE_CHn[3:0] (n
= 0 to 3 or 0 to 7) bits in the configuration register (see the
Channel n Input Range Registers).
AVDD
RFB
AVDD
D1P
ESD
10MΩ
AIN_P
1MΩ
1MΩ
V-
D2P
AVDD
D1n
Input
Source
VOUT
V+
AIN_N
D2n
ESD
RDC
VB
AGND
Figure 4. Input Floating Detection Connection
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
Auxiliary Channel
Device Functional Modes
nRST/nPD (Input)
nRST/nPD is a dual-function pin. The timing of this pin is
shown in Figure 6, and Table 4 explains the usage of this pin.
The chip has a true differential input channel (AUX_INP and
AUX_INN). This AUX channel goes to ADC only through the
MUX. There is no PGA, driver or low pass filter in the AUX
channel.
tPL_RST_PD
The absolute input on AUX_INP and AUX_INN must be 0 to
VREF. The differential input range of VAUX_INP - VAUX_INN is -VREF
nRST/nPD
to +VREF
.
Figure 6. nRST/nPD Pin Timing
ADC Description
The chip output code is in straight-binary format.
Table 4. nRST/nPD Pin Functionality
Condition
Device Mode
40ns < tPL_RST_PD ≤ 100ns The device goes into RESET mode.
FFFFh
8000h
0001h
The device is in RESET mode and has
the possibility to go into PWR_DOWN
mode. Note that this setting is not
100ns < tPL_RST_PD < 400ns
recommended.
The device goes into PWR_DOWN
tPL_RST_PD ≥ 400ns
mode and the program registers are
reset to default value.
The chip can be powered down by pulling nRST/nPD pin for
at least 400ns. And this operation is asynchronous to chip's
operation clock and working status. In power-down mode, the
chip has no response to any digital inputs except operating on
nRST/nPD pin.
1LSB
FSR/2
FSR - 1LSB
NFS
PFS
Analog Input (AIN_nP –AIN_nN)
Figure 5. Device Transfer Function (Straight-Binary
Format)
When chip goes into RESET mode and PWR_DOWN mode,
the program registers are reset to default value.
When the nRST/nPD pin is pulled high again, the chip wakes
up and goes into a default state. To let the chip work correctly,
it must re-configure the program registers accordingly.
Table 3. ADC LSB Values for Different Input Ranges (VREF
= 4.096V)
Positive Negative
Full-Scale Full-Scale
Full-Scale
Range (V)
LSB
(µV)
Input Range
(V)
(V)
-10.24
-5.12
-2.56
0
±2.5 × VREF
±1.25 × VREF
±0.625 × VREF
10.24
5.12
2.56
10.24
5.12
20.48
10.24
5.12
312.5
156.25
78.125
156.25
78.125
(1)
0 to 2.5 × VREF
0 to 1.25 × VREF
10.24
5.12
(1)
0
NOTE: 1. These two unipolar input ranges are only valid for
unipolar single-ended input with AIN_nN = AGND.
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
starts to be shifted out on SDO at the 16th falling edge of
Data Acquisition Example
This section briefly introduces how the chip works and
interfaces with the host controller. Figure 7 shows the timing
marks.
SCLK.
T3: After the 16th falling edge of the SCLK, the chip doesn't
read any more data on SDI. The host controller can read the
ADC result at every falling edge of the SCLK cycle which is
from 17th to 32nd. If there are more SCLK cycles, the SDO is
filled with 0 until next conversion is initiated.
As shown in Figure 7, there are four events T1 ~ T4.
T1: The input signal is sampled at the moment of the nCS
falling edge. The ADC conversion is driven by internal
oscillator clock. The current ADC result is from the input
channel selected by previous data frame. The current SDI
data setting is for the next conversion. The SDO goes low
because of there is no ADC conversion result during the first
16 SCLK cycles.
T4: The host controller stops the data frame by pulling nCS
high. The SDO goes into 3-state until the next data frame
starts.
Daisy-Chain Topology
A typical connection diagram showing multiple devices in
daisy-chain mode is shown in Figure 8. The devices can enter
daisy-chain mode without any special hardware or software
configuration.
T2: The conversion time is 16 SCLK cycles. Therefore, the
maximum SCLK frequency must be compliance with the
timing requirement (which is listed in Electrical Characteristics
table). Otherwise, if the conversion time is not enough, the
ADC conversion result is corrupt. The MSB of ADC result
Sample
N+1
Sample N
T1
T2
T3
T4
nCS
SCLK
SDO
1
2
15
16
17
18
31
32
DO15
XX
DO14
XX
DO1
DO0
DO12
DI14
DI1
DI0
XX
XX
SDI
DI15
Figure 7. Timing Diagram of Device Operation Using the Serial Interface
nCS_H
SCLK_H
SDO_H
SDI
SCLK
nCS
SDI
SCLK
nCS
SDI
SCLK
nCS
EOC/nINT
DAISY
SDO
DAISY
SDO
DAISY
SGM51652H4
SGM51652H8
#1
SGM51652H4
SGM51652H8
#2
SGM51652H4
SGM51652H8
#3
SDO
DGND
SDI_H
Figure 8. Daisy-Chain Connection Schematic
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
A typical timing diagram for three devices connected in
daisy-chain mode is shown in Figure 9.
Continued Operation in the Selected Mode (NO_OP)
If the chip receives a NO_OP command (0x0000), it will follow
the same settings which are already in the program registers.
The previous selected mode can be STDBY, PWR_DOWN,
AUTO_SCAN and MAN_CH_n.
As shown in the example, the three chips are connected in
daisy-chain mode in Figure 9. Each chip samples its
respective signal input on the falling edge of the nCS. At the
first 16 SCLK cycles, SDO outputs keep low. At the second
16 SCLK cycles, each chip outputs its ADC result to SDO,
and receives the data from DAISY pin. On every
subsequence SCLK cycle, the DAISY pin data is shifted in
and stored in internal register, and the chip shifts out the
internal shift register data to its SDO pin. In this example, 16 ×
3 = 48 SCLK cycles are required to shift all data to the tail
chip SDO pin. In total 64 SCLK cycles for all 3 chips to
conversion and shift out all data.
If the NO_OP command (0x0000) occurs during any other
configure operation to the command register, the chip retains
the old settings of the program registers. Then the chip goes
back to IDLE state and waits for a new command.
Frame Abort Condition (FRAME_ABORT)
As shown in Data Acquisition Example section, a complete
command is at least composed of 16 SCLK cycles, and the
command is locked in at the falling of the 16th SCLK. If the
SCLK is not accumulated to 16, the chip keeps waiting and
the nCS must stay low all operation process. If the nCS goes
high before the command transmission is completed, the chip
goes to an invalid state. It will not skip out the invalid condition
until a new proper command is performed.
Device Modes
After power-up, the SGM51652H4 and SGM51652H8 stay in
IDLE state and don’t perform any function until a command
from the host controller.
Sample
Sample
N+1
N
nCS#1
nCS#2
nCS#3
1
16
1
16
1
16
1
16
SCLK#1
SCLK#2
SCLK#3
From Device #1
Conversion N
SDO#1
DAISY#2
From Device #2
Conversion N
From Device #1
Conversion N
SDO#2
DAISY#3
From Device #3
Conversion N
From Device #2
Conversion N
From Device #1
Conversion N
SDO#3
SDI#1
SDI#2
SDI#3
Config
Figure 9. Timing Diagram of Three Devices Connected in Daisy-Chain Mode
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
STANDBY Mode (STDBY)
But the chip doesn't do conversion, thus any conversion data
read back is invalid (more details in Program Register
Read/Write Operation section).
The chip supports a low power consumption standby mode
(STDBY). In STDBY mode, only parts of the circuits are
powered off, and they will take the chip about 20μs to exit the
STDBY mode. After getting out of the STDBY, the chip
program registers retain its customer's setting value.
Figure 11 shows the command AUTO_SCAN or MAN_CH_n
can call the chip out of the STDBY mode. It is valid at the
rising edge of the nCS. It will take the chip about 30μs to fully
be ready to sample and do conversion after exiting STDBY
mode. It is necessary to hold nCS high at least 30μs before a
new data frame starting. On the next nCS falling edge, the
chip samples the input channel which is selected by
MAN_CH_n or the first channel of the AUTO_SCAN mode
sequence (more details refer to Figure 7).
As shown in Figure 10, issuing a STDBY command 0x8200,
the command will be valid and the chip goes into STDBY
mode on the rising edge of nCS. To exit STDBY mode, a valid
command AUTO_SCAN or MAN_CH_n must be issued and it
will be valid on the rising edge of nCS (see Figure 11). In the
STDBY mode, the program registers can be read or written.
Sample
N
Enter STDBY Mode
nCS
1
1
16
17
18
24
32
SCLK
SDI
If Write or Read Program Register
Data of Program Register
0x8200
Do Not Care
SDO
Do Not Care
Data of Sample N
Figure 10. Timing Diagram for Entering and Remaining in STDBY Mode
Exit STDBY Mode
New Sample by MAN_CH_n or AUTO_SCAN
nCS
t7
1
1
16
32
SCLK
SDI
AUTO_SCAN or MAN_CH_n
NO_OP
SDO
Do Not Care
Data of Conversion
Figure 11. Timing Diagram for Exiting STDBY Mode
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
Power-Down Mode (PWR_DOWN)
edge of nCS (See Figure 13). Being in the PWR_DOWN
mode, the program registers can be read or written. But the
chip doesn't do conversion, thus any conversion data read
back is invalid (more details in Program Register Read/Write
Operation section).
The chip supports both software and hardware power-down
mode (PWR_DOWN). The hardware power-down mode is
talked in the nRST/nPD section. When the chip is waked up
from software power-down, all previous settings of program
registers are retained. When the chip is waked up from
hardware power-down mode, all the registers are reset to
default values. It will take the chip about 15ms to fully power
up and ready to work after receiving wake up command
(AUTO_SCAN or MAN_CH_n).
Figure 13 shows the command AUTO_SCAN or MAN_CH_n
can call the chip out of the PWR_DOWN mode. It is valid at
the rising edge of the nCS. It will take the chip about 15ms to
fully be ready to sample and do conversion after exiting
PWR_DOWN mode. It is necessary to hold nCS high at least
15ms before a new data frame starting. On the next nCS
falling edge, the chip samples the input channel which is
selected by MAN_CH_n or the first channel of the
AUTO_SCAN mode sequence (more details refer to Figure
8).
As shown in Figure 12, issuing a PWR_DOWN command
0x8300, the command will be valid and the chip goes into
PWR_DOWN mode on the rising edge of nCS. To exit
PWR_DOWN mode, a valid command AUTO_SCAN or
MAN_CH_n must be issued and it will be valid on the rising
To enter PWR_DOWN mode,
nCS can go high after 16th SCLK
Sample
Enter PWR_DOWN Mode
N
if does not want read data.
nCS
1
1
16
17
18
24
32
SCLK
SDI
If Write or Read Program Register
Data of Program Register
0x8300
Do Not Care
SDO
Do Not Care
Data of Sample N
Figure 12. Timing Diagram for Entering and Remaining in PWR_DOWN Mode
Exit PWR_DOWN Mode
New Sample by MAN_CH_n or AUTO_SCAN
nCS
15ms
1
1
16
32
SCLK
SDI
AUTO_SCAN or MAN_CH_n
NO_OP
SDO
Do not care
Data of Conversion
Figure 13. Timing Diagram for Exiting PWR_DOWN Mode
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
Auto Channel Enable with Reset (AUTO_SCAN)
In Figure 14, if a chip is set to work in AUTO_SCAN (0xA000)
mode, it can scan all selected channels automatically. In
order to read every selected channel conversion result
correctly, each of the data frame must be at least 32 SCLK
cycles.
channels in ascending order from the lowest channel. When it
scans all channels, it will repeat the cycle from the lowest
channel. The input range of each channel can be configured
separately in the Range Select Registers.
An example is shown in Figure 15, during the AUTO_SCAN
operation sequence, if an AUTO_SCAN command is inserted,
the chip re-starts scanning from the lowest selected channel.
Figure 14 shows a scan sequence from channel 1 to channel
4 and an AUTO_SCAN command is inserted after channel 3
conversion.
The selected channels which the chip goes through in
AUTO_SCAN mode is configured by the program register
0x01 and register 0x02 (please see the Program Register
Map section). In this mode, the chip goes through all selected
After AUTO_SCAN command,
nCS can go high after 16th SCLK
if does not want read data.
Enter AUTO_SCAN Mode
Sample 1st Selected Channel
In AUTO_SCAN Mode
Sample 2nd Selected Channel
Sample
N
nCS
1
1
16
17
18
16
17
18
32
32
SCLK
SDI
0xA000
Do Not Care
0x0000
Do Not Care
Data of 1st Selected Channel
SDO
Do Not Care
Do Not Care
Data of Sample N
Figure 14. Timing Diagram for Entering AUTO_SCAN Mode
Sample N
Channel 1 Sample
Channel 2 Sample
Channel 3 Sample
Channel 1 Sample
nCS
1
16 17
32
1
1617
32
1
16 17
32
1
16 17
32
1
1617
32
SCLK
SDI
AUTO_SCAN
xxxx
0x0000
0x0000
xxxx
0x0000
0x0000
AUTO_SCAN
xxxx
0x0000
0x0000
xxxx
xxxx
Sample N Data
Ch 1 Data
Ch 2 Data
0x0000
Ch 3 Data
Ch 1 Data
SDO
Previous XX Mode
AUTO_SCAN Mode
Channel 1 to Channel 4 are scanned in sequence
AUTO_SCAN Mode
Data of Sample N
Channel scan sequence re-started
Figure 15. Example of Device Operation in AUTO_SCAN Mode
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
An example is shown in Figure 17, if there is no other new
valid command, the chip will keep sampling the current
channel selected by MAN_CH_n. The input range of each
channel can be configured separately in the Range Select
Registers. Figure 17 shows an example MAN_CH_3 to
MAN_CH_1 in manual select mode.
Manual Channel n Select (MAN_CH_n)
As shown in Figure 16, the chip can work in manual channel
mode (MAN_CH_n) and do conversion in a specified channel
by manual mode command. In order to read every selected
channel conversion result correctly, each of the data frame
must be at least 32 SCLK cycles. Refer to Table 5 for a list of
commands of MAN_CH_n mode.
Enter MAN_CH_n Mode
Sample
In MAN_CH_n Mode
1
st Selected Channel n
Sample 2nd Selected Channel n
Sample
N
nCS
1
1
16
17
18
16
17
18
32
32
SCLK
SDI
MAN_CH_n Command
Do Not Care
Do Not Care
0x0000
Do Not Care
SDO
Do Not Care
Data of Sample N
Data of Selected Channel n
Figure 16. Timing Diagram for Entering MAN_CH_n Scan Mode
Sample N
Channel 3 Sample
Channel 3 Sample
Channel 3 Sample
Channel 1 Sample
nCS
SCLK
SDI
1
16 17
32
1
1617
32
1
16 17
32
1
16 17
32
1
1617
32
MAN_CH_3
xxxx
0x0000
0x0000
xxxx
0x0000
0x0000
MAN_CH_1
xxxx
0x0000
0x0000
xxxx
xxxx
Sample N Data
Ch 3 Data
Ch 3 Data
0x0000
Ch 3 Data
Ch 1 Data
SDO
Previous XX Mode
MAN_CH_n Mode
Channel n is continuously sampled if no new command is input
MAN_CH_n Mode
Data of Sample N
Channel switched from 3 to 1
Figure 17. Example of Device Operation in MAN_CH_n Mode
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
Channel Sequencing Modes
selected channel is sampled in the next data frame. Figure 18
shows an example channel sequence switching from
AUTO_SCAN (channel 2, 3, 5 are selected) to MAN_CH_n
(MAN_CH_4).
The chip supports two kinds of channel sequence modes,
auto channel scanning (AUTO_SCAN) and manual channel
selection (MAN_CH_n).
In AUTO_SCAN mode, the chip goes through all selected
channels in ascending order from the lowest channel.
Figure 19 shows an example channel sequence switching
from MAN_CH_n (MAN_CH_5) to AUTO_SCAN (channel 2,
3, 5 are selected). A new command is executed in the next
operation frame.
In MAN_CH_n mode, the chip samples the same input
channel if there is no new command input. If a new input
channel is selected by MAN_CH_n command, then the new
Sample N
Channel 2 Sample
Channel 3 Sample
Channel 5 Sample
Channel 4 Sample
nCS
SCLK
SDI
1
16 17
32
1
1617
32
1
16 17
32
1
16 17
32
1
1617
32
AUTO_SCAN
xxxx
0x0000
0x0000
xxxx
0x0000
0x0000
xxxx
MAN_CH_4
xxxx
0x0000
0x0000
xxxx
Sample N Data
Ch 2 Data
Ch 3 Data
0x0000
Ch 5 Data
Ch 4 Data
SDO
Previous XX Mode
Data of sample N
AUTO_SCAN Mode
Channel2, 3, 5 are selected
MAN_CH_n Mode
Figure 18. Transitioning from AUTO_SCAN to MAN_CH_n Mode
Channel 4 Sample
Channel 2 Sample
Channel 3 Sample
Channel 5 Sample
Sample N
nCS
SCLK
SDI
1
16 17
32
1
1617
32
1
16 17
32
1
16 17
32
1
1617
32
MAN_Ch_4
xxxx
AUTO_SCAN
xxxx
0x0000
0x0000
xxxx
MAN_CH_4
xxxx
0x0000
0x0000
xxxx
Sample N Data
0x0000
Ch 4 Data
Ch 2 Data
0x0000
Ch 3 Data
Ch 5 Data
SDO
Previous XX Mode
Data of Sample N
AUTO_SCAN Mode
Channel 2, 3, 5 are selected
MAN_CH_n Mode
Figure 19. Transitioning from MAN_CH_n to AUTO_SCAN Mode
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
Reset Program Registers (RST)
Step1: Change to manual mode, and selected target channel
n by MAN_CH_n command.
The chip supports both hardware and software reset (RST
command 0x8500). In both cases, all program registers are
reset to default values. The hardware reset is explained in
nRST/nPD section.
Step2: Write 0x80 to INPUT FLOATING_DETECTION_EN
Register (address is 0x0D, see Table 16).
Step3: Perform consecutive 256 times of conversions. Note
that, to perform a complete input floating detection, there
must be a consecutive 256 times conversions, it can’t be
interrupted by normal input sampling. At same time, if there is
still an input signal at input pin, the input floating detection will
report an untrusted result.
As shown in Figure 20, a valid RST command can be issued
during any data frame. After receiving the RST command, the
chip reset all program registers on the rising edge of nCS. In
the RESET mode, the program registers can be read or
written. But the chip doesn't do conversion, thus any
conversion data read back is invalid (more details in Program
Register Read/Write Operation section).
Step4: Read INPUT FLOATING_DETECTION_STATUS
Register (address is 0x0E, see Table 17). Note that the alarm
bit in INPUT_FLOATING_DETECTION_STATUS register will
not be cleared, until an input floating detection operation is
performed again and the inputs of ADC are connected with an
input signal source.
An AUTO_SCAN command or a MAN_CH_n command can
call the chip out of RESET mode. To initiate a conversion on
a particular analog channel, a valid AUTO_SCAN or
MAN_CH_n command must be executed using the default
program register settings.
For an example operation sequences of channel 1, please
refer to Figure 23.
Input Floating Detection Function Operating
Sequences
The device provides a function to detect input floating. To
perform this function, it is necessary to follow the operations
as bellow.
Sample
N
Enter RST mode, all program registers
are reset to default value.
To enter RST mode, nCS can go high after
16th SCLK if does not want read data.
nCS
1
1
16
17
18
24
32
SCLK
SDI
If Write or Read Program Register
Data of Program Register
0x8500
Do Not Care
Do Not Care
Data of Sample N
SDO
Figure 20. Timing Diagram of Reset Program Registers (RST)
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
DETAILED DESCRIPTION (continued)
MAN_CH_n
Command
Enable Floating
Detection Reg
Read
Sample
1st
Sample
256th
Floating Status REG
nCS
SCLK
SDI
1
16 17
32
1
1617
32
1
16 17
32
1
16 17
32
1
1617
32
MAN_CH_1
xxxx
xxxx
0x1B80
0x0000
xxxx
0x0000
xxxx
0x0000
0x0000
xxxx
0x1Cxx
0x0000
xxxx
0x80xx
0x0000
1st Data
256th Data
Ch 1 Status
SDO
Channel 1
Enable of
INPUT_FLOATING_DETETION_EN
Data of
Manual Scan Mode
INPUT_FLOATING_DETETION_
STATUS
Figure 21. Input Floating Detection Operating Sequences
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS
The SGM51652H4 and SGM51652H8 have two kinds of
internal registers, command registers and program registers.
sequence, SDO output format, and input range settings of
each individual channels.
The command registers are listed in Table 5. They are used
for working modes setting, including AUTO_SCAN,
MAN_CH_n, STDBY, PWR_DOWN and RST.
Command Register Description
The command register is a 16-bit, write-only register which is
used for setting SGM51652H4/SGM51652H8 working
modes.
The program registers are listed in Table 8. They are used for
working conditions setting, including channels scanning
Table 5. Command Register Maps
MSB Byte
Register
LSB Byte
Command
Operation in Next Frame
(Hex)
B15 B14 B13 B12 B11 B10 B9
B8
0
B[7:0]
Continued Operation
Repeat operation in previous
mode
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0000 0000
0000 0000
0000 0000
0000h
8200h
8300h
(NO_OP)
Standby (STDBY)
0
Go to standby mode
Power-Down
1
Go to power-down mode
(PWR_DOWN)
Reset program registers
(RST)
Auto Ch. Sequence with
Reset (AUTO_SCAN)
Manual Ch 0 Selection
(MAN_Ch_0)
Manual Ch 1 Selection
(MAN_Ch_1)
Manual Ch 2 Selection
(MAN_Ch_2)
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
8500h
A000h
C000h
C400h
C800h
CC00h
D000h
D400h
D800h
DC00h
E000h
Reset program register
Auto mode enabled following a
reset
Select channel 0
Select channel 1
Select channel 2
Select channel 3
Select channel 4
Select channel 5
Select channel 6
Select channel 7
Select AUX channel
Manual Ch 3 Selection
(MAN_Ch_3)
Manual Ch 4 Selection
(MAN_Ch_4) (1)
Manual Ch 5 Selection
(MAN_Ch_5) (1)
Manual Ch 6 Selection
(MAN_Ch_6) (1)
Manual Ch 7 Selection
(MAN_Ch_7) (1)
Manual AUX Selection
(MAN_AUX)
NOTE: 1. Only for the SGM51652H8.
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DECEMBER 2022
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS (continued)
Program Register Description
Table 7. The data bit DB[15:9] is register address. The data
bit DB[8] is write or read instruction bit.
The program registers are 16-bit, write and read available
registers which are used for setting SGM51652H4/
SGM51652H8 working condition setting.
In a writing cycle, data on SDI pin DIN[7:0] is the data to be
written to the target register. The data on SDO pin DIN[7:0] is
the data readback from the target register. The readback data
can be used to verify whether the writing is successful. An
example timing diagram of writing cycle is shown in Figure
22.
The program registers are listed in Table 8. They are used for
working conditions setting, including channels scanning
sequence in AUTO_SCAN mode, set chip ID in daisy chain
mode, SDO output format, and input range settings of each
individual channels.
In a reading cycle, the SDI data bit DB[8] is read instruction
bit. The data on SDO DOUT[7:0] is the readback data from
the target address program register. The readback data is
MSB first. An example timing diagram of reading cycle is
shown in Figure 23.
Program Register Read/Write Operation
The program register is a 16-bit read and write available
register. The operation data frame must be at least 24 SCLK
cycles. The operation data format is shown in Table 6 and
Table 6. Write Cycle Command Word
Write/Read
Data (DB[7:0])
(DB[8])
Pin
Register Address (DB[15:9])
SDI
ADDR[6:0]
1
DIN[7:0]
Table 7. Read Cycle Command Word
Write/Read
(DB[8])
Pin
SDI
Register Address (DB[15:9])
Data (DB[7:0])
XXXXX
ADDR[6:0]
0
0000
000
SDO
0
DOUT[7:0]
Sample N
nCS
1
8
9
10
24
17
16
SCLK
SDI
WR
DIN[7:0]
DB[15:9] = ADDR[6:0]
Do Not Care
Do Not Care
Data of Target Program Register
DIN[7:0]
SDO
Do Not Care
Figure 22. Timing Diagram of Program Register Write Cycle
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34
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS (continued)
Sample N
nCS
1
8
9
10
24
17
16
SCLK
SDI
RD
Do Not Care
Do Not Care
DB[15:9] = ADDR[6:0]
Do Not Care
Do Not Care
Data of Target Program Register
DOUT[7:0]
SDO
Figure 23. Timing Diagram of Program Register Read Cycle
Program Register Map
Table 8. Program Register Map
Register
Default
Value
Register
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits[15:9]
Auto Scan Sequencing Control
AUTO_SEQ_EN
01h
02h
FFh
00h
CH7_EN (1)
CH7_PD (1)
CH6_EN CH5_EN CH4_EN CH3_EN CH2_EN CH1_EN CH0_EN
CH6_PD CH5_PD CH4_PD CH3_PD CH2_PD CH1_PD CH0_PD
Channel Power-Down
Device Features Selection Control
Feature Select
03h
00h
DEV[1:0]
0
0
0
SDO[2:0]
Range Select Registers
Channel 0 Input Range
Channel 1 Input Range
Channel 2 Input Range
Channel 3 Input Range
05h
06h
07h
08h
00h
00h
00h
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Range Select Channel 0 [3:0]
Range Select Channel 1 [3:0]
Range Select Channel 2 [3:0]
Range Select Channel 3 [3:0]
Channel 4 Input
09h
0Ah
0Bh
0Ch
00h
00h
00h
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Range Select Channel 4 [3:0]
Range Select Channel 5 [3:0]
Range Select Channel 6 [3:0]
Range Select Channel 7 [3:0]
Range(1)
Channel 5 Input
Range(1)
Channel 6 Input
Range(1)
Channel 7 Input
Range(1)
Command Read Back (Read-Only)
Command Read Back 3Fh
00h
COMMAND_WORD[7:0]
Input Floating Detection and Status
INPUT_
FLOATING_
DETECTION_
EN
INPUT_FLOATING_
0Dh
00h
00h
0
0
0
0
0
0
0
DETECTION_EN
INPUT_FLOATING_
0Eh
CH7_FT (1)
CH6_FT CH5_FT CH4_FT CH3_FT CH2_FT CH1_FT CH0_FT
DETECTION_STATUS
NOTE:
1. All the operations of channel 7 to channel 4 are not applicable to the 4-channel version chip. A write operation on any of these
bits or registers has no effect on chip behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS (continued)
Auto-Scan Sequence Enable Register (Address = 01h)
The default value for this register is 0xFF. If no channels are
included in the auto sequence (that is, the value for this
register is set to 0x00), then channel 0 is selected for
conversion by default.
Program Register Descriptions
Auto-Scan Sequencing Control Registers
In AUTO_SCAN mode, the chip scans all the enabled
channels in ascending order automatically. Each of all
channels can be separately enabled or disabled. All the
disabled channels can be powered down in the Power-Down
register individually (details see Table 10).
Table 9. AUTO_SEQ_EN Register Details
BITS
BIT NAME
DEFAULT TYPE (2)
DESCRIPTION
0 = Channel 7 is not enabled in AUTO_SCAN mode
1 = Channel 7 is enabled in AUTO_SCAN mode (default)
D[7]
CH7_EN (1)
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = Channel 6 is not enabled in AUTO_SCAN mode
1 = Channel 6 is enabled in AUTO_SCAN mode (default)
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CH6_EN (1)
CH5_EN (1)
CH4_EN (1)
CH3_EN
0 = Channel 5 is not enabled in AUTO_SCAN mode
1 = Channel 5 is enabled in AUTO_SCAN mode (default)
0 = Channel 4 is not enabled in AUTO_SCAN mode
1 = Channel 4 is enabled in AUTO_SCAN mode (default)
0 = Channel 3 is not enabled in AUTO_SCAN mode
1 = Channel 3 is enabled in AUTO_SCAN mode (default)
0 = Channel 2 is not enabled in AUTO_SCAN mode
1 = Channel 2 is enabled in AUTO_SCAN mode (default)
CH2_EN
0 = Channel 1 is not enabled in AUTO_SCAN mode
1 = Channel 1 is enabled in AUTO_SCAN mode (default)
CH1_EN
0 = Channel 0 is not enabled in AUTO_SCAN mode
1 = Channel 0 is enabled in AUTO_SCAN mode (default)
CH0_EN
NOTES:
1. All the operations of channel 7 to channel 4 are not applicable to the 4-channel version chip. A write operation on any of these
bits or registers has no effect on chip behavior. A read operation on any of these bits or registers outputs all '1' on the SDO line.
2. R/W = Read/Write.
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS (continued)
Channel Power-Down Register (Address = 02h)
In MAN-Ch_n mode, if the selected channel is powered down,
the data output of the corresponding ADC channel is invalid,
and it can also trigger a false alarm condition.
The default value of this register is 0x00.
In AUTO_SCAN mode, if all the channels are powered down
(the value for this register is set to 0xFF), the output data of
the ADC is invalid.
Table 10. Channel Power-Down Register Details
BITS
BIT NAME
DEFAULT
TYPE
DESCRIPTION
0 = Channel 7 is not powered down (2) (default)
1 = Channel 7 is powered down
D[7]
CH7_PD (1)
0
R/W
0 = Channel 6 is not powered down (default)
1 = Channel 6 is powered down
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CH6_PD(1)
CH5_PD(1)
CH4_PD(1)
CH3_PD
CH2_PD
CH1_PD
CH0_PD
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = Channel 5 is not powered down (default)
1 = Channel 5 is powered down
0 = Channel 4 is not powered down (default)
1 = Channel 4 is powered down
0 = Channel 3 is not powered down (default)
1 = Channel 3 is powered down
0 = Channel 2 is not powered down (default)
1 = Channel 2 is powered down
0 = Channel 1 is not powered down (default)
1 = Channel 1 is powered down
0 = Channel 0 is not powered down (default)
1 = Channel 0 is powered down
NOTES:
1. All the operations of channel 7 to channel 4 are not applicable to the 4-channel version chip. A write operation on any of these
bits or registers has no effect on chip behavior. A read operation on any of these bits or registers outputs all '1' on the SDO line.
2. A channel is not powered down, if this channel is supposed to be scanned in AUTO_SCAN sequence, it is necessary to enable
the corresponding bit in AUTO_SEQ_EN Register at same time.
SG Micro Corp
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS (continued)
Device Features Selection Control Register (Address = 03h)
This register is used for the chip ID setting in daisy chain connection and the output data format.
Table 11. Feature Select Register Details
BITS
BIT NAME
DEFAULT
TYPE
DESCRIPTION
Device ID Bits
00 = ID for device 0 in daisy-chain mode (default)
01 = ID for device 1 in daisy-chain mode
10 = ID for device 2 in daisy-chain mode
11 = ID for device 3 in daisy-chain mode
D[7:6]
DEV[1:0]
00
R/W
D[5:3]
D[2:0]
Reserved
SDO[2:0]
000
000
R (1)
R/W
Must be set to 0.
Setting output data format on SDO pin. Refer to Table 12.
NOTE: 1. R = Read only.
Table 12. Program Register Bits Description for SDO Data Format
Output Format
Bits D[8:5]
SDO Format
SDO[2:0]
Beginning of the Output Bit
Stream
Bits D[24:9]
Bits D[4:3]
Bits D[2:0]
Conversion result for selected
channel (MSB-first)
000
001
010
011
16th SCLK falling edge, no latency
16th SCLK falling edge, no latency
16th SCLK falling edge, no latency
16th SCLK falling edge, no latency
SDO pulled low
Conversion result for selected
channel (MSB-first)
Channel address (1)
Channel address (1)
Channel address (1)
SDO pulled low
Conversion result for selected
channel (MSB-first)
Device
SDO pulled
low
address (1)
Conversion result for selected
channel (MSB-first)
Device
Input range (1)
address (1)
NOTE: 1. Table 3 lists descriptions for these channel addresses, chip address, and input range.
Table 13. SDO Data Bit Description
BITS
DESCRIPTION
D[24:9]
16 bits of conversion result for the channel represented in MSB-first format.
Four Bits of Channel Address
0000 = Channel 0
0001 = Channel 1
0010 = Channel 2
D[8:5]
0011 = Channel 3
0100 = Channel 4 (valid only for the SGM51652H8)
0101 = Channel 5 (valid only for the SGM51652H8)
0110 = Channel 6 (valid only for the SGM51652H8)
0111 = Channel 7 (valid only for the SGM51652H8)
D[4:3]
D[2:0]
Two bits of device address (mainly useful in daisy-chain mode).
Three LSB bits of input voltage range (refer to the Range Select Registers section).
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SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS (continued)
Range Select Registers (Addresses 05h - 0Ch)
channel 6, address 0Ch is range setting for channel 7,
address 0Ch is range setting for channel 7.
Address 05h is range setting for channel 0, address 06h is
range setting for channel 1, address 07h is range setting for
channel 2, address 08h is range setting for channel 3,
address 09h is range setting for channel 4, address 0Ah is
range setting for channel 5, address 0Bh is range setting for
Each channel input range can be selected by these registers
individually. (n = 0 to 3 for the SGM51652H4 and n = 0 to 7 for
the SGM51652H8). The default value of these registers is
00h.
Table 14. Channel n Input Range Register Details
BITS
BIT NAME
DEFAULT
TYPE
DESCRIPTION
D[7:4]
Reserved
0000
R
Must always be set to 0.
Input Range Selection Bits for Channel n
(n = 0 to 3 for the SGM51652H4 and n = 0 to 7 for the SGM51652H8)
0000 = Input range is set to ±2.5 × VREF (default)
0001 = Input range is set to ±1.25 × VREF
D[3:0]
RANGE_CHn[3:0]
0000
R/W
0010 = Input range is set to ±0.625 × VREF
0101 = Input range is set to 0 to 2.5 × VREF
0110 = Input range is set to 0 to 1.25 × VREF
Command Read-Back Register (Address = 3Fh)
command word on SDO is 8-bit MSB first format plus 8-bit '0'
This register reports the chip current working mode. If this
register is read, the chip feedback the previous command
word executed in previous data frame. The feedback
(see Table 15). It starts from the 16th falling edge of SCLK. A
32 SCLK cycles operation is not necessary, 24 SCLK cycles
are enough.
Table 15. Command Read-Back Register Details
BITS
BIT NAME
DEFAULT
TYPE
DESCRIPTION
0000
0000
D[7:0] COMMAND_WORD[15:8]
R
Command Executed in Previous Data Frame
SG Micro Corp
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DECEMBER 2022
39
SGM51652H4
SGM51652H8
16-Bit, 500kSPS, 4- and 8-Channel, Single-Supply,
SAR ADCs with Bipolar Input Ranges
REGISTER MAPS (continued)
Input Floating Detection and Status (Address = 0Dh - 0Eh)
Table 16. INPUT_FLOATING_DETECTION_EN Register Details (Address = 0Dh)
BITS
BIT NAME
DEFAULT TYPE
DESCRIPTION
Floating Detection Enable
0 = Disable FLOATING_DETECTION mode (default)
1 = Enable FLOATING_DETECTION mode
After the floating detection is completed, this bit is automatically set to 0.
D[7] INPUT_FLOATING_DETECTION_EN
0
R/W
R
D[6:0]
Reserved
Reserved.
Table 17. INPUT_FLOATING_DETECTION_STATUS Register Details (Address = 0Eh)
BITS
BIT NAME
DEFAULT
TYPE
DESCRIPTION
Channel 7 FLOATINT_STATUS
0 = Channel 7 is not in FLOATING status (default)
1 = Channel 7 is in FLOATING status
D[7]
CH7_FT (1)
0
R/W
Channel 6 FLOATINT_STATUS
0 = Channel 6 is not in FLOATING status (default)
1 = Channel 6 is in FLOATING status
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CH6_FT (1)
CH5_FT (1)
CH4_FT (1)
CH3_FT
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel 5 FLOATINT_STATUS
0 = Channel 5 is not in FLOATING status (default)
1 = Channel 5 is in FLOATING status
Channel 4 FLOATINT_STATUS
0 = Channel 4 is not in FLOATING status (default)
1 = Channel 4 is in FLOATING status
Channel 3 FLOATINT_STATUS
0 = Channel 3 is not in FLOATING status (default)
1 = Channel 3 is in FLOATING status
Channel 2 FLOATINT_STATUS
0 = Channel 2 is not in FLOATING status (default)
1 = Channel 2 is in FLOATING status
CH2_FT
Channel 1 FLOATINT_STATUS
0 = Channel 1 is not in FLOATING status (default)
1 = Channel 1 is in FLOATING status
CH1_FT
Channel 0 FLOATINT_STATUS
0 = Channel 0 is not in FLOATING status (default)
1 = Channel 0 is in FLOATING status
CH0_FT
NOTE: 1. Only for the SGM51652H8.
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (DECEMBER 2022) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
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DECEMBER 2022
40
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TSSOP-38
D
E1
E
5.94
1.78
b
e
0.30
0.50
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
θ
A1
H
c
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
MIN
MAX
A
A1
A2
b
1.200
0.150
1.000
0.270
0.200
9.800
4.500
6.550
0.047
0.006
0.039
0.011
0.008
0.386
0.177
0.258
0.050
0.800
0.170
0.090
9.600
4.300
6.250
0.002
0.031
0.007
0.004
0.378
0.169
0.246
c
D
E
E1
e
0.500 BSC
0.250 TYP
0.020 BSC
0.010 TYP
H
L
0.450
1°
0.750
7°
0.018
1°
0.030
7°
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
TX00183.001
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
TSSOP-38
13″
16.4
6.80
10.20
1.60
4.0
8.0
2.0
16.0
Q1
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
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TX20000.000
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