SGM5347-12 [SGMICRO]
8 Channels, 12-Bit Digital-to-Analog Converter with Output Operational Amplifier;
| 型号： | SGM5347-12 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 8 Channels, 12-Bit Digital-to-Analog Converter with Output Operational Amplifier |
| 文件： | 总15页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM5347-12
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
GENERAL DESCRIPTION
FEATURES
The SGM5347-12 features 8 channels of 12-bit digital-to-
analog converter (DAC) with output amplifiers. The
output amplifier provides high current drive capability.
The digital data is input via a serial link bus. Only three
control lines are required, and cascaded connections
can be used. The SGM5347-12 provides daisy-chain
capability, which can update multiple SGM5347-12s
simultaneously by using a single serial interface.
● Low Power Consumption (0.5mW/CH)
● Integrating 8 Channels of 12-Bit DAC
● Build-In Analog Output Amplifier:
Sink/Source Current with Short Current Control
● Daisy-Chain Operation
● 8 Channels Outputs Update Simultaneously
● Independent Channel Power-Down Function
0.6μA (TYP) ICC for Power-Down Mode
● The Range of D/A Conversion can be Independently
Set by Separating the Power Supply for MCU Interface
and Operational Amplifier and the Power Supply for
DAC
The SGM5347-12 is available in Green SOIC-16 and
TSSOP-16 packages. It operates over an ambient
temperature range of -40℃ to +125℃.
● Capable of Being Controlled Directly by a 3V MCU
● Power-On Reset: Output Reset to GND
● Serial Data Input: Up to 2.5MHz Operation
● Power Supply Voltage Range: 2.8V to 5.5V
● Available in Green SOIC-16 and TSSOP-16
Packages
SG Micro Corp
DECEMBER2019–REV. A
www.sg-micro.com
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGMMP0XS16
XXXXX
SOIC-16
-40℃ to +125℃
-40℃ to +125℃
SGM5347-12XS16G/TR
Tape and Reel, 2500
Tape and Reel, 4000
SGM5347-12
SGMMP1
XTS16
XXXXX
TSSOP-16
SGM5347-12XTS16G/TR
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage Range (1)
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
VCC.................................................................-0.3V to 6.5V
VREF+ ..............................................................-0.3V to 6.5V
VREF-................................................................ GND ± 0.3V
Input Voltage Range, VIN ........................ -0.3V to VCC + 0.3V
Output Voltage Range, VOUT................... -0.3V to VCC + 0.3V
Package Thermal Resistance
ESD SENSITIVITY CAUTION
SOIC-16................................................................. 90℃/W
TSSOP-16............................................................ 120℃/W
Junction Temperature ...............................................+150℃
Storage Temperature Range...................... -65℃ to +150℃
Lead Temperature (Soldering, 10s) ...........................+260℃
ESD Susceptibility
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM ..........................................................................4000V
CDM ..........................................................................1000V
NOTE: 1. VCC ≥ VREF+
.
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage 1
DISCLAIMER
SG Micro Corp reserves the right to make any change in
V
CC..................................................................2.8V to 5.5V
circuit design, or specifications without prior notice.
GND...............................................................................0V
Power Supply Voltage 2 (VREF+ - VREF- ≥ 0.5V)
V
REF+ ................................................................ 0.5V to VCC
REF-........................................................................... GND
V
Oscillation Limited Output Capacitance, COL .........2nF (TYP)
Digital Data Setting Range .............................. #000 to #FFF
Operating Temperature Range................... -40℃ to +125℃
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
2
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
PIN CONFIGURATIONS
(TOP VIEW)
VREF-
AO2
AO3
AO4
AO5
AO6
AO7
VREF+
1
2
3
4
5
6
7
8
16 GND
15 AO1
14 DIN
13 CLK
12 LD
11 DOUT
10 AO8
9
VCC
SOIC-16/TSSOP-16
PIN DESCRIPTION
PIN
1
NAME
VREF-
TYPE
FUNCTION
‒
‒
Negative Reference Voltage Input Pin. Always connect this pin to ground in application.
Positive Reference Voltage Input Pin.
8
VREF+
9
VCC
‒
Power Supply Pin. Power supply pin of MCU interface and operational amplifier.
Ground Pin. Ground pin of MCU interface and operational amplifier.
DAC Output Pins. These pins are 12-bit DAC outputs with operational amplifiers.
Data Output Pin. This pin outputs MSB of the 16-bit shift register.
16
GND
‒
15, 2, 3, 4,
5, 6, 7, 10
AO1-AO8
DOUT
O
O
11
Load Signal Input Pin. If LD pin is brought from low to high, the data of shift register is
loaded to the decoder and the register for DAC output.
12
LD
I
Shift Clock Input Pin. The input signal from the DIN pin is input to a 16-bit shift register on
the rising edge of the shift clock.
13
14
CLK
DIN
I
I
Serial Data Input Pin. This pin inputs 16-bit length serial data.
NOTE: DIN, CLK, and LD pins should remain "L" level at non-data transfer.
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
3
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 5.5V, TA = -40℃ to +125℃, VREF+ = VCC, VREF- = GND, CL = 200pF to GND, input code range from 48 to 4047.
Typical values are at TA = +25℃, unless otherwise noted.)
PARAMETER
Analog DC Performance
Resolution
INL (1)
DNL (2)
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bit
LSB
3
11
0.85
15
Monotonicity guaranteed by design
-0.7
LSB
Offset
3
0.1
10
2
mV
Gain Error
0.45
60
%FSR
μV/℃
ppmFS/℃
Offset Drift
Gain Drift
15
0μA current load
200μA current load
1mA current load
0μA current load
200μA current load
1mA current load
3
15
Zero Code Error
Full Scale Error
5
mV
mV
8
3
25
6
20
5
Zero Code Drift
μV/℃
μV/℃
Full Scale Error Drift
Analog AC Performance
Output Settling Time
Slew Rate
5
To 1LSB
7
0.9
30
17
300
8
μs
CLOAD = 200pF
Code = 0x800, f = 1kHz
30kHz LPF
V/μs
Noise Density
nV/ Hz
√
Noise
μVRMS
kHz
μs
Multiplying Bandwidth
Wake-Up Time
CLOAD = 200pF
Output Characteristics
Output Resistance
0.3
37
37
5
Ω
Sink
Short Current
mA
Source
VCC = 2.8V
VCC = 5.5V
Continuous Current (3)
mA
nF
10
2
Maximum Capacitance Load
Reference Characteristics
VREF+
0.5
VCC
V
Input Impedance
25
kΩ
Digital Input Characteristics
Input Current
0.1
1
μA
VCC = 2.8V to 3.6V
VCC = 4.5V to 5.5V
VCC = 2.8V to 3.6V
VCC = 4.5V to 5.5V
0.6
0.8
Input Low Voltage
V
2.3
3.5
Input High Voltage
Input Hysteresis
V
V
0.2
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
4
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 5.5V, TA = -40℃ to +125℃, VREF+ = VCC, VREF- = GND, CL = 200pF to GND, input code range from 48 to 4047.
Typical values are at TA = +25℃, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power-On Reset
MIN for minimum entry level, MAX for maximum release
level
Reset Level
2.45
2.6
40
2.78
V
Hysteresis
Difference between reset release level and entry level
mV
Power Consumption
ICC
VCC = 5V
0.5
0.2
0.8
0.4
3
Normal Operation Mode
Power-Down Mode
mA
IREF+
VREF+ = 5V
V
CC = 5V
0.6
μA
VREF+ = 5V
0.01
1
NOTES:
1. Nonlinearity error: The error of the I/O curve deviated from the ideal straight line between output voltages at "#030" and
"#FCF".
2. Differential nonlinearity error: The error deviated from the ideal increment given when the digital value is incremented by one
bit.
3. At +125℃, please limit the output current of each channel to 5mA for maximum operating life time.
Analog output
Ideal straight line
VAOH
Nonlinearity error
VAOL
Digital setting
#030
#FCF
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
5
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
TIMING CHARACTERISTICS
(VCC = 2.8V to 5.5V, TA = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
tCKL
tCKH
tCr
CONDITIONS
MIN
200
200
TYP
MAX
UNITS
ns
"L" Level Clock Pulse Width
ns
"H" Level Clock Pulse Width
Clock Rising Time
Clock Falling Time
Data Setup Time
200
ns
tCf
tDCH
tCHD
tCHL
tLDC
tLDH
tDO
30
60
ns
ns
ns
ns
ns
ns
μs
ns
Data Hold Time
200
100
100
70
Load Setup Time
Load Hold Time
"H" Level Load Pulse Width
Data Output Delay Time
D/A Output Settling Time
LD Hold Time after the 16th Rising Edge of CLK
350
100
tLDD
tSH
60
tCf
tCKH
14
CLK
1
2
13
tCr
15
16
tCKL
tCHD
DB15
DB0
DIN
LD
tSH
tDCH
tLDD
D/A Output
(AO1 to AO8)
tDO
DOUT
NOTES:
1. The D/A output evaluation levels are 90% and 10% of VCC. The other evaluation levels are 80% and 20% of VCC
2. Please ensure of the 16 bits of data are sent before the rising edge of LD.
.
Figure 1. Input/Output Timing Diagram
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
6
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25℃, unless otherwise noted.
DNL vs. Output Codes
DNL vs. Output Codes
VCC = VREF+ = 5V
0.5
0.25
0
0.5
0.25
0
VCC = VREF+ = 2.8V
-0.25
-0.5
-0.25
-0.5
0
1024
2048
Output Codes
3072
4096
0
1024
2048
3072
4096
100 125
100 125
Output Codes
INL vs. Output Codes
INL and DNL vs. Temperature
5
2.5
0
3
2
INL, VCC = 5.5V
DNL, VCC = 2.8V
1
0
-1
-2
-3
DNL, VCC = 5.5V
-2.5
-5
0
1024
2048
3072
4096
-50
-25
0
25
50
75
Output Codes
Temperature (℃)
ICC vs. Temperature
IREF+ vs. Temperature
0.52
0.5
0.25
0.2
VCC = 5V
0.48
0.46
0.44
0.42
0.15
0.1
VCC = 5V
VCC = 2.8V
VCC = 2.8V
0.05
0
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
Temperature (℃)
Temperature (℃)
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
7
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
Zero Code Error vs. Temperature
VCC = 5V
Full Scale Error vs. Temperature
6
5
4
3
2
1
0
6
5
4
3
2
1
0
VCC = 5V
VCC = 2.8V
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Glitch Response
Wake-Up Time
50
40
30
VCC = 5V
VCC = VREF+ = 5V, Code from 0x7FF to 0x800
20
10
0
AOx
LD
-10
-20
-30
-40
-50
Time (2μs/div)
Time (2μs/div)
DAC-to-DAC Crosstalk
VCC = 5V
Settling Time
2.55
2.54
VCC = 5V
2.53
2.52
LD
2.51
2.50
2.49
2.48
2.47
AOx
Time (1μs/div)
Time (2μs/div)
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
8
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
REGISTER MAPS
Data for Shift Register
•
•
•
SGM5347-12 has a 16-bit shift register for chip control.
It is necessary to set the data as following configuration to a 16-bit shift register.
The data consists of 16 bits: a 4-bit address selection and a 12-bit DAC control signal.
Address Selection Signal
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSB LSB
DAC Control Signal
DOUT
←
←
DIN
12-Bit DAC
Figure 2. Serial Data
Address Selection Signal
Input Data Signal
Address Selected
DB15
DB14
DB13
DB12
Don't care.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AO1 selected.
AO2 selected.
AO3 selected.
AO4 selected.
AO5 selected.
AO6 selected.
AO7 selected.
AO8 selected.
PWR_DWN.
CONTROL.
Don't care.
Don't care.
Don't care.
Don't care.
Don't care.
DAC Control Signal
Input Data Signal
DAC Output Voltage
= VREF-
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
0
~
1
1
0
0
1
~
1
1
0
1
0
~
0
1
= VLB + VREF-
= 2 × VLB + VREF-
~
= 4094 × VLB + VREF-
= 4095 × VLB + VREF-
NOTE: VLB = (VREF+ - VREF-)/4096.
SG Micro Corp
DECEMBER 2019
www.sg-micro.com
9
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
REGISTER MAPS (continued)
PWR_DWN Register
DB11
PD_AO8
0
DB10
PD_AO7
0
DB9
PD_AO6
0
DB8
PD_AO5
0
DB7
PD_AO4
0
DB6
PD_AO3
0
DB5
PD_AO2
0
DB4
PD_AO1
0
DB3
DB2
DB1
DB0
N/A
N/A
N/A
N/A
Don't care
PWR_DWN register is not readable. Setting the bit to 1 powers down the corresponding DAC channel. Clearing the bit brings it
up. If all the channels are powered down then the bias circuit will be powered down as well.
CONTROL Register
DB11
N/A
X
DB10
N/A
X
DB9
N/A
X
DB8
N/A
X
DB7
RST
X
DB6
UPDATE
0
DB5
SYNC
0
DB4
3K_PULL
0
DB3
DB2
DB1
DB0
N/A
N/A
N/A
N/A
Don't care
Table 1. CONTROL Register Details
BITS
BIT NAME
DESCRIPTION
DB[11:8]
N/A
1 = Reset internal circuit other than the shift register. Will be automatically cleared to 0 after writing a 1. Since
the reset doesn't hold, the next frame can be used for command. For example, at the first frame, the RST bit is
written so that all DAC outputs reset to 0 at rising edge of the LD signal. The second frame can be a data
writing command, but the DAC outputs won't be changed from 0 until writing of the data takes effect by the LD
signal of the second frame
DB[7]
RST
1 = The rising edge of LD signal updates data in DIN register of all 8 channels to the corresponding data
registers. The bit is then automatically cleared to 0
0 = The rising edge of LD signal loads the data in shift register to DIN and DATA
1 = The rising edge of LD signal only loads the data in shift register to DIN register indicated by ADDR but does
not update the data register. LD will update all 8 channels when writing to channel 8
0 = The pull-down resistance is around 300kΩ
DB[6]
DB[5]
UPDATE
SYNC
DB[4]
3K_PULL
N/A
1 = Enable the 3kΩ pull-down resistors for all the 8 channels. The pull-down resistors are only enabled in
power-down mode
DB[3:0]
Don't care
Example one of a simultaneous update:
1. Write 0x020 to CONTROL register.
2. Write data to channel 1, to channel 2 … to channel 7.
3. Writing data to channel 8 causes all the 8 channels to update at the same time. Then the following writings are still
simultaneously updated.
4. Write 0x000 to CONTROL register to exit simultaneous update mode.
Example two of a simultaneous update:
1. Write 0x020 to CONTROL register.
2. Write data to channel 1, to channel 2 … to channel 7.
3. Write 0x060 to CONTROL register to update all the 8 channels. Then the following writings are still simultaneously updated.
4. Write 0x000 to CONTROL register to exit simultaneous update mode.
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
10
8 Channels, 12-Bit Digital-to-Analog Converter
with Output Operational Amplifier
SGM5347-12
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (DECEMBER 2019) to REV.A
Page
Changed from product preview to production data ..................................................................................................................................................All
SG Micro Corp
www.sg-micro.com
DECEMBER 2019
11
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TSSOP-16
D
E1
E
5.94
1.78
0.42
e
b
0.65
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
A1
θ
H
c
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
MIN
MAX
0.047
0.006
0.041
0.012
0.008
0.201
0.177
0.260
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
5.100
4.500
6.600
0.050
0.800
0.190
0.090
4.860
4.300
6.200
0.002
0.031
0.007
0.004
0.191
0.169
0.244
c
D
E
E1
e
0.650 BSC
0.25 TYP
0.026 BSC
0.01 TYP
L
0.500
1°
0.700
7°
0.02
1°
0.028
7°
H
θ
SG Micro Corp
www.sg-micro.com
TX00020.001
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
SOIC-16
D
e
1.75
E1
E
5.60
0.65
1.27
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
b
c
θ
A1
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
1.750
0.250
1.550
0.510
0.250
MIN
MAX
0.069
0.010
0.061
0.020
0.010
0.402
0.157
0.244
A
A1
A2
b
1.350
0.100
1.350
0.330
0.170
9.800
3.800
5.800
0.053
0.004
0.053
0.013
0.006
0.386
0.150
0.228
c
D
E
10.200
4.000
6.200
E1
e
1.27 BSC
0.050 BSC
L
0.400
0°
1.270
8°
0.016
0°
0.050
8°
θ
SG Micro Corp
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TX00012.000
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
TSSOP-16
SOIC-16
13″
13″
12.4
16.4
6.90
6.50
5.60
1.20
2.10
4.0
4.0
8.0
8.0
2.0
2.0
12.0
16.0
Q1
Q1
10.30
SG Micro Corp
TX10000.000
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PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
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TX20000.000
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