SGM5351-16 [SGMICRO]

16-Bit, Ultra-Low Glitch, Voltage-Output Digital-to-Analog Converter;
SGM5351-16
型号: SGM5351-16
厂家: Shengbang Microelectronics Co, Ltd    Shengbang Microelectronics Co, Ltd
描述:

16-Bit, Ultra-Low Glitch, Voltage-Output Digital-to-Analog Converter

文件: 总20页 (文件大小:1398K)
中文:  中文翻译
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SGM5351-16  
16-Bit, Ultra-Low Glitch,  
Voltage-Output Digital-to-Analog Converter  
GENERAL DESCRIPTION  
FEATURES  
The SGM5351-16 is a low power, single channel, 16-bit,  
voltage-output DAC. It operates from a 2.7V to 5.5V  
supply and the monotonicity is guaranteed by design.  
Power Supply Range: 2.7V to 5.5V  
16-Bit DAC, Monotonicity Guaranteed by Design  
6LSB (TYP) Relative Accuracy  
Low Power Operation: 100μA at 2.7V  
Power-On Reset to Zero-Scale  
10μs (TYP) Settling Time  
The SGM5351-16 sets the output range by using an  
external reference voltage. It incorporates a power-on  
reset circuit that ensures the DAC output powers to 0V  
and remains powered up at this level until a valid write  
takes place. The SGM5351-16 provides a power-down  
mode accessed via the serial interface that reduces the  
current consumption of the device to 450nA (TYP) at  
5.5V. The SGM5351-16 consumes 0.27mW (TYP) at  
2.7V in normal mode, which reduces to less than 1μW  
in powerdown mode, the low power consumption in  
normal mode is very suitable for portable battery-  
operated equipment.  
3-Wire Serial Interface with Schmitt Trigger Logic  
Inputs  
Rail-to-Rail Buffered Voltage-Output Operation  
Binary Code Input  
Power-Down Function  
nSYNC Interrupt Facility  
Available in a Green MSOP-8 Package  
APPLICATIONS  
The SGM5351-16 uses a 3-wire serial interface which  
can be operated at clock rates to 30MHz and is  
compatible with standard SPI interface.  
Portable Instrumentation  
Programmable Attenuators  
Process Control  
The SGM5351-16 is available in a Green MSOP-8  
package. It operates over an ambient temperature  
range of -40to +125.  
Closed-Loop Servo-Control  
Data Acquisition Systems  
SG Micro Corp  
JANUARY 2022 – REV. A. 1  
www.sg-micro.com  
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
PACKAGE/ORDERING INFORMATION  
SPECIFIED  
TEMPERATURE  
RANGE  
PACKAGE  
DESCRIPTION  
ORDERING  
NUMBER  
PACKAGE  
MARKING  
PACKING  
OPTION  
MODEL  
SGMSVP  
XMS8  
XXXXX  
SGM5351-16  
MSOP-8  
SGM5351-16XMS8G/TR  
Tape and Reel, 4000  
-40to +125℃  
MARKING INFORMATION  
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.  
X X X X X  
Vendor Code  
Trace Code  
Date Code - Year  
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If  
you have additional comments or questions, please contact your SGMICRO representative directly.  
OVERSTRESS CAUTION  
ABSOLUTE MAXIMUM RATINGS  
Stresses beyond those listed in Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to  
absolute maximum rating conditions for extended periods  
may affect reliability. Functional operation of the device at any  
conditions beyond those indicated in the Recommended  
Operating Conditions section is not implied.  
Input Voltage Range............................................ -0.3V to 6V  
Digital Input Voltage Range .................... -0.3V to VCC + 0.3V  
Output Voltage Range ............................ -0.3V to VCC + 0.3V  
Package Thermal Resistance  
MSOP-8, θJA .......................................................... 168/W  
MSOP-8, θJC ............................................................ 65/W  
Junction Temperature.................................................+150℃  
Storage Temperature Range .......................-65to +150℃  
Lead Temperature (Soldering, 10s)............................+260℃  
ESD Susceptibility  
ESD SENSITIVITY CAUTION  
This integrated circuit can be damaged if ESD protections are  
not considered carefully. SGMICRO recommends that all  
integrated circuits be handled with appropriate precautions.  
Failure to observe proper handling and installation procedures  
can cause damage. ESD damage can range from subtle  
performance degradation tocomplete device failure. Precision  
integrated circuits may be more susceptible to damage  
because even small parametric changes could cause the  
device not to meet the published specifications.  
HBM...........................................................................±4000V  
CDM ..........................................................................±1000V  
RECOMMENDED OPERATING CONDITIONS  
Supply Voltage Range (VCC to GND)..................2.7V to 5.5V  
Digital Input Voltage Range (DIN/OUT, SCLK, and nSYNC)  
................................................................................ 0V to VCC  
Reference Input Voltage Range, VREF .................... 0V to VCC  
Output Amplifier Feedback Input, VFB .............................VOUT  
Operating Temperature Range....................-40to +125℃  
DISCLAIMER  
SG Micro Corp reserves the right to make any change in  
circuit design, or specifications without prior notice.  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
2
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
PIN CONFIGURATION  
(TOP VIEW)  
VCC  
1
2
3
4
8
7
6
5
GND  
VREF  
DIN/OUT  
SCLK  
nSYNC  
VFB  
VOUT  
MSOP-8  
PIN DESCRIPTION  
PIN  
NAME  
TYPE (1)  
FUNCTION  
1
2
VCC  
P
I
Power Supply Pin. It can be operated from 2.7V to 5.5V.  
Reference Voltage Input Pin.  
VREF  
Output Amplifier Feedback Input Pin. Connect to VOUT externally for the voltage-output  
operation.  
3
4
VFB  
I
VOUT  
O
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.  
Frame Synchronization Input Pin. Active low. When this pin goes low, data is transferred  
into the input shift register on the falling edges of SCLK. After the 24th falling edge of  
SCLK, the DAC is updated. If nSYNC is brought high before this edge, the rising edge of  
nSYNC acts as an interrupt and the write sequence is ignored by the DAC.  
5
6
nSYNC  
SCLK  
I
I
Serial Clock Input Pin. Data can be transferred at clock rates to 30MHz Schmitt-Trigger  
logic input.  
Serial Data Input/Output Pin. Data is clocked into the 24-bit input shift register on the  
falling edge of SCLK.  
7
8
DIN/OUT  
GND  
I/O  
G
Ground Pin.  
NOTE:  
1. I = Input, O = Output, I/O = Input or Output, P = Power, G = Ground.  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
3
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
ELECTRICAL CHARACTERISTICS  
(VCC = 2.7V to 5.5V, TA = -40to +125, typical values are at TA = +25, unless otherwise noted.)  
PARAMETER  
Static Performance (1)  
Resolution  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
16  
Bits  
Measured by line passing through codes 485 and 64741  
at VREF = 5.4V, codes 970 and 63947 at VREF = 2.5V  
Relative Accuracy  
6
12  
LSB  
Differential Nonlinearity  
Zero-Code Error  
DNL  
0.5  
1
LSB  
mV  
2.5V ≤ VREF ≤ 5.5V, -40≤ TA +125℃  
Measured by line passing through codes 485 and 64741  
0.55  
2.5  
% of  
FSR  
% of  
FSR  
Full-Scale Error  
Measured by line passing through codes 485 and 64741  
Measured by line passing through codes 485 and 64741  
0.06  
0.2  
Gain Error  
0.05  
4
0.15  
Zero-Code Error Drift  
μV/℃  
ppm of  
FSR/℃  
Gain Temperature Coefficient  
1
Power-Supply Rejection Ratio  
Output Characteristics (2)  
Output Voltage Range  
Output Voltage Settling Time  
Slew Rate  
PSRR  
RL = 2kΩ, CL = 200pF  
RL = 2kΩ, CL = 50pF  
0.15  
mV/V  
0
VREF  
V
10  
1
μs  
V/μs  
2
RL = ∞  
Capacitive Load Stability  
nF  
RL = 2kΩ  
10  
20  
0.1  
0.3  
38  
36  
16  
14  
Code Change Glitch Impulse  
Digital Feedthrough  
1LSB change around major carry  
50kΩ series resistance on digital lines  
At mid-code input  
nV-s  
nV-s  
DC Output Impedance  
V
CC = 5V  
Short-Circuit Current  
Power-Up Time  
mA  
VCC = 3V  
V
CC = 5V  
Coming out of power-down mode  
μs  
VCC = 3V  
AC Performance  
BW = 20kHz, VCC = 5V, fOUT = 1kHz,  
Signal-to-Noise Ratio  
SNR  
THD  
54  
-62  
66  
dB  
dB  
dB  
dB  
1st 19 harmonics removed for SNR calculation  
BW = 20kHz, VCC = 5V, fOUT = 1kHz,  
Total Harmonic Distortion  
1st 19 harmonics removed for SNR calculation  
Spurious-Free Dynamic  
Range  
BW = 20kHz, VCC = 5V, fOUT = 1kHz,  
SFDR  
SINAD  
1st 19 harmonics removed for SNR calculation  
BW = 20kHz, VCC = 5V, fOUT = 1kHz,  
Signal-to-Noise and Distortion  
53  
1st 19 harmonics removed for SNR calculation  
Reference Input  
V
REF = VCC = 5V  
21  
15  
26  
22  
Reference Input Current  
μA  
VREF = VCC = 3.6V  
Reference Input Range  
0
VCC  
V
Reference Input Impedance  
235  
kΩ  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
4
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
ELECTRICAL CHARACTERISTICS (continued)  
(VCC = 2.7V to 5.5V, TA = -40to +125, typical values are at TA = +25, unless otherwise noted.)  
PARAMETER  
Logic Inputs (2)  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Input Current  
10  
nA  
V
VCC = 5.5V  
VCC = 2.7V  
VCC = 5.5V  
VCC = 2.7V  
1
Input Low Voltage  
VIL  
VIH  
0.6  
2.1  
1.5  
Input High Voltage  
V
Pin Capacitance  
Power Requirements  
Supply Voltage  
2
pF  
VCC  
2.7  
5.5  
150  
130  
2
V
Normal mode, input code = 32768,  
no load, does not include reference  
current, VIH = VCC, VIL = GND  
VCC = 5.5V  
VCC = 2.7V  
VCC = 5.5V  
VCC = 2.7V  
108  
100  
0.45  
0.32  
95  
Supply Current  
ICC  
μA  
All power-down modes,  
V
IH = VCC, VIL = GND  
2
IOUT/ICC Power Efficiency  
ILOAD = 2mA, VCC = 5V  
%
Specified Performance  
Temperature  
-40  
125  
NOTES:  
1. Linearity calculated using a reduced codes range of 485 and 64741 at VREF = 5.4V, codes 970 and 63947 at VREF = 2.5V;  
output unloaded, 100mV headroom between reference and supply.  
2. Guaranteed by design. Not production tested.  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
5
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TIMING CHARACTERISTICS  
(VCC = 2.7V to 5.5V, TA = -40to +125, unless otherwise noted.) (1) (2)  
PARAMETER  
SYMBOL  
CONDITIONS  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 3.6V  
VCC = 3.6V to 5.5V  
VCC = 2.7V to 5.5V  
VCC = 2.7V to 5.5V  
VCC = 2.7V to 5.5V  
MIN  
50  
33  
10  
11  
11  
11  
0
TYP  
MAX  
UNITS  
SCLK Cycle Time (3)  
SCLK High Time  
SCLK Low Time  
t1  
ns  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
nSYNC Falling Edge to SCLK Rising Edge Setup Time  
Data Setup Time  
0
5
5
5
Data Hold Time  
5
0
24th SCLK Falling Edge to nSYNC Rising Edge  
0
22  
26  
100  
15  
0
Minimum nSYNC High Time  
24th SCLK Falling Edge to nSYNC Falling Edge  
DIN/OUT Tri-State to Driven  
24th SCLK Falling Edge to DIN/OUT Tri-State  
t9  
ns  
ns  
ns  
t10  
t11  
NOTES:  
1. All input signals are specified with tR = tF = 5ns (10% to 90% of VCC) and timed from a voltage level of (VIL + VIH)/2.  
2. Refer to Figure 1 and Figure 2.  
3. Maximum SCLK frequency is 30MHz at VCC = 3.6V to 5.5V and 20MHz at VCC = 2.7V to 3.6V.  
t1  
t9  
SCLK  
1
6
24  
t2  
t8  
t7  
t3  
t4  
nSYNC  
t6  
t5  
DIN/OUT  
DB23  
DB19  
0
DB17  
DB0  
DB23  
NOTE: 1. When DB[18] = 0, this is a write operation, the data DB[17:0] is locked into DAC on each falling edge of SCLK.  
Figure 1. Serial Write Operation  
t1  
t9  
24  
SCLK  
1
t2  
t8  
t3  
t7  
t4  
nSYNC  
t6  
(1)  
(2)  
t10  
t5  
t11  
DIN/OUT  
1
DB23  
DB19  
DB0  
DB17  
DB23  
NOTES:  
1. When DB[18] = 1, this is a read operation, the data DB[17:0] is read from DAC. On the rising edge of 7th of SCLK, the DIN/OUT is  
switched from input to output, the data of internal register is put on the bus on each rising edge of SCLK.  
2. On the 24th falling edge of SCLK, the DIN/OUT is turned off to Hi-Z.  
Figure 2. Serial Read Operation  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
6
 
 
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS  
TA = +25, unless otherwise noted.  
INL vs. Digital Input Code (-40)  
DNL vs. Digital Input Code (-40)  
VCC = 5V  
INL vs. Digital Input Code (+25)  
DNL vs. Digital Input Code (+25)  
VCC = 5V  
INL vs. Digital Input Code (+125)  
DNL vs. Digital Input Code (+125)  
VCC = 5V  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
7
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
TA = +25, unless otherwise noted.  
Zero-Scale Error vs. Temperature  
VCC = 5V, VREF = 4.99V  
Full-Scale Error vs. Temperature  
VCC = 5V, VREF = 4.99V  
10  
5
10  
5
0
0
-5  
-5  
-10  
-10  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature ()  
Temperature ()  
Source and Sink Current Capability  
DAC Loaded with FFFFh  
Supply Current vs. Digital Input Code  
VCC = VREF = 5V  
6
5
4
3
2
1
0
160  
140  
120  
100  
80  
Reference Current Included  
60  
40  
VCC = 5.5V,  
REF = 5.49V  
20  
V
DAC Loaded with 0000h  
0
0
1
2
3
4
5
6
7
8
9
10  
0
16384  
32768  
49152  
65536  
ISOURCE/SINK (mA)  
Digital Input Code  
Supply Current vs. Temperature  
VCC = VREF = 5V  
Supply Current vs. Logic Input Voltage  
140  
120  
100  
80  
400  
350  
300  
250  
200  
150  
100  
50  
60  
40  
VCC = VREF = 5V,  
TA = +25, SCL Input (All other inputs = GND)  
20  
0
0
-50  
-25  
0
25  
50  
75  
100  
125  
0
1
2
3
4
5
Logic Input Voltage (V)  
Temperature ()  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
8
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
TA = +25, unless otherwise noted.  
Supply Current vs. Supply Voltage  
Power-Down Current vs. Supply Voltage  
VCC = VREF  
200  
180  
160  
140  
120  
100  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
VCC = VREF, Reference Current Included,  
No Load  
2.7  
3.1  
3.5  
3.9  
4.3  
4.7  
5.1  
5.5  
2.7  
3.1  
3.5  
3.9  
4.3  
4.7  
5.1  
5.5  
Supply Voltage (V)  
Supply Voltage (V)  
Full-Scale Settling Time, 5V Rising Edge  
Trigger Pulse 5V/div  
Full-Scale Settling Time, 5V Falling Edge  
Trigger Pulse 5V/div  
VCC = 5V  
V
REF = 4.096V  
From Code: FFFF  
To Code: 0000  
VCC = 5V  
Falling Edge 1V/div  
V
REF = 4.096V  
Rising Edge 1V/div  
From Code: 0000  
To Code: FFFF  
Time (2μs/div)  
Time (2μs/div)  
Half-Scale Settling Time, 5V Rising Edge  
Trigger Pulse 5V/div  
Half-Scale Settling Time, 5V Falling Edge  
Trigger Pulse 5V/div  
Falling Edge 1V/div  
VCC = 5V  
VCC = 5V  
V
REF = 4.096V  
VREF = 4.096V  
Rising Edge 1V/div  
From Code: 4000  
To Code: CFFF  
From Code: CFFF  
To Code: 4000  
Time (2μs/div)  
Time (2μs/div)  
SG Micro Corp  
JANUARY 2022  
www.sg-micro.com  
9
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
TA = +25, unless otherwise noted.  
Glitch Energy: 5V, 1LSB Step, Rising Edge  
Glitch Energy: 5V, 1LSB Step, Falling Edge  
VOUT  
VOUT  
VCC = 5V  
REF = 4.096V  
VCC = 5V  
REF = 4.096V  
V
V
From Code: 7FFF  
To Code: 8000  
From Code: 8000  
To Code: 7FFF  
Time (2μs/div)  
Time (2μs/div)  
Glitch Energy: 5V, 16LSB Step, Rising Edge  
Glitch Energy: 5V, 16LSB Step, Falling Edge  
VOUT  
VOUT  
VCC = 5V  
REF = 4.096V  
VCC = 5V  
REF = 4.096V  
V
V
From Code: 8000  
To Code: 8010  
From Code: 8010  
To Code: 8000  
Time (2μs/div)  
Time (2μs/div)  
Glitch Energy: 5V, 256LSB Step, Rising Edge  
Glitch Energy: 5V, 256LSB Step, Falling Edge  
VOUT  
VOUT  
VCC = 5V  
REF = 4.096V  
VCC = 5V  
REF = 4.096V  
V
V
From Code: 8000  
To Code: 80FF  
From Code: 80FF  
To Code: 8000  
Time (500ns/div)  
Time (500ns/div)  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
10  
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
TA = +25, unless otherwise noted.  
INL vs. Digital Input Code (-40)  
INL vs. Digital Input Code (+25)  
INL vs. Digital Input Code (+125)  
DNL vs. Digital Input Code (-40)  
VCC = 2.7V  
DNL vs. Digital Input Code (+25)  
VCC = 2.7V  
DNL vs. Digital Input Code (+125)  
VCC = 2.7V  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
11  
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
TA = +25, unless otherwise noted.  
Zero-Scale Error vs. Temperature  
VCC = 2.7V, VREF = 2.69V  
Full-Scale Error vs. Temperature  
VCC = 2.7V, VREF = 2.69V  
10  
5
10  
5
0
0
-5  
-5  
-10  
-10  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature ()  
Temperature ()  
Source and Sink Current Capability  
DAC Loaded with FFFFh  
Supply Current vs. Digital Input Code  
VCC = VREF = 2.7V  
3
2.5  
2
140  
120  
100  
80  
Reference Current Included  
1.5  
1
60  
40  
0.5  
0
VCC = 2.7V,  
REF = 2.69V  
20  
V
DAC Loaded with 0000h  
0
0
1
2
3
4
5
6
7
8
9
10  
0
16384  
32768  
49152  
65536  
ISOURCE/SINK (mA)  
Digital Input Code  
Supply Current vs. Temperature  
VCC = VREF = 2.7V  
Supply Current vs. Logic Input Voltage  
140  
120  
100  
80  
150  
140  
130  
120  
110  
100  
90  
60  
40  
VCC = VREF = 2.7V,  
TA = +25, SCL Input (All other inputs = GND)  
20  
80  
0
70  
-50  
-25  
0
25  
50  
75  
100  
125  
0
0.5  
1
1.5  
2
2.5  
3
Logic Input Voltage (V)  
Temperature ()  
SG Micro Corp  
www.sg-micro.com  
JANUARY 2022  
12  
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
TA = +25, unless otherwise noted.  
Full-Scale Settling Time: 2.7V Rising Edge  
Trigger Pulse 2.7V/div  
Full-Scale Settling Time: 2.7V Falling Edge  
Trigger Pulse 2.7V/div  
VCC = 2.7V  
REF = 2.5V  
V
From Code: FFFF  
To Code: 0000  
VCC = 2.7V  
V
REF = 2.5V  
From Code: 0000  
To Code: FFFF  
Rising Edge 0.5V/div  
Falling Edge 0.5V/div  
Time (2μs/div)  
Time (2μs/div)  
Half-Scale Settling Time: 2.7V Rising Edge  
Trigger Pulse 2.7V/div  
Half-Scale Settling Time: 2.7V Falling Edge  
Trigger Pulse 2.7V/div  
VCC = 2.7V  
VCC = 2.7V  
Rising Edge 0.5V/div  
V
REF = 2.5V  
V
REF = 2.5V  
From Code: 4000  
To Code: CFFF  
From Code: CFFF  
To Code: 4000  
Falling Edge 0.5V/div  
Time (2μs/div)  
Time (2μs/div)  
Glitch Energy: 2.7V, 1LSB Step, Rising Edge  
Glitch Energy: 2.7V, 1LSB Step, Falling Edge  
VOUT  
VOUT  
VCC = 2.7V  
REF = 2.5V  
VCC = 2.7V  
VREF = 2.5V  
V
From Code: 7FFF  
To Code: 8000  
From Code: 8000  
To Code: 7FFF  
Time (2μs/div)  
Time (2μs/div)  
SG Micro Corp  
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JANUARY 2022  
13  
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
TA = +25, unless otherwise noted.  
Glitch Energy: 2.7V, 16LSB Step, Rising Edge  
Glitch Energy: 2.7V, 16LSB Step, Falling Edge  
VOUT  
VOUT  
VCC = 2.7V  
REF = 2.5V  
VCC = 2.7V  
REF = 2.5V  
V
V
From Code: 8000  
To Code: 8010  
From Code: 8010  
To Code: 8000  
Time (2μs/div)  
Time (2μs/div)  
Glitch Energy: 2.7V, 256LSB Step, Rising Edge  
Glitch Energy: 2.7V, 256LSB Step, Falling Edge  
VOUT  
VOUT  
VCC = 2.7V  
REF = 2.5V  
VCC = 2.7V  
VREF = 2.5V  
V
From Code: 8000  
To Code: 80FF  
From Code: 80FF  
To Code: 8000  
Time (500ns/div)  
Time (500ns/div)  
Output Noise Density  
270  
250  
230  
210  
190  
170  
150  
130  
110  
90  
VCC = 5V  
70  
100  
1000  
10000  
100000  
Frequency (Hz)  
SG Micro Corp  
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JANUARY 2022  
14  
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
FUNCTIONAL BLOCK DIAGRAM  
VCC  
VFB  
VOUT  
16-Bit  
DAC  
VREF  
REF (+)  
nSYNC  
SCLK  
Control  
Logic  
Resistor  
Network  
DIN/OUT  
GND  
Figure 3. Block Diagram  
SG Micro Corp  
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JANUARY 2022  
15  
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
DETAILED DESCRIPTION  
DAC Section  
nSYNC Interrupt  
The SGM5351-16 is a resistor string DAC followed by an  
output buffer amplifier. The input code to the SGM5351-16 is  
straight binary, so the ideal output voltage can be calculated  
based on the following equation:  
In a normal write/read sequence, the nSYNC line must be  
kept low for at least 24 falling edges of SCLK and the DAC is  
updated on the 24th falling edge. However, if nSYNC goes  
high before the 24th falling edge, this write/read operation is  
invalid and ignored. An example is shown in Figure 5.  
DIN  
65536  
(1)  
VOUT  
=
× VREF  
Power-On Reset  
Where:  
The SGM5351-16 has a power-on reset circuit, which can  
control the output voltage during power-up. On power-up, the  
DAC output voltages are 0V.  
DIN = Equal decimal code that is loaded to the DAC register,  
it’s from 0 to 65535.  
Serial Interface  
Power-Down Modes  
The SGM5351-16 supports four separate modes of operation.  
The 3-wire serial interface (nSYNC, SCLK, and DIN/OUT) is  
compatible with SPI interface standard. The SGM5351-16  
supports 3-wire SPI read and write operation. See Figure 1  
for an example of a write sequence, and see Figure 2 for an  
example of a read sequence.  
The detailed operating mode is shown in Table 1.  
Table 1. Operating Modes  
PD1 (DB[17]) PD0 (DB[16])  
Normal Mode  
Operating Mode  
Input Shift Register  
0
0
Normal operation  
The input shift register is 24 bits wide, as shown in Figure 4.  
The first 5 bits are unused bits. DB[18] is a write or read  
selection bit. These bits are transferred to the DAC register  
on the 24th falling edge of SCLK.  
Power-Down Modes  
0
1
1
1
0
1
Output typically 1kΩ to GND  
Output typically 100kΩ to GND  
Hi-Z  
Bit  
Number  
23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
Write  
Unused  
Unused  
0
1
PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
Data (1)  
Read  
Data (1)  
NOTE:  
1. When in write data mode, DB[18] = 0, DB[17:0] are the data to be written to DAC; when in read data mode, DB[18] = 1,  
DB[17:0] are the data to be read out from DAC.  
Figure 4. Data Input Register Format  
24th Falling Edge  
24th Falling Edge  
SCLK  
nSYNC  
DIN/OUT  
DB23  
DB0  
DB23  
DB0  
Valid Write Sequence: Output Updates on the 24th Falling Edge  
Figure 5. nSYNC Interrupt Facility  
SG Micro Corp  
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JANUARY 2022  
16  
 
 
 
16-Bit, Ultra-Low Glitch,  
SGM5351-16  
Voltage-Output Digital-to-Analog Converter  
REVISION HISTORY  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
JANUARY 2022 ‒ REV.A to REV.A.1  
Page  
Updated Electrical Characteristics section................................................................................................................................................................4  
Changes from Original (DECEMBER 2021) to REV.A  
Page  
Changed from product preview to production data .................................................................................................................................................All  
SG Micro Corp  
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JANUARY 2022  
17  
PACKAGE INFORMATION  
PACKAGE OUTLINE DIMENSIONS  
MSOP-8  
b
E1  
E
4.8  
1.02  
e
0.41  
0.65  
RECOMMENDED LAND PATTERN (Unit: mm)  
D
L
A
c
A1  
θ
A2  
Dimensions  
In Millimeters  
Dimensions  
In Inches  
Symbol  
MIN  
MAX  
1.100  
0.150  
0.950  
0.380  
0.230  
3.100  
3.100  
5.050  
MIN  
MAX  
0.043  
0.006  
0.037  
0.015  
0.009  
0.122  
0.122  
0.199  
A
A1  
A2  
b
0.820  
0.020  
0.750  
0.250  
0.090  
2.900  
2.900  
4.750  
0.032  
0.001  
0.030  
0.010  
0.004  
0.114  
0.114  
0.187  
c
D
E
E1  
e
0.650 BSC  
0.026 BSC  
L
0.400  
0°  
0.800  
6°  
0.016  
0°  
0.031  
6°  
θ
NOTES:  
1. Body dimensions do not include mode flash or protrusion.  
2. This drawing is subject to change without notice.  
SG Micro Corp  
TX00014.000  
www.sg-micro.com  
PACKAGE INFORMATION  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
P2  
P0  
W
Q2  
Q4  
Q2  
Q4  
Q2  
Q4  
Q1  
Q3  
Q1  
Q3  
Q1  
Q3  
B0  
Reel Diameter  
P1  
A0  
K0  
Reel Width (W1)  
DIRECTION OF FEED  
NOTE: The picture is only for reference. Please make the object as the standard.  
KEY PARAMETER LIST OF TAPE AND REEL  
Reel Width  
Reel  
Diameter  
A0  
B0  
K0  
P0  
P1  
P2  
W
Pin1  
Package Type  
W1  
(mm)  
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant  
MSOP-8  
13″  
12.4  
5.20  
3.30  
1.50  
4.0  
8.0  
2.0  
12.0  
Q1  
SG Micro Corp  
TX10000.000  
www.sg-micro.com  
PACKAGE INFORMATION  
CARTON BOX DIMENSIONS  
NOTE: The picture is only for reference. Please make the object as the standard.  
KEY PARAMETER LIST OF CARTON BOX  
Length  
(mm)  
Width  
(mm)  
Height  
(mm)  
Reel Type  
Pizza/Carton  
13″  
386  
280  
370  
5
SG Micro Corp  
www.sg-micro.com  
TX20000.000  

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