SGM61430 [SGMICRO]
4.5V to 36V Input, 3A, Synchronous Buck Converter;
| 型号： | SGM61430 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 4.5V to 36V Input, 3A, Synchronous Buck Converter |
| 文件： | 总24页 (文件大小：997K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM61430/SGM61431
4.5V to 36V Input, 3A,
Synchronous Buck Converters
GENERAL DESCRIPTION
FEATURES
The SGM61430 and SGM61431 are internally
compensated, synchronous Buck converters with a
wide 4.5V to 36V input voltage range and 3A output
current capability. These devices can be easily used in
various industrial applications powered from unregulated
sources. Easy compensation and cycle-by-cycle current
limit are obtained by peak current mode control. With
64μA (TYP, SGM61430) quiescent current and ultra-low
0.6μA (TYP) shutdown current, they are well suited for
battery powered systems to prolong battery life. Internal
compensation allows quick and low component count
design.
● Wide 4.5V to 36V Input Voltage Range
● Up to 3A Continuous Output Current
● SGM61430:
0.8V to 24V Output Voltage Range
PFM at Light Load Condition
● SGM61431:
0.8V to 24V Output Voltage Range
FPWM at Light Load Condition
● 390kHz Switching Frequency (Normal Operation)
● SYNC Input for External Switching Clock
● Integrated RDSON Switches: 115mΩ/90mΩ (TYP)
● High Efficiency at Light Load Condition
● Ultra-Low Shutdown Current: 0.6μA (TYP)
● Peak Current Mode Control
● Precision Enable Threshold with UVLO Setting
● Cycle-by-Cycle Current Limit
● 1.5ms (TYP) Internal Soft-Start Time
● -40℃ to +125℃ Operating Temperature Range
● Available in a Green SOIC-8 (Exposed Pad) Package
Both SGM61430 and SGM61431 can operate at fixed
frequency with moderate or heavy load condition. In light
load condition, the SGM61430 enters in the pulse
frequency modulation (PFM) mode to improve high
efficiency, while the SGM61431 works in the forced
pulse width modulation (FPWM) mode to achieve low
output ripple and good regulation.
The EN/SYNC employs an enable divider to establish a
precision threshold that simplifies UVLO adjustment,
device on/off control and power sequencing. Thermal
shutdown and output short-circuit protection (hiccup
mode) are also provided.
APPLICATIONS
Industrial Power Supplies
Telecom and Datacom Systems
General Purpose Wide VIN Regulation
The SGM61430 and SGM61431 are both available in a
Green SOIC-8 (Exposed Pad) package and can operate
over -40℃ to +125℃ ambient temperature range.
TYPICAL APPLICATION
VIN up to 36 V
VIN
BOOT
RBST
CIN
REN
SGM61430/1
CBOOT
EN/SYNC
SW
FB
VOUT
L
RFBT
VCC
COUT
CVCC
RFBB
PGND
AGND
Figure 1. Typical Application Circuit
SG Micro Corp
www.sg-micro.com
JANUARY2023–REV. A.2
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM
61430XPS8
XXXXX
SGM
61431XPS8
XXXXX
SOIC-8
(Exposed Pad)
SGM61430
SGM61431
-40℃ to +125℃ SGM61430XPS8G/TR
-40℃ to +125℃ SGM61431XPS8G/TR
Tape and Reel, 4000
Tape and Reel, 4000
SOIC-8
(Exposed Pad)
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
Input Voltages:
RECOMMENDED OPERATING CONDITIONS
Input Voltages:
VIN to PGND ................................................... -0.3V to 42V
EN to AGND ...........................................-5.5V to VIN + 0.3V
FB to AGND.................................................... -0.3V to 4.5V
AGND to PGND.............................................. -0.3V to 0.3V
Output Voltages:
VIN to PGND.....................................................4.5V to 36V
EN to AGND........................................................-5V to 36V
FB to AGND ....................................................-0.3V to 1.2V
Output Voltage Range.........................................0.8V to 24V
Output Current Range..............................................0A to 3A
Operating Ambient Temperature Range ..... -40℃ to +125℃
SW to PGND...........................................-0.3V to VIN + 0.3V
SW to PGND (Less than 10ns Transients) ......... -5V to 42V
BOOT to SW................................................... -0.3V to 5.5V
VCC to AGND................................................. -0.3V to 5.5V
Package Thermal Resistance
OVERSTRESS CAUTION
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
SOIC-8 (Exposed Pad), θJA ..................................... 41℃/W
SOIC-8 (Exposed Pad), θJB .................................. 23.6℃/W
SOIC-8 (Exposed Pad), θJC (TOP) .............................. 37℃/W
SOIC-8 (Exposed Pad), θJC (BOT) ............................. 2.9℃/W
Package Thermal Characterization Parameter
SOIC-8 (Exposed Pad), ψJT.................................. 12.6℃/W
SOIC-8 (Exposed Pad), ψJB.................................... 3.7℃/W
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................4000V
CDM ............................................................................1000V
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
JANUARY 2023
2
4.5V to 36V Input, 3A,
SGM61430/SGM61431
PIN CONFIGURATION
Synchronous Buck Converters
(TOP VIEW)
1
2
3
8
7
6
SW
BOOT
VCC
FB
PGND
VIN
Exposed
Pad
AGND
EN/SYNC
4
5
SOIC-8 (Exposed Pad)
PIN DESCRIPTION
PIN
NAME
TYPE (1)
FUNCTION
Switching Node Output. Switching node of the internal synchronous Buck converter with N-MOSFET
switches. Connect to the output inductor and bootstrap capacitor.
1
SW
P
P
P
A
Bootstrap Input. Bootstrap supply for high-side driver. Connect a 470nF ceramic capacitor between BOOT
and SW pins.
2
BOOT
VCC
FB
3
LDO (Internal Bias) Output. This pin is provided for bypassing to AGND only. Never load VCC.
Feedback Input. Connect the midpoint of the feedback resistor divider.
4
Active High Enable and Synchronous Input. Do not float.
EN: This pin can be connected to VIN pin via a resistor if the shutdown feature is not required or to a
resistor divider to adjust UVLO threshold.
5
EN/SYNC
A
SYNC: An external clock with positive pulses can be coupled to this pin by a small capacitor for
synchronizing the internal switching oscillator.
6
7
AGND
VIN
G
P
Analog Ground. Reference for internal analog signals and logic. Connect it to system ground.
Power Supply Input Pin. Connect CIN as close as possible between this pin and PGND pin.
Power Ground. It is internally connected to converter return. Returns of the CIN and COUT capacitors should
be connected close to this pin. Connect to system ground, exposed pad and AGND together.
8
PGND
G
G
Exposed
Pad
Thermal Exposed Pad. Must be connected to ground plane on PCB. It is the main thermal relief path for the
die.
—
NOTE: 1. A = analog, P = power, G = ground.
SG Micro Corp
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JANUARY 2023
3
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
ELECTRICAL CHARACTERISTICS
(VIN = 12V, TJ = -40℃ to +125℃, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
Input Voltage Range
Input UVLO Rising Threshold
Input UVLO Hysteresis
Shutdown Current into VIN
Quiescent Current into VIN
Enable
VIN
4.5
4.1
36
V
V
VIN_UVLO Rising threshold, TJ = -40℃ to +125℃
4.3
290
0.6
64
4.5
VUVLO_HYS Falling hysteresis
mV
μA
μA
ISHDN
IQ
VIN = 6V to 36V, VEN = 0V, TJ = -40℃ to +125℃
1.8
SGM61430, VIN = 12V, VFB = 0.9V, Non-switching
Enable Rising Threshold
Enable Hysteresis
VEN_H
TJ = -40℃ to +125℃
1.35
1.50
430
10
1.65
V
VEN_HYS
mV
nA
μA
VIN = 4.5V to 36V, VEN = 2V, TJ = -40℃ to +125℃
500
1
Input Leakage Current at EN Pin
Voltage Reference
IEN
VIN = VEN = 36V
TJ = +25℃
VIN = 6V to 36V
0.782
0.780
0.804
0.804
10
0.824
0.826
Reference Voltage
VREF
V
TJ = -40℃ to +125℃
Input Leakage Current at FB Pin
Internal LDO
ILKG_FB VFB = 0.8V
nA
Internal LDO Output Voltage
Current Limit
VCC
VIN = 6V to 36V, TJ = -40℃ to +125℃
4.6
5.0
5.3
V
Peak Inductor Current Limit
Valley Inductor Current Limit
Zero Cross Current Limit
Negative Current Limit (FPWM)
Integrated MOSFETs
IHS_LIMIT TJ = +25℃
ILS_LIMIT TJ = +25℃
5.0
2.2
5.9
2.9
6.8
3.5
A
A
A
A
IL_ZC
SGM61430
SGM61431
-0.04
-2.0
IL_NEG
High-side MOSFET On-Resistance
Low-side MOSFET On-Resistance
Thermal Shutdown
RDSON_HS VIN = 12V, IOUT = 0.5A
RDSON_LS VIN = 12V, IOUT = 0.5A
115
90
mΩ
mΩ
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSHDN
THYS
175
20
℃
℃
SG Micro Corp
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JANUARY 2023
4
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
TIMING REQUIREMENTS
(TJ = -40℃ to +125℃, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Hiccup Mode
Number of Cycles that LS Current Limit
is Tripped to Enter Hiccup Mode
(1)
NOC
128
30
Cycles
ms
Hiccup Retry Delay Time
tOC
Soft-Start
The time of internal reference to increase from
0V to 0.8V.
Internal Soft-Start Time
tSS
1.5
ms
NOTE: 1. Guaranteed by design.
SWITCHING CHARACTERISTICS
(TJ = -40℃ to +125℃, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SW (SW Pin)
Default Switching Frequency
Minimum Turn-On Time
Minimum Turn-Off Time
SYNC (EN/SYNC Pin)
SYNC Frequency Range
fSW
TJ = -40℃ to +125℃
310
390
110
80
470
kHz
ns
tON_MIN
tOFF_MIN
ns
fSYNC
VSYNC
200
2.8
2200
5.5
kHz
V
Amplitude of SYNC Clock AC Signal
(Measured at SYNC Pin)
Minimum SYNC Clock On/Off Time
tSYNC_MIN
100
ns
SG Micro Corp
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JANUARY 2023
5
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25℃, VIN = 12V, fSW = 390kHz, L = 10μH and COUT = 100μF, unless otherwise noted.
Efficiency vs. Load Current (SGM61430)
Efficiency vs. Load Current (SGM61431)
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
0
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 36V
VOUT = 5V, fSW = 390kHz
VOUT = 5V, fSW = 390kHz
0.001
0.01
0.1
Load Current (A)
1
10
0
0.5
1
1.5
2
2.5
3
Load Current (A)
Quiescent Current vs. Junction Temperature (SGM61430)
90
Current Limit vs. Junction Temperature (SGM61430/1)
7
HS
80
70
60
50
40
6
5
4
3
2
LS
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
VIN_UVLO Rising vs. Junction Temperature (SGM61430/1)
4.310
VIN_UVLO Hysteresis vs. Junction Temperature (SGM61430/1)
300
4.305
4.300
4.295
4.290
4.285
295
290
285
280
275
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Temperature (℃)
Temperature (℃)
SG Micro Corp
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JANUARY 2023
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, fSW = 390kHz, L = 10μH and COUT = 100μF, unless otherwise noted.
Load Regulation (SGM61430)
Load Regulation (SGM61431)
5.12
5.11
5.10
5.09
5.08
5.07
5.06
5.05
5.04
5.03
5.02
0.50
0.40
0.30
0.20
0.10
0.00
-0.10
-0.20
-0.30
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 36V
VOUT = 5V
0.0 0.5
VOUT = 5V
0.0 0.5
1.0
1.5
2.0
2.5
3.0
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Load Transient (SGM61430/1)
Steady State (SGM61430/1)
AC Coupled
VOUT
AC Coupled
VOUT
VSW
IOUT
IL
VIN = 12V, VOUT = 5V, IOUT = 0.3A to 3A, 2.5A/μs
VIN = 12V, VOUT = 5V, IOUT = 3A
Time (200μs/div)
Time (2μs/div)
Steady State (SGM61430)
Steady State (SGM61431)
AC Coupled
AC Coupled
VOUT
VOUT
VSW
VSW
IL
IL
VIN = 12V, VOUT = 5V, IOUT = 0A
VIN = 12V, VOUT = 5V, IOUT = 0A
Time (10ms/div)
Time (2μs/div)
SG Micro Corp
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JANUARY 2023
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, fSW = 390kHz, L = 10μH and COUT = 100μF, unless otherwise noted.
Start Up by VIN (SGM61430)
Start Up by VIN (SGM61431)
VOUT
VIN
VSW
IL
VOUT
VIN
VSW
IL
VIN = 12V, VOUT = 5V, IOUT = 0A
VIN = 12V, VOUT = 5V, IOUT = 0A
Time (1ms/div)
Time (800μs/div)
Start Up by VIN (SGM61430/1)
Start Up by EN (SGM61430/1)
VOUT
VOUT
VIN
EN
VSW
VSW
IL
IL
VIN = 12V, VOUT = 5V, IOUT = 3A
VIN = 12V, VOUT = 5V, IOUT = 3A
Time (1ms/div)
Time (1ms/div)
Start Up by EN (SGM61430)
Start Up by EN (SGM61431)
VOUT
EN
VSW
IL
VOUT
EN
VSW
IL
VIN = 12V, VOUT = 5V, IOUT = 0A
VIN = 12V, VOUT = 5V, IOUT = 0A
Time (1ms/div)
Time (800μs/div)
SG Micro Corp
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JANUARY 2023
8
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, fSW = 390kHz, L = 10μH and COUT = 100μF, unless otherwise noted.
Shutdown by VIN (SGM61430)
Shutdown by VIN (SGM61431)
VOUT
VIN
VSW
IL
VOUT
VIN
VSW
IL
VIN = 12V, VOUT = 5V, IOUT = 0A
VIN = 12V, VOUT = 5V, IOUT = 0A
Time (50ms/div)
Time (10ms/div)
Shutdown by VIN (SGM61430/1)
Shutdown by EN (SGM61430/1)
VOUT
VOUT
EN
VIN
VSW
IL
VSW
IL
VIN = 12V, VOUT = 5V, IOUT = 3A
VIN = 12V, VOUT = 5V, IOUT = 3A
Time (500μs/div)
Time (100μs/div)
Shutdown by EN (SGM61430)
Shutdown by EN (SGM61431)
VOUT
EN
VSW
IL
VOUT
EN
VSW
IL
VIN = 12V, VOUT = 5V, IOUT = 0A
VIN = 12V, VOUT = 5V, IOUT = 0A
Time (200ms/div)
Time (1s/div)
SG Micro Corp
www.sg-micro.com
JANUARY 2023
9
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, fSW = 390kHz, L = 10μH and COUT = 100μF, unless otherwise noted.
Short Protection (SGM61430/1)
Short Recovery (SGM61430/1)
VOUT
VOUT
VSW
IL
VSW
IL
VIN = 12V, VOUT = 5V, IOUT = short to 1A
VIN = 12V, VOUT = 5V, IOUT = 1A to short
Time (20ms/div)
Time (20ms/div)
SG Micro Corp
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JANUARY 2023
10
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
FUNCTIONAL BLOCK DIAGRAM
EN/SYNC
VCC
Enable Signal
EN Level
Detector
1pF
VIN
LDO
SYNC Signal
800kΩ
Boot Charge
50pF
Current
Sense
Minimum Clamp
Pulse Skip
Boot UVLO
BOOT
-
FB
Error Amplifier
+
+
HS MOSFET
Current
Comparator
SW
Power Stage
and
Dead Time
Control
Logic
0.804V
Reference
Voltage
VCC
Slope
Compensation
Soft-Start
Current
Sense
Overload
Recovery
Maximum
Clamp
LS MOSFET
Current Limit
SYNC Signal
Oscillator
PGND
AGND
Figure 2. Block Diagram
SG Micro Corp
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JANUARY 2023
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
DETAILED DESCRIPTION
Overview
The output voltage is sensed by a resistor divider
through FB pin and is regulated by feedback loop. This
voltage is compared to an accurate reference and the
voltage error signal is used as set point for an inner
current loop that adjusts the peak inductor current. The
input to the current loop is clamped to a fixed level to
limit the maximum peak current and is compared to the
actual peak current, sensed by the voltage drop across
the HS switch to control the HS switch on-time. The
loop internal compensation allows easy and stable
design of the power supply with a few external
elements for almost any output capacitor arrangement.
The SGM61430 and SGM61431 are 3A output
synchronous Buck converters with internal compensation
and peak current mode control. They can operate from
an input voltage range of 4.5V to 36V. These devices
need a few external components and provide an easy
and small size power supply solution for industrial
applications with good thermal performance. With 64μA
(TYP, SGM61430) quiescent current and 0.6μA (TYP)
shutdown current, they are also well suited for battery
powered applications.
Both devices normally operate at fixed 390kHz frequency.
At light load condition, the SGM61430 enters PFM mode
to keep high efficiency, and the SGM61431 maintains
FPWM mode to keep low output ripple and tight voltage
regulation at light loads. The normal frequency can be
synchronized to an external clock between 200kHz and
2.2MHz.
VSW
D = tON/tSW
VIN
tON
tOFF
t
0
-VD
tSW
IL
Accurate EN input threshold and internal soft-start time
(1.5ms TYP) add more design flexibility to these devices.
ILPK
IOUT
Additional features such as thermal shutdown, input
under-voltage lockout, cycle-by-cycle current limit, and
short-circuit protection (hiccup mode) are also provided.
ΔIL
t
0
Figure 3. Converter Switching Waveforms in CCM
Switching Frequency and Current Mode
Control
Output Voltage Setting
The Functional Block Diagram and basic waveforms of
these Buck synchronous converters are shown in
Figure 2 and Figure 3. The N-MOSFETs are used for
high-side (HS) and low-side (LS) (synchronous rectifier)
switches. The HS duty cycle (D = tON/tSW) is controlled
in closed loop to regulate and maintain the output
voltage at a constant level. The switching period is tSW
= 1/fSW, and the HS on-time is tON. When HS is turned
on, the SW node voltage sharply rises towards VIN, and
The output voltage can be stepped down to as low as
the 0.804V reference voltage (VREF). An external
feedback resistor divider along with the internal
reference is used to set the output voltage (VOUT) as
shown in Figure 4. The VREF is compared to the VFB
voltage and the control loop adjusts the duty cycle to
null the VREF - VFB.
VOUT
RFBT
the inductor current (IL) starts ramping up with (VIN
-
SGM61430/1
FB
VOUT)/L slope. When HS is turned off, the LS is turned
on after a very short dead time to avoid shoot-through,
and IL ramps down with -VOUT/L slope. When the
inductor current is continuous (either due to sufficient
load or FPWM), the output voltage is proportional to the
input voltage and duty cycle (VOUT = D × VIN) if
component parasitics are ignored.
RFBB
Figure 4. Output Voltage Setting
Use Equation 1 to calculate the output voltage:
VOUT - VREF
(1)
RFBT
=
×RFBB
VREF
SG Micro Corp
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JANUARY 2023
12
4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
DETAILED DESCRIPTION (continued)
The SGM61430/1 switching action can be synchronized to
an external clock from 200kHz to 2.2MHz. Figure 6
shows the device synchronized to an external system
clock.
Use 1% or higher quality resistors with low thermal
tolerance for an accurate and thermally stable output
voltage. The low-side resistor RFBB is selected based on
the desired current in the divider. Typically, a 10kΩ to
100kΩ resistor is selected for RFBB
.
VIN
Lower RFBB values increase loss and reduce light load
efficiency, however, improve VOUT accuracy in PFM.
Large RFBT values (>1MΩ) are not recommended
because the feedback path impedance will be too high
and more noise sensitive. If a large RFBT value is
necessary, the PCB layout design will be more critical
because the feedback path must be short and away
from noise sources such as SW node or inductor body.
SGM61430/1
RENT
EN/SYNC
RENB
Figure 5. Changing the System UVLO
EN/SYNC Input
The EN/SYNC pin is an input and must not be left open.
The simplest way to enable the device is to connect this
pin to VIN pin via a resistor. This allows for self-startup
of the SGM61430/1 when VIN > VIN_UVLO. This pin can
also be used to turn the device on or off with logic or
analog signals. If VEN < 1.07V (TYP), the device will
shut down. Only if VEN > 1.50V (TYP) the device will start
operation.
VIN
SGM61430/1
RENT
CSYNC
EN/SYNC
RENB
Clock
Source
The system UVLO level can be increased accurately
with a resistor divider (see Figure 5). This feature can
be used for power supply sequencing which is required
for proper power up of the system voltage rails. It can
also be used as protection, such as preventing supply
battery from depletion. Control of the enable input by
logic signals may also be used for sequencing or
protection.
Figure 6. Synchronization to External Clock
VSYNC
VSW
The EN/SYNC pin can also be used to synchronize the
internal oscillator to an AC coupled external clock (see
Figure 6). The SW cycles synchronize to the rising
edges of the clock. Synchronization range is from
200kHz to 2.2MHz. The clock signal peak-to-peak
voltage must exceed 2.8V to override the internal
oscillator but must be kept below 5.5V. Also the on and
off pulse widths of the clock must be at least 100ns
(TYP). 3.3V clock amplitude and CSYNC = 1nF (coupling
capacitor) should be sufficient for most designs. Keep
the RENT||RENB near 100kΩ range for stable syncing.
The RENT is necessary for external syncing but the RENB
is only needed for UVLO adjustment.
IL
Time (2μs/div)
Figure 7. Synchronizing in PWM Mode
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
DETAILED DESCRIPTION (continued)
BOOT (Bootstrap Voltage)
Due to losses in heavy load conditions there is a small
increase in duty cycle and the actual VIN_MAX is higher
than Equation 4 prediction.
The gate driver of the HS N-MOSFET switch requires a
voltage higher than VIN that is present on its drain. A
bootstrap voltage regulator is integrated to provide this
voltage which is powered by bootstrapping through a
small ceramic capacitor placed between the BOOT and
SW pins. CBOOT is charged in each cycle when the LS
switch is turned on (VSW ≈ 0V) and discharges to the
The minimum VIN is estimated by:
VOUT
(5)
V
=
IN_MIN
1 - fSW × tOFF_MIN
Compensation and Feed-Forward
Capacitor (CFF)
boot regulator when the HS switch is turned on (VSW
≈
VIN). A 0.47μF ceramic capacitor with 16V or higher
The SGM61430 and SGM61431 are internally
compensated (see Figure 2) and are stable over the
entire fSW and VOUT operating range. However, the
phase margin can be low for some ranges of VOUT when
low ESR ceramic capacitors are used in the output. In
such cases, it is recommended to use a feed-forward
capacitor (CFF) in parallel with the RFBT to improve the
transient response as shown in Figure 8.
rated voltage is recommended.
VCC Decoupling
The VCC pin is connected to the output of an LDO that
is integrated in the device and provides a 5V supply
(nominal) for the internal circuitry and MOSFET drivers.
It is intended for bypassing LDO output to ground and
should not be loaded. A 2.2µF to 10µF stable ceramic
capacitor rated for 16VDC or higher must be placed as
close as possible to VCC pin and grounded to the
exposed pad and ground pins. The device may be
damaged if VCC pin is shorted to ground during
operation.
VOUT
RFBT
CFF
SGM61430/1
FB
RFBB
Minimum On-Time and Off-Time
Figure 8. Improving Loop Compensation by
Feed-Forward Capacitor
The shortest duration for the HS switch on-time (tON_MIN
)
is 110ns (TYP). For the off-time (tOFF_MIN) the minimum
value is 80ns (TYP). The duty cycle (or equivalently the
VOUT/VIN ratio) range in CCM operation is limited by
tON_MIN and tOFF_MIN depending on the switching
frequency. The minimum and maximum allowed duty
cycles are given by Equations 2 and 3:
The CFF in parallel with RFBT places an additional zero
before the loop cross over frequency and boosts the
phase margin. The zero will be located at:
1
(6)
fZ_CFF
=
2π×CFF ×RFBT
DMIN = tON_MIN × fSW
(2)
Refer to Table 1 for a list of suitable COUT, CFF and RFBT
combinations. If for similar COUT values, other RFBT
values are used, adjust the CFF such that (CFF × RFBT) is
unchanged. CFF must also be modified if COUT is
changed. For COUT capacitors with lower ESR, larger
CFF values are needed. For example, with electrolytic
capacitors (large ESR), the location of ESR zero,
(Equation 7), is typically low enough for phase boost at
crossover and CFF is not needed.
and
D
MAX = 1 - tOFF_MIN × fSW
(3)
Note that the duty cycle has a more limited range at
higher frequencies. DMAX limits the lowest VIN voltage
for a given VOUT
.
For any given output voltage, the switching frequency is
an important factor to maximize efficiency and input
voltage range and minimize solution size. The highest
input voltage can be calculated from:
1
(7)
fZ_ESR
=
2π×COUT ×ESR
VOUT
(4)
V
=
IN_MAX
fSW × tON_MIN
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
DETAILED DESCRIPTION (continued)
Continuous Conduction Mode (CCM)
In CCM, the frequency is fixed and the output voltage
ripple will be minimal. The maximum output current of
3A is supplied in CCM.
Note that CFF increases the feedback of the output
ripple and the coupled noise to the FB node. A large
CFF value can deteriorate the VOUT regulation. If
significant derating for the CFF value at cold operating
temperatures is expected, it is better to use larger COUT
capacitance rather than increasing the nominal CFF
value.
Light Load Operation with PFM (SGM61430)
If the output current of the SGM61430 falls below ∆IL/2,
its operating mode changes to DCM (also called diode
emulation mode or DEM). In DCM, the LS switch is
turned off when its current reverses direction and drops
to IL_ZC (IL_ZC = -40mA TYP). Switching and conduction
losses in DCM are lower than FPWM operation at light
load condition, even before entering PFM.
Thermal Shutdown (TSD)
If the junction temperature exceeds +175℃ (TYP), the
device will shut down. It will recover automatically with
a normal power up sequence and soft-start when the
temperature falls below +155℃ (TYP).
At light load condition, the device enters PFM to keep
its high efficiency. PFM is activated when the HS switch
reaches its minimum on-time (tON_MIN) or minimum peak
current (inductor IPEAK_MIN = 300mA TYP). In PFM, fSW is
reduced to maintain regulation. With reduced frequency,
the switching losses are also dropped and efficiency is
improved. There is no synchronization to the external
clock in PFM mode.
Functional Modes
Shutdown Mode
The EN input controls the device on/off condition. If VEN
< 1.07V (TYP), the device will shut down. The device
will also turn off if either VIN or VCC falls below its UVLO
threshold.
Active Mode
If VEN is above its precision threshold, and VIN and VCC
are above their UVLO levels, the device will be
activated. EN pin can be connected to VIN to allow
self-startup when VIN voltage is in the 4.5V to 36V
operating range. VCC, UVLO and EN/SYNC settings in
active mode are explained in the previous sections.
Light Load Operation with FPWM (SGM61431)
For FPWM option, SGM61431 is locked in PWM mode
from full load to no load. Negative inductor currents are
allowed at light load to continue PWM operation. It is a
tradeoff that sacrifices light load efficiency for lower
output ripple, better output regulation and keeping
switching frequency fixed. To avoid fatal negative
These operating modes are possible depending on the
load current: (∆IL = inductor peak-to-peak current ripple)
current in the LS switch, this current is limited at IL_NEG
.
1. CCM: Fixed frequency continuous conduction mode:
both SGM61430 and SGM61431 can operate in CCM
when IOUT > ∆IL/2.
Synchronization is available over the full load range in
the FPWM mode.
2. DCM: Fixed frequency discontinuous conduction mode:
only for SGM61430 (PFM).
3. PFM: Pulse frequency modulation (SGM61430 only):
the switching frequency reduces at very light load
operation, when HS switch reaches its minimum
on-time or IPEAK_MIN falls below 300mA (TYP).
4. FPWM: Forced pulse width modulation mode for
SGM61431 only: it operates with fixed frequency at
light load operation.
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
DETAILED DESCRIPTION (continued)
Over-Current Protection (OCP) and
Short-Circuit Protection (SCP)
Cycle-by-cycle current limit for both peak and valley
currents (upper and lower switches peak currents) are
included in the SGM61430/1. If the OCP or SCP
persists, it will enter hiccup mode to avoid thermal
shutdown.
is still higher than its limit (ILS_LIMIT) and keeps
conducting until the current falls below ILS_LIMIT. During
OCP or SCP, the LS current limit is not effective until
the HS current limit is triggered.
A short dead time is considered after the LS switch is
turned off, in which both switches are kept off and then
a new cycle starts by turning the HS switch on.
The HS switch over-current protection is natural in peak
current mode control. In each cycle the HS current
sensing starts a short time (blanking time) after it is
turned on. The slope compensation ramp is deducted
from the EA (Error Amplifier) output to avoid sub
harmonic oscillations and the result is compared to the
HS current to determine the HS turn-off time (on-time).
See Figure 2 for details. Before comparison, the EA
output is clamped to a fixed maximum threshold
(IHS_LIMIT) to limit the current. So, the peak current limit
of the high-side switch is not affected by the slope
compensation and remains constant over the full duty
cycle range.
If the LS switch over-current detection continues for
128 successive cycles, hiccup current protection will be
started in which the regulator remains off for 30ms
(TYP) before restarting the converter. If OCP or SCP is
still detected after this restart, a new hiccup cycle will
be repeated. Hiccup mode is considered to protect the
device from overheating and damage in severe
over-current conditions.
In the SGM61431 (FPWM option), the inductor current
can go negative at light load or during transients. For
this device, the LS switch current is limited by negative
current (IL_NEG) and if the magnitude of the negative
current exceeds this limit, the LS switch will turn off until
the next cycle to protect the switch from large currents.
When the LS switch turns on the inductor current starts
falling. The LS current is sensed while it is on and the
switch will not turn off at the end of cycle if this current
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
APPLICATION INFORMATION
The design method and component selection for the
SGM61430/1 Buck converters are explained in this
section. Schematic of a basic design is shown in Figure
9. Only a few external components are needed to
provide a constant output voltage from a wide input
voltage range.
component selection. Consider the following notes
when using this table.
1. Choose the inductance for VIN = 36V.
2. COUT values in the table are actual derated values.
Use higher nominal values for ceramic capacitors.
3. Use RFBT = 0Ω to set VOUT = 0.804V. Use RFBB
14.3kΩ for any other VOUT setting.
=
The external components are designed based on the
application requirements and device stability. Some
suitable output filters (L and COUT) along with CFF and
RFBT values are provided in Table 1 to simplify
4. If any other RFBT value is designed, resize CFF to
keep (CFF × RFBT) unchanged.
5. If the selected output capacitance has high ESR, the
CFF is not necessary for extra phase boost.
7
2
VIN
VIN
BOOT
R4
C1
C1A
C1B
10Ω
10μF
10μF
0.22μF
SGM61430/1
C4
R3
402kΩ
0.47μF
1
L1 10μH
VOUT
5V
5
3
GND
SW
FB
EN/SYNC
VCC
C2
C2A
C2B
47μF
47μF
4.7μF
C5 56pF
4
C3
2.2μF
R1 75kΩ
R2
14.3kΩ
GND
8
6
GND
GND
GND
Figure 9. SGM61430/1 Basic Application Schematic
Table 1. Some Typical L, COUT and CFF Values for Stable Operation
fSW (kHz)
390
VOUT (V)
L (µH)
6.8
10
COUT (µF)
150
CFF (pF)
RFBB (kΩ)
14.3
RFBT (kΩ)
44.2
75
3.3
5
75
56
-
390
100
14.3
390
12
24
15
68
14.3
200
390
15
47
-
14.3
412
Design Requirements
The design process will be explained by an example with the required input parameters listed in Table 2.
Table 2. Design Example Parameters
PARAMETER
Input Voltage (VIN)
Output Voltage (VOUT
SGM61430/1
12V (TYP), variation range is from 8V to 28V
)
5V
3A
Maximum Output Current (DC) (IOUT_MAX
Transient Response (0.3A to/from 3A)
Output Voltage Ripple
)
5% (VOUT drop/rise)
50mV
Input Voltage Ripple
400mV
Switching Frequency (fSW
)
390kHz
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
APPLICATION INFORMATION (continued)
4× I - IOL
Input Capacitor
(
)
OH
(10)
(11)
COUT
>
>
High frequency decoupling on the input supply pins is
necessary for the device. A bulk capacitor may also be
needed in some applications. Typically, 10μF to 22μF
high quality ceramic capacitor (X5R, X7R or better) with
voltage rating twice the maximum input voltage is
fSW × VUS
IO2 H - IO2 L
COUT
×L
2
V
OUT + VOS - VO2UT
In this example, maximum acceptable ripple is 50mV.
Assuming ΔVOUT_ESR = ΔVOUT_C = 50mV and KIND = 0.4.
Equation 8 results in ESR < 41.7mΩ and Equation 9
leads to COUT > 7.5μF. If the overshoot/undershoot
transient requirement is 5% then VUS = VOS = 5% × VOUT
= 250mV. Equations 10 and 11, IOH = 2.5A, IOL = 0.2A,
lead to COUT > 94μF and COUT > 24μF respectively. Now
considering all conditions and including voltage
derating of the ceramic capacitors, COUT is composed of
recommended for decoupling capacitor. If the source is
away from the device (> 5cm) some bulk capacitance is
also needed to damp the voltage spikes caused by the
wiring or PCB trace parasitic inductances. In this
example, 2×10μF/50V/X7R capacitors and a 0.1μF
ceramic capacitor placed right beside the device VIN
and GND pins for very high-frequency filtering are
used.
a
47μF/16V ceramic capacitor parallel with
a
Output Capacitor
100μF/10V capacitor with 5mΩ ESR.
The main factors for designing COUT are output voltage
ripple, control loop stability and the magnitude of output
voltage overshoot/undershoot after a load transients.
Output Voltage Setting
An external resistor divider is used to set the output
voltage as shown in Figure 8. Use Equation 12 to set
The output voltage ripple has two main components.
One is due to the ac current (ΔIL) going through the
capacitor ESR:
VOUT
:
VOUT - VREF
VREF
(12)
RFBT
=
×RFBB
(8)
ΔVOUT_ESR = ΔIL ×ESR = KIND ×IOUT ×ESR
where VREF = 0.804V is the internal reference. For
example, by choosing RFBB = 14.3kΩ, the RFBT value for
5V output will be calculated as 75kΩ.
and the other one is caused by the charge and
discharge of capacitor by the ac current (ΔIL):
ΔIL
KIND ×IOUT
(9)
ΔVOUT_C
=
=
Switching Frequency
8× fSW ×COUT
8× fSW ×COUT
The SGM61430/1 switching frequency is 390kHz (TYP).
However, it can be modified by synchronizing to an
external clock in the 200kHz to 2.2MHz range. It may
also drop due to PFM operation.
These AC components are not in phase and the total
peak-to-peak ripple is less than ∆VOUT_ESR + ∆VOUT_C
.
In many applications, tight regulation in response to
large and fast load transients is required. This can be a
more severe condition on designing COUT value.
Typically the control loop recovers the output voltage
after four or five cycles and COUT should be large
enough to provide the difference between current
received from inductor and the current delivered to the
load during this period. The minimum capacitance
needed to limit the undershoot to VUS when the load
steps up from IOL to IOH is given in Equation 10. Similarly,
when the load steps from IOH down to IOL, COUT should
be large enough to absorb the extra energy coming
from the inductor without a large voltage overshoot (VOS)
as calculated in Equation 11:
Inductor
Three main inductor parameters that need to be
designed are inductance, saturation current and rated
current. The DCR is also an important factor for
efficiency. Physical dimensions, form factor and
shielded or non-shielded structure are other important
factors that are selected based on the application. The
inductance is designed by selecting the peak-to-peak
current ripple (ΔIL) that is given by Equation 13. ΔIL is
increase at higher input voltages, so VIN_MAX is used in
the equation. The minimum required inductance (LMIN
)
is calculated from Equation 14. KIND represents the ratio
of inductor ripple current to the maximum output current
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
APPLICATION INFORMATION (continued)
(KIND =ΔIL/IOUT_MAX). It is typically chosen between 20%
For slightly larger ESR values, choose a CFF value that
is less than Equation 16 estimate. For larger ESR values,
CFF is not needed. Table 1 gives a quick starting point.
In this example, a 56pF/50V/COG is selected for CFF.
to 40%.
VOUT
×
V
- VOUT
(
)
IN_MAX
(13)
(14)
ΔIL =
VIN_MAX × L × fSW
Bootstrap Capacitor
V
− VOUT
VOUT
VIN _ MAX × fSW
IN _ MAX
The bootstrap capacitor powers the floating power
MOSFET driver. It is recommended to use
0.47μF/16V/X5R ceramic capacitor.
LMIN
=
×
IOUT ×KIND
During a short or over current, either RMS or peak
inductor current can increase significantly. The inductor
rated RMS and saturation current ratings should be
higher than those peaks respectively. It is generally
desired to choose an smaller inductance value to have
faster transient response, smaller size, and lower DCR.
However, reducing the inductance increases the
current ripple that may result in over current detection
and triggering OCP before reaching full load current.
Moreover, higher current ripple increases core,
conduction, and capacitor losses. Output voltage ripple
will also be higher with the same output capacitance. In
general, choosing a too small inductance is not
recommended for peak current mode control. On the
other hand, too large inductance is also not
recommended, because the reduced current ripple
degrades the comparator signal to noise ratio.
The value of BST resistor generally is recommended to
be in the range from 0 to 10Ω. BST resistor determines
the turning on speed of the high side MOSFET. For the
design where the critical path layout could not be
optimized and follow the recommended layout, the 10Ω
BST resistor is recommended to be used to in series
with the Bootstrap capacitor.
VCC Decoupling Capacitor (LDO Output)
Use a 2.2μF/16V/X7R capacitor for decoupling VCC to
assure stability of the device. It must be placed with
minimum distance between VCC and GND pins.
VIN UVLO Adjustment
The system UVLO threshold can be increase using two
external resistors RENT and RENB (see Figure 5) to form
a voltage divider between VIN and EN pins. The UVLO
comparator provides a rising threshold (power-up) and
a falling threshold (power-down) for VIN. Use Equation
17 to set the UVLO rising threshold.
Selecting KIND = 0.4 results in LMIN = 8.78µH. A 10μH
ferrite inductor with 5A RMS rating and 7.6A saturation
current is selected as the closest standard value.
RENT + RENB
(17)
= VEN_H ×
V
IN_RISING
Designing Feed-Forward Capacitor
RENB
Even though the SGM61430/1 are internally
compensated, with low ESR ceramic capacitors, the
phase margin can be low depending on the VOUT and
fSW values. By adding an external feed-forward
capacitor (CFF) in parallel with the RFBT, the phase
margin can be improved (phase boost around
crossover frequency). Without CFF, and if ESR is very
small, the crossover frequency (fX) can be estimated
from Equation 15, in which COUT is the actual derated
value:
V
EN_H is the EN rising threshold (1.50V TYP). Choose a
large value for RENB (e.g., 287kΩ), to minimize supply
drain. The RENT value is given by:
V
IN_RISING
(18)
RENT
=
- 1 ×R
ENB
VEN_H
The resulting falling threshold can be calculated from:
RENT + RENB
(19)
V
= V
- VEN_HYS
×
(
)
IN_FALLING
EN_H
RENB
8.32
(15)
VOUT ×COUT
In which the VEN_HYS is 0.43V (TYP).
fX =
In this example, VIN_RISING = 6.0V is needed that results
Then CFF value can be estimated from:
in RENT = 853kΩ and a UVLO falling threshold of 4.29V.
1
(16)
CFF
=
4π× fX ×RFBT
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
Synchronous Buck Converters
APPLICATION INFORMATION (continued)
Layout Example
Layout
Consider the following layout design guidelines for a
high-quality power supply with good thermal and EMI
performances.
VOUT
GND
1. Place CINx as close as possible to the VIN and PGND
pins. CINx and COUTx returns should be close together
and connected on the top layer PGND pin/plane and
PAD.
L
RFBB
CFF
RFBT
SW
2. Place CVCC bypass capacitor right beside the VCC
and ground pins on the top layer.
CIN3
CIN2
COUT COUT2 COUT3
3. Minimize FB trace length and keep both feedback
resistors close to the FB pin. Bring the VOUT sense trace
from the point where VOUT accuracy is important and
keep it away from the noisy nodes (SW), preferably
through another layer that is on the other side of a
CIN1
VIN
GND
shield layer. Place CFF right beside RFBT
.
4. Use one of the mid-layers as ground plane for noise
shielding and extra path for heat dissipation.
Figure 10. Top Layer
5. Connect the ground layer to only one ground point
on the top layer. The feedback and enable circuit
returns must be routed separately through the ground
plane to avoid large load currents or high di/dt switching
currents to flow in these sensitive analog ground traces.
Bad grounding results in poor regulation and erratic
output ripple.
GND
6. Choose wide traces for VIN, VOUT and ground to
minimize voltage drops and maximize efficiency.
7. Use an array of thermal vias (e.g., 8 filled vias) under
the exposed pad and connect them to the ground
planes on mid-layers and the bottom layer. Maximize
the heat sinking copper areas and solidify them with
metal coatings such that the die temperature remains
below +125℃ in all operating conditions.
GND
Figure 11. Bottom Layer
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4.5V to 36V Input, 3A,
SGM61430/SGM61431
REVISION HISTORY
Synchronous Buck Converters
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
JANUARY 2023 ‒ REV.A.2 to REV.A.3
Page
Changed Detailed Description ...........................................................................................................................................................................16
JULY 2022 ‒ REV.A.1 to REV.A.2
Page
Added thermal information...................................................................................................................................................................................2
JANUARY 2022 ‒ REV.A to REV.A.1
Page
Added SGM61431 part......................................................................................................................................................................................All
Changes from Original (SEPTEMBER 2021) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
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PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
SOIC-8 (Exposed Pad)
D
e
3.22
E1
E
E2
2.33 5.56
1.91
b
D1
1.27
0.61
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
A1
c
θ
A2
Dimensions
In Millimeters
Symbol
MIN
MOD
MAX
1.700
0.150
1.650
0.510
0.250
5.100
3.420
4.000
6.200
2.530
A
A1
A2
b
0.000
1.250
0.330
0.170
4.700
3.020
3.800
5.800
2.130
-
-
-
c
-
D
-
D1
E
-
-
E1
E2
e
-
-
1.27 BSC
L
0.400
0°
-
-
1.270
8°
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
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PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
SOIC-8
(Exposed Pad)
13″
12.4
6.40
5.40
2.10
4.0
8.0
2.0
12.0
Q1
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PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
相关型号：
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