SI5381A-D04991-GM_技术文档

Si5381/82 Data Sheet

Multi-DSPLL Wireless Jitter Attenuator / Clock Multiplier with

Ultra-Low Noise

KEY FEATURES

• Supports simultaneous Ethernet, CPRI and

general-purpose clocking in a single device

The Si5381/82 is an ultra high performance wireless jitter attenuator with multiple

DSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) ap-

plications. The industry’s first multi-PLL wireless jitter attenuator device is capable of

replacing multiple discrete, high performance, VCXO-based jitter attenuators with a

fully integrated single chip solution. The featured multi-PLL architecture supports in-

dependent timing paths for Ethernet and CPRI (Common Public Radio Interface)

clock cleaning , and generates any low-jitter, general-purpose clocks. The fixed fre-

quency oscillator provides frequency stability for free-run and holdover modes. This

all-digital solution provides superior performance that is highly immune to external

board disturbances such as power supply noise.

• Input frequency range:

• Differential: 8 kHz - 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range:

• CPRI: up to 2.94912 GHz

• Other differential: up to 735 MHz

• LVCMOS: up to 250 MHz

• Ultra-low RMS jitter:

• 72 fs typ (12 kHz–20 MHz)

Applications:

• Phase noise of 122.88MHz carrier frequency:

• 118 dBc/Hz @ 100Hz offset

• Wireless Infrastructure

• eCPRI RRH (Remote Radio Head)

• BBU (Baseband Unit)

• DU (Distribution Unit)

• Test and Measurement

• ITU-T G.8262 compliant

54 MHz

OSC

÷INT

t

OUT0A

IN_SEL

t

÷INT

OUT0

OUT1

OUT2

DSPLL

B

14.7456 GHz

PLL

IN0

IN1

IN2

IN3

÷INT

t

DSPLL

A

÷INT

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT9A

Si5382

DSPLL

C

DSPLL

D

Any-Rate

PLLs

Si5381

NVM

I²C/SPI

Control

Status

Status Flags

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Table of Contents

1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1.1 Si5381/82 CPRI Frequency Configuration . . . . . . . . . . . . . . . . . . . 6

3.1.2 Si5381/82 Configuration for Wireless Clock Generation . . . . . . . . . . . . . . . 7

3.2 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4.1 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.2 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.3 Lock Acquisition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.4 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.4.6 VCO Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.5 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6 Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.6.1 Manual Input Switching (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . .12

3.6.2 Automatic Input Selection (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . .13

3.6.3 Hitless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6.4 Ramped Input Switching . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6.5 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6.6 Input Configuration and Terminations . . . . . . . . . . . . . . . . . . . . .14

3.7 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.1 Input LOS Detection. . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.2 Reference Clock LOS Detection. . . . . . . . . . . . . . . . . . . . . . .15

3.7.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.7.4 LOL Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.7.5 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.8 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.8.1 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.8.2 Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.8.3 Output Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.8.4 Programmable Common Mode Voltage For Differential Outputs . . . . . . . . . . . .21

3.8.5 LVCMOS Output Impedance and Drive Strength Selection. . . . . . . . . . . . . .22

3.8.6 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . .22

3.8.7 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . .22

3.8.8 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.8.9 Output Disable During LOL . . . . . . . . . . . . . . . . . . . . . . . .22

3.8.10 Output Disable During Reference LOS . . . . . . . . . . . . . . . . . . . .22

3.8.11 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . .22

3.8.12 Synchronous Output Disable Feature . . . . . . . . . . . . . . . . . . . .23

3.8.13 Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .23

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3.8.14 Output Divider (R) Synchronization . . . . . . . . . . . . . . . . . . . . .23

3.9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.10 In-Circuit Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.11 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.12 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .24

3.13 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory

Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .24

4. Register Map

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.2 High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . .26

5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 40

7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8. Typical Operating Characteristics

9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

. . . . . . . . . . . . . . . . . . . . . .42

10.1 Si5381/82 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . .50

11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

14. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 55

14.1 Revision 0.96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

14.2 Revision 0.95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

14.3 Revision 0.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

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Rev. 0.96 | 3

Si5381/82 Data Sheet

Features List

1. Features List

The Si5381/82 features are listed below:

• ITU-T G.8262 compliant

• Highly configurable outputs compatible with LVDS, LVPECL,

LVCMOS, CML, and HCSL. CML outputs can be programmed

to have 100-1600 mVpp single-ended swing.

• Digital frequency synthesis eliminates external VCXO and ana-

log loop filter components

• Status monitoring (LOS, OOF, LOL)

• DSPLL_B supports high-frequency, CPRI clocking. Remain-

ing DSPLLs support Ethernet and general-purposing clock- • Pin controlled input switching

ing

• Optional zero delay mode

• Input frequency range:

• Hitless input clock switching: automatic or manual

• Differential: 8 kHz to 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range:

• Automatic free-run and holdover modes

• Fastlock feature

• Core voltage:

• CPRI: up to 2.94912 GHz with JESD204B support

(DSPLL_B)

• VDD: 1.8 V ±5%

• VDDA: 3.3 V ±5%

• Other differential: up to 735 MHz (DSPLL_A/C/D)

• LVCMOS: up to 250 MHz

• Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V

• Output-output skew: 75 ps max

• Serial interface: I2C or SPI

• Ultra-low RMS jitter (12kHz - 20MHz):

• 72 fs typ at 122.88 MHz (DSPLL_B)

• 88 fs typ at 156.25 MHz (DSPLL_A/C/D)

• 79 fs typ at 322.265625 MHz (DSPLL_A/C/D)

• In-circuit programmable with non-volatile OTP memory

• ClockBuilder ProTM software simplifies device configuration

• Temperature range: –40 to +85 °C

• Pb-free, RoHS-6 compliant

• Typical phase noise of 122.88 MHz carrier frequency

(DSPLL_B):

• -118 dBc/Hz @ 100 Hz offset

• -133 dBc/Hz @ 1 kHz offset

• -142 dBc/Hz @ 10 kHz offset

• -149 dBc/Hz @ 100 kHz offset

• -154 dBc/Hz @ 1 MHz offset

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Rev. 0.96 | 4

Si5381/82 Data Sheet

Ordering Guide

2. Ordering Guide

Table 2.1. Ordering Guide

Number of Maximum Output Frequency

Clock In-

Ordering Part

Number

Refer-

ence

#

RoHS-6,

Pb-Free

Temperature

Range

Package

Other

DSPLL

puts/

CPRI Clocks

Clocks

Outputs

Si5381A-E-GM

Si5382A-E-GM

XO

4

2

4 / 12

2.94912 GHz

735 MHz

64-Lead

9x9 mm

QFN

Yes

–40 to +85 °C

Si5381A-E-EVB

Si5382A-E-EVB

Note:

Evaluation Board

1. Add an “R” at the end of the device to denote tape and reel options.

2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by ClockBuilder Pro. Part number

format is: Si5381E-Exxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration.

Figure 2.1. Ordering Part Number Fields

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Rev. 0.96 | 5

Si5381/82 Data Sheet

Functional Description

3. Functional Description

The Si5381/82 integrates four/two any-frequency DSPLLs in a monolithic IC for applications that require a combination of CPRI, Ether-

net, and general-purpose clocking. Any clock input can be routed to any DSPLL. The output of any DSPLL can be routed to any of the

device clock outputs. Based on 4th generation DSPLL technology, the Si5381/82 provides a clock-tree-on-a-chip solution for applica-

tions that need a mix of different clock frequencies. DSPLL B acts as the high-frequency DSPLL, typically used for CPRI clocks while

DSPLLs A/C/D act as Ethernet and general purpose DSPLLs.

As shown in the figure below, the DSPLL_B of Si5381/82 is locked to it's reference input. The output is then supplied to DSPLLs A/C/D.

The benefit is a more efficient and cost effective, lower-jitter yet frequency flexible clock-tree in a chip architecture. However, it should

be noted that large transients or loss of lock on DSPLL_B could have some minor impact on DSPLLs A/C/D. It is recommended that

DSPLLs A/C/D loop bandwidth be set to > 10 times DSPLL_B's loop bandwidth for optimal tracking. Please consult with Silicon Labs

applications engineering for optimal settings for any given frequency plan.

54 MHz

OSC

DSPLL_B

Output

DSPLL_B

Input

DSPLL_B

DSPLLs

A/C/D

DSPLL A/C/D

Outputs

DSPLLs A/C/D

Inputs

Figure 3.1. High-frequency DSPLL

3.1 Frequency Configuration

The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile

memory. DSPLL_B generates CPRI frequencies. For DSPLL_A/C/D, fractional frequency multiplication (Mn/Md) allows each of the

DSPLLs to lock to any input frequency and generate virtually any output frequency. However, DSPLL_A,C,D are not recommended to

generate CPRI clocks as the performance is not as good as when using DSPLL_B, which is optimized for its frequencies. All divider

values for a specific frequency plan are easily determined using the ClockBuilder Pro utility. The Si5382 supports one Ethernet or gen-

eral-purpose DSPLL (DSPLL_A).

3.1.1 Si5381/82 CPRI Frequency Configuration

The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.

The combination of flexible integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies

for applications that require ultra-low phase noise and spurious performance. The table below shows a list of possible output frequen-

cies for wireless applications. Note that these CPRI frequencies may be generated with an Ethernet input clock to DSPLL_B. These

frequencies are distributed to the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10

unique integer-ratio related frequencies on the Si5381/82. The ClockBuilder Pro software utility provides a simple means of automati-

cally calculating the optimum divider values (P, M, N and R) for the frequencies listed in the table below.

Table 3.1. Example of Possible Wireless Clock Frequencies

Device Clock Frequencies Fout (MHz)

15.36

19.20

30.72

38.40

61.44

76.80

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Si5381/82 Data Sheet

Functional Description

Device Clock Frequencies Fout (MHz)

122.88

153.60

184.32

245.76

307.20

368.64

491.52

614.40

737.28

983.04

1228.80

1474.56

2949.12

3.1.2 Si5381/82 Configuration for Wireless Clock Generation

The Si5381/82 can be used as a high performance, fully integrated wireless jitter cleaner while eliminating the need for discrete VCXO

and loop filter components. The Si5381/82 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks

(DCLK) and system reference clocks (SYSREF). The clock outputs can be independently configured as device clocks or SYSREF

clocks to drive JESD204B converters, FPGAs, or other logic devices. An example frequency configuration is shown in the figure below.

In this case, N and R dividers determine both device and sysref frequencies. The SYSREF clock is always periodic and can be control-

led (on/off) without glitches by enabling or disabling its output through register writes.

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Si5381/82 Data Sheet

Functional Description

Si5381/82

VDDO3

OUT3

OUT3b

÷R₃

÷R₄

VDDO4

OUT4

OUT4b

Device

Clocks

&

SYSREF

(Group 1)

÷N₁

VDDO5

OUT5

OUT5b

÷R₅

÷R₆

÷R₇

÷R₈

VDDO6

OUT6

OUT6b

From

DSPLL B

VDDO7

OUT7

OUT7b

VDDO8

OUT8

OUT8b

Device

Clocks

&

÷N₄

SYSREF

(Group 2)

OUT9

OUT9b

÷R₉

OUT9A

OUT9Ab

÷R_9A

VDDO9

VDDO1

OUT1

OUT1b

÷R₁

÷R₂

VDDO2

OUT2

OUT2b

From DSPLL

A/C/D

Ethernet,

Processor

Clocks

VDDO0

OUT0A

OUT0Ab

÷R_0A

÷R₀

OUT0

OUT0b

Figure 3.2. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks

3.2 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-

tings in the range of 1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always

remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.

3.3 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g., 1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a

temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable

the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The DSPLL

will revert to its normal loop bandwidth once lock acquisition has completed.

3.4 Modes of Operation

Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or

Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.3 Modes of Operation on page 9. The follow-

ing sections describe each of these modes in greater detail.

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Rev. 0.96 | 8

Si5381/82 Data Sheet

Functional Description

3.4.1 Initialization and Reset

Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks are generated until the initialization is complete. There are two types of resets available. A hard reset

is functionally similar to a device power-up. All registers are restored to the values stored in NVM, and all circuits including the serial

interface is restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset register bit. A soft

reset bypasses the NVM download. It is simply used to initiate register configuration changes.

Power-Up

Reset and

Initialization

No valid

input clocks

selected

Free-run

Valid input clock

selected

An input is

qualified and

available for

selection

Lock Acquisition

(Fast Lock)

Phase lock on

selected input

clock is achieved

An input is

qualified and

available for

selection

VCO Freeze

State

Locked

Mode

No valid input

clocks available

for selection

Holdover

Mode

Input Clock

Switch

Selected input

clock fails

Yes

No

Other Valid

Clock Inputs

Available?

Yes

Holdover

History

Valid?

No

Figure 3.3. Modes of Operation

3.4.2 Freerun Mode

The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency ac-

curacy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the reference clock on the

XA/XB pins. For example, if the oscillator stability is ±50 ppm, then all the output clocks will be generated at their configured frequency

with ±50 ppm stability in freerun mode. Any drift of the oscillator frequency is tracked at the output clock frequencies. Free run mode is

maintained as long as no input clocks are valid.

3.4.3 Lock Acquisition Mode

The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL automatically starts

the lock acquisition process. If the fast lock feature is enabled, the DSPLL acquires lock using the Fastlock Loop Bandwidth setting and

then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition, the output generates a

clock that follows the VCO frequency change as it pulls in to the input clock frequency.

3.4.4 Locked Mode

Once locked, the DSPLL generates output clocks that are both frequency and phase locked to their selected input clocks. At this point,

any oscillator frequency drift does not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is achieved.

See 3.7.4 LOL Detection for more details on the operation of the loss-of-lock circuit.

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Si5381/82 Data Sheet

Functional Description

3.4.5 Holdover Mode

If holdover history is valid, the DSPLL automatically enters holdover mode when the selected input clock becomes invalid and no other

valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to mini-

mize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL

stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is

calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are program-

mable as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows

ignoring frequency data that may be corrupt just before the input clock failure.

Clock Failure and Entry

into Holdover

Historical Frequency Data Collected

time

Programmable historical data window used to

determine the final holdover value

Programmable delay

120 seconds

0

Figure 3.4. Programmable Holdover Window

When entering holdover, the DSPLL pulls its output clock frequency to the calculated averaged holdover frequency. While in holdover,

the output frequency drift is entirely dependent on the external reference clock connected to the XA/XB pins. If the clock input becomes

valid, the DSPLL automatically exits the holdover mode and re-acquires lock to the new input clock. This process involves pulling the

output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is glitchless and its rate is control-

led by the DSPLL or the Fastlock bandwidth.

The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference be-

tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-

ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40

values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit

from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on

ramped input switching, see 3.6.4 Ramped Input Switching.

Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable

holdover exit BW.

3.4.6 VCO Freeze Mode

If there are no valid clock inputs available for selection and the holdover history is not valid, the DSPLL automatically enters VCO

Freeze mode. The DSPLL uses the last measured input frequency to set the output frequencies in VCO Freeze mode. If a valid input

clock appears, the DSPLL automatically exits VCO Freeze mode and reacquires a lock to the new input clock.

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Si5381/82 Data Sheet

Functional Description

3.5 External Reference (XA/XB)

An external crystal oscillator (XO) is required to set the reference for the Si5381/82. Only a 54 MHz XO is used as the reference to the

wireless jitter attenuator. For the jitter and phase noise performance that is specified in this data sheet, only the recommended 54 MHz

XO's specified for the Si5380/81/82/86 can be used in the Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Ref-

erence Manual.

Place the XO as close to the XaXb pins as possible. See figure below for guidelines on how to connect the XO to the XaXb input. C1

increases the slew rate to the Xa input, which is needed to get the jitter and phase noise performance that is specifed in this data sheet.

XO/Clock

Appro. Vpp @ XAInput

XO VDD

3.3V

2.5V

R1

R2

C1

453 Ω

274 Ω

549 Ω

732 Ω

12 pf

30 pf

1.8V

C1

R1

Note: 2.5 Vpp

diff max

0.1 uf

R2

Note: 2.0 Vpp_se max

50

0.1 uf

XB

0.1 uf

nc nc

X1

XB

XA

X2

XA

X2

2xC_L

OSC

÷ P^REF

Differential XO/Clock

Connection

Single-Ended XO/Clock

Connection

Figure 3.5. XA/XB Input

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Si5381/82 Data Sheet

Functional Description

3.6 Inputs (IN0, IN1, IN2, IN3)

There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and single-ended clocks.

A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs as shown in the figure

below.

Input Crosspoint

IN0

0

÷P₀

IN0b

DSPLL

1

2

A

3

0

IN1

1

2

3

DSPLL

B

÷P₁

÷P₂

÷P₃

IN1b

0

1

2

3

DSPLL

C

IN2

IN2b

0

1

2

3

DSPLL

D

IN3/FB_IN

IN3b/FB_INb

Figure 3.6. DSPLL Input Selection Crosspoint

3.6.1 Manual Input Switching (IN0, IN1, IN2, IN3)

Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection

as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the

device automatically enters free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN)

and is not available for selection as a clock input.

Table 3.2. Manual Input Selection Using IN_SEL[1:0] Pins

IN_SEL[1:0]

Selected Input

Zero Delay Mode Disabled

Zero Delay Mode Enabled

0

1

0

1

0

1

IN0

IN1

IN2

IN3

IN0

IN1

IN2

Reserved

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Rev. 0.96 | 12

Si5381/82 Data Sheet

Functional Description

3.6.2 Automatic Input Selection (IN0, IN1, IN2, IN3)

An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection

criteria is based on input clock qualification, input priority, and the revertive option. Only input clocks that are valid can be selected by

the automatic clock selection state machine. If there are no valid input clocks available the DSPLL will enter the holdover mode. With

revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority be-

comes valid then an automatic switchover to that input is initiated. With non-revertive switching, the active input always remains

selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority is initiated.

3.6.3 Hitless Input Switching

Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that

have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they

have to be exactly at the same frequency, or at a fractional frequency relationship to each other. When hitless switching is enabled, the

DSPLL simply absorbs the phase difference between the two input clocks during a input switch. When disabled, the phase difference

between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature

supports clock frequencies down to the minimum input frequency of 7.68 MHz.

3.6.4 Ramped Input Switching

When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input

switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients

and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off

when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp

rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover see 3.4.5 Holdover

Mode.

3.6.5 Glitchless Input Switching

The DSPLL has the ability of switching between two input clock frequencies that are up to 40 ppm apart. The DSPLL will pull-in to the

new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if enabled. The loss of lock (LOL) indicator will

assert while the DSPLL is pulling-in to the new clock frequency. There will be no abrupt phase change at the output during the transi-

tion.

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Rev. 0.96 | 13

Si5381/82 Data Sheet

Functional Description

3.6.6 Input Configuration and Terminations

Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are in the

figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle pulsed CMOS signals can be dc-coupled. Un-

used inputs can be disabled and left unconnected when not in use.

Standard AC-coupled Differential LVDS

PULSED CMOS

50

INx

100

STANDARD

LVCMOS

INxb

3.3 V, 2.5V

50

LVDS or CML

Si5381/82

Standard AC-coupled Differential LVPECL

PULSED CMOS

STANDARD

50

INx

100

INxb

50

3.3 V, 2.5 V

LVPECL

LVCMOS

Si5381/82

Standard AC-coupled Single-ended

PULSED CMOS

STANDARD

50

INx

3.3 V, 2.5 V, 1.8 V

LVCMOS

INxb

LVCMOS

Si5381/82

Pulsed CMOS DC-coupled Single-ended

PULSED CMOS

STANDARD

R1

INx

50

R2

INxb

3.3 V, 2.5 V, 1.8 V

LVCMOS

Si5381/82

R1

Ω

R2

Ω

VDD

1.8V

2.5V

3.3V

324

511

634

665

475

365

Resistor values for

f^IN_PULSED< 1 MHz

LVCMOS DC-coupled Single-ended

PULSED CMOS

STANDARD

INx

50

INxb

3.3 V, 2.5 V, 1.8 V

LVCMOS

Si5381/82

Figure 3.7. Termination of Differential and LVCMOS Input Signals

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Rev. 0.96 | 14

Si5381/82 Data Sheet

Functional Description

3.7 Fault Monitoring

All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the fig-

ure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. There

is also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL loses synchronization.

XB

XA

LOS

DSPLL A

LOL

PD

LPF

÷M

IN0

Precision

Fast

LOS

OOF

÷P₀

÷P₁

÷P₂

÷P₃

DSPLL B

IN0b

LOL

PD

LPF

÷M

IN1

Precision

Fast

IN1b

Precision

Fast

IN2

DSPLL C

LOL

PD

IN2b

LPF

÷M

IN3

Precision

Fast

IN3b

DSPLL D

LOL

PD

LPF

÷M

Figure 3.8. Si5381/82 Fault Monitors

3.7.1 Input LOS Detection

The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of

the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal

sensitivity is configurable using the ClockBuilder Pro utility.

The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current

LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available.

Sticky

Monitor

LOS

en

Live

Figure 3.9. LOS Status Indicators

3.7.2 Reference Clock LOS Detection

A LOS monitor is available to ensure that the external reference oscillator is valid. By default the output clocks are disabled when

XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is

detected.

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Rev. 0.96 | 15

Si5381/82 Data Sheet

Functional Description

3.7.3 OOF Detection

Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This

OOF reference can be selected as either:

• The XA/XB reference

• Any input clock (IN0, IN1, IN2, IN3)

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure

below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky

register bit stays asserted until cleared.

Sticky

Monitor

Precision

Fast

en

LOS

OOF

Live

Figure 3.10. OOF Status Indicator

3.7.3.1 Precision OOF Monitor

The precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the selected

OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range which is register configura-

ble up to ±20 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling

at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency

range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of

the external XO reference is available. This option is register configurable.

OOF Declared

OOF Cleared

f_IN

Hysteresis

-4 ppm

(Clear)

-6 ppm

(Set)

+4 ppm

(Clear)

+6 ppm

(Set)

0 ppm

OOF Reference

Figure 3.11. Example of Precise OOF Monitor Assertion and Deassertion Triggers

3.7.3.2 Fast OOF Monitor

Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored

input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in

frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quick-

ly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than

±4000 ppm.

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Rev. 0.96 | 16

Si5381/82 Data Sheet

Functional Description

3.7.4 LOL Detection

The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock.

There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency

difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL

indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator

to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from

toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The

live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects

the current state of the LOL monitor.

Sticky

Si5381/82

LOS

LOL Status Registers

Live

LOLb

DSPLL D

DSPLL C

DSPLL B

DSPLL A

LOL Monitor

LOL

Clear

t

LOL

Set

DSPLL A

f_IN

PD

LPF

÷M

Figure 3.12. LOL Status Indicators

Each of the LOL frequency monitors has an adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having

two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status.

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Rev. 0.96 | 17

Si5381/82 Data Sheet

Functional Description

An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase

detector and LOL is indicated when there’s more than 1 ppm frequency difference is shown in the following figure.

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

Lost Lock

LOL

Hysteresis

LOCKED

0

0.1

1

10,000

Phase Detector Frequency Difference (ppm)

Figure 3.13. LOL Set and Clear Thresholds

Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards.

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input

clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The

configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using

the ClockBuilder Pro utility.

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Rev. 0.96 | 18

Si5381/82 Data Sheet

Functional Description

3.7.5 Interrupt Pin (INTRb)

An interrupt pin (INTRb) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are

maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the sticky status registers.

mask

IN0_LOS_FLG

IN0

mask

IN0_OOF_FLG

mask

IN1_LOS_FLG

IN1

mask

IN1_OOF_FLG

mask

IN2_LOS_FLG

IN2

mask

IN2_OOF_FLG

INTRb

mask

IN3_LOS_FLG

IN3

mask

IN3_OOF_FLG

mask

XAXB_LOS_FLG

mask

LOLA_FLG

mask

LOLB_FLG

mask

LOL

LOLC_FLG

mask

LOLD_FLG

mask

HOLDA_FLG

mask

HOLDB_FLG

mask

HOLD

HOLDC_FLG

mask

HOLDD_FLG

Figure 3.14. Interrupt Triggers and Masks

3.8 Outputs

The Si5381/82 supports up to twelve differential output drivers. Each driver has a configurable voltage swing and common mode volt-

age covering a wide variety of differential signal formats. In addition to supporting differential signals, any of the outputs can be config-

ured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 24 single-ended outputs, or any combination of differential and

single-ended outputs.

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Rev. 0.96 | 19

Si5381/82 Data Sheet

Functional Description

3.8.1 Output Crosspoint

A crosspoint allows any of the output drivers to connect with any of the MultiSynths as shown in the figure below. The crosspoint config-

uration is programmable and can be stored in NVM so that the desired output configuration is ready at power up.

Figure 3.15. MultiSynth to Output Driver Crosspoint

3.8.2 Output Signal Format

The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including

LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8

V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended outputs.

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Rev. 0.96 | 20

Si5381/82 Data Sheet

Functional Description

3.8.3 Output Terminations

The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure.

AC-coupled LVDS/LVPECL

DC-coupled LVDS

V_DDO= 3.3 V, 2.5 V, 1.8 V

V_DDO= 3.3 V, 2.5 V

50

OUTx

100

OUTxb

100

OUTxb

Internally

self-biased

Si5386

AC-coupled LVPECL / CML

DC-coupled LVCMOS

3.3 V, 2.5 V, 1.8 V

LVCMOS

VDD – 1.3 V

V_DDO= 3.3 V, 2.5 V, 1.8 V

V_DDO= 3.3 V, 2.5 V

50

Rs

OUTx

50

OUTx

OUTxb

Si5386

AC-coupled HCSL

VDD_RX

V_DDO= 3.3 V, 2.5 V, 1.8 V

R1

OUTx

OUTxb

50

Standard

HCSL

Receiver

Si5386

R2

For V_CM= 0.35 V

VDD_RX

R1

R2

442 Ω

56.2 Ω

59 Ω

3.3 V

2.5 V

1.8 V

332 Ω

243 Ω

63.4 Ω

Figure 3.16. Supported Output Terminations

3.8.4 Programmable Common Mode Voltage For Differential Outputs

The common mode voltage (V_CM) for the differential modes are programmable so that LVDS specifications can be met and for the best

signal integrity with different supply voltages. When dc coupling the output driver, it is essential that the receiver have a relatively high

common mode impedance so that the common mode current from the output driver is very small.

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Rev. 0.96 | 21

Si5381/82 Data Sheet

Functional Description

3.8.5 LVCMOS Output Impedance and Drive Strength Selection

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source

termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-

ble output impedance selections for each VDDO options as shown in the table below.

Table 3.3. LVCMOS Output Impedance and Drive Strength Selections

VDDO

OUTx_CMOS_DRV

Source Impedance (Zs)

Drive Strength (Iol/Ioh)

3.3 V

0x01

0x02

0x03*

0x01

0x02

0x03*

38 Ω

30 Ω

22 Ω

43 Ω

35 Ω

24 Ω

31 Ω

10 mA

12 mA

17 mA

6 mA

2.5 V

1.8 V

8 mA

11 mA

5 mA

Note: Use of the lowest impedance setting is recommended for all supply voltages for best edge rates.

3.8.6 LVCMOS Output Signal Swing

The signal swing (V_OL/V_OH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

3.8.7 LVCMOS Output Polarity

When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock

on the OUTx pin is generated with the same polarity (in phase) as the clock on the OUTxb pin. The polarity of these clocks is configura-

ble, enabling complementary clock generation and/or inverted polarity with respect to other output drivers.

3.8.8 Output Enable/Disable

The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held

high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually

disabled through register control.

3.8.9 Output Disable During LOL

By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option

to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.

3.8.10 Output Disable During Reference LOS

The external XA/XB reference provides a critical function for the operation of the DSPLLs. In the event of the XO failure, the device will

assert an XAXB_LOS alarm. By default, all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to

leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability is indeterminate during this fault condi-

tion.

3.8.11 Output Driver State When Disabled

The disabled state of an output driver is configurable as disable low or disable high.

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Rev. 0.96 | 22

Si5381/82 Data Sheet

Functional Description

3.8.12 Synchronous Output Disable Feature

The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock

period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When

this feature is turned off, the output clock will disable immediately without waiting for the period to complete.

3.8.13 Zero Delay Mode

A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.

The zero delay mode is configured for DSPLL_B only by opening the internal feedback loop through software configuration and closing

the loop externally as shown in the figure below.

This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the

outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize

the input-to-output delay. Note that the nominal input-to-output delay is the trace delay from OUTx to FB_IN. The OUT9A and FB_IN

pins are recommended for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled when zero de-

lay mode is used. A differential external feedback path connection is necessary for best performance. Note that the hitless switching

feature is not available when zero delay mode is enabled.

IN0

IN0b

IN1

Si5381/82

÷P₀

÷P₁

÷P₂

DSPLL B

÷M

IN1b

PD LPF

IN2

IN2b

÷5

IN3/FB_IN

÷P₃

VDDO0

IN3b/FB_INb

OUT0A

OUT0Ab

÷R_0A

÷R₀

OUT0

OUT0b

VDDO2

OUT2

OUT2b

t₁

÷N₁

÷R₂

VDDO8

OUT8

OUT8b

÷R₈

t₄

÷N₄

OUT9

OUT9b

÷R₉

OUT9A

÷R_9A

OUT9Ab

VDDO9

External Feedback Path

Figure 3.17. Si5381/82 Zero Delay Mode Setup

3.8.14 Output Divider (R) Synchronization

All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable

phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same

result. R divider setting of 2 produces a 180 degree phase change compared to high R divider settings.

3.9 Power Management

Unused inputs and output drivers can be powered down when unused. Consult the Reference Manual and ClockBuilder Pro configura-

tion utility for details.

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Rev. 0.96 | 23

Si5381/82 Data Sheet

Functional Description

3.10 In-Circuit Programming

The Si5381/82 is fully configurable using the serial interface (I²C or SPI). At power-up the device downloads its default register values

from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to

generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power

supply voltages applied to its V_DDand V_DDApins. The NVM is two time writable. Once a new configuration has been written to NVM,

the old configuration is no longer accessible. Refer to the Reference Manual for a detailed procedure for writing registers to NVM.

3.11 Serial Interface

Configuration and operation of the Si5381/82 is controlled by reading and writing registers using the I²C or SPI interface. The I2C_SEL

pin selects I²C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or

3-wire. See the Reference Manual for details.

3.12 Custom Factory Preprogrammed Parts

For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered

with a specific configuration written into NVM. A factory preprogrammed part will generate clocks at power-up. Custom, factory-preprog-

rammed devices are available. The ClockBuilder Pro custom part number wizard can be used to quickly and easily generate a custom

part number for your configuration.

In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your

design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local

Silicon Labs sales representative. Samples of your preprogrammed device will typically ship in about two weeks.

3.13 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices

As with essentially all modern software utilities, ClockBuilder Pro is continually being updated and enhanced. By registering at www.si-

labs.com, you will be notified about changes and their impact. This update process will ultimately enable ClockBuilder Pro users to ac-

cess all features and register setting values documented in this data sheet and the Reference Manual.

However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register

setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assis-

tance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock

outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro

project file with your specific features and register settings enabled using what's referred to as the manual "settings override" feature of

CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro

design report are shown in the following table.

Table 3.4. Setting Overrides

Location

Customer Name

FORCE_HOLD_PLLA

OOF_DIV_CLK_DIS

Engineering Name

OLA_HO_FORCE

OOF_DIV_CLK_DIS

Type

No NVM

User

Target

N/A

Dec Value

Hex Value

0x1

0x0435[0]

0x0B48[0:4]

1

0

OPN and EVB

0x00

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Rev. 0.96 | 24

Si5381/82 Data Sheet

Functional Description

Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the

NVM file. The flowchart for this process is shown in the following figure.

End: Place

sample order

Start

Do I need a

pre-programmed device with

a feature or setting which is

unavailable in ClockBuilder

Pro?

Generate

Custom OPN

in CBPro

Configure device

using CBPro

No

Yes

Contact Silicon Labs

Technical Support

to submit & review

your

Yes

non-standard

configuration

request & CBPro

project file

Receive

updated CBPro

project file

from

Silicon Labs

with “Settings

Override”

Does the updated

CBPro Project file

match your

Load project file

into CBPro and test

requirements?

Figure 3.18. Process for Requesting Non-Standard CBPro Features

Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx.

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Rev. 0.96 | 25

Si5381/82 Data Sheet

Register Map

4. Register Map

The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible

registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as

frequency configuration, and general device settings. A high level map of the registers is shown in “6.2. High-Level Register Map” .

Refer to the Reference Manual for a complete list of register descriptions and settings. Silicon Labs strongly recommends using Clock-

Builder Pro to create and manage register settings.

4.1 Addressing Scheme

The device registers are accessible using a 16-bit address that consists of an 8-bit page address plus an 8-bit register address. By

default, the page address is set to 0x00. Changing to another page is accomplished by writing to the "Set Page Address" byte located

at address 0x01 of each page.

4.2 High-Level Register Map

Table 4.1. High-Level Register Map

16-Bit Address

Content

8-bit Page Address

8-bit Register Address Range

00

01

Revision IDs

Set Page Address

02–0A

0B–15

17–1B

1C

Device IDs

Alarm Status

INTR Masks

00

Reset controls

1D

FINC, FDEC Control Bits

SPI (3-Wire vs 4-Wire)

Alarm Configuration

NVM Controls

2B

2C–E1

E2–E4

FE

Device Ready Status

Set Page Address

01

08–3A

41–42

FE

Output Driver Controls

Output Driver Disable Masks

Device Ready Status

Set Page Address

01

02–05

08–2F

30

Reference Clock Frequency Adjust

Input Divider (P) Settings

Input Divider (P) Update Bits

Output Divider (R) Settings

User Scratch Pad Memory

Device Ready Status

02

47–6A

6B–72

FE

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Rev. 0.96 | 26

Si5381/82 Data Sheet

Register Map

16-Bit Address

Content

8-bit Page Address

8-bit Register Address Range

01

02–37

0C

Set Page Address

MultiSynth Divider (N0–N4) Settings

MultiSynth Divider (N0) Update Bit

MultiSynth Divider (N1) Update Bit

MultiSynth Divider (N2) Update Bit

MultiSynth Divider (N3) Update Bit

MultiSynth Divider (N4) Update Bit

FINC/FDEC Settings N0–N4

Output Delay (Δt) Settings

Device Ready Status

17

22

03

2D

38

39–58

59–62

FE

04

05

87

Zero Delay Mode Set Up

Fast Lock Loop Bandwidth

Feedback Divider (M) Settings

Input Select Control

0E–14

15–1F

2A

2B

Fast Lock Control

2C–35

36

Holdover Settings

Input Clock Switching Mode Select

Input Priority Settings

38–39

3F

Holdover History Valid Data

Reserved

06–08

09

00–FF

01

Set Page Address

1C

Zero Delay Mode Settings

Control I/O Voltage Select

Input Settings

43

49

10–FF

00–FF

Reserved

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Rev. 0.96 | 27

Si5381/82 Data Sheet

Electrical Specifications

5. Electrical Specifications

Table 5.1. Recommended Operating Conditions

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Min

–40

—

Typ

25

Max

85

Unit

°C

V

Ambient Temperature

Maximum Junction Temperature

Core Supply Voltage

T_A

TJ_MAX

V_DD

—

125

1.89

3.47

1.71

3.14

1.80

3.30

V_DDA

V_DDO

V

Output Driver Supply Voltage

V

2.38

1.71

2.50

1.80

2.62

1.89

Note:

1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-

ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 5.2. DC Characteristics

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

I_DD

Test Condition

Min

—

Typ

175

120

21

Max

—

Unit

mA

Core Supply Current

Notes 1, 2

I_DDA

—

LVPECL Output³

@ 156.25 MHz

LVDS Output³

@ 156.25 MHz

3.3 V LVCMOS⁴

Output

Output Buffer Supply Current

I_DDO

—

25

—

15

21

18

25

mA

@ 156.25 MHz

2.5 V LVCMOS⁴

Output

—

16

12

18

13

—

mA

@ 156.25 MHz

1.8 V LVCMOS⁴

Output

@ 156.25 MHz

Note 1,5

Total Power Dissipation

P_d

1125

mW

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Rev. 0.96 | 28

Si5381/82 Data Sheet

Electrical Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Si5381/82 test configuration: 8 clock outputs enabled (2 x 983.04 MHz, 2 x 491.52 MHz, 1 x 245.76 MHz, 3 x 122.88 MHz; 2.5

LVDS). Excludes power in termination resistors.

2. VDDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers.

3. Differential outputs terminated into an AC coupled 100 Ω load.

4. LVCMOS outputs measured into a 6-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV

= 3, which is the strongest driver setting.

5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is

not available. All EVBs support detailed current measurements for any configuration.

LVCMOS Output Test Configuration

Differential Output Test Configuration

Trace length 5

inches

I_DDO

0.1 uF

56 Ω

0.1 uF

56 Ω

499 Ω

4.7 pF

50

I_DDO

50 Ω Scope Input

50

OUT

100

OUT

OUTb

50

499 Ω

4.7 pF

0.1 uF

Table 5.3. Input Clock Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Standard Differential or Single-Ended/LVCMOS — AC-coupled (IN0, IN1, IN2, IN3)

Input Frequency Range

Input Voltage Amplitude

Single-Ended Input Amplitude

f_{IN_DIFF}

f_{IN_SE}

Differential

0.008

—

750

250

MHz

Single-ended/

LVCMOS

V_{IN_DIFF}

f_{IN_DIFF}< 250 MHz

100

225

—

1800

mVpp_se

250 MHz < f_{IN_DIFF}

750 MHz

<

V_{IN_SE}

SR

f_{IN_SE}< 250 MHz

100

400

—

3600

—

mVpp_se

V/µs

Slew Rate^{1, 2}

Duty Cycle

DC

C_IN

40

—

60

—

%

Capacitance

2.4

pF

Pulsed CMOS — DC-coupled (IN0, IN1, IN2, IN3)³

Input Frequency

Input Voltage

f_{IN_CMOS}

V_IL

0.008

–0.2

0.49

400

40

—

250

0.33

—

MHz

V

V_IH

V

Slew Rate^{1, 2}

Duty Cycle

SR

—

V/µs

%

DC

Clock Input

60

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Rev. 0.96 | 29

Si5381/82 Data Sheet

Electrical Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

PW

Test Condition

Min

1.6

—

Typ

—

Max

—

Unit

ns

Minimum Pulse Width

Input Resistance

Pulse Input

R_IN

8

—

kΩ

XO (applied to XA/XB)⁴

Frequency

f_{IN_REF}

f_RANGE

—

54

—

MHz

ppm

Total Frequency Tolerance⁵

Input Voltage Amplitude

-50

+50

V_{IN_SE}

V_{IN_DIFF}

SR

Single-ended Input

Differential Input

Single-ended Input

Differential Input

365

1500

400

40

—

2000

2500

—

mVpp_se

mVpp_diff

V/µs

Slew Rate^{1, 2}

SR_{IN_DIFF}

DC

—

V/µs

Input Duty Cycle

Activity Dip⁶

60

%

2

ppm/C

Note:

1. Imposed for phase noise performance.

2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR.

3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks <1 MHz, which must be dc-coupled, having a

duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since the input

thresholds (VIL, VIH) of this buffer are non-standard, refer to the input attenuator circuit for dc-coupled Pulsed LVCMOS in the

Si5381/82 Reference Manual. Otherwise, for standard LVCMOS input clocks, use the “AC-coupled Singled-Ended” mode as

shown in 3.6.6 Input Configuration and Terminations.

4. Refer to the Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 54

MHz XOs.

5. Includes aging and temperature impacts from -40C to 85C.

6. Activity dip is also called frequency perturbation.

Table 5.4. Serial and Control Input Pin Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Serial and Control Input Pins (IN_SEL[1:0], RSTb, OEb, PDNb, A1/SDO, SCLK, A0/CSb, SDA/SDIO)

1

Input Voltage Thresholds

V_IL

V_IH

—

V

0.3 x V_DDIO

—

1

0.7 x V_DDIO

Input Capacitance

Input Resistance

Minimum Pulse Width

Note:

C_IN

I_L

—

2

—

pF

kΩ

ns

20

—

PW

RSTb, PDNb

100

1. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. See the Si5381/82 Reference Manual for more

details on the register settings.

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Rev. 0.96 | 30

Si5381/82 Data Sheet

Electrical Specifications

Table 5.5. Differential Clock Output Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

N >= 10

N = 9

Min

0.0001

—

Typ

—

Max

1474.56

—

Unit

MHz

Output Frequency⁶

f_OUT

1638.4

1843.2

2106.53

N = 8

—

N = 7⁷

N = 6

—

48

45

40

25

—

2457.6

—

52

55

60

75

MHz

%

N = 5

2949.12

Duty Cycle

DC

fOUT < 400 MHz

400 MHz < f_OUT< 800 MHz

800 MHz < fOUT < 1474.56 MHz

f > 1474.56 MHz

Differential output

—

0

%

Output-Output Skew⁷

T_SK

ps

Specified for outputs using the same

DSPLL

Differential output Specified for outputs

using different DSPLLs

-150

—

0

150

50

ps

OUT-OUTb Skew

T_{SK_OUT}

Measured from the positive to negative

output pins

Output Voltage Amplitude¹

Normal Mode

V_OUT

V_DDO= 3.3 V, 2.5

V, or 1.8 V

LVDS

350

660

470

810

550

mVpp_se

V_DDO= 3.3 V, 2.5

V

LVPECL

1000

Common Mode Voltage ^{1,2, 3}

Normal Mode

LVDS

VCM

V_DDO= 3.3 V

1.10

1.90

1.15

0.87

—

1.25

2.05

1.25

0.93

170

1.35

2.15

1.35

1.00

240

V

LVPECL

V_DDO= 2.5 V

V_DDO= 1.8 V

LVPECL, LVDS

sub-LVDS

Rise and Fall Times

(20% to 80%)

t_R/t_F

Normal Mode

ps

Ω

Differential Output Impe-

dance²

Z_O

Normal Mode

—

100

—

Power Supply Noise Rejec-

tion⁴

PSRR

Normal Mode

10 kHz sinusoidal noise

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

—

–93

–84

–79

—

dBc

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Rev. 0.96 | 31

Si5381/82 Data Sheet

Electrical Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output-output Crosstalk⁵

XTALK

Differential

—

–75

—

dB

Note:

1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output

driver can be programmed independently. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV)

higher than the TIA/EIA-644 maximum. Refer to the Si5381/82 Reference Manual for recommended output settings.

2. Not all combinations of voltage amplitude and common mode voltages settings are possible.

3. Driver output impedance depends on selected output mode (Normal, Low Power). Refer to the Si5381/82 Reference Manual for

more information.

4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and

noise spur amplitude measured.

5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 122.88 MHz and the aggressor at 156.25

MHz. Refer to application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Sys-

tems”, guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk.

6. VDDO = 2.5 V or 3.3 V required for fOUT > 1474.56 MHz

7. For any R divider settings that differ by a power of 2.

OUTx

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

OUTxb

Table 5.6. LVCMOS Clock Output Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

f_OUT

Test Condition

Min

0.0001

47

Typ

—

Max

250

53

Unit

MHz

%

Output Frequency

Duty Cycle

DC

fOUT <100 MHz

—

100 MHz < fOUT < 250 MHz

44

—

55

Output Voltage High^{1, 2, 3}

V_OH

VDDO = 3.3 V

OUTx_CMOS_DRV=1

IOH = –10 mA

IOH = –12 mA

IOH = –17 mA

VDDO x

0.75

—

V

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

VDDO = 2.5 V

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

IOH = –6 mA

IOH = –8 mA

IOH = –11 mA

VDDO x

0.75

—

VDDO = 1.8 V

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

IOH = –4 mA

IOH = –5 mA

VDDO x

0.75

—

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Rev. 0.96 | 32

Si5381/82 Data Sheet

Electrical Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Voltage Low^{1, 2, 3}

V_OL

VDDO = 3.3 V

IOL = 10 mA

OUTx_CMOS_DRV=1

—

VDDO x

0.15

V

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

IOL = 12 mA

IOL = 17 mA

VDDO = 2.5 V

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

IOL = 6 mA

IOL = 8 mA

IOL = 11 mA

—

VDDO x

0.15

V

VDDO = 1.8 V

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

IOL = 4 mA

IOL = 5 mA

—

VDDO x

0.15

LVCMOS Rise and Fall

Times³

tr/tf

VDDO = 3.3 V

420

475

525

550

625

705

ps

VDDO = 2.5 V

VDDO = 1.8 V

(20% to 80%)

Note:

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the

Si5381/82 Reference Manual for more details on register settings.

2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.

3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.

AC Output Test Configuration

DC Test Configuration

Trace length 5 inches

0.1 uF

499 Ω

4.7 pF

I_DDO

50

I_OL/I_OH

50 Ω Scope Input

OUT

56 Ω

0.1 uF

Zs

OUTb

V_OL/V_OH

499 Ω

4.7 pF

56 Ω

Table 5.7. Output Serial and Status Pin Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Serial and Status Output Pins (INTRb, LOLb, SDA/SDIO², A1/SDO)

V_DDIO¹x 0.75

—

Output Voltage

V_OH

V_OL

IOH = –2 mA

IOL = 2 mA

—

V

V_DDIO1 x 0.15

V

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Rev. 0.96 | 33

Si5381/82 Data Sheet

Electrical Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C)

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Users normally select this option in the Clock-

Builder Pro GUI. Alternatively, refer to the Si5381/82 Reference Manual for more details on register settings.

2. The V_OHspecification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused

with I2C_SEL pulled high internally. V_OLremains valid in all cases.

Table 5.8. Performance Characteristics

(V_DD= 1.8 V ±5%, or 3.3 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

PLL Loop Bandwidth

f_BW

1

—

4000

Hz

Programming Range¹

Initial Start-Up Time

t_START

Time from power-up or de-as-

sertion of PDNb to when the

device generates free-running

clocks

—

30

45

ms

PLL Lock Time

t_ACQ

Fastlock enabled,

—

500

700

600

—

ms

fIN = 19.44 MHz²

Fastlock enabled, ZDM,

fIN = 19.44 MHz²

POR to Serial Interface Ready³

Input-to-Output Delay Variation

Jitter Peaking

t_RDY

t_IODELAY

J_PK

—

15

—

ms

ns

Different parts and outputs

1.2

0.1

25 MHz input, 25 MHz output,

loop bandwidth of 4 Hz

dB

Jitter Tolerance

J_TOL

Compliant with G.8262 Op-

tions 1&2

—

3180

—

UI pk-pk

Carrier Frequency = 10.3125

GHz

Jitter Modulation Frequency =

10 Hz

Maximum Phase Transient

t_SWITCH

Single automatic switch be-

tween two 2 MHz inputs,

DSPLL BW = 400 Hz

—

0.2

0.3

ns

Single manual switch between

two 2 MHz inputs, DSPLL BW

= 400 Hz

0.25

Pull-in Range

ω_P

-20

—

20

—

ppm

RMS Jitter Generation⁴

J_GEN

12 kHz to 20 MHz

72

fs RMS

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Rev. 0.96 | 34

Si5381/82 Data Sheet

Electrical Specifications

(V_DD= 1.8 V ±5%, or 3.3 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

—

Typ

-118

-133

-142

-149

-154

-165

-95

Max

—

Unit

Phase Noise Performance⁴(122.88

MHz Carrier Frequency)

PN

100 Hz

dBc/Hz

dBc

1 kHz

—

10 kHz

100 kHz

—

1 MHz

—

10 MHz

—

Spur Performance (122.88 MHz Carri-

er Frequency)

SPUR

From 1 MHz to 30 MHz offset

—

Note:

1. Actual loop bandwidth may be lower; please refer to CBPro for actual value on your frequency plan.

2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock

time was measured with nominal and fastlock bandwidths, both set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively,

using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first

rising edge of the clock reference and the LOL indicator de-assertion.

3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.

4. Jitter generation test conditions: fIN=156.25MHz, DSPLL LBW = 40Hz. Jitter integrated from 12 kHz to 20 MHz offset. Does not

include jitter from PLL input reference.

Table 5.9. I2C Timing Specifications (SCL,SDA)

Parameter

Symbol

Test Condition

Min

Max

Min

Fast Mode

400 kbps

Max

Unit

Standard Mode

100 kbps

SCL Clock Frequency

SMBus Timeout

f_SCL

—

25

100

—

400

35

kHz

ms

µs

When Timeout is Enabled

35

—

25

Hold Time (Repeated)

START Condition

t_HD:STA

4.0

0.6

—

Low Period of the SCL

Clock

t_LOW

4.7

4.0

4.7

—

1.3

0.6

—

µs

HIGH Period of the SCL

Clock

t_HIGH

Set-up Time for a Repea-

ted START Condition

t_SU:STA

Data Hold Time

t_HD:DAT

t_SU:DAT

t_r

100

250

—

100

20

—

ns

Data Set-up Time

Rise Time of Both SDA

and SCL Signals

1000

300

Fall Time of Both SDA and

SCL Signals

t_f

—

300

—

300

—

ns

µs

Set-up Time for STOP

Condition

t_SU:STO

4.0

0.6

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Rev. 0.96 | 35

Si5381/82 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Max

Min

Max

Unit

Bus Free Time between a

STOP and START Condi-

tion

t_BUF

4.7

—

1.3

—

µs

Data Valid Time

t_VD:DAT

t_VD:ACK

—

3.45

—

0.9

µs

Data Valid Acknowledge

Time

Figure 5.1. I²C Serial Port Timing Standard and Fast Modes

Table 5.10. SPI Timing Specifications (4-Wire)

Parameter

Symbol

f_SPI

Min

—

Typ

—

Max

20

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

SCLK Period

T_DC

40

50

—

60

T_C

—

ns

Delay Time, SCLK Fall to SDO

Active

T_D1

—

18

ns

Delay Time, SCLK Fall to SDO

T_D2

T_D3

—

15

ns

Delay Time, CSb Rise to SDO

Tri-State

Setup Time, CSb to SCLK

T_SU1

T_H1

T_SU2

T_H2

5

—

ns

Hold Time, SCLK Fall to CSb

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

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Rev. 0.96 | 36

Si5381/82 Data Sheet

Electrical Specifications

Parameter

Symbol

Min

Typ

Max

Unit

Delay Time Between Chip Selects

(CSb)

T_CS

2

—

T_c

T_D1

T_C

T_SU1

SCLK

T_H1

CSb

T_SU2

T_H2

T_CS

SDI

T_D2

T_D3

SDO

Figure 5.2. 4-Wire SPI Serial Interface Timing

Table 5.11. SPI Timing Specifications (3-Wire)

Parameter

Symbol

f_SPI

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

T_DC

T_C

SCLK Period

ns

Delay Time, SCLK Fall to SDIO Turn-on

Delay Time, SCLK Fall to SDIO Next-bit

Delay Time, CSb Rise to SDIO Tri-State

Setup Time, CSb to SCLK

Hold Time, SCLK Fall to CSb

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

Delay Time Between Chip Selects (CSb)

T_D1

20

15

—

ns

T_D2

ns

T_D3

ns

T_SU1

T_H1

T_SU2

T_H2

ns

5

—

ns

5

—

ns

5

—

ns

T_CS

2

—

T_c

T_SU1

T_C

SCLK

T_H1

T_D1

T_D2

CSb

T_SU2

T_H2

T_CS

SDIO

T_D3

Figure 5.3. 3-Wire SPI Serial Interface Timing

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Rev. 0.96 | 37

Si5381/82 Data Sheet

Electrical Specifications

Table 5.12. Thermal Characteristics (QFN-64)

Parameter

Symbol

Test Condition1

Still Air

Value

22

Unit

Thermal Resistance

Junction to Ambient

ϴ_JA

°C/W

Air Flow 1 m/s

Air Flow 2 m/s

19.4

18.3

9.5

Thermal Resistance

Junction to Case

ϴ_JC

Thermal Resistance

Junction to Board

ϴ_JB

Ψ_JB

Ψ_JT

9.4

9.3

0.2

Thermal Resistance

Junction to Top Center

Note:

1. Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GNP pad: 36, Number of Cu Layers: 4

Table 5.13. Absolute Maximum^{1, Electrical Specifications, 2}

Parameter

Symbol

VDD

Test Condition

Value

Unit

V

DC Supply Voltage

–0.5 to 3.8

–1.0 to 3.8

–0.5 to 3.8

VDDA

VDDO

VI1

V

Input Voltage Range

IN0 – IN3

V

VI2

IN_SEL[1:0], RSTb, PDNb,

OEb, I2C_SEL, SYNC

V

SDA/SDIO, A1/SDO, SCLK,

A0/CSb

VI3

LU

XA/XB

–0.5 to 2.7

V

Latch-up Tolerance

JESD78 Compliant

ESD Tolerance

HBM

T_JCT

T_STG

T_PEAK

100 pF, 1.5 kΩ

2.0

kV

°C

Junction Temperature

Storage Temperature Range

Soldering Temperature

–55 to 125

–55 to +150

260

(Pb-free profile)²

Soldering Temperature Time at TPEAK(Pb-

free profile)³

T_P

20–40

sec

silabs.com | Building a more connected world.

Rev. 0.96 | 38

Si5381/82 Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Value

Unit

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to

the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

2. For detailed MSL and packaging information, go to RoHS Information.

3. The device is compliant with JEDEC J-STD-020.

silabs.com | Building a more connected world.

Rev. 0.96 | 39

Si5381/82 Data Sheet

Typical Application Schematic

6. Typical Application Schematic

SysClk

PHY1

PHY2

Si5381/82

RX1

TX1

PCIe

SerDes

RFFE

RF

JESD204B

Transceiver

RX2

TX2

RFFE

DFE

ASIC/

FPGA

Baseband

Processor

RX1

TX1

RFFE

RF

JESD204B

Transceiver

RX2

TX2

Figure 6.1. Application Block Diagram of μBTS

silabs.com | Building a more connected world.

Rev. 0.96 | 40

Si5381/82 Data Sheet

Detailed Block Diagrams

7. Detailed Block Diagrams

54 MHz

OSC

3

Si5381/82

IN_SEL[1:0]

Si5381

VDDO0

Si5382

OUT0A

OUT0Ab

÷R^0A

÷R⁰

PD LPF

M^n_A

OUT0

OUT0b

÷

M^d_A

DSPLL B

VDDO1

OUT1

OUT1b

14.7456 GHz PLL

÷R¹

÷R²

÷R³

÷R₄

÷R⁵

÷R⁶

÷R⁷

÷R⁸

VDDO2

OUT2

OUT2b

IN0

÷P⁰

÷P¹

IN0b

PD LPF

M^n_B

÷N¹

÷N⁴

VDDO3

OUT3

OUT3b

÷5

IN1

÷

M^d_B

DSPLL A

IN1b

VDDO4

OUT4

OUT4b

IN2

÷P²

÷P³

IN2b

PD LPF

M^n_C

VDDO5

OUT5

OUT5b

IN3/FB_IN

÷

IN3b/FB_INb

M^d_C

DSPLL C

VDDO6

OUT6

OUT6b

VDDO7

OUT7

OUT7b

PD LPF

M^n_D

÷

M^d_D

VDDO8

OUT8

OUT8b

DSPLL D

Any Rate PLLs

I2C_SEL

OUT9

OUT9b

SDA/SDIO

÷R⁹

SPI/

NVM

I²C

A1/SDO

SCLK

OUT9A

OUT9Ab

÷R^9A

A0/CSb

VDDO9

Status

Monitors

INTRb

Figure 7.1. Si5381/82 Block Diagram

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Rev. 0.96 | 41

Si5381/82 Data Sheet

Typical Operating Characteristics

8. Typical Operating Characteristics

The phase noise plots below were taken under the following conditions: V_DD= 1.8 V; V_DDA= 3.3 V; V_DDS= 3.3 V, 1.8 V; OLBW =

40Hz; T_a= 25 °C.

Figure 8.1. f_IN= 156.25 MHz, f_OUT= 122.88 MHz

Figure 8.2. f_IN= 156.25 MHz, f_OUT= 156.25 MHz

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Rev. 0.96 | 42

Si5381/82 Data Sheet

Typical Operating Characteristics

Figure 8.3. f_IN= 322.265625 MHz, f_OUT= 322.265625 MHz

silabs.com | Building a more connected world.

Rev. 0.96 | 43

Si5381/82 Data Sheet

Pin Descriptions

9. Pin Descriptions

Top View

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

IN1

SYNC

LOL

3

IN_SEL0

IN_SEL1

PDN

RST

X1

VDD

4

OUT6

VDDO6

OUT5

VDDO5

I2C_SEL

OUT4

VDDO4

OUT3

VDDO3

5

6

7

8

XA

GND

Pad

9

XB

10

11

12

13

14

15

X2

OE

INTR

VDDA

IN2

SCLK 16

silabs.com | Building a more connected world.

Rev. 0.96 | 44

Si5381/82 Data Sheet

Pin Descriptions

Table 9.1. Si5381/82 Pin Descriptions

Pin Number

Function

Type¹

Name

Inputs

IN0

IN0b

IN1

63

64

1

I

Clock Inputs. These pins accept

an input clock for synchronizing

the device. They support both

differential and single-ended

clock signals. Refer to section

3.6 Inputs (IN0, IN1, IN2, IN3)

for input termination options.

These pins are high-impedance

and must be terminated exter-

nally, when being used. The

negative side of the differential

input must be ac-grounded

when accepting a single-ended

clock. Unused inputs may be

left unconnected.

IN1b

IN2

2

14

15

IN2b

IN3/FB_IN

61

62

I

Clock Input 3/External Feed-

back Input.

IN3/FB_INb

By default, these pins are used

as the 4th clock input (IN3/IN3).

They can also be used as the

external feedback input (FB_IN/

FB_IN) for the optional zero de-

lay mode. See section

3.6.1 Manual Input Switching

(IN0, IN1, IN2, IN3) for details

on the optional zero delay

mode.

Outputs

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Rev. 0.96 | 45

Si5381/82 Data Sheet

Pin Descriptions

Pin Number

Function

Type¹

O

Name

OUT0A

OUT0Ab

OUT0

21

20

24

23

28

27

31

30

35

34

38

37

42

41

45

44

51

50

54

53

56

55

59

58

Output Clocks. These output

clocks support a programmable

signal swing and common mode

voltage. Desired output signal

format is configurable using reg-

ister control. Termination rec-

ommendations are provided in

section 3.8.3 Output Termina-

tions and section . Unused out-

puts should be left unconnec-

ted.

O

OUT0b

OUT1

O

OUT1b

OUT2

O

OUT2b

OUT3

O

OUT3b

OUT4

O

OUT4b

OUT5

O

OUT5b

OUT6

O

OUT6b

OUT7

O

OUT7b

OUT8

O

OUT8b

OUT9

O

OUT9b

OUT9A

OUT9Ab

O

Serial Interface

I2C_SEL

39

18

I

I2C Select. This pin selects the

serial interface mode as I2C

(I2C_SEL = 1) or SPI (I2C_SEL

= 0). This pin is internally

pulled high.

SDA/SDIO

I/O

Serial Data Interface. This is

the bidirectional data pin (SDA)

for the I2C mode, the bidirec-

tional data pin (SDIO) in the 3-

wire SPI mode, or the input

data pin (SDI) in 4-wire SPI

mode. When in I2C mode, this

pin must be pulled-up using

an external resistor of at least

1 kW. No pull-up resistor is

needed when in SPI mode.

This pin is 3.3 V tolerant.

silabs.com | Building a more connected world.

Rev. 0.96 | 46

Si5381/82 Data Sheet

Pin Descriptions

Pin Number

Function

Type¹

Name

A1/SDO

17

I/O

Address Select 1/Serial Data

Output. In I2C mode this pin

functions as the A1 address

input pin. In 4-wire SPI mode,

this is the serial data output

(SDO) pin. This pin is 3.3 V

tolerant.

SCLK

16

I

Serial Clock Input. This pin

functions as the serial clock in-

put for both I2C and SPI

modes. When in I2C mode,

this pin must be pulled-up us-

ing an external resistor of at

least 1 kW. No pull-up resistor

is needed when in SPI mode.

This pin is 3.3 V tolerant.

A0/CSb

19

I

Address Select 0/Chip Select.

This pin functions as the hard-

ware controlled address A0 in

I2C mode. In SPI mode, this pin

functions as the chip select in-

put (active low). This pin is inter-

nally pulled-up. This pin is 3.3 V

tolerant.

Control/Status

Interrupt². This pin is asserted

low when a change in device

status has occurred. This pin

must be pulled-up using an ex-

ternal resistor of at least 1 kW. It

should be left unconnected

when not in use.

INTRb

PDNb

RSTb

12

O

Power Down². The device en-

ters into a low power mode

when this pin is pulled low. This

pin is internally pulled-up. This

pin is 3.3 V tolerant. It can be

left unconnected when not in

use.

5

I

Device Reset.²Active low input

that performs power-on reset

(POR) of the device. Resets all

internal logic to a known state

and forces the device registers

to their default values. Clock

outputs are disabled during re-

set. This pin is internally pulled-

up. This pin is 3.3 V tolerant.

6

I

Output Enable². This pin disa-

bles all outputs when held high.

This pin is internally pulled low

and can be left unconnected

when not in use. This pin is 3.3

V tolerant.

OEb

11

I

silabs.com | Building a more connected world.

Rev. 0.96 | 47

Si5381/82 Data Sheet

Pin Descriptions

Pin Number

Function

Type¹

Name

LOLb

Loss Of Lock². This output pin

indicates when the DSPLL is

locked (high) or out-of-lock

(low). It can be left unconnected

when not in use.

47

O

SYNC

48

I

Output Clock Synchroniza-

tion². An active low signal on

this pin resets the output divid-

ers for the purpose of re-align-

ing the output clocks. This pin is

internally pulled-up and can be

left unconnected when not in

use.

Input Reference Select². The

IN_SEL[1:0] pins are used in

manual pin controlled mode to

select the active clock input as

shown in Table 3.2 Manual In-

put Selection Using IN_SEL[1:0]

Pins on page 12

IN_SEL0

IN_SEL1

3

4

I

XA

XB

8

9

I

Oscillator input. Single-ended

input must be connected to the

XA pin, with the XB pin appro-

priately terminated.

RSVD

7

NC

Reserved. Leave disconnected.

10

25

Power

VDD

32

46

60

P

Core Supply Voltage. The de-

vice operates from a 1.8 V sup-

ply. A 1 uF bypass capacitor

should be placed very close to

each pin.

VDDA

13

P

Core Supply Voltage 3.3 V. This

core supply pin requires a 3.3 V

power source. A 1 uF bypass

capacitor should be placed very

close to this pin.

silabs.com | Building a more connected world.

Rev. 0.96 | 48

Si5381/82 Data Sheet

Pin Descriptions

Pin Number

Function

Type¹

Name

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDO5

VDDO6

VDDO7

VDDO8

VDDO9

GND PAD

22

26

29

33

36

40

43

49

52

57

P

Output Clock Supply Voltage.

Supply voltage (3.3 V, 2.5 V, 1.8

V) for OUTn, OUTn outputs.

Note that VDDO0 supplies pow-

er to OUT0 and OUT0A;

VDDO9 supplies power to

OUT9 and OUT9A. Leave

VDDO pins of unused output

drivers unconnected. An alter-

native option is to connect the

VDDO pin to a power supply

and disable the output driver to

minimize current consumption.

Ground Pad. This pad provides

connection to ground and must

be connected for proper opera-

tion.

Note:

1. I = Input, O = Output, P = Power

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

silabs.com | Building a more connected world.

Rev. 0.96 | 49

Si5381/82 Data Sheet

Package Outlines

10. Package Outlines

10.1 Si5381/82 9x9 mm 64-QFN Package Diagram

Figure 10.1. Si5381/82 9x9 mm 64-QFN Package Diagram

Table 10.1. Package Diagram Dimensions

Dimension

MIN

0.80

0.00

0.18

NOM

0.85

MAX

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

9.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

9.00 BSC

5.20

E

E2

L

5.10

0.30

—

5.30

0.50

0.15

0.10

0.08

0.10

0.40

aaa

bbb

ccc

ddd

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Rev. 0.96 | 50

Si5381/82 Data Sheet

PCB Land Pattern

11. PCB Land Pattern

The following figure illustrates the PCB land pattern details for the devices. The table lists the values for the dimensions shown in the

illustration.

Figure 11.1. PCB Land Pattern

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Rev. 0.96 | 51

Si5381/82 Data Sheet

PCB Land Pattern

Table 11.1. PCB Land Pattern Dimensions

Dimension

Si5381/82 (Max)

C1

C2

E

8.6

0.50

0.30

0.50

5.5

X1

Y1

X2

Y2

5.5

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication

Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electropolished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

4. A 2x2 array of 0.65mm square openings on a 0.90mm pitch should be used for the center ground pad.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Rev. 0.96 | 52

Si5381/82 Data Sheet

Top Marking

12. Top Marking

Si538fg-

Rxxxxx-GM

YYWWTTTTTT

e4

TW

Figure 12.1. Si5381/82 Top Marking

Table 12.1. Top Marking Explanation

Line

Characters

Description

Base part number and Device Grade for Any-frequency, Any-output, Jitter

Cleaning Clock:

f = 1, Quad DSPLL Clock

f = 2, Dual DSPLL Clock

1

Si538fg-

g = A (External XO)

R = Product revision. (Refer to 2. Ordering Guide for latest revision).

xxxxx = Customer specific NVM sequence number. Optional NVM code as-

signed for custom, factory pre-programmed devices.

2

3

Rxxxxx-GM

Characters are not included for standard, factory default configured devices.

See 2. Ordering Guide for more information.

-GM = Package (QFN) and temperature range (–40 to +85 °C)

YYWW = Characters correspond to the year (YY) and work week (WW) of

package assembly.

YYWWTTTTTT

TTTTTT = Manufacturing trace code.

Circle w/ 1.6 mm (64-QFN) diameter Pin 1 indicator; left-justified

4

e4

Pb-free symbol; Center-Justified

TW

TW = Taiwan; Country of Origin (ISO Abbreviation)

silabs.com | Building a more connected world.

Rev. 0.96 | 53

Si5381/82 Data Sheet

Device Errata

13. Device Errata

Log in or register at https://www.silabs.com/support/resources.ct-errata.p-timing_clocks to access the device errata document.

silabs.com | Building a more connected world.

Rev. 0.96 | 54

Si5381/82 Data Sheet

Document Change List

14. Document Change List

14.1 Revision 0.96

April, 2019

• Tightened Output-Out Skew (different MultiSynths) specifications.

• Added Input-Output Delay Variation specifications.

14.2 Revision 0.95

September, 2018

• Reorganized and rewritten to address updates that are focused on the ultra-high performance wireless jitter attenuator feature for

optimized wireless BBU (Baseband Unit) and DU (Distribution Unit) applications.

14.3 Revision 0.9

September, 2017

• Initial release.

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Rev. 0.96 | 55

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without

further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior

notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance

of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to

design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required

or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,

can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no

circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs

disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.

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型号：	SI5381A-D04991-GM
厂家：	SILICON
描述：	Processor Specific Clock Generator, 外围集成电路
文件：	总56页 (文件大小：907K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI5381A-D04991-GM [SILICON]

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