SI4020_技术文档

Si4020 Universal ISM

Si4020

Band FSK Transmitter

PIN ASSIGNMENT

DESCRIPTION

Silicon Labs’ Si4020 is a single chip, low power, multi-channel FSK

transmitter designed for use in applications requiring FCC or ETSI

conformance for unlicensed use in the 315, 433, 868, and 915 MHz bands.

Used in conjunction with IA4320, Silicon Labs’ FSK receiver, the Si4020

transmitter feature EZRadio^TMtechnology, which produces a flexible, low

cost, and highly integrated solution that does not require production

alignments. All required RF functions are integrated. Only an external crystal

and bypass filtering are needed for operation.

Microcontroller Mode

EEPROM Mode

The Si4020 features a completely integrated PLL for easy RF design, and its

rapid settling time allows for fast frequency hopping, bypassing multipath

fading and interference to achieve robust wireless links. In addition, highly

stable and accurate FSK modulation is accomplished by direct closed-loop

modulation with bit rates up to 256 kbps. The PLL’s high resolution allows

the use of multiple channels in any of the bands.

This document refers to Si4020-IC Rev I1.

See www.silabs.com/integration for any applicable

errata. See back page for ordering information.

FEATURES

The integrated power amplifier of the transmitter has an open-collector

differential output that directly drive a loop antenna with programmable

output level. No additional matching network is required. An automatic

antenna tuning circuit is built in to avoid costly trimming procedures and de-

tuning due to the “hand effect”.

• Fully integrated (low BOM, easy design-in)

• No alignment required in production

• Fast settling, programmable, high-resolution PLL

• Fast frequency hopping capability

• Stable and accurate FSK modulation with programmable

deviation

• High bit rate (up to 256 kbps)

• Direct loop antenna drive

• Automatic antenna tuning circuit

• Programmable output power level

• Alternative OOK support

For low-power applications, the device supports automatic activation from

sleep mode. Active mode can be initiated by several wake-up events (on-chip

timer timeout, low supply voltage detection, or activation of any of the four

push-button inputs).

The Si4020’s on-chip digital interface supports both a microcontroller mode

and an EEPROM mode. The latter allows complete data transmitter

operation without a microcontroller (both control commands and data are

read from the EEPROM). Any wake-up event can start a transmission of the

corresponding data stored in the EEPROM.

• EEPROM mode supported

• SPI bus for applications with microcontroller

• Clock output for microcontroller

• Integrated programmable crystal load capacitor

• Power-saving sleep mode

• Multiple event handling options for wake-up activation

• Push-button event handling with switch de-bounce

• Wake-up timer

FUNCTIONAL BLOCK DIAGRAM

• Low battery detection

• 2.2 to 5.4 V supply voltage

RFP

REFERENCE

CRYSTAL

OSCILLATOR

XTL

SYNTHESIZER

RFN

• Low power consumption

• Low standby current (0.3 µA)

CLOCK

FREQUENCY

• Compact 16-pin TSSOP package

LOAD CAP

LEVEL

OOK

MOD

TYPICAL APPLICATIONS

• Remote control

• Home security and alarm

• Wireless keyboard/mouse and other PC peripherals

• Toy control

nIRQ/nLBD

CLK/SDO

SDI

LOW BAT

LOW

BATTERY

DETECT

TRESHOLD

CONTROLLER

SCK

TIMEOUT

PERIOD

nSEL

VDD

VSS

WAKE-UP

TIMER

FSK

• Remote keyless entry

• Tire pressure monitoring

• Telemetry

• Personal/patient data logging

• Remote automatic meter reading

PB1 PB2 PB3 PB4

1

Si4020-DS Rev 1.9r 0308

www.silabs.com/integration

Si4020

Wake-Up Timer

DETAILED DESCRIPTION

The Si4020 FSK transmitter is designed to cover the unlicensed

frequency bands at 315, 433, 868, and 915 MHz. The device

facilitates compliance with FCC and ETSI requirements.

The wake-up timer has very low current consumption (1.5 uA

typical) and can be programmed from 1 ms to several days with

an accuracy of ±5%.

It calibrates itself to the crystal oscillator at every startup. When

the oscillator is switched off, the calibration circuit switches on

the crystal oscillator only long enough for a quick calibration (a

few milliseconds) to facilitate accurate wake-up timing.

PLL

The programmable PLL synthesizer determines the operating

frequency, while preserving accuracy based on the on-chip

crystal-controlled reference oscillator. The PLL’s high resolution

allows the usage of multiple channels in any of the bands. The

FSK deviation is selectable (from 30 to 240 kHz with 30 kHz

increments) to accommodate various bandwidth, data rate and

crystal tolerance requirements, and it is also highly accurate due

to the direct closed-loop modulation of the PLL. The transmitted

digital data can be sent asynchronously through the FSK pin or

over the control interface using the appropriate command.

Event Handling

In order to minimize current consumption, the device supports

sleep mode. Active mode can be initiated by several wake-up

events: timeout of wake-up timer, detection of low supply

voltage, pressing any of the four push-button inputs, or through

the serial interface. The push-button inputs can be driven by a

logic signal from a microcontroller or controlled directly by

normally open switches. Pull-up resistors are integrated.

The RF VCO in the PLL performs automatic calibration, which

requires only a few microseconds. To ensure proper operation in

the programmed frequency band, the RF VCO is automatically

calibrated upon activation of the synthesizer. If temperature or

supply voltage change significantly or operational band has

changed, VCO recalibration is recommended.. Recalibration can

be initiated at any time by switching the synthesizer off and back

on again.

If any wake-up event occurs, the wake-up logic generates an

interrupt, which can be used to wake up the microcontroller,

effectively reducing the period the microcontroller has to be

active. The cause of the interrupt can be read out from the

transmitters by the microcontroller through the nIRQ pin.

Interface

An SPI compatible serial interface lets the user select the

operating frequency band and center frequency of the

synthesizer, polarity and deviation of FSK modulation, and output

power level. Division ratio for the microcontroller clock, wake-up

timer period, and low battery detector threshold are also

programmable. Any of these auxiliary functions can be disabled

when not needed. All parameters are set to default after power-

on; the programmed values are retained during sleep mode.

RF Power Amplifier (PA)

The power amplifier has an open-collector differential output and

can directly drive a loop antenna with a programmable output

power level. An automatic antenna tuning circuit is built in to

avoid costly trimming procedures and the so-called “hand effect.”

The transmitters can operate in On-Off Keying (OOK) mode by

switching the power amplifier on and off. When the appropriate

control bit is set using the Power Setting Command, the FSK pin

becomes an enable input (active high) for the power amplifier.

EEPROM Mode

In simple applications, the on-chip digital controller provides the

transmitters with direct interface to a serial (SPI) EEPROM. In this

case, no external microcontroller is necessary. Wake-up events

initiate automatic readout of the assigned command sequence

from EEPROM memory. For every event, there is a dedicated

starting address available in the EEPROM.

Crystal Oscillator

The chip has a single-pin crystal oscillator circuit, which provides

a 10 MHz reference signal for the PLL. To reduce external parts

and simplify design, the crystal load capacitor is internal and

programmable. Guidelines for selecting the appropriate crystal

can be found later in this datasheet.

Programming the EEPROM is very simple. Any control command

can be programmed in the EEPROM sequentially (same as in

microcontroller mode).

The transmitters can supply the clock signal for the

microcontroller, so accurate timing is possible without the need

for a second crystal. When the chip receives a Sleep Command

from the microcontroller and turns itself off, it provides several

further clock pulses (“clock tail”) for the microcontroller to be

able to go to idle or sleep mode. The length of the clock tail is

programmable.

The internal power-on reset (POR) is a dedicated event, which

can be used to program the basic settings of the transmitters. In

this case the chip starts to read out the preprogrammed data

from the 00h address in EEPROM. Data can be transmitted with

the help of the Data Transmit Command, which tells the

transmitters how many bytes must be transmitted. The whole

process finishes with a Sleep Command.

Low Battery Voltage Detector

The low battery voltage detector circuit monitors the supply

voltage and generates an interrupt if it falls below

a

programmable threshold level. The detector circuit has 50 mV

hysteresis.

2

Si4020

PACKAGE PIN DEFINITIONS, MICROCONTROLLER MODE

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Microcontroller Mode Pin Assignment

1

Name

SDI

Type

DI

Function

Data input of serial control interface

2

SCK

nSEL

PB1

PB2

PB3

PB4

CLK

XTL

DI

Clock input of serial control interface

3

DI

Chip select input of serial control interface (active low)

Push-button input #1 (active low with internal pull-up resistor)

Push-button input #2 (active low with internal pull-up resistor)

Push-button input #3 (active low with internal pull-up resistor)

Push-button input #4 (active low with internal pull-up resistor)

Microcontroller clock (1 MHz-10 MHz)

4

DI

5

DI

6

DI

7

DI

8

DO

AIO

S

9

Crystal connection (other terminal of crystal to VSS)

Ground reference

10

11

12

13

14

15

16

VSS

MOD

RFN

RFP

nIRQ

VDD

FSK

DI

Connect to logic high (microcontroller mode)

Power amplifier output (open collector)

AO

DO

S

Power amplifier output (open collector)

Interrupt request output for microcontroller (active low) and status read output

Positive supply voltage

DI

Serial data input for FSK modulation

3

Si4020

Typical Application, Microcontroller Mode

VDD

C1

C2

C3

2.2µF

10nF

GND

OPTIONAL

GP3

GP4

GP6

GP7

GP8

GP9

To other

circuits

Antenna

MICRO

CONTROLLER

GP2

GP1

GP0

SDI

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FSK

VDD

nIRQ

RFP

RFN

MOD

VSS

XTL

SCK

nSEL

PB1

PB2

PB3

PB4

CLK

IA4220

GP5

CLKin

(EC osc. mode)

GND

X1

10MHz

GND

OPTIONAL

GND

Note:

For detailed information about the supply decoupling capacitors see page 6.

4

Si4020

PACKAGE PIN DEFINITIONS, EEPROM MODE

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

EEPROM Mode Pin Assignment

1

Name

SDI

Type

DI

Function

Data input of serial control interface

2

SCK

nSEL

PB1

DO

DI

Clock output of serial control interface

3

Chip select output of serial control interface (active low)

Push-button input #1 (active low with internal pull-up resistor)

Push-button input #2 (active low with internal pull-up resistor)

Push-button input #3 (active low with internal pull-up resistor)

Push-button input #4 (active low with internal pull-up resistor)

Data output of serial control interface

4

5

PB2

DI

6

PB3

DI

7

PB4

DI

8

SDO

XTL

DO

AIO

S

9

Crystal connection (other terminal of crystal to VSS)

Ground reference

10

11

12

13

14

15

16

VSS

MOD

RFN

RFP

nLBD

VDD

FSK

DI

Connect to logic low (EEPROM mode)

Power amplifier output (open collector)

Low battery voltage detector output (active low)

Positive supply voltage

AO

DO

S

DI

Not used, connect to VDD or VSS

5

Si4020

Typical Application, EEPROM Mode

VDD

C1

C2

C3

2.2µF

10nF

1

2

3

4

8

7

6

5

nCS

SO

VCC

HOLD

SCK

SI

GND

EEPROM

25AA080

nWP

GND

OPTIONAL

SD

I

SCK

Antenna

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FSK

VDD

nLBD

RFP

RFN

MOD

VSS

XTL

nSEL

PB1

PB2

PB3

PB4

SD0

x

IA4220

X1

10MHz

GND

Recommended supply decoupling capacitor values

C2 and C3 should be 0603 size ceramic capacitors to achieve the best supply decoupling. The capacitor values are valid for both

stand-alone and microcontroller mode.

Band [MHz]

315

C1

C2

C3

2.2µF

10nF

390pF

220pF

47pF

33pF

433

868

915

6

Si4020

GENERAL DEVICE SPECIFICATIONS

All voltages are referenced to V_ss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol

V_dd

Parameter

Min

-0.5

-25

Max

6.0

Units

V

Positive supply voltage

V_in

Voltage on any pin except open collector outputs

Voltage on open collector outputs

Input current into any pin except VDD and VSS

Electrostatic discharge with human body model

Storage temperature

V_dd+0.5

6.0

V

V_oc

V

I_in

25

mA

V

ESD

T_st

1000

125

ºC

-55

T_ld

Lead temperature (soldering, max 10 s)

260

Recommended Operating Range

Symbol

V_dd

Parameter

Min

2.2

Max

5.4

Units

V

Positive supply voltage

V_oc

Voltage on open collector outputs (Max 6.0 V)

Ambient operating temperature

V_dd- 1

-40

V_dd+ 1

85

V

T_op

ºC

ELECTRICAL SPECIFICATION

(Min/max values are valid over the whole recommended operating range, typical conditions: T_op= 27 C; V_dd= V_oc= 2.7 V)

o

DC Characteristics

Symbol

Parameter

Conditions/Notes

315 MHz band

Min

Typ

9

Max

Units

433 MHz band

10

12

13

11

12

14

15

0.3

1.5

Supply current

(TX mode, P_out= 0 dBm)

I_{dd_TX_0}

mA

868 MHz band

915 MHz band

315 MHz band

433 MHz band

Supply current

(TX mode, P_out= P_max

I_{dd_TX_PMAX}

mA

)

868 MHz band

915 MHz band

I_pd

I_wt

Standby current in sleep mode

All blocks disabled (Note 1)

µA

Wake-up timer current consumption

Low battery detector current

consumption

I_lb

0.5

µA

I_x

V_lba

V_lb

V_il

Idle current

Only crystal oscillator is on

Programmable in 0.1 V steps

1.5

75

mA

mV

V

Low battery detection accuracy

Low battery detector threshold

Digital input low level

Digital input high level

Digital input current

2.2

5.3

0.3*V_dd

V

V_ih

I_il

0.7*V_dd

-1

V

V_il= 0 V

1

µA

V

I_ih

Digital input current

V_ih= V_dd, V_dd= 5.4 V

I_ol= 2 mA

-1

V_ol

V_oh

Digital output low level

Digital output high level

0.4

I_oh= -2 mA

V_dd-0.4

V

Note for table above is on page 7.

7

Si4020

AC Characteristics

Symbol

Parameter

Conditions/Notes

Min

8

Typ

Max

12

Units

f_ref

PLL reference frequency

Crystal operation mode is parallel (Note 2)

315 MHz band, 2.5 kHz resolution

433 MHz band, 2.5 kHz resolution

868 MHz band, 5.0 kHz resolution

915 MHz band, 7.5 kHz resolution

10

MHz

310.24

430.24

860.48

900.72

319.75

439.75

879.51

929.27

f_o

Output frequency (programmable)

MHz

µs

Frequency error < 10 kHz after 10 MHz

step

t_lock

PLL lock time

20

After turning on from idle mode, with

crystal oscillator already stable

t_sp

PLL startup time

250

2.5

µs

I_OUT

Open collector output current (Note 3) At all bands

0.1

mA

Available output power

(315 and 433 MHz band)

With optimal antenna impedance

(Note 4)

P_maxL

3

1

dBm

Available output power

(868 and 915 MHz band)

With optimal antenna impedance

(Note 4)

P_maxH

P_out

dBm

dBc

Typical output power

Selectable in 3 dB steps (Note3)

P_max-21

P_max

-50

At max power with loop antenna

(Note 5)

P_sp

Spurious emission

At low bands

At high bands

1.5

1.6

2.3

2.2

3.1

2.8

Output capacitance (set by the

automatic antenna tuning circuit)

C_o

pF

Quality factor of the output

capacitance

Q_o

16

18

22

100 kHz from carrier

1 MHz from carrier

-75

-85

L_out

Output phase noise

dBc/Hz

BR_FSK

BR_OOK

df_fsk

FSK bit rate

256

512

240

kbps

kHz

OOK bit rate

FSK frequency deviation

Programmable in 30 kHz steps

30

Crystal load capacitance

See Crystal Selection Guidelines

Programmable in 0.5 pF steps, tolerance

+/- 10%

C_xl

8.5

16

pF

Internal POR timeout

(Note 6)

t_POR

t_sx

After V_ddhas reached 90% of final value

Crystal ESR < 100 Ohms (Note 7)

100

5

ms

Crystal oscillator startup time

1

Crystal oscillator must be enabled to

ensure proper calibration at startup

(Note 7)

t_PBt

Wake-up timer clock accuracy

+/-10%

ms

t_wake-up

C_{in, D}

t_{r, f}

Programmable wake-up time

Digital input capacitance

Digital output rise/fall time

1

2 · 10⁹

2

ms

pF

ns

15 pF pure capacitive load

10

All notes for table above are on page 7.

8

Si4020

Note 1: Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years using a 60-second wake-up period

for sending 100 byte packets in length at 19.2 kbps with +3 dBm output power in the 915 MHz band.

Note 2: Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency

parameters will change accordingly.

Note 3: Adjustable in 8 steps.

Note 4: Optimal antenna admittance/impedance for the Si4020:

Yantenna [S]

9.4E-4 - j4.5E-3

8.4E-4 - j6.25E-3

1.15E-3 - j1.2E-2

1.2E-3 - j1.25E-2

Zantenna [Ohm]

43 + j214

Lantenna [nH]

112.00

315 MHz

434 MHz

868 MHz

915 MHz

21 + j157

59.00

7.9 + j83

15.30

7.6 + j79

13.90

Note 5: With selective resonant antennas (see: Application Notes available from http://www.silabs.com/integration).

Note 6: During this period, no commands are accepted by the chip. For detailed information see the Reset modes section.

Note 7: The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR

crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray

capacitance.

9

Si4020

TYPICAL PERFORMANCE DATA

Unmodulated RF Spectrum

The output spectrum is measured at different frequencies. The output is loaded with 50 Ohms through a matching network.

At 315 MHz

At 433 MHz

15:18:59 Oct 29, 2003

#Atten 5 dB

15:37:47 Dec 15, 2003

Atten 5 dB

Mkr1 315.0010 MHz

-22.7 dBm

Mkr1 434.0630 MHz

-23.41 dBm

Ref -10 dBm

Samp

Log

Ref -10 dBm

Samp

Log

1

10

dB/

VAvg

100

VAvg

100

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

Center 315 MHz

Res BW 10 kHz

Span 2 MHz

Sweep 40.74 ms (2001 pts)

Center 434.1 MHz

Res BW 10 kHz

Span 2 MHz

Sweep 40.74 ms (2001 pts)

VBW 10 kHz

At 915 MHz

At 868 MHz

15:20:49 Oct 29, 2003

#Atten 5 dB

15:28:02 Dec 15, 2003

Atten 5 dB

Mkr1 868.0680 MHz

-23.23 dBm

Mkr1 915.0000 MHz

-24.63 dBm

Ref -10 dBm

Samp

Log

10

dB/

Ref -10 dBm

Samp

Log

10

dB/

1

VAvg

100

VAvg

100

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

Center 868.1 MHz

Res BW 10 kHz

Span 2 MHz

Sweep 40.74 ms (2001 pts)

Center 915 MHz

Res BW 10 kHz

Span 2 MHz

Sweep 40.74 ms (2001 pts)

VBW 10 kHz

10

Si4020

Modulated RF Spectrum

At 433 MHz with

At 868 MHz with

180 kHz Deviation at 64 kbps

15:43:45 Oct 29, 2003

Atten 5 dB

15:46:09 Oct 29, 2003

Ref -10 dBm

#Peak

Log

10

dB/

Ref -10 dBm

#Peak

Log

Atten 5 dB

10

dB/

VAvg

100

W1S2

S3 FC

AA

VAvg

100

W1S2

S3 FC

AA

Center 434 MHz

Res BW 10 kHz

Span 2 MHz Center 868 MHz

Sweep 20.07 ms (2001 pts) Res BW 10 kHz

Span 2 MHz

Sweep 20.07 ms (2001 pts)

VBW 100 kHz

Spurious RF Spectrum

With 10 MHz CLK Output Enabled at 433 MHz

Antenna Tuning Characteristics

750–970 MHz

16:29:03 Jun 17, 2003

16:54:54 Mar 11, 2003

Mkr1 ∆ 20.0 MHz

Mkr1 915.0 MHz

-37.62 dBm

Ref 0 dBm

#Peak

Log

10

dB/

Atten 10 dB

-55.11 dB

Ref -36 dBm

#Atten 0 dB

Peak

Log

1

*

1

1R

dB/

Marker ∆

20.000000 MHz

-55.11 dB

Marker

915.000000 MHz

-37.62 dBm

W1S2

S3 FC

AA

V1 M2

S3 FC

AA

1

Center 434.8 MHz

#Res BW 3 kHz

Span 50 MHz Start 700 MHz

Sweep 45.47 s (401 pts) #Res BW 1 MHz

Stop 1.05 GHz

Sweep 50 ms (401 pts)

#VBW 300 Hz

VBW 1 MHz

The antenna tuning characteristics was recorded in “max-hold” state of the spectrum analyzer. During the measurement, the

transmitters were forced to change frequencies by forcing an external reference signal to the XTL pin. While the carrier was changing

the antenna tuning circuit switched trough all the available states of the tuning circuit. The graph clearly demonstrates that while the

complete output circuit had about a 40 MHz bandwidth, the tuning allows operating in a 220 MHz band. In other words the tuning

circuit can compensate for 25% variation in the resonant frequency due to any process or manufacturing spread.

11

Si4020

CONTROL INTERFACE

Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on

pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits

sent is an integer multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits.

All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power

On Reset (POR) circuit sets default values in all control and command registers.

Timing Specification

Symbol

t_CH

Parameter

Minimum value [ns]

Clock high time

25

10

25

5

t_CL

Clock low time

t_SS

Select setup time (nSEL falling edge to SCK rising edge)

Select hold time (SCK falling edge to nSEL rising edge)

Select high time

t_SH

t_SHI

t_DS

Data setup time (SDI transition to SCK rising edge)

Data hold time (SCK rising edge to SDI transition)

Data delay time

t_DH

5

t_OD

10

25

t_BL

Push-button input low time

Timing Diagram

t_SHI

t_SS

nSEL

t_CH

t_CL

t_OD

t_SH

SCK

t_DS

t_DH

BIT15

BIT14

BIT13

BIT8

BIT7

BIT1

BIT0

SDI

POR

WK-UP

nIRQ

12

Si4020

Control Commands

Control Command

Related Parameters/Functions

Frequency band, microcontroller clock output, crystal load capacitance, frequency

deviation

1

2

Configuration Setting Command

Crystal oscillator, synthesizer, power amplifier, low battery detector, wake-up timer, clock

output buffer

Power Management Command

3

4

5

6

7

8

9

Frequency Setting Command

Data Rate Command

Carrier frequency

Bit rate (at EEPROM mode only)

Nominal output power, OOK mode

Low battery threshold limit

Length of the clock tail after power down

Push-button related functions

Wake-up time period

Power Setting Command

Low Battery Detector Command

Sleep Command

Push-Button Command

Wake-Up Timer Command

10 Data Transmit Command

11 Status Register Command

Data transmission

Transmitter status read

Note: In the following tables the POR column shows the default values of the command registers after power-on.

1. Configuration Setting Command

bit

15

1

14

0

13

0

12

b1

11

b0

10

d2

9

8

7

6

5

4

3

2

1

0

POR

d1

d0

x3

x2

x1

x0

ms

m2 m1 m0

8080h

b1

b0

0

Frequency Band [MHz]

x3 x2 x1 x0

Crystal Load Capacitance [pF]

0

1

315

433

868

915

0

1

0

1

0

1

8.5

9.0

1

0

9.5

1

10.0

…

Clock Output Frequency

[MHz]

d2 d1 d0

1

0

1

15.5

16.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.25

1.66

2

The resulting output frequency can be calculated as:

SIGN

f_out= f₀– (-1) * (M + 1) * (30 kHz)

2.5

3.33

5

where:

f₀is the channel center frequency (see the next command)

M is the three bit binary number <m2 : m0>

SIGN = (ms) XOR (FSK input)

10

13

Si4020

2. Power Management Command

bit

15

1

14

1

13

0

12

0

11

0

10

0

9

0

8

0

7

6

5

4

3

2

1

0

POR

a1

a0

ex

es

ea

eb

et

dc

C000h

Bits 5-0, enable the corresponding block of the transmitters, i.e. the crystal oscillator is enabled by the ex bit, the synthesizer by es, the

power amplifier by ea and the low battery detector by eb, while the wake-up timer by et. The bit dc disables the clock output buffer.

When receiving the Data Transmit Command, the chip supports automatic on/off control over the crystal oscillator, the PLL and the PA.

If bit a1 is set, the crystal oscillator and the synthesizer are controlled automatically. Data Transmit Command starts up the crystal oscillator

and as soon as a stable reference frequency is available the synthesizer starts. After a subsequent delay to allow locking of the PLL, if a0 is

set the power amplifier is turned on as well.

Note:

• To enable the automatic internal control of the crystal oscillator, the synthesizer and the power amplifier, the corresponding bits

(ex, es, ea) must be zero in the Power Management Command.

• In microcontroller mode, the ex bit should be set in the Power Management Command for the correct control of es and ea. The

oscillator can be switched off by clearing the ex bit after the transmission.

• In EEPROM operation mode after an identified Data Transmit Command the internal logic switches on the synthesizer and PA. At

the end of Data Transmit Command header if necessary the current clock cycle is automatically extended to ensure the PLL

stabilization and RF power ramp-up.

• In EEPROM operation mode the internal logic switches off the PA when the given number of bytes is transmitted. (See: Data

Transmit Command in EEPROM operation.)

• When the chip is controlled by a microcontroller, the Sleep Command can be used to indicate the end of the data transmission

process, because in microcontroller mode the Data Transmit Command does not contain the length of the TX data.

• For processing the events caused by the peripheral blocks (POR, LBD, wake-up timer, push-buttons) the chip requires operation of

the crystal oscillator. This operation is fully controlled internally, independently from the status of the ex bit, but if the dc bit is zero,

the oscillator remains active until Sleep Command is issued. (This command can be considered as an event controller reset.)

Oscillator control logic

14

Si4020

3. Frequency Setting Command

bit

15

1

14

0

13

1

12

0

11

10

9

8

7

6

5

4

3

2

1

0

POR

f11 f10

f9

f8

f7

f6

f5

f4

f3

f2

f1

f0

A7D0h

The 12-bit parameter of the Frequency Setting Command

<f11 : f0> has the value F. The value F should be in the range

of 96 and 3903. When F is out of range, the previous value is

kept. The synthesizer center frequency f₀can be calculated as:

The constants C1 and C2 are determined by

the selected band as:

Band [MHz]

315

C1

1

C2

31

43

30

f₀= 10 MHz * C1 * (C2 + F/4000)

433

1

868

2

915

3

Note:

• For correct operation of the frequency synthesizer, the frequency and band of operation need to be programmed before the

synthesizer is started. Directly after activation of the synthesizer, the RF VCO is calibrated to ensure proper operation in the

programmed frequency band.

• When coding for the Si4020, it is suggested that recalibration routines be added to compensate for significant changes in

temperature and supply voltages.

4. Data Rate Command

bit

15

1

14

1

13

0

12

0

11

1

10

0

9

0

8

0

7

6

5

4

3

2

1

0

POR

r7

r6

r5

r4

r3

r2

r1

r0

C800h

In EEPROM mode the transmitted bit rate is determined by the 8-bit value R (bits <r7 : r0>) as:

BR = 10 MHz / 29 / (R+1)

Apart from setting custom values, the standard bit rates from 2.4 to 115.2 kbps can be approximated with minimal error.

The commands are read out with a different fixed bit rate:

F_sck= 10 MHz / 29 / 3 [~115.2 kHz]

5. Power Setting Command

bit

7

1

6

0

5

1

4

1

3

2

1

0

POR

B0h

ook

p2

p1

p0

The bit ook enables the OOK mode for the PA, in this case the data to be transmitted are received through the FSK pin.

p2 p1 p0 Relative Output Power [dB]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

-3

-6

The output power is given in the table as relative to the

maximum available power, which depends on the actual

antenna impedance. (See: Antenna Application Note

available from www.silabs.com/integration).

-9

-12

-15

-18

-21

15

Si4020

6. Low Battery Detector Command

bit

15

1

14

1

13

0

12

0

11

0

10

0

9

1

8

0

7

0

6

0

5

0

4

3

2

1

0

POR

t4

t3

t2

t1

t0

C200h

The 5-bit value T of <t4 : t0> determines the threshold voltage V_lbof the detector:

V_lb= 2.25 V + T * 0.1 V

7. Sleep Command

bit

15

1

14

1

13

0

12

0

11

0

10

1

9

0

8

0

7

6

5

4

3

2

1

0

POR

s7

s6

s5

s4

s3

s2

s1

s0

C400h

The effect of this command depends on the Power Management Command. It immediately disables the power amplifier (if a0=1 and

ea=0) and the synthesizer (if a1=1 and es=0). Stops the crystal oscillator after S periods of the microcontroller clock (if a1=1 and

ex=0) to enable the microcontroller to execute all necessary commands before entering sleep mode itself. The 8-bit value S is

determined by bits <s7 : s0>.

8. Push-Button Command

bit

15

1

14

1

13

0

12

0

11

1

10

0

9

1

8

0

7

6

5

4

3

2

1

0

POR

p4

d1

d0

b4

b3

b2

b1

bc

CA00h

If the corresponding bit was set (b1-b4) the event remains active while the button is pressed. In EEPROM mode, the chip is continuously

performing the routine assigned to the push-button while it is pressed. In microcontroller mode, the chip continuously generates interrupts

on nIRQ until the push-button is released. Weak pull-up currents are switched off when bc is high.

The d0, d1 bits set the de-bouncing time period:

d1

0

d0

0

De-bouncing Time [ms]

160

0

1

40

1

0

10

1

0 (Bypassed)

Note:

• Until the de-bouncing time has expired, the crystal oscillator remains switched on, independent of the status of the ex bit in the

Power Management Command. (Because the circuit uses the crystal oscillator signal for timing.)

If the p4 bit is set, the controller performs the routine assigned to the fourth button when PB1 and PB2 are pressed down

simultaneously. With the addition of this feature, there is a way to build a device that uses 3 buttons, but performs 4 functions.

It is possible to detect multiple pressed push-buttons in both modes. In EEPROM mode the controller executes sequentially all the

routines belonging to the pressed buttons.

16

Si4020

Simultaneously Pressed Push-Button Detect by Microcontroller

Microcontroller mode

Vdd

POR

(internal)

Push button

input 1

Push button

input 2

nIRQ

SPI

POR

PB1

PB2

PB1

PB2

PB1

PB_nIRQdly*

Status rd

Note:

*PB_nIRQdly is equal with the

debounce time

Simplified Block Diagram of Push-Button 1–4 Inputs

Notice:

Only one EVENT is

serviced simultaneously

the others are pending.

POR, LBD, WAKE UP TIMER,

P. BUTTONS EVENT FLAGS

VDD

WEAK PULL-UP

ENABLE/DISABLE

EVENT FLAG

bc

D

Q

Push-button1,2,3

Digital glitch

filter

CLR

CLK

SLEEP Command *

CLR for P.B1,2

STAT. REG. READ Command **

COUNT/SINGLE

Internal

blocker signal

to

b1, b2, b3

Push-button1

and

Push-button2

p4

To Digital glitch filter for

Push-button4

Push-button1

Push-button2

Note:

* In EEprom mode

** In uC controlled mode

With internal weak pull-up

Push-button4

17

Si4020

9. Wake-Up Timer Command

bit

15

1

14

1

13

1

12

r4

11

r3

10

r2

9

8

7

6

5

4

3

2

1

0

POR

r1

r0

m7 m6

m5 m4 m3 m2 m1 m0

E000h

The wake-up time period can be calculated as:

T_wake-up= M * 2^R[ms] ,

where M is defined by the <m7 : m0> digital value and R is defined by the <r4 : r0> digital value.

The value of R should be in the range of 0 and 23. The maximum achievable wake-up time period can be up to 24 days.

Note:

• For continual operation the et bit should be cleared and set at the end of every cycle.

Software reset: Sending FF00h command to the chip triggers software reset. For more details see the Reset modes section.

10. Data Transmit Command

This command is not needed if the transmitters’ power management bits (ex, es, ea) are fully controlled by the microcontroller and

TX data comes through the FSK pin.

In EEPROM operation mode:

bit

15

1

14

1

13

0

12

0

11

0

10

1

9

1

8

0

7

6

5

4

3

2

1

0

POR

- -

n7

n6

n5

n4

n3

n2

n1

n0

In microcontroller slave mode:

bit

7

1

6

1

5

0

4

0

3

0

2

1

0

POR

- -

This command indicates that the following bitstream coming in via the serial interface is to be transmitted. In EEPROM mode, the 8-

bit value N of bits <n7 : n0> contains the number of data bytes to follow.

Note:

• If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs t_sxtime, to switch on. The actual value

depends on the type of quartz crystal used.

• If the synthesizer was formerly switched off (es=0), the internal PLL needs t_spstartup time. Valid data can be transmitted only when

the internal locking process is finished.

• In EEPROM mode, before issuing the Data Transmit Command, the power amplifier must be enabled, with the ea or a0 bit in the

Power Management Command.

• In EEPROM mode, when N bytes have been read and transmitted the controller continues reading the EEPROM and processing the

data as control commands. This process stops after Sleep Command has been read from the EEPROM.

18

Si4020

Data Transmit Sequence Through the FSK Pin

P o w e r M a n a g e m e n t C o m m a n d

nSEL

C 0 h

3 8 h

SCK

SDI

instruction

tsx *

xtal osc. stable

Xtal osc staus

Internal operations

a0, a1 = 0

ex, es, ea = 1

tsp *

synthesizer / PLL /

PA status

synthesizer on, PLL locked, PA ready to transmit

T X D A T A

d o n ' t c a r e

FSK

NOTE:

* See page 6 for the timing values

Data Transmit Sequence Through the SDI Pin

Note:

• Do not send CLK pulses with the TX data bits; otherwise they will be interpreted as commands.

• This mode is not SPI compatible, therefore it is not recommended in microcontroller mode.

• If the crystal oscillator and the PLL are running, the t_sx+t_spdelay is not needed.

19

Si4020

11. Status Register Read Command

bit

15

1

14

1

13

0

12

0

11

1

10

1

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

POR

- -

With this command, it is possible to read the chip’s status register through the nIRQ pin. This command clears the last serviced

interrupt and processing the next pending one will start (if there is any).

Status Register Read Sequence

nSEL

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

instruction

SDI

status out

POR

PB1

PB2

PB3

PB4

LBD

nIRQ

WK-UP

20

Si4020

EEPROM MODE

In this mode, the transmitters can operate with a standard at least 1 kbyte serial EEPROM with an SPI interface, and no

microcontroller is necessary. The following events cause wake-up of the device:

Event Number N

EEPROM entry point

0000h

Description

0

1

2

3

4

5

6

power-on

0080h

low level on input PB1

low level on input PB2

low level on input PB3

low level on input PB4

low supply voltage level

wake-up timer timeout

0100h

0180h

0200h

0280h

0300h

After any of these events, the crystal oscillator turns on and the device starts to read bytes from the EEPROM continuously (block

read) starting from address N * 128 (decimal) and executes them as commands as described in the previous section.

Note: Zero bytes can be put in the EEPROM for timing purposes. Never put more than 31 consecutive zero bytes into the EEPROM’s

active region (between the actual entry point and the closing Sleep Command).

Example EEPROM Hex Content

Power-On Reset:

00000000

00000010

00000020

00000030

00000040

00000050

00000060

00000070

C0

00

C4 CA

1E

00

C8

00

23

00

C4

00

Short Explanation:

Data in Address, Command, and Parameter fields are hexadecimal values.

For the detailed description of the control command bits, see previous section.

Address

Command

Parameter

Related Control Command

Remarks

Crystal – Synthesizer – Power Amplifier auto

on/off mode enable

00–01

C0

C4

Power Management

02–03

04–05

06-07

CA

C8

C4

1E

23

00

Push Button

Bit Rate

Sleep

Continuous execution for all push buttons

BR = 10M / 29 / ( 35+1 ) ~ 9600 bps

Power down

21

Si4020

Push-button 1:

00000080

00000090

000000A0

000000B0

000000C0

000000D0

000000E0

000000F0

88

55

00

72

55

00

A6

55

00

10

55

00

C6

55

00

60

55

00

55

C4

00

55

00

55

00

55

00

55

00

55

00

55

00

55

00

55

00

55

00

Short Explanation:

Address

80–81

82–83

84–85

86–E5

E6–E7

Command

Parameter

872

Related Control Command

Configuration Control

Frequency

Remarks

8

A

433MHz band, Xtal C_L=12pF f_dev=90kHz

f_c=(43+1552/4000)*10MHz

Transmit the next 96 bytes

Data

610

C6

60

Data Transmit

60x55

00

C4

Sleep

Power down, go to address 80 (see note)

Note:

• This routine is repeatedly executed while PB1 is pressed, because continuous execution was selected at POR (CA1E code issued in the

power-on reset section before).

RX-TX ALIGNMENT PROCEDURES

RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is

suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.

To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not

measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier

frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the

TX and RX side there should be no offset if the CLK signals have identical frequencies.

It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out

the status byte from the receiver, the actual measured offset frequency will be reported. In order to get accurate values the AFC has

to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).

22

Si4020

CRYSTAL SELECTION GUIDELINES

The crystal oscillator of the Si4020 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in

order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5

pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be

used.

When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C₀) value is expected for the

crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However,

lower C₀and ESR values guarantee faster oscillator startup.

The crystal frequency is used as the reference of the PLL, which generates the RF carrier frequency (f_c). Therefore, f_cis directly

proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be

determined from the maximum allowable carrier frequency error.

Maximum XTAL Tolerances Including Temperature and Aging [ppm]

Bit Rate: 2.4kbps

Transmitter Deviation [+/- kHz]

30

60

90

120

150

180

210

315 MHz

30

20

10

75

50

25

100

75

100

60

100

75

100

75

100

433 MHz

868 MHz

915 MHz

40

50

75

Bit Rate: 9.6kbps

Transmitter Deviation [+/- kHz]

30

60

90

120

150

180

210

315 MHz

433 MHz

868 MHz

915 MHz

25

15

8

70

50

25

100

75

100

60

100

75

100

75

100

40

8

40

50

70

75

Bit Rate: 38.3kbps

Transmitter Deviation [+/- kHz]

30

60

90

120

150

180

210

315 MHz

433 MHz

868 MHz

915 MHz

don’t use

don't use

30

20

10

75

50

30

25

100

75

100

60

100

75

100

75

40

60

75

Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by

changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is

in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C₀.

Note: There may be other requirements for the TX carrier accuracy with regards to the requirements as defined by standards and/or channel

separations.

23

Si4020

RESET MODES

The chip will enter into reset mode if any of the following conditions are met:

• Power-on reset: During a power up sequence until the V_ddhas reached the correct level and stabilized

• Power glitch reset: Transients present on the V_ddline

• Software reset: Special control command received by the chip

Power-on reset

After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp

signal), which is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual

V_ddand the internal reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the V_ddvoltage

is less than 1.6V (typical) the chip stays in reset mode regardless the voltage difference between the V_ddand the internal ramp

signal.

The reset event can last up to 150ms supposing that the V_ddreaches 90% its final value within 1ms. During this period the chip does

not accept control commands via the serial control interface.

Power-on reset example:

Power glitch reset

The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be

changed by the appropriate control command (see Related control commands at the end of this section). In normal mode the power

glitch detection circuit is disabled.

There can be spikes or glitches on the V_ddline if the supply filtering is not satisfactory or the internal resistance of the power supply is

too high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the V_ddhas

a rising rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the V_ddreaches the reset

threshold voltage (600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of

the current consumption (for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason

the sensitive reset cannot be disabled step-by-step decrease of the current consumption (by turning off the different stages one by

one) can help to avoid this problem.

Any negative change in the supply voltage will not cause reset event unless the V_ddlevel reaches the reset threshold voltage (250mV

in normal mode, 1.6V in sensitive reset mode).

If the sensitive mode is disabled and the power supply turned off the V_ddmust drop below 250mV in order to trigger a power-on reset

event when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that

no reset will be generated upon power-up because the power glitch detector circuit is disabled.

Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.

24

Si4020

Sensitive Reset Enabled, Ripple on V_dd:

V_dd

Reset threshold voltage

(600mV)

Reset ramp line

(100mV/ms)

1.6V

time

H

nRes

output

L

Sensitive reset disabled:

V_dd

Reset threshold voltage

(600mV)

Reset ramp line

(100mV/ms)

250mV

time

H

nRes

output

L

Software reset

Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The

result of the command is the same as if power-on reset was occurred.

V_ddline filtering

During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to

keep the V_ddline as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part

getting out from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the

disturbing signal below 10mV_p-pin the DC – 50kHz range for 200ms from V_ddramp start.. Typical example when a switch-mode

regulator is used to supply the radio, switching noise may be present on the V_ddline. Follow the manufacturer’s recommendations

how to decrease the ripple of the regulator IC and/or how to shift the switching frequency.

Related control commands

“Low Battery Detector Command”

Setting bit<6> to high will change the reset mode to normal from the default sensitive.

“SW Reset Command”

Issuing FF00h command will trigger software reset. See the Wake-up Timer Command.

25

Si4020

SIMPLIFIED INTERNAL CONTROL AND TIMING

The internal controller uses the clock generated by the crystal oscillator to sequentially process the various events and to de-bounce

the push-button (PB) inputs. If the oscillator is not running, internal logic automatically turns it on temporarily and then off again.

Such events are: any wake-up event (POR, PB press, wake-up timer timeout, and low supply voltage detection), PB release and

status read request by the microcontroller.

If two wake-up events occur in succession, the crystal oscillator stays on until the next status read (acknowledgment of the first

event).

Simplified Internal Control and Timing Diagrams

Microcontroller mode (ec=0, ex=0)

Vdd

POR

(internal)

Push-button

inpu t x

Debouncing Time + T sx*

Osc_On

(In terna l)

SPI

Status rd cmd

nIRQ

Stat. b its

(PO R)

Stat. b its

(PB x)

Tsx*

Microcontroller modewith multiple event read (ec=0, ex=0)

Vdd

POR

(internal)

Push-button

inpu t x

Osc_On

(In terna l)

SPI

Status rd cmd

nIRQ

Stat. b its

(PO R)

Stat. b its

(PB x)

1us

Tsx*

Microcontroller mode (ec=1, ex=0)

Vdd

POR

(internal)

Push-button

inpu t x

Osc_On

(In terna l)

SPI

Status rd

Slee p cmd

Status rd

Sleep cmd

Tclk_tail**

Note:

Tsx : Crystal oscillator st

*

artup t ime

** Length of Tclk_tail is determined by the parameter in the Sleep comm

a nd

26

Si4020

MATCHING NETWORK FOR A 50 OHM SINGLE ENDED OUTPUT

Matching Network Schematic

Si4020

L1 [nH]

72

L2 [nH]

110

82

L3 [nH]

390

C1 [pF]

3.9

C2 [pF]

C3 [pF]

56..100

27..56

315 MHz

433 MHz

868 MHz

915 MHz

2.2

1.5

1

43

390

2.7

10

27

100

1.8

10

27

100

1.8

1

27..56

27

Si4020

EXAMPLE APPLICATIONS

For Microcontroller Mode

Schematic

PCB Layout of Keyboard Transmitter Demo Circuit Using Microcontroller Mode (operating in the 915 MHz band)

Bottom Layer

Top Layer

28

Si4020

For EEPROM Mode

Schematic

PCB Layout of Push-Button Transmitter Demo Circuit Using EEPROM Mode (operating in the 434 MHz band)

Bottom Layer

Top Layer

29

Si4020

PACKAGE INFORMATION

16-pin TSSOP

See Detail “A”

Section B-B

Gauge Plane

0.25

Detail “A”

Dimensions in mm

Nom.

Dimensions in Inches

Nom.

Symbol

Min.

Max.

Min.

Max.

0,047

0,006

0,041

0,012

0,010

0,008

0,006

0,201

A

1,20

0,15

1,05

0,30

0,25

0,20

0,16

5,10

A1

A2

b

0,05

0,80

0,19

0,09

4,90

0,002

0,031

0,007

0,004

0,90

0,22

0,035

0,009

b1

c

c1

D

5,00

0.65 BSC.

6.40 BSC.

4,40

0,193

0,197

0.026 BSC.

0.252 BSC.

0,173

e

E

E1

L

4,30

0,50

4,50

0,75

0,169

0,020

0,177

0,030

0,60

0,024

L1

R

1.00 REF.

0.39 REF.

0,09

0

0,004

0

R1

1

8

2

3

12 REF.

30

Si4020

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31

Si4020


型号：	SI4020
厂家：	SILICON
描述：	Fully integrated (Iow BOM, easy design-in) No alignment required in production Fast settling, programmable, high-resolution PLL 完全集成（ IOW BOM ，易于设计的）无生产快速稳定所需的对齐方式，可编程，高清晰度PLL
文件：	总32页 (文件大小：1064K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI4020 [SILICON]

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