SI53152-A01AGMR_技术文档

Si53152

PCI-EXPRESS

G

EN 1, GEN 2, GEN 3, AND

G

EN

4

F

ANOUT

B

UFFER

Features



PCI-Express Gen 1, Gen 2, Gen 3,  Dedicated output enable pin for

and Gen 4 common clock

compliant

Supports Serial ATA (SATA) at

100 MHz

100–210 MHz operation

Low power, push pull, differential

output buffers

Internal termination for maximum

integration

each clock

Two PCI-Express buffered clock

outputs

Supports LVDS outputs

I²C support with readback

capabilities

Extended temperature:

–40 to 85 °C

3.3 V Power supply

24-pin QFN package



Ordering Information:

See page 17

Applications



Network attached storage

Multi-function Printer



Wireless access point

Routers

Pin Assignments

Description

24

23

22

21

20

19

OE_DIFF1*

VDD

18

17

16

15

VDD

1

2

3

4

5

6

The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source

two PCIe clocks simultaneously. The device has two hardware output enable

inputs for enabling the respective differential outputs on the fly. The device

also features output enable control through I²C communication. I²C

programmability is also available to dynamically control skew, edge rate and

amplitude on the true, compliment, or both differential signals on the clock

outputs. This control feature enables optimal signal integrity as well as

optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is

quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for

free at www.silabs.com/pcie-learningcenter.

NC

VDD

DIFF1

25

GND

VSS

14 DIFF0

OE_DIFF0*

VDD

13

DIFF0

7

8

9

10

11

12

*Note: Internal 100 kohm pull-up.

Patents pending

Functional Block Diagram

DIFF0

DIFFIN

DIFF1

Control & Memory

SCLK

SDATA

Control

RAM

OE [1:0]

Rev. 1.2 4/16

Si53152

2

Rev. 1.2

Si53152

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Rev. 1.2

3

Si53152

1. Electrical Specifications

Table 1. DC Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

3.3 V Operating Voltage

VDD core

3.3 ± 5%

3.135

3.3

3.465

V

3.3 V Input High Voltage

3.3 V Input Low Voltage

Input High Voltage

V

Control input pins

SDATA, SCLK

2.0

—

V

+ 0.3

V

IH

DD

V

– 0.3

0.8

IL

SS

V

2.2

—

1.0

5

V

IHI2C

Input Low Voltage

V

SDATA, SCLK

—

V

ILI2C

Input High Leakage Current

I

Except internal pull-down

A

IH

resistors, 0 < V < V

IN

DD

Input Low Leakage Current

I

Except internal pull-up resis-

tors, 0 < V < V

–5

—

A

IL

IN

DD

3.3 V Output High Voltage

(Single-Ended Outputs)

V

I

= –1 mA

2.4

—

0.4

10

V

OH

3.3 V Output Low Voltage

(Single-Ended Outputs)

V

I

OL

= 1 mA

OL

OZ

High-impedance Output

Current

I

–10

µA

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

C

1.5

—

5

6

pF

IN

C

OUT

L

7

nH

mA

IN

DD_3.3V

Dynamic Supply Current

I

All outputs enabled. Differ-

ential clock with 5” traces

and 2 pF load at 100 MHz.

20

4

Rev. 1.2

Si53152

Table 2. AC Electrical Specifications

Parameter

DIFFIN at 0.7 V

Symbol

Test Condition

Min

Typ

Max Unit

Input Frequency Range

f

100

0.6

—

210

4

MHz

V/ns

in

Rising and Falling Slew Rates for

Each Clock Output Signal in a

Given Differential Pair

T / T

Single ended measurement:

R

F

V

= 0.175 to V = 0.525 V

OL

OH

(Averaged)

Differential Input High Voltage

Differential Input Low Voltage

V

150

—

mV

IH

V

–150

550

IL

Crossing Point Voltage at 0.7 V

Swing

V

Single-ended measurement

250

OX

Vcross Variation over all edges

Differential Ringback Voltage

Time before ringback allowed

V

—

140

100

—

mV

ps

OX

V

–100

500

RB

STABLE

T

Absolute Maximum Input

Voltage

V

1.15

V

MAX

Absolute Minimum Input

Voltage

V

–0.3

45

—

V

MIN

Duty Cycle for Each Clock

Output Signal in a Given

Differential Pair

T

Measured at crossing point V

Determined as a fraction of

55

%

DC

OX

Rise/Fall Matching

T

—

20

%

RFM

2 x (T – T )/(T + T )

R

F

R

F

DIFF at 0.7 V

Duty Cycle

T

Measured at 0 V differential

45

—

0

—

55

50

%

ps

DC

Clock Skew

T

SKEW

Additive Peak Jitter

Pk-Pk

10

Additive PCIe Gen 2

Phase Jitter

RMS

10 kHz < F < 1.5 MHz

0

0.5

0.10

GEN2

1.5 MHz< F < Nyquist Rate

0

Additive PCIe Gen 3

Phase Jitter

RMS

Includes PLL BW 2–4 MHz

(CDR = 10 MHz)

0

GEN3

GEN4

Additive PCIe Gen 4 Phase Jitter RMS

PCIe Gen 4

—

0.10

50

ps

Additive Cycle to Cycle Jitter

Long Term Accuracy

Notes:

T

Measured at 0 V differential

CCJ

L

100

ppm

ACC

1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

Rev. 1.2

5

Si53152

Table 2. AC Electrical Specifications (Continued)

Parameter

Symbol

T / T

Test Condition

Min

Typ

Max Unit

Rising/Falling Slew Rate

Measured differentially from

±150 mV

2.5

—

8

V/ns

R

F

Crossing Point Voltage at 0.7 V

Swing

V

300

—

550

mV

OX

Enable/Disable and Set-Up

Clock Stabilization from

Power-up

T

Measured from the point when

—

5

ms

ns

STABLE

both V and clock input are valid

DD

Stopclock Set-up Time

T

10.0

—

SS

Notes:

1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

Table 3. Absolute Maximum Conditions

Parameter

Main Supply Voltage

Symbol

Test Condition

Min

Typ

Max Unit

V

Functional

—

4.6

150

85

V

DD_3.3V

Input Voltage

V

Relative to V

–0.5

–65

–40

—

V

DC

IN

SS

Temperature, Storage

T

Non-functional

Functional

°C

S

Temperature, Operating Ambient

Temperature, Junction

T

—

°C

A

T

Functional

—

150

35

J

Dissipation, Junction to Case

Dissipation, Junction to Ambient

ESD Protection (Human Body Model)

Flammability Rating

Ø

JEDEC (JESD 51)

—

°C/W

V

JC

JA

—

37

ESD

JEDEC (JESD 22-A114) 2000

UL (Class)

—

HBM

UL-94

V–0

Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up.

Power supply sequencing is not required.

6

Rev. 1.2

Si53152

2. Functional Description

2.1. OE Pin Definition

The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE

2

pin needs to be logic high and the I C output enable bit needs to be logic high. There are two methods to disable

2

the output clocks: the OE is pulled to a logic low, or the I C enable bit is set to a logic low. The OE pins are required

to be driven at all times even though they have an internal 100 k resistor.

2.2. OE Assertion

The OE signals are active high inputs used for synchronous stopping and starting the DIFF output clocks respectively

while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high

causes stopped respective DIFF outputs to resume normal operation. No short or stretched clock pulses are

produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two

to six output clock cycles.

2.3. OE Deassertion

When the OE pin is deasserted by making it logic low, the corresponding DIFF output is stopped, and the final output

state is driven low.

Rev. 1.2

7

Si53152

3. Test and Measurement Setup

This diagram shows the test load configuration for differential clock signals.

M easurem ent

P oint

L1

O U T+

50

2 pF

L1 = 5"

M easurem ent

P oint

L1

O U T-

50

Figure 1. 0.7 V Differential Load Configuration

Figure 2. Differential Output Signals (for AC Parameters Measurement)

8

Rev. 1.2

Si53152

V_MIN= –0.30V

Figure 3. Single-ended Measurement for Differential Output Signals

(for AC Parameters Measurement)

Rev. 1.2

9

Si53152

4. Control Registers

2

4.1. I C Interface

2

To enhance the flexibility and function of the clock buffer, an I C interface is provided. Through the I C Interface,

various device functions are available, such as individual clock output enable. The registers associated with the I C

2

Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register

changes are normally made at system initialization, if any are required. Power management functions can only be

programed in program mode and not in normal operation modes.

4.2. Data Protocol

2

The I C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block

write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller

can access individually indexed bytes.

The block write and block read protocol is outlined in Table 4 while Table 5 outlines byte write and byte read

protocol. The slave receiver address is 11010110 (D6h).

Table 4. Block Read and Block Write Protocol

Block Write Protocol

Description

Block Read Protocol

Description

Bit

1

Bit

1

Start

8:2

9

8:2

9

Slave address—7 bits

Write

Slave address—7 bits

Write

10

Acknowledge from slave

Command Code—8 bits

Acknowledge from slave

Byte Count—8 bits

Acknowledge from slave

Command Code—8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

27:21

28

Acknowledge from slave

Data byte 1—8 bits

Acknowledge from slave

Data byte 2—8 bits

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N—8 bits

Acknowledge from slave

Stop

Slave address—7 bits

Read = 1

36:29

37

29

Acknowledge from slave

Byte Count from slave—8 bits

Acknowledge

45:38

46

37:30

38

....

46:39

47

Data byte 1 from slave—8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave—8 bits

Acknowledge

....

Data bytes from slave/Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

Stop

....

10

Rev. 1.2

Si53152

Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol

Description

Byte Read Protocol

Description

Bit

1

Start

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

37:30

38

39

Rev. 1.2

11

Si53152

Control Register 0. Byte 0

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

R/W

Reset settings = 00000000

Bit

Name

Reserved

Function

7:0

Control Register 1. Byte 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

R/W

Reset settings = 00000000

Bit

Name

Reserved

Function

7:0

12

Rev. 1.2

Si53152

Control Register 2. Byte 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

DIFF0_OE

DIFF1_OE

Name

Type

R/W

Reset settings = 11000000

Bit

Name

Function

7

DIFF0_OE

Output Enable for DIFF0.

0: Output disabled.

1: Output enabled.

6

DIFF1_OE

Reserved

Output Enable for DIFF1

0: Output disabled.

1: Output enabled.

5:0

Control Register 3. Byte 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Rev Code[3:0]

Vendor ID[3:0]

R/W

Reset settings = 00001000

Bit

Name

Function

7:4

Rev Code[3:0]

Vendor ID[3:0]

Program Revision Code.

3:0

Vendor Identification Code.

Control Register 4. Byte 4

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

BC[7:0]

R/W

Reset settings = 00000110

Bit

Name

BC[7:0]

Function

7:0

Byte Count Register.

Rev. 1.2

13

Si53152

Control Register 5. Byte 5

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]

Type

R/W

R/W R/W R/W R/W

Reset settings = 11011000

Bit

Name

Function

7

DIFF_Amp_Sel

Amplitude Control for DIFF Differential Outputs.

0: Differential outputs with Default amplitude.

1: Differential outputs amplitude is set by Byte 5[6:4].

6

5

DIFF_Amp_Cntl[2]

DIFF_Amp_Cntl[1]

DIFF_Amp_Cntl[0]

Reserved

DIFF Differential Outputs Amplitude Adjustment.

000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV

100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV

4

3:0

14

Rev. 1.2

Si53152

5. Pin Descriptions: 24-Pin QFN

24

23

22

21

20

19

OE_DIFF1*

VDD

18

17

16

15

VDD

1

2

3

4

5

6

NC

VDD

DIFF1

25

GND

VSS

14 DIFF0

13

OE_DIFF0*

VDD

DIFF0

7

8

9

10

11

12

*Note: Internal 100 kohm pull-up.

Figure 4. 24-Pin QFN

Table 6. Si53152 24-Pin QFN Descriptions

Pin #

Name

Type

Description

PWR 3.3 V power supply.

1

VDD

NC No connect.

PWR 3.3 V power supply.

GND Ground.

2

3

4

5

NC

VDD

VSS

I,PU Active high input pin enables DIFF0 (internal 100 k pull-up).

OE_DIFF0

Refer to Table 1 on page 4 for OE specifications.

PWR 3.3 V power supply.

NC No connect.

6

7

VDD

NC

NC No connect.

8

NC

NC No connect.

9

NC

NC No connect.

10

11

12

13

14

15

NC

NC No connect.

NC

PWR 3.3 V power supply.

O, DIF 0.7 V, 100 MHz differential clock.

VDD

DIFF0

DIFF1

Rev. 1.2

15

Si53152

Table 6. Si53152 24-Pin QFN Descriptions (Continued)

Pin #

Name

Type

Description

O, DIF 0.7 V, 100 MHz differential clock.

PWR 3.3 V power supply.

16

DIFF1

VDD

17

18

I,PU Active high input pin enables DIFF1 (internal 100 k pull-up).

OE_DIFF1

Refer to Table 1 on page 4 for OE specifications.

I

SMBus compatible SCLOCK.

19

20

21

22

SCLK

SDATA

VDD

I/O SMBus compatible SDATA.

PWR 3.3 V power supply.

I

0.7 V Differential True Input, typically 100 MHz. Input frequency range

100 to 210 MHz.

DIFFIN

O

0.7 V Differential Complement Input, typically 100 MHz. Input frequency

range 100 to 210 MHz.

23

DIFFIN

GND Ground.

24

25

VSS

GND

GND Ground for bottom pad of the IC.

16

Rev. 1.2

Si53152

6. Ordering Guide

Part Number

Lead-free

Package Type

Temperature

Si53152-A01AGM

Si53152-A01AGMR

24-pin QFN

Extended, –40 to 85 C

24-pin QFN—Tape and Reel

Rev. 1.2

17

Si53152

7. Package Outline

Figure 5 illustrates the package details for the Si53152. Table 7 lists the values for the dimensions shown in the

illustration.

Figure 5. 24-Pin Quad Flat No Lead (QFN) Package

Table 7. Package Diagram Dimensions

Symbol

Millimeters

Nom

Min

0.70

0.00

0.20

Max

0.80

0.05

0.30

A

A1

b

0.75

0.025

0.25

D

4.00 BSC

2.70

D2

e

2.60

2.80

0.50 BSC

4.00 BSC

2.70

E

E2

L

2.60

0.30

2.80

0.50

0.40

aaa

bbb

ccc

ddd

0.10

0.08

0.07

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise

noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components

18

Rev. 1.2

Si53152

8. PCB Land Pattern

Figure 6. Si53152 24-Pin TDFN Land Pattern

Table 8. Si53152 24-Pin Land Pattern Dimensions

Dimension

mm

4.0

C1

C2

E

4.0

0.50 BSC

0.30

X1

X2

Y1

2.70

0.80

Rev. 1.2

19

Si53152

Table 8. Si53152 24-Pin Land Pattern Dimensions (Continued)

Y2

2.70

Notes:

General

1. All dimensions shown are in millimeters (mm).

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least

Material Condition (LMC) is calculated based on a Fabrication Allowance of

0.05 mm.

Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance

between the solder mask and the metal pad is to be 60 µm minimum, all the

way around the pad.

Stencil Design

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal

walls should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1 for all pads.

Card Assembly

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

20

Rev. 1.2

Si53152

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 1.0

 Updated Features and Description.

 Updated Table 2.

 Updated Table 3.

 Updated Section 4.1.

Revision 1.0 to Revision 1.1

 Updated Features on page 1.

 Updated Description on page 1.

 Updated specs in Table 2, “AC Electrical

Specifications,” on page 5.

Revision 1.1 to Revision 1.2

 Added condition for Clock Stabilization from Power-

up, T

, in Table 2.

STABLE

Rev. 1.2

21

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型号：	SI53152-A01AGMR
厂家：	SILICON
描述：	Low Skew Clock Driver, 53152 Series, 4 True Output(s), 0 Inverted Output(s), QFN-24 驱动逻辑集成电路
文件：	总22页 (文件大小：393K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI53152-A01AGMR [SILICON]

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