SI5323-B-GMR [SILICON]
Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36;
| 型号： | SI5323-B-GMR |
| 厂家： | 
SILICON |
| 描述： | Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36 衰减器 时钟 |
| 文件： | 总16页 (文件大小：648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5323
PRELIMINARY DATA SHEET
PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
Features
The Si5323 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging
from 8 kHz to 707 MHz and generates two equal
frequency-multiplied clock outputs ranging from 8 kHz
to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of
popular SONET, Ethernet, and Fibre Channel rates.
The Si5323 is based on Silicon Laboratories' 3rd-
Selectable output frequencies ranging from 8 kHz to
1050 MHz
Ultra-low jitter clock outputs with jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Dual clock inputs w/manual or automatically
controlled hitless switching
®
Dual clock outputs with selectable signal format
generation DSPLL technology, which provides any-
(LVPECL, LVDS, CML, CMOS)
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the
application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5323 is ideal for providing clock
multiplication and jitter attenuation in high performance
timing applications.
Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
LOL, LOS alarm outputs
Pin-controlled output phase adjust
Pin-programmable settings
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 line cards
Optical modules
Test and measurement
Xtal or Refclock
CKOUT1
CKIN1
®
Signal Format
DSPLL
CKOUT2
CKIN2
Disable/BYPASS
Loss of Signal
Loss of Lock
Control
Signal Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select
Bandwidth Select
Rate Select
Manua/l/Auto Switch
Clock Select
Latency Control
Preliminary Rev. 0.2 3/07
Copyright © 2007 by Silicon Laboratories
Si5323
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5323
Table 1. Performance Specifications
(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
Test Condition
Min
–40
Typ
25
Max
85
Unit
ºC
V
T
A
V
2.97
2.25
1.62
3.3
2.5
1.8
251
3.63
2.75
1.98
279
DD
V
V
Supply Current
I
f
= 622.08 MHz
mA
DD
OUT
Both CKOUTs enabled
LVPECL format output
CKOUT2 disabled
—
—
217
204
243
234
mA
mA
f
= 19.44 MHz
OUT
Both CKOUTs enabled
CMOS format output
CKOUT2 disabled
—
194
TBD
—
220
TBD
mA
mA
Tristate/Sleep Mode
Input Clock Frequency
(CKIN1, CKIN2)
CK
Input frequency and clock
multiplication ratio pin-select-
able from table of values
using FRQSEL and FRQTBL
settings. Consult Silicon Lab-
oratories configuration soft-
ware DSPLLsim or Any-Rate
Precision Clock Family Ref-
erence Manual at
0.008
0.008
707.35
MHz
F
Output Clock Frequency
(CKOUT1, CKOUT2)
CK
—
1049.76
MHz
OF
www.silabs.com/timing for table
selections.
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing CK
0.25
0.9
1.0
1.1
—
—
—
—
—
—
—
—
1.9
1.4
1.7
1.95
11
VPP
V
NDPP
Common Mode Voltage
CK
1.8V ±10%
2.5V ±10%
NVCM
V
3.3V ±10%
V
Rise/Fall Time
Duty Cycle
CK
20–80%
ns
%
NTRF
CK
Whichever is less
40
60
NDC
50
—
ns
Output Clocks (CKOUT1, CKOUT2)
Common Mode
V
LVPECL
100 Ω load
line-to-line
V
– 1.42
—
—
—
V – 1.25
DD
V
V
V
OCM
DD
Differential Output Swing
V
1.1
0.5
1.9
0.93
OD
Single Ended Output
Swing
V
SE
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.2
Si5323
Table 1. Performance Specifications (Continued)
(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Rise/Fall Time
Symbol
CKO
Test Condition
Min
—
Typ
230
—
Max
350
55
Unit
ps
20–80%
TRF
Duty Cycle
CKO
45
%
DC
PLL Performance
Jitter Generation
J
f
= 622.08 MHz,
—
0.3
TBD
ps rms
GEN
OUT
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
—
—
—
0.3
TBD
0.1
ps rms
dB
Jitter Transfer
J
0.05
TBD
PK
External Reference Jitter
Transfer
J
TBD
dB
PKEXTN
Phase Noise
CKO
f
= 622.08 MHz
—
TBD
TBD
dBc/Hz
PN
OUT
100 Hz offset
1 kHz offset
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz offset
100 kHz offset
1 MHz offset
Subharmonic Noise
Spurious Noise
Package
SP
SP
Phase Noise @ 100 kHz Off-
set
SUBH
SPUR
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
—
TBD
TBD
dBc
Thermal Resistance
Junction to Ambient
θ
Still Air
—
38
—
ºC/W
JA
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
V
DC Supply Voltage
V
–0.5 to 3.6
DD
DIG
JCT
STG
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
V
DD
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ)
ESD MM Tolerance
T
–55 to 150
–55 to 150
2
C
T
C
kV
V
200
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.2
3
Si5323
155.52 MHz in, 622.08 MHz out
0
-20
-40
-60
-80
-100
-120
-140
-160
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
4
Preliminary Rev. 0.2
Si5323
Figure 2. Si5323 Typical Application Circuit
Preliminary Rev. 0.2
5
Si5323
The Si5323 provides a digital hold capability that allows
the device to continue generation of a stable output
1. Functional Description
The Si5323 is a jitter-attenuating precision clock clock when the selected input reference is lost. During
multiplier for high-speed communication systems, digital hold, the DSPLL generates an output frequency
including SONET OC-48/OC-192, Ethernet, and Fibre based on a historical average that existed a fixed
Channel. The Si5323 accepts dual clock inputs ranging amount of time before the error event occurred,
from 8 kHz to 707 MHz and generates two frequency- eliminating the effects of phase and frequency
multiplied clock outputs ranging from 8 kHz to transients that may occur immediately preceding digital
1050 MHz.
The two input clocks are at the same hold.
frequency and the two output clocks are at the same
frequency. The input clock frequency and clock
multiplication ratio are selectable from a table of popular
SONET, Ethernet, and Fibre Channel rates. In addition
to providing clock multiplication in SONET and datacom
applications, the Si5323 supports SONET-to-datacom
frequency translations. Silicon Laboratories offers a PC-
based software utility, DSPLLsim, that can be used to
look up valid Si5323 frequency translations. This utility
can be downloaded from www.silabs.com/timing. This
information is also available in the Any-Rate Precision
Clock Family Reference Manual, also available from
www.silabs.com/timing.
The Si5323 has two differential clock outputs. The
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, the second clock output can be powered down
to minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. For system-level debugging, a bypass mode is
available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
1.1. External Reference
The Si5323 is based on Silicon Laboratories' 3rd- An external, 38.88 MHz clock or
a
low-cost
®
generation DSPLL technology, which provides any- 114.285 MHz 3rd overtone crystal is used as part of a
rate frequency synthesis and jitter attenuation in a fixed-frequency oscillator within the DSPLL. This
highly integrated PLL solution that eliminates the need external reference is required for the device to perform
for external VCXO and loop filter components. The jitter attenuation. Silicon Laboratories recommends
Si5323 PLL loop bandwidth is selectable via the using a high-quality crystal from TXC (www.txc.com.tw),
BWSEL[1:0] pins and supports a range from 60 Hz to part number 7MA1400014. An external 38.88 MHz
8.4 kHz. The DSPLLsim software utility can be used to clock from a high quality OCXO or TCXO can also be
calculate valid loop bandwidth settings for a given input used as a reference for the device.
clock frequency/clock multiplication ratio.
In digital hold, the DSPLL remains locked to this
The Si5323 supports hitless switching between the two external reference. Any changes in the frequency of this
input clocks in compliance with GR-253-CORE and GR- reference when the DSPLL is in digital hold will be
1244-CORE that greatly minimizes the propagation of tracked by the output of the device. Note that crystals
phase transients to the clock outputs during an input can have temperature sensitivities.
clock transition (<200 ps typ). Manual and automatic
1.2. Further Documentation
revertive and non-revertive input clock switching options
are available via the AUTOSEL input pin. The Si5323 Consult the Silicon Laboratories Any-Rate Precision
monitors both input clocks for loss-of-signal and Clock Family Reference Manual (FRM) for more
provides a LOS alarm when it detects missing pulses on detailed information about the Si5323. The FRM can be
either input clock. The device monitors the lock status of downloaded from www.silabs.com/timing.
the PLL. The lock detect algorithm works by
Silicon Laboratories has developed
a PC-based
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock.
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. This utility can be downloaded
from www.silabs.com/timing.
6
Preliminary Rev. 0.2
Si5323
2. Pin Descriptions: Si5323
36 35 34 33 32 31 30 29 28
RST
FRQTBL
C1B
1
27 FRQSEL3
26
2
3
4
5
6
7
8
9
FRQSEL2
25 FRQSEL1
C2B
24
23
FRQSEL0
BWSEL1
GND
Pad
VDD
XA
22 BWSEL0
XB
21
20
19
CS_CA
INC
GND
DEC
AUTOSEL
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 3. Si5323 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level Description
1
RST
I
LVCMOS
3-Level
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5323 will perform an internal self-calibration.
This pin has a weak pull-up.
2
FRQTBL
I
Frequency Table Select.
Selects SONET/SDH, datacom, or SONET/SDH to datacom
frequency table.
L = SONET/SDH
M = Datacom
H = SONET/SDH to Datacom
This pin has a weak pull-down.
3
4
C1B
C2B
O
O
LVCMOS
LVCMOS
CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
Preliminary Rev. 0.2
7
Si5323
Table 3. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
5, 10,
32
V
V
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V pins:
DD
DD
DD
5
10
32
0.1 µF
0.1 µF
0.1 µF
A 1.0 µF should be placed as close to device as is practical.
7
6
XB
XA
I
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator based reference. If external reference is
used, apply reference clock to XA input and leave XB pin
floating. External reference must be from a high-quality clock
source (TCXO, OCXO). Frequency of crystal or external
clock is set by the RATE pin.
8, 31
9
GND
GND
I
Supply
3-Level
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
AUTOSEL
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selec-
tion to be used.
L = Manual
M = Automatic non-revertive
H = Automatic revertive
11
15
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external
crystal or reference clock to be applied to the XA/XB port.
RATE[1:0]
LM
MM
HH
= 38.88 MHz external clock
= 114.285 MHz 3rd OT Crystal
= Converts part to Si5322
= Reserved
All Others
12
13
CKIN2+
CKIN2–
I
I
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
14
DBL2_BY
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled
8
Preliminary Rev. 0.2
Si5323
Table 3. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
16
17
CKIN1+
CKIN1–
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
19
LOL
O
LVCMOS
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
DEC
I
Latency Decrement.
A pulse on this pin decreases the input to output device
latency by 1/f
(approximately 200 ps). There is no limit on
OSC
the range of latency adjustment by this method. If both INC
and DEC are tied high, phase buildout is disabled and the
device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input
clock transition. Detailed operations and timing characteris-
tics for this pin may be found in the Any-Rate Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
20
INC
I
LVCMOS
Latency Increment.
A pulse on this pin increases the input to output device
latency by 1/f
(approximately 200 ps). There is no limit on
OSC
the range of latency adjustment by this method. If both INC
and DEC are tied high, phase buildout is disabled and the
device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input
clock transition. Detailed operations and timing characteris-
tics for this pin may be found in the Any-Rate Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
21
CS_CA
I/O
LVCMOS
Input Clock Select/Active Clock Indicator.
If manual clock selection mode is chosen (AUTOSEL = L),
this pin functions as the manual input clock selector. This
input is internally deglitched to prevent inadvertent clock
switching during changes in the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If automatic clock selection mode is chosen (AUTOSEL = M
or H), this pin indicates which of the two input clocks is cur-
rently the active clock. If alarms exist on both CKIN1 and
CKIN2, indicating that the digital hold state has been
entered, CA will indicate the last active clock that was used
before entering the hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
Preliminary Rev. 0.2
9
Si5323
Table 3. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
23
22
BWSEL1
BWSEL0
I
3-Level
Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock
Family Reference Manual.
27
26
25
24
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
I
O
I
3-Level
Multiplier Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting. Consult
the Any-Rate Precision Clock Family Reference Manual or
DSPLLsim configuration software for settings, both available
for download at www.silabs.com/timing.
29
28
CKOUT1–
CKOUT1+
Multi
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
33
30
SFOUT0
SFOUT1
3-Level
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
SFOUT[1:0]
Signal Format
Reserved
HH
HM
HL
Reserved
CML
MH
MM
ML
LH
LVPECL
Reserved
LVDS
CMOS
LM
LL
Tristate/Sleep
Reserved
34
35
CKOUT2–
CKOUT2+
O
Multi
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
36
NC
—
—
No Connect.
These pins must be left unconnected for normal operation.
GND
PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
10
Preliminary Rev. 0.2
Si5323
3. Ordering Guide
Ordering Part Number
Si5323-B-GM
Package
Temperature Range
36-Lead 6 x 6 mm QFN
–40 to 85 °C
Preliminary Rev. 0.2
11
Si5323
4. Package Outline: 36-Lead QFN
Figure 3 illustrates the package details for the Si5323. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 3. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.75
12º
A
A1
b
L
0.01
θ
0.23
aaa
bbb
ccc
ddd
eee
—
—
0.10
0.10
0.05
0.10
0.05
D
6.00 BSC
4.10
—
—
D2
e
3.95
4.25
—
—
0.50 BSC
6.00 BSC
4.10
—
—
E
—
—
E2
3.95
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
12
Preliminary Rev. 0.2
Si5323
5. Recommended PCB Layout
Figure 4. PCB Land Pattern Diagram
Preliminary Rev. 0.2
13
Si5323
Table 5. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
14
Preliminary Rev. 0.2
Si5323
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Updated Figure 2, “Si5323 Typical Application
Circuit,” on page 5 to show external reference
interface.
Added RATE0 and expanded the RATE[1:0]
description in 2. ‘Pin Descriptions: Si5323”.
Updated 3."Ordering Guide" on page 11.
Added 5. ‘Recommended PCB Layout”.
Preliminary Rev. 0.2
15
Si5323
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: Clockinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
16
Preliminary Rev. 0.2
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