Si5376B-A-GL [SILICON]
4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR;
| 型号： | Si5376B-A-GL |
| 厂家： | 
SILICON |
| 描述： | 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR 衰减器 |
| 文件： | 总66页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5376
4-PLL ANY-FREQUENCY PRECISION CLOCK
MULTIPLIER/JITTER ATTENUATOR
Features
Highly-integrated, 4 PLL clock
multiplier/jitter attenuator
Four independent DSPLLs support
any-frequency synthesis and jitter
attenuation
Supports all ITU G.709 and any
custom FEC ratios (239/237,
255/238, 255/237, 255/236, 253/226)
Integrated loop filter with
programmable bandwidth
Simultaneous free-run and
synchronous operation
Automatic/manual hitless input clock
switching
Selectable output clock signal format
(LVPECL, LVDS, CML, CMOS)
LOL and interrupt alarm outputs
I2C programmable
Single 1.8 V ±5% or 2.5 V ±10%
operation with high PSRR on-chip
voltage regulator
8 inputs/8 outputs
Each DSPLL can generate any
frequency from 2 kHz to 808 MHz
from a 2 kHz to 710 MHz input
350 fs rms (12 kHz– 20 MHz) and
410 fs rms (50 kHz–80 MHz)
typical
Meets ITU-T G.8251 and Telcordia
GR-253-CORE OC-192 jitter
specifications
Programmable loop bandwidth:
60 Hz to 8 kHz
Faster lock acquisition compared to
the Si5374: <1.2 s
Ordering Information:
See page 61.
10x10 mm PBGA
For a very low-loop BW version, see
the Si5374
Applications
High-density, any-port, any-protocol, 1/2/4/8/10G Fibre Channel
any-frequency line cards
ITU-T G.709 OTN custom FEC
10/40/100G
GbE/10 GbE Synchronous Ethernet
Carrier Ethernet, multi-service
switches and routers
MSPP, ROADM, P-OTS,
muxponders
OC-48/192, STM-16/64
Description
The Si5376 is a highly-integrated, 4-PLL, jitter-attenuating precision clock
multiplier for applications requiring sub-1 ps jitter performance. Each of the
DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to
710 MHz and generates two independent synchronous output clocks ranging
from 2 kHz to 808 MHz. The device provides virtually any frequency translation
combination across this operating range. For asynchronous, free-running clock
generation applications, the Si5376’s reference oscillator can be used as a clock
source for any of the four DSPLLs. The Si5376 input clock frequency and clock
multiplication ratio are programmable through an I2C interface. The Si5376 is
based on Silicon Laboratories’ third-generation DSPLL® technology, which
provides any-frequency synthesis and jitter attenuation in a highly-integrated
PLL solution that eliminates the need for external VCXO and loop filter
components. Each DSPLL loop bandwidth is digitally-programmable, providing
jitter performance optimization at the application level. The device operates from
a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR.
The Si5376 is ideal for providing clock multiplication and jitter attenuation in
high-port-count optical line cards requiring independent timing domains.
Rev. 1.0 9/12
Copyright © 2012 by Silicon Laboratories
Si5376
Si5376
Functional Block Diagram
PLL Bypass
Input Stage
Synthesis Stage
Output Stage
CKIN1P_A
PLL Bypass
CKOUT1P_A
CKOUT1N_A
÷ N31
Input
Monitor
CKIN1N_A
÷ NC1
f3
f3
f3
®
fOSC
DSPLL
÷ NC1_HS
÷ NC1_HS
÷ NC1_HS
÷ NC1_HS
CKIN2P_A
Hitless
Switch
A
CKIN2N_A
÷ NC2
÷ N32
CKOUT2P_A
CKOUT2N_A
Internal
Osc
PLL Bypass
÷ N2
PLL Bypass
CKIN3P_B
PLL Bypass
CKOUT3P_B
CKOUT3N_B
÷ N31
Input
Monitor
CKIN3N_B
÷ NC1
®
fOSC
fOSC
fOSC
DSPLL
CKIN4P_B
Hitless
Switch
B
CKIN4N_B
÷ NC2
÷ N32
CKOUT4P_B
CKOUT4N_B
Internal
Osc
PLL Bypass
÷ N2
PLL Bypass
CKIN5P_C
PLL Bypass
CKOUT5P_C
CKOUT5N_C
÷ N31
Input
Monitor
CKIN5N_C
÷ NC1
®
DSPLL
CKIN6P_C
Hitless
Switch
C
CKIN6N_C
÷ NC2
÷ N32
CKOUT6P_C
CKOUT6N_C
Internal
Osc
PLL Bypass
÷ N2
PLL Bypass
CKIN7P_D
PLL Bypass
CKOUT7P_D
CKOUT7N_D
÷ N31
Input
Monitor
CKIN7N_D
÷ NC1
f3
®
DSPLL
CKIN8P_D
Hitless
Switch
D
CKIN8N_D
÷ NC2
÷ N32
CKOUT8P_D
CKOUT8N_D
Internal
Osc
PLL Bypass
÷ N2
RSTL_q
VDD_q
GND
High PSRR
Voltage Regulator
Status / Control
CS_CA_q
OSC_P/N
Low Jitter
XO or Clock
SCL SDA
IRQ_q
LOL_q
2
Rev. 1.0
Si5376
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3. Typical Phase Noise Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5. Si5376 Application Examples and Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.1. Schematic and PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.2. Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.3. SCL Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.4. RSTL_x Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.5. Reference Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.6. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.7. OSC_P and OSC_N Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
8. Pin Descriptions: Si5376 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
10. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
12.1. Si5376 Top Marking (PBGA, Lead-Free) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
12.2. Top Marking Explanation (PBGA, Lead-Free) . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
12.3. Si5376 Top Marking (PBGA, Lead-Finish) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
12.4. Top Marking Explanation (PBGA, Lead-Finish) . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Rev. 1.0
3
Si5376
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Ambient Temperature
T
–40
2.25
1.71
25
2.5
1.8
85
C
V
V
A
Supply Voltage during
Normal Operation
V
2.5 V Nominal
1.8 V Nominal
2.75
1.89
DD
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
V
SIGNAL +
Single-Ended
Peak-to-Peak Voltage
V
ICM , VOCM
Differential I/Os
VISE,VOSE
SIGNAL –
(SIGNAL +) – (SIGNAL –)
Differential Peak-to-Peak Voltage
V ,VOD
ID
VICM, VOCM
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
Figure 1. Differential Voltage Characteristics
80%
20%
CKIN, CKOUT
tF
tR
Figure 2. Rise/Fall Time Characteristics
4
Rev. 1.0
Si5376
Table 2. DC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1
Supply Current
I
LVPECL Format
622.08 MHz Out
—
1000
1100
mA
DD
All CKOUTs Enabled
LVPECL Format
622.08 MHz Out
4 CKOUTs Enabled
—
—
—
—
870
820
780
660
970
940
880
—
mA
mA
mA
mA
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
CMOS Format
19.44 MHz Out
4 CKOUTs Enabled
Disable Mode
2
CKINn Input Pins
Input Common Mode
Voltage (Input Thresh-
old Voltage)
V
1.8 V ± 5%
2.5 V ± 10%
Single-ended
0.9
1
—
—
40
—
1.4
1.7
60
—
V
V
ICM
Input Resistance
CKN
20
0.2
k
RIN
Single-Ended Input
Voltage Swing
(See Absolute Specs)
V
f
f
f
f
< 212.5 MHz
V
V
V
V
ISE
CKIN
PP
PP
PP
PP
See Figure 1.
> 212.5 MHz
0.25
0.2
—
—
—
—
—
—
CKIN
See Figure 1.
< 212.5 MHz
CKIN
Differential Input
Voltage Swing
(See Absolute Specs)
V
ID
See Figure 1.
> 212.5 MHz
0.25
CKIN
See Figure 1.
3,4
Output Clocks (CKOUTn)
Common Mode
CKO
LVPECL 100 load
V
1.42
–
—
—
V –1.25
DD
V
VCM
DD
line-to-line
Differential Output
Swing
CKO
LVPECL 100 load
1.1
1.9
V
PP
VD
line-to-line
Notes:
1. Current draw is independent of supply voltage.
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD = 2.5 V.
4. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
5
Si5376
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single Ended Output
Swing
CKO
LVPECL 100 load
0.5
—
0.93
V
VSE
PP
line-to-line
Differential Output
Voltage
CKO
CML 100 load
350
—
425
500
—
mV
VD
PP
line-to-line
Common Mode Output
Voltage
CKO
CML 100 load
V
–0.36
DD
V
VCM
line-to-line
Differential Output
Voltage
CKO
LVDS
100 load line-to-line
500
350
1.125
—
700
425
1.2
900
500
1.275
—
mV
mV
VD
PP
PP
Low Swing LVDS
100 load line-to-line
Common Mode Output
Voltage
CKO
LVDS 100 load
V
VCM
line-to-line
Differential Output
Resistance
CKO
CML, LVPECL, LVDS
200
RD
Output Voltage Low
CKO
CKO
CMOS
—
—
—
0.4
—
V
V
VOLLH
Output Voltage High
V
= 1.71 V
0.8 x
VOHLH
DD
CMOS
ICMOS[1:0] = 11
= 1.8 V
V
DD
Output Drive Current
(CMOS driving into
CKO
—
7.5
5.5
3.5
1.75
20
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
mA
IO
V
DD
CKO
for output low
VOL
ICMOS[1:0] = 10
= 1.8 V
—
—
—
—
—
—
—
or CKO
for output
VOH
V
DD
high. CKOUT+ and
CKOUT– shorted
externally)
ICMOS[1:0] = 01
= 1.8 V
V
DD
ICMOS[1:0] = 00
= 1.8 V
V
DD
ICMOS[1:0] = 11
= 2.5 V
V
DD
ICMOS[1:0] = 10
= 2.5 V
15
V
DD
ICMOS[1:0] = 01
= 2.5 V
10
V
DD
ICMOS[1:0] = 00
= 2.5 V
5
V
DD
Notes:
1. Current draw is independent of supply voltage.
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD = 2.5 V.
4. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6
Rev. 1.0
Si5376
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
2-Level LVCMOS Input Pins
Input Voltage Low
Input Voltage High
V
V
V
V
V
= 1.71 V
= 2.25 V
= 1.89 V
= 2.25 V
—
—
—
—
—
—
0.5
0.7
—
V
V
V
V
IL
DD
DD
DD
DD
V
1.4
1.8
IH
—
LVCMOS Output Pins
Output Voltage Low
V
IO = 2 mA
= 1.71 V
—
—
—
—
—
—
0.4
0.4
—
V
V
V
V
OL
V
V
DD
Output Voltage Low
Output Voltage High
Output Voltage High
Notes:
IO = 2 mA
= 2.25 V
DD
V
IO = –2 mA
= 1.71 V
V
–
DD
0.4
OH
V
DD
IO = –2 mA
= 2.25 V
V
–
—
DD
0.4
V
DD
1. Current draw is independent of supply voltage.
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD = 2.5 V.
4. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
7
Si5376
Table 3. AC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1
Single-Ended Reference Clock Input Pin OSC_P (OSC_N with cap to GND)
OSC_P to OSC_N
Resistance
OSC
RATE_REG = 0101 or
0110, ac coupled
—
100
—
—
RIN
Input Voltage Swing
OSC
RATE_REG = 0101 or
0110, ac coupled
0.5
1.2
V
VPP
PP
1
Differential Reference Clock Input Pins (OSC_P/OSC_N)
Input Voltage Swing
OSC
RATE_REG = 0101 or
0110, ac coupled
0.5
—
2.4
V
VPP
PP
CKINn Input Pins
Input Frequency
CKN
0.002
40
—
—
710
60
MHz
%
F
Input Duty Cycle
(Minimum Pulse
Width)
CKN
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high-frequency
clocks)
DC
2
—
—
—
11
ns
ns
Input Rise/Fall Time
CKN
20–80%
—
TRF
See Figure 2
CKOUTn Output Pins
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKO
CKO
0.002
—
808
MHz
F
Maximum Output
Frequency in CMOS
Format
—
—
—
212.5
350
MHz
ps
F
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKO
CKO
CKO
Output not configured for
CMOS or Disabled
See Figure 2
230
TRF
Output Rise/Fall
(20–80%) @
212.5 MHz output
CMOS Output
—
—
—
—
8
2
ns
ns
TRF
TRF
V
= 1.71
DD
C
= 5 pF
LOAD
Output Rise/Fall
(20–80%) @
CMOS Output
= 2.25
V
DD
212.5 MHz output
C
= 5 pF
LOAD
Notes:
1. A crystal may not be used in place of an oscillator.
2. Input to output skew after an ICAL is not controlled and can be any value.
8
Rev. 1.0
Si5376
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Duty Cycle
Uncertainty @
622.08 MHz
CKO
100 Load
Line-to-Line
Measured at 50% Point
(differential)
—
—
±40
ps
DC
LVCMOS Input Pins
Minimum Reset Pulse
Width
t
1
—
—
—
µs
RSTMN
Reset to Microproces-
sor Access Ready
t
—
10
ms
READY
LVCMOS Output Pins
Rise/Fall Times
t
C
= 20pf
LOAD
—
—
25
—
—
ns
RF
See Figure 2
LOSn Trigger Window
LOS
From last CKINn to
Internal detection of LOSn
N3 ≠ 1
4.5 x N3
—
T
CKIN
TRIG
Time to Clear LOL
after LOS Cleared
t
LOS to LOL
Fold = Fnew
—
10
ms
CLRLOL
Stable OSC_P, OSC_N
reference
Notes:
1. A crystal may not be used in place of an oscillator.
2. Input to output skew after an ICAL is not controlled and can be any value.
Rev. 1.0
9
Si5376
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
2
Device Skew
Output Clock Skew
t
of CKOUTn to of
CKOUT_m, CKOUTn
and CKOUT_m at same
frequency and signal
format
—
—
100
ps
SKEW
PHASEOFFSET = 0
CKOUT_ALWAYS_ON = 1
SQ_ICAL = 1
Phase Change due to
Temperature Variation
t
Max phase changes from
–40 to +85 °C
—
300
500
ps
TEMP
Notes:
1. A crystal may not be used in place of an oscillator.
2. Input to output skew after an ICAL is not controlled and can be any value.
Table 4. Microprocessor Control
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
2
I C Bus Lines (SDA, SCL)
Input Voltage Low
VIL
—
—
—
—
—
—
0.25 x V
V
V
V
V
V
I2C
DD
Input Voltage High
VIH
0.7 x V
V
DD
I2C
DD
DD
Hysteresis of Schmitt
Trigger Inputs
VHYS
V
= 1.8 V
0.1 x V
—
I2C
DD
DD
V
= 2.5
0.05 x V
—
—
DD
DD
Output Voltage Low
VOL
V
= 1.8 V
0.2 x V
I2C
DD
IO = 3 mA
V
= 2.5
—
—
0.4
V
DD
IO = 3 mA
10
Rev. 1.0
Si5376
Table 5. Performance Specifications
VDD = 1.8 V ±5% or 2.5 V ±10%, TA = –40 to 85 °C
Parameter
PLL Performance*
Lock Time
Symbol
Test Condition
Min
Typ
Max
Unit
t
Start of ICAL to of LOL,
FASTLOCK disabled
—
—
35
1200
—
ms
ps
LOCKMP
Output Clock Phase Change
t
After clock switch
200
P_STEP
f3 128 kHz
Closed Loop Jitter Peaking
Jitter Tolerance
J
—
0.05
—
0.1
—
dB
PK
J
Jitter Frequency Loop
5000/BW
ns
TOL
Bandwidth
pk-pk
CKO
1 kHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
—
—
—
—
—
–106
–114
–116
–132
–70
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
Phase Noise
fout = 622.08 MHz
PN
Spurious Noise
Jitter Generation
SP
Max spur @ n x F3
(n 1, n x F3 < 100 MHz)
SPUR
J
f
= f
= 622.08 MHz,
—
350
410
fs rms
GEN
IN
OUT
BW = 120 Hz
LVPECL output
12 kHz–20 MHz
50 kHz–80 MHz
—
410
—
fs rms
*Note: fin = fout = 622.08 MHz; BW = 120 Hz; LVDS.
Rev. 1.0
11
Si5376
Table 6. Thermal Characteristics1,2
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Junction
Temperature
—
125
—
°C
Thermal Resistance
Junction to Ambient
Still Air
—
—
—
—
16
14
13
12
—
—
—
—
°C/W
°C/W
JA
Air Flow 1 m/s
Air Flow 2 m/s
Air Flow 3 m/s
Thermal Resistance
Junction to Case
Still Air
—
3.4
—
JC
Notes:
1. In most circumstances the Si5376 does not require special thermal management. A system level thermal analysis is
strongly recommend. Contact Silicon Labs applications for further details if required.
2. Thermal characteristic for the 80-pin Si5376 on an 8-layer PCB.
Table 7. Absolute Maximum Ratings
Parameter
DC Supply Voltage
Symbol
Value
Unit
V
V
–0.5 to 2.8
DD
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
V
DIG
DD
CLKINnP/N_q
CKN
OSC
0 to V
V
VIN
VIN
DD
OSC_P, OSC_N Voltage Limits
Operating Junction Temperature
Storage Temperature Range
0 to 1.2
–55 to 150
–55 to 150
2
V
T
°C
°C
kV
JCT
T
STG
ESD HBM Tolerance (100 pF, 1.5 k); All pins
except CKINnP/N-q
ESD MM Tolerance; All pins except
CKINnP/N_q
200
700
V
V
V
ESD HBM Tolerance (100 pF, 1.5 k);
CKINnP/N_q
ESD MM Tolerance; CKINnP/N_q
Latch-Up Tolerance
125
JESD78 Compliant
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
12
Rev. 1.0
Si5376
2. Typical Application Schematic
4-Port 10G Line Card
with SyncE and IEEE1588
Independent Port Timing
FPGA
Ethernet
Datapath
4
4
4
1588
Slave
PHY
IEEE
10G
Tx
Tx
Rx
Tx
Tx
SyncE
Recovered
Clocks
1588
Si5376
Recovered
Clocks
SyncE_1
1588_1
Port
Independent
Timing
(SyncE or 1588)
DSPLL
DSPLL
DSPLL
DSPLL
SyncE_2
1588_2
SyncE_3
1588_3
SyncE_4
1588_4
Rev. 1.0
13
Si5376
3. Typical Phase Noise Plot
155.52 MHz input
698.8123 MHz OTU4 output
295 fs RMS jitter (12 kHz to 20 MHz)
Figure 3. Typical Phase Noise Plot
14
Rev. 1.0
Si5376
4. Functional Description
PLL Bypass
Input Stage
Synthesis Stage
Output Stage
CKIN1P_A
CKIN1N_A
PLL Bypass
CKOUT1P_A
CKOUT1N_A
÷ N31
Input
Monitor
÷ NC1
f3
f3
f3
f3
®
fOSC
DSPLL
÷ NC1_HS
÷ NC1_HS
÷ NC1_HS
÷ NC1_HS
CKIN2P_A
CKIN2N_A
Hitless
Switch
A
÷ NC2
÷ N32
CKOUT2P_A
CKOUT2N_A
Internal
Osc
PLL Bypass
÷ N2
PLL Bypass
CKIN3P_B
CKIN3N_B
PLL Bypass
CKOUT3P_B
CKOUT3N_B
÷ N31
÷ N32
Input
Monitor
÷ NC1
®
fOSC
fOSC
fOSC
DSPLL
CKIN4P_B
CKIN4N_B
Hitless
Switch
B
÷ NC2
CKOUT4P_B
CKOUT4N_B
Internal
Osc
PLL Bypass
÷ N2
PLL Bypass
CKIN5P_C
CKIN5N_C
PLL Bypass
CKOUT5P_C
CKOUT5N_C
÷ N31
÷ N32
Input
Monitor
÷ NC1
®
DSPLL
CKIN6P_C
CKIN6N_C
Hitless
Switch
C
÷ NC2
CKOUT6P_C
CKOUT6N_C
Internal
Osc
PLL Bypass
÷ N2
PLL Bypass
CKIN7P_D
CKIN7N_D
PLL Bypass
CKOUT7P_D
CKOUT7N_D
÷ N31
Input
Monitor
÷ NC1
®
DSPLL
CKIN8P_D
CKIN8N_D
Hitless
Switch
D
÷ NC2
÷ N32
CKOUT8P_D
CKOUT8N_D
Internal
Osc
PLL Bypass
÷ N2
RSTL_q
VDD_q
GND
High PSRR
Voltage Regulator
Status / Control
CS_CA_q
OSC_P/N
Low Jitter
SCL SDA
IRQ_q
LOL_q
XO or Clock
Figure 4. Functional Block Diagram
The Si5376 is a highly integrated jitter-attenuating clock multiplier that integrates four fully independent DSPLLs
and provides ultra-low jitter generation with less than 410 fs RMS. Configuration and control of the Si5376 is mainly
2
handled through the I C interface. The device accepts clock inputs ranging from 2 kHz to 710 MHz and generates
independent, synchronous clock outputs ranging from 2 kHz to 808 MHz for each DSPLL. Virtually any frequency
translation (M/N) combination across its operating range is supported. The Si5376 supports a digitally
programmable loop bandwidth that can range from 60 Hz to 8.4 kHz requiring no external loop filter components.
An external single-ended or differential reference clock or XO is required for the device to enable ultra-low jitter
generation and jitter attenuation.
The device monitors each input clock for loss-of-signal (LOS) and provides a LOS alarm when missing pulses on
any of the input clocks are detected. The device monitors the lock status of each DSPLL and provides a Loss-of-
Lock (LOL) alarm when the DSPLL is unlocked. The lock detect algorithm continuously monitors the phase of the
selected input clock in relation to the phase of the feedback clock. The Si5376 provides a holdover capability that
allows the device to continue generation of a stable output clock when the input reference is lost. The reference
oscillator can be internally routed into CKIN2_q, so free-running clock generation is supported for each DSPLL
offering simultaneous synchronous and asynchronous operation.
The output drivers are configurable to support common signal formats, such as LVPECL, LVDS, CML, and CMOS
loads. If the CMOS signal format is selected, each differential output buffer generates two in-phase CMOS clocks
at the same frequency. For system-level debugging, a DSPLL bypass mode drives the clock output directly from
the selected input clock, bypassing the internal DSPLL.
Silicon Laboratories offers a PC-based software utility, Si537xDSPLLsim that can be used to determine valid
frequency plans and loop bandwidth settings to simplify device setup. Si537xDSPLLsim provides the optimum
input, output, and feedback divider values for a given input frequency and clock multiplication ratio that minimizes
phase noise. This utility can be downloaded from http://www.silabs.com/timing. For further assistance, refer to the
Si53xx Any-Frequency Precision Clocks Family Reference Manual.
Rev. 1.0
15
Si5376
5. Si5376 Application Examples and Suggestions
5.1. Schematic and PCB Layout
For a typical application schematic and PCB layout, see the Si537x-EVB Evaluation Board User's Guide, which
can be downloaded from www.silabs.com/timing.
In order to preserve the ultra low jitter of the Si5376 in applications where the four different DSPLL's are each
operating at different frequency, special care and attention must be paid to the PCB layout. The following is a list of
rules that should be observed:
1. The four Vdd supplies should be isolated from one another with four ferrite beads. They should be
separately bypassed with capacitors that are located very close to the Si5376 device.
2. Use a solid and undisturbed ground plane for the Si5376 and all of the clock input and output return paths.
3. For applications that wish to logically connect the four RESET signals, do not tie them together underneath
the BGA package. Instead connect them outside of the BGA footprint.
4. As much as is possible, do not route clock input and output signals underneath the BGA package. The
clock output signals should go directly outwards from the BGA footprint.
5. Avoid placing the OSC_P and OSC_N signals on the same layer as the clock outputs. Add grounded guard
traces surrounding the OSC_P and OSC_N signals.
6. Where possible, place the CKOUT and CKIN signals on separate PCB layers with a ground layer between
them. The use of ground guard traces between all clock inputs and outputs is recommended.
For more information, see the Si537x-EVB Evaluation Board User's Guide and Appendix I of the Si53xx Reference
Manual, Rev 0.5 or higher.
5.2. Thermal Considerations
The Si5376 dissipates a significant amount of heat and it is important to take this into consideration when designing
the Si5376 operating environment. Among other issues, high die temperatures can result in increased jitter and
decreased long term reliability. It is therefore recommended that one or more of the following occur:
1. Use a heat sink—A heat sink example is Aavid part number 375324B00035G.
2. Use a Vdd voltage of 1.8 V.
3. Limit the ambient temperature to significantly less that 85 °C.
4. Implement very good air flow.
5.3. SCL Leakage
2
When selecting pull up resistors for the two I C signals, note that there is an internal pull down resistor of 18 k
from the SCL pin to ground. This comment does not apply to the SDA pin.
5.4. RSTL_x Pins
It is recommended that the four RSTL_x pins (RSTL_A, RSTL_B, RSTL_C and RSTL_D) be logically connected
together such that all four DSPLLs are either in or out of reset mode. When a DSPLL is in reset mode, its VCO will
not be locked to any signal and may drift across its operating range. If a drifting VCO has a frequency similar to that
of an operating VCO, there could be some crosstalk between the two VCOs. To avoid this from occurring during
device initialization, DSPLLsim loads each DSPLL with default Free Run frequency plans with VCO values apart
from one another. If the four RSTL_x pins are directly connected to one another, the connections should not be
made directly underneath the BGA package. Instead, the connections should be made outside the package
footprint.
16
Rev. 1.0
Si5376
5.5. Reference Oscillator Selection
Care should be taken during the selection of the external oscillator that is connected to the OSC_P and OSC_N
pins. There is no jitter attenuation from the OSC reference inputs to the output; so, to achieve low output jitter, a
low-jitter reference OSC must be used. Also, the output drift during holdover will be the same as the drift of the
OSC reference. For example, a Stratum 3 application will require an OSC reference source that has Stratum 3
stability (though Stratum 3 accuracy is not required).
The OSC frequency can be any value from 109 to 125.5 MHz. See the RATE_REG (reg 2) description. Alternately,
for applications with less demanding jitter requirements, the OSC frequency can be in the range from 37 to
41 MHz. For applications that use Free Run mode, the freedom to use any OSC frequency within these bands can
be used to select an OSC frequency that has an integer relationship to the desired output frequency, which will
make it easier to find a high-performance frequency plan.
If Free Run is not being used, an OSC frequency that is not integer-related to the output frequency is preferred. A
recommended choice for an external oscillator is the Silicon Labs 530EB121M109DG, which is a 2.5 V, LVPECL
device with a temperature stability of 20 ppm. It was used to take the typical phase noise plot on page 14. For more
details and a more complete discussion of these topics, see the Si53xx Reference Manual.
5.6. Alarms
To assist in the programming of the IRQ_n pins, refer to the below diagram of the Si5376 alarm structure.
LOSx_INT
LOS1_INT
LOS2_INT
FOS1_INT
LOSX_FLG
LOSX_MSK
in
in
in
out
out
out
Sticky
Write 0
to clear
INT_POL
LOS1_FLG
LOS1_MSK
Sticky
Write 0
to clear
IRQ_PIN
LOS2_FLG
LOS2_MSK
Sticky
Write 0
to clear
E
IRQ_n
FOS1_FLG
FOS1_MSK
in
out
Sticky
Write 0
to clear
FOS2_INT
LOL_INT
FOS2_FLG
FOS2_MSK
in
out
Sticky
Write 0
to clear
LOL_FLG
LOL_MSK
in
out
Sticky
Write 0
to clear
Figure 5. Si5376 Alarm Structure
Rev. 1.0
17
Si5376
5.7. OSC_P and OSC_N Connection
Figures 6, 7, and 8 show examples of connecting various OSC reference sources to the OSC_P and OSC_N pins.
A crystal may not be used in place of an external oscillator.
Si5376
1.2 V
0.01 F
OSC-P
100
OSC-N
LVDS, LVPECL, CML, etc.
2.5 k
0.01 F
0.6 V
Figure 6. Differential OSC Reference Input Example for Si5376
Si5376
1.2 V
0.01 F
OSC-P
OSC-N
100
LVDS, LVPECL, CML, etc.
2.5 k
0.01 F
0.6 V
Figure 7. Single-Ended OSC Reference Input Example for Si5376
2.5 V
2.5 V
150
82
150
Si5376
OSC-P
1.2 V
10 nF
CMOS
XO
E5
E6
OSC-N
10 nF
0.6 V
Figure 8. Single-Ended, 2.5 V, CMOS XO Connection
18
Rev. 1.0
Si5376
6. Register Map
2
The Si5376 has four identical register maps for each DSPLL. Each DSPLL has a unique I C address enabling
2
independent control and device configuration. The I C address is 11010 [A1] [A0] for the entire device. Each
corresponding DSPLL [A1] [A0] address is fixed as below.
[A1] [A0]
DSPLLA:
DSPLLB:
DSPLLC:
DSPLLD:
0
0
1
1
0
1
0
1
Note: The Si5376 register map is similar, but not identical, to the Si5324 device.
All register bits that are not defined in this map should always be written with the specific reset values. Writing to
these bits with values other than the specified reset values may result in undefined device behavior. Registers not
listed, such as Register 64, should never be written to.
Table 8. Si5376 Registers
Reg.
D7
D6
D5
D4
D3
D2
D1
D0
0
FREE_RU
N
CKOUT_
ALWAYS_ON
BYPASS_REG
1
2
CK_PRIOR2[1:0]
CK_PRIOR1[1:0]
RATE_REG [3:0]
BWSEL_REG[3:0]
3
CKSEL_REG[1:0]
AUTOSEL_REG[1:0]
ICMOS[1:0]
DHOLD
SQ_ICAL
4
HIST_DEL[4:0]
5
6
SFOUT2_REG[2:0}
SFOUT1_REG[2:0]
FOSREFSEL[2:0]
7
8
HLOG_2[1:0]
HLOG_1[1:0]
HIST_AVG[4:0]
9
10
11
19
20
21
DSBL2_ REG DSBL1_ REG
PD_CK2
LOCKT[2:0]
LOL_PIN
PD_CK1
FOS_EN
Write 0
FOS_THR[1:0]
VALTIME[1:0]
Write 0
Write 0
IRQ_PIN
Write 0
CK1_ACTV_PI
N
CKSEL_PIN
22
CK_ACTV_
POL
LOL_POL
INT_POL
23
24
25
31
32
LOS2_MSK
FOS2_MSK
LOS1_MSK
FOS1_MSK
LOSX_MSK
LOL_MSK
N1_HS[2:0]
NC1_LS[19:16]
NC1_LS[15:8]
Rev. 1.0
19
Si5376
Table 8. Si5376 Registers (Continued)
Reg.
D7
D6
D5
D4
D3
D2
D1
D0
33
34
35
36
40
41
42
43
44
45
46
47
48
55
128
NC1_LS[7:0]
NC2_LS[19:16]
NC2_LS[15:8]
NC2_LS[7:0]
N2_HS[2:0]
N2_LS[19:16]
N2_LS[15:8]
N2_LS[7:0]
N31[18:16]
N31[15:8]
N31[7:0]
N32[18:16]
N32[15:8]
N32[7:0]
CLKIN2RATE[2:0]
CLKIN1RATE[2:0]
CK2_ACTV_RE CK1_ACTV_R
G
EG
129
130
LOS2_INT
FOS2_INT
LOS1_INT
FOS1_INT
LOSX_INT
LOL_INT
DIGHOLD
VALID
131
132
134
135
136
137
138
139
LOS2_FLG
FOS1_FLG
LOS1_FLG
LOL_FLG
LOSX_FLG
FOS2_FLG
PARTNUM_RO[11:4]
PARTNUM_RO[3:0]
ICAL
REVID_RO[3:0]
RST_REG
FASTLOCK
LOS2_EN [1:1] LOS1_EN [1:1]
FOS2_EN FOS1_EN
LOS2_EN[0: LOS1_EN[0:
0] 0]
142
143
INDEPENDENTSKEW1[7:0]
INDEPENDENTSKEW2[7:0]
20
Rev. 1.0
Si5376
7. Register Descriptions
Register 0.
Bit
D7
D6
FREE_RUN CKOUT_ALWAYS_ON
R/W R/W
D5
D4
D3
D2
D1
D0
Name
Type
BYPASS_REG
R/W
R
R
R
R
R
Reset value = 0001 0100
Bit
7
Name
Function
Reserved
FREE_RUN
Reserved.
Free Run.
6
Internal to the device, route XA/XB to CKIN2. This allows the DSPLL to lock to
its XA-XB reference to support free-running clock generation.
0: Disable
1: Enable
5
CKOUT_ALWAYS_ON CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if
SQ_ICAL is on and ICAL is not complete or successful. See Table 9 on
page 55.
0: Squelch output until device is calibrated (ICAL).
1: Provide an output.
Notes:
1. The frequency may be significantly off until the device is calibrated.
2. Must be set to 1 to control output to output skew.
4:2
1
Reserved
Reserved.
BYPASS_REG
Bypass Register.
This bit enables or disables PLL bypass mode. Use only when the device is in
digital hold or before the first ICAL. Bypass mode does not support CMOS
clock outputs.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypass-
ing PLL.
0
Reserved
Reserved.
Rev. 1.0
21
Si5376
Register 1.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CK_PRIOR2 [1:0]
R/W
CK_PRIOR1 [1:0]
R/W
Type
R
Reset value = 1110 0100
Bit
7:4
3:2
Name
Function
Reserved
CK_PRIOR2 [1:0] 2nd Priority Input Clock.
Selects which of the input clocks will be 2nd priority in the autoselection state
machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: Reserved
11: Reserved
1:0
CK_PRIOR1 [1:0] 1st Priority Input Clock.
Selects which of the input clocks will be 1st priority in the autoselection state
machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: Reserved
11: Reserved
22
Rev. 1.0
Si5376
Register 2.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
BWSEL_REG [3:0]
R/W
RATE_REG[3:0]
R/W
Reset value = 0100 0010
Bit
Name
BWSEL_REG [3:0] BWSEL_REG.
Function
7:4
Selects nominal f3dB bandwidth for PLL. See Si53xDSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to
take effect.
3:0
RATE_REG [3:0] RATE Setting for Oscillator.
An external oscillator or other clock source must be used. It is not possible to
use just a crystal.
Setting
0101
0110
Minimum
37
109
Recommended Maximum
Units
MHz
MHz
40
41
121.109
125.5
Others: Reserved
Rev. 1.0
23
Si5376
Register 3.
Bit
D7
D6
CKSEL_REG[1:0]
R/W
D5
DHOLD
R/W
D4
SQ_ICAL
R/W
D3
D2
D1
D0
Name
Type
R
R
R
R
Reset value = 0000 0101
Bit
7:6 CKSEL_REG [1:0] CKSEL_REG.
If the device is operating in register-based manual clock selection mode
Name
Function
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input
clock will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the
CS_CA input pin continues to control clock selection and CKSEL_REG is of no con-
sequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: Reserved
11: Reserved
5
DHOLD
DHOLD.
Forces the device into digital hold. This bit overrides all other manual and automatic
clock selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of the
input clocks.
4
SQ_ICAL
Reserved
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (dis-
abled) during an internal calibration. See Table 9 on page 55.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0
24
Rev. 1.0
Si5376
Register 4.
Bit
D7
D6
D5
D4
D3
D2
HIST_DEL [4:0]
R/W
D1
D0
Name
Type
AUTOSEL_REG [1:0]
R/W
R
Reset value = 0001 0010
Bit
Name
AUTOSEL_REG [1:0] AUTOSEL_REG [1:0].
Selects input clock selection control method.
Function
7:6
00: Manual (either register or pin controlled, see CKSEL_PIN)
01: Automatic non-revertive
10: Automatic revertive
11: Reserved
5
Reserved
4:0
HIST_DEL [4:0]
HIST_DEL [4:0].
Selects amount of delay to be used in generating the history information used
for Digital Hold.
Register 5.
Bit
D7
ICMOS [1:0]
R/W
D6
D5
D4
D3
D2
D1
D0
Name
Type
R
R
R
R
R
R
Reset value = 1110 1101
Bit
Name
Function
7:6
ICMOS [1:0] ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buffer drive
strength. The first number below refers to 2.5 V operation; the second to 1.8 V operation.
These values assume CKOUT+ is tied to CKOUT-.
00: 5 mA/1.75 mA
01: 10 mA/3.5 mA
10: 15 mA/5.5 mA
11: 20 mA/7.5 mA
5:0
Reserved
Rev. 1.0
25
Si5376
Register 6.
Bit
D7
D6
D5
D4
SFOUT2_REG [2:0]
R/W
D3
D2
D1
SFOUT1_REG [2:0]
R/W
D0
Name
Type
R
R
Reset value = 0010 1101
Bit
7:6
5:3
Name
Function
Reserved
SFOUT2_
REG [2:0]
SFOUT2_REG [2:0].
Controls output signal format and disable for CKOUT2 output buffer.
000: Reserved
001: Disable CKOUT2
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL (not available when V = 1.8 V)
DD
110: CML
111: LVDS
2:0
SFOUT1_
REG [2:0]
SFOUT1_REG [2:0].
Controls output signal format and disable for CKOUT1 output buffer.
000: Reserved
001: Disable CKOUT1
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL (not available when V = 1.8 V)
DD
110: CML
111: LVDS
26
Rev. 1.0
Si5376
Register 7.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
FOSREFSEL [2:0]
R/W
R
R
R
R
R
Reset value = 0010 1010
Bit
7:3
2:0
Name
Function
Reserved
FOSREFSEL FOSREFSEL [2:0].
[2:0]
Selects which input clock is used as the reference frequency for Frequency offset (FOS)
monitoring.
000: OSC (External reference)
001: CKIN1
010: CKIN2
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Rev. 1.0
27
Si5376
Register 8.
Bit
D7
HLOG_2[1:0]
R/W
D6
D5
HLOG_1[1:0]
R/W
D4
D3
D2
D1
D0
Name
Type
R
R
R
R
Reset value = 0000 0000
Bit
Name
Function
7:6
HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0.
Entrance and exit from this state will occur without glitches or runt pulses.
10:Holds CKOUT2 output at static logic 1.
Entrance and exit from this state will occur without glitches or runt pulses.
11: Reserved
5:4
3:0
HLOG_1 [1:0] HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0.
Entrance and exit from this state will occur without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1.
Entrance and exit from this state will occur without glitches or runt pulses.
11: Reserved
Reserved
Register 9.
Bit
D7
D6
D5
HIST_AVG [4:0]
R/W
D4
D3
D2
D1
D0
Name
Type
R
R
R
Reset value = 1100 0000
Bit
Name
HIST_AVG [4:0] HIST_AVG [4:0].
Function
7:3
Selects amount of averaging time to be used in generating frequency history informa-
tion for Digital Hold.
2:0
Reserved
28
Rev. 1.0
Si5376
Register 10.
Bit
D7
D6
D5
D4
D3
DSBL2_REG DSBL1_REG
R/W R/W
D2
D1
D0
Name
Type
R
R
R
R
R
R
Reset value = 0000 0000
Bit
7:4
3
Name
Function
Reserved
DSBL2_REG DSBL2_REG.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
2
DSBL1_REG DSBL1_REG.
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
1:0
Reserved
Register 11.
Bit
D7
D6
D5
D4
D3
D2
D1
PD_CK2
R/W
D0
PD_CK1
R/W
Name
Type
R
R
R
R
R
R
Reset value = 0100 0000
Bit
7:2
1
Name
Function
Reserved
PD_CK2
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
0
PD_CK1
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
Rev. 1.0
29
Si5376
Register 19.
Bit
D7
D6
D5
D4
VALTIME [1:0]
R/W
D3
D2
D1
LOCKT [2:0]
R/W
D0
Name FOS_EN
FOS_THR [1:0]
R/W
Type
R/W
Reset value = 0010 1100
Bit
Name
Function
7:5
FOS_EN
FOS_EN.
Frequency Offset Enable globally disables FOS. See the individual FOS enables
(FOSX_EN, register 139).
0: FOS disable
1: FOS enabled by FOSx_EN
6:5 FOS_THR [1:0] FOS_THR [1:0].
Frequency Offset at which FOS is declared:
00: ± 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK.
01: ± 48 to 49 ppm SONET Minimum Clock (SMC) with SMC used for REFCLK.
10: ± 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
4:3
2:0
VALTIME [1:0] VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 seconds
LOCKT [2:0] LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-
gered by phase slip in DSPLL. To minimize lock time during an ICAL, a LOCKT value of
001 is recommended. Refer to the Family Reference Manual for more details.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: 0.833 ms
30
Rev. 1.0
Si5376
Register 20.
Bit
D7
D6
D5
D4
D3
Write 0
W
D2
Write 0
W
D1
LOL_PIN
R/W
D0
IRQ_PIN
R/W
Name
Type
R
R
R
R
Reset value = 0011 1110
Bit
7:4
3:2
1
Name
Reserved
Write 0
Function
Write to zero.
LOL_PIN.
LOL_PIN
The LOL_INT status bit can be reflected on the LOL output pin.
0: LOL output pin tristated
1: LOL_INT status reflected to output pin
0
IRQ_PIN
IRQ_PIN.
Reflects interrupt status on the IRQ output pin.
0: Output is disabled.
1: Output is enabled.
Rev. 1.0
31
Si5376
Register 21.
Bit
D7
D6
Write 0
W
D5
D4
D3
D2
D1
CK1_ACTV_PIN CKSEL_ PIN
R/W R/W
D0
Name
Type
Write 0
W
R
R
R
R
Reset value = 1111 1111
Bit
7:6
5:2
1
Name
Write 0
Function
Write zero.
Reserved
CK1_ACTV_PIN CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin
controlled clock selection is being used.
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
0
CKSEL_PIN
CKSEL_PIN.
If manual clock selection is used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.
32
Rev. 1.0
Si5376
Register 22.
Bit
D7
D6
D5
D4
D3
CK_ACTV_POL
R/W
D2
D1
LOL_POL
R/W
D0
INT_POL
R/W
Name
Type
R
R
R
R
R
Reset value = 1101 1111
Bit
7:4
3
Name
Function
Reserved
CK_ACTV_ POL CK_ACTV_POL.
Sets the active polarity for the CS_CA signals when reflected on an output pin.
0: Active low
1: Active high
2
1
Reserved
LOL_POL
LOL_POL.
Sets the active polarity for the LOL status when reflected on an output pin.
0: Active low
1: Active high
0
INT_POL
INT_POL.
Sets the active polarity for the interrupt status when reflected on the INT_C1B out-
put pin.
0: Active low
1: Active high
Rev. 1.0
33
Si5376
Register 23.
Bit
D7
D6
D5
D4
D3
D2
LOS2_ MSK
R/W
D1
LOS1_ MSK
R/W
D0
LOSX_ MSK
R/W
Name
Type
R
R
R
R
R
Reset value = 0001 1111
Bit
7:3
2
Name
Function
Reserved
LOS2_MSK
LOS2_MSK.
Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS2_FLG register.
0: LOS2 alarm triggers active interrupt on IRQ output (if IRQ=1).
1: LOS2_FLG ignored in generating interrupt output.
1
0
LOS1_MSK
LOSX_MSK
LOS1_MSK.
Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS1_FLG register.
0: LOS1 alarm triggers active interrupt on IRQ output (if IRQ=1).
1: LOS1_FLG ignored in generating interrupt output.
LOSX_MSK.
Determines if a LOS on OSC (LOSX_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOSX_FLG register.
0: LOSX alarm triggers active interrupt on IRQ output (if IRQ=1).
1: LOSX_FLG ignored in generating interrupt output.
34
Rev. 1.0
Si5376
Register 24.
Bit
D7
D6
D5
D4
D3
D2
FOS2_MSK
R/W
D1
FOS1_MSK
R/W
D0
LOL_MSK
R/W
Name
Type
R
R
R
R
R
Reset value = 0011 1111
Bit
7:3
2
Name
Function
Reserved
FOS2_MSK FOS2_MSK.
Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS2_FLG register.
0: FOS2 alarm triggers active interrupt on IRQ output (if IRQ_PIN=1).
1: FOS2_FLG ignored in generating interrupt output.
1
0
FOS1_MSK FOS1_MSK.
Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS1_FLG register.
0: FOS1 alarm triggers active interrupt on IRQ output (if IRQ_PIN=1).
1: FOS1_FLG ignored in generating interrupt output.
LOL_MSK
LOL_MSK.
Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-
ter do not change the value held in the LOL_FLG register.
0: LOL alarm triggers active interrupt on IRQ output (if IRQ_PIN=1).
1: LOL_FLG ignored in generating interrupt output.
Rev. 1.0
35
Si5376
Register 25.
Bit
D7
D6
N1_HS [2:0]
R/W
D5
D4
D3
D2
D1
D0
Name
Type
R
R
R
R
R
Reset value = 0010 0000
Bit
Name
Function
7:5
N1_HS [2:0] N1_HS [2:0].
Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider.
000: N1 = 4
001: N1 = 5
010: N1 = 6
011: N1 = 7
100: N1 = 8
101: N1 = 9
110: N1 = 10
111: N1 = 11
4:0
Reserved
Register 31.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC1_LS [19:16]
R/W
R
R
R
R
Reset value = 0000 0000
Bit
7:4
3:0
Name
Function
Reserved
NC1_LS
[19:16]
NC1_LS [19:16].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111=2
20
Valid divider values=[1, 2, 4, 6, ..., 2 ]
36
Rev. 1.0
Si5376
Register 32.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC1_LS [15:8]
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0
NC1_LS
[15:8]
NC1_LS [15:8].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111=2
20
Valid divider values=[1, 2, 4, 6, ..., 2 ]
Register 33.
Bit
D7
D6
D5
D4
NC1_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0011 0001
Bit
Name
Function
7:0
NC1_LS
[19:0]
NC1_LS [7:0].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111=2
20
Valid divider values=[1, 2, 4, 6, ..., 2 ]
Rev. 1.0
37
Si5376
Register 34.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC2_LS [19:16]
R/W
R
R
R
R
Reset value = 0000 0000
Bit
7:4
3:0
Name
Function
Reserved
NC2_LS
[19:16]
NC2_LS [19:16].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000=1
00000000000000000001=2
00000000000000000011=4
00000000000000000101=6
...
20
11111111111111111111=2
20
Valid divider values=[1, 2, 4, 6, ..., 2 ]
Register 35.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC2_LS [15:8]
R/W
Reset value = 0000 0000
Bit
Name
NC2_LS [15:8] NC2_LS [15:8].
Function
7:0
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111=2
20
Valid divider values=[1, 2, 4, 6, ..., 2 ]
38
Rev. 1.0
Si5376
Register 36.
Bit
D7
D6
D5
D4
NC2_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0011 0001
Bit
Name
NC2_LS [7:0] NC2_LS [7:0].
Function
7:0
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [1, 2, 4, 6, ..., 2 ]
Rev. 1.0
39
Si5376
Register 40.
Bit
D7
D6
N2_HS [2:0]
R/W
D5
D4
D3
D2
N2_LS [19:16]
R/W
D1
D0
Name
Type
R
Reset value = 1100 0000
Bit
Name
Function
7:5
N2_HS [2:0]
N2_HS [2:0].
Sets value for N2 high speed divider which drives N2LS low-speed divider.
000: 4
001: 5
010: 6
011: 7
100: 8
101: 9
110: 10
111: 11
4
Reserved
3:0
N2_LS [19:16] N2_LS [19:16].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [2, 4, 6, ..., 2 ]
40
Rev. 1.0
Si5376
Register 41.
Bit
D7
D6
D5
D4
N2_LS [15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0000 0000
Bit
Name
N2_LS [15:8] N2_LS [15:8].
Function
7:0
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [2, 4, 6, ..., 2 ]
Register 42.
Bit
D7
D6
D5
D4
N2_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 1111 1001
Bit
Name
N2_LS [7:0] N2_LS [7:0].
Function
7:0
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [2, 4, 6, ..., 2 ]
Rev. 1.0
41
Si5376
Register 43.
Bit
D7
D6
D5
D4
D3
D2
D1
N31 [18:16]
R/W
D0
Name
Type
R
R
R
R
R
Reset value = 0000 0000
Bit
7:3
2:0
Name
Function
Reserved
N31 [18:16] N31 [18:16].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values = [1, 2, 3, ..., 2 ]
Register 44.
Bit
D7
D6
D5
D4
N31_[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0000 0000
Bit
Name
N31_[15:8] N31_[15:8].
Function
7:0
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values = [1, 2, 3, ..., 2 ]
42
Rev. 1.0
Si5376
Register 45.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N31_[7:0]
R/W
Reset value = 0000 1001
Bit
Name
Function
7:0
N31_[7:0
N31_[7:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values = [1, 2, 3, ..., 2 ]
Register 46.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N32_[18:16]
R/W
R
R
R
R
R
Reset value = 0000 0000
Bit
7:3
2:0
Name
Function
Reserved
N32_[18:16] N32_[18:16].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values = [1, 2, 3, ..., 2 ]
Rev. 1.0
43
Si5376
Register 47.
Bit
D7
D6
D5
D4
N32_[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0000 0000
Bit
Name
N32_[15:8] N32_[15:8].
Function
7:0
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values = [1, 2, 3, ..., 2 ]
Register 48.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N32_[7:0]
R/W
Reset value = 0000 1001
Bit
Name
Function
7:0
N32_[7:0]
N32_[7:0].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values = [1, 2, 3, ..., 2 ]
44
Rev. 1.0
Si5376
Register 55.
Bit
D7
D6
D5
D4
CLKIN2RATE[2:0]
R/W
D3
D2
D1
D0
Name
Type
CLKIN1RATE[2:0]
R/W
R
R
Reset value = 0000 0000
Bit
7:6
5:3
Name
Function
Reserved
CLKIN2RATE[2:0] CLKIN2RATE_[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
2:0
CLKIN1RATE [2:0] CLKIN1RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
Rev. 1.0
45
Si5376
Register 128.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CK2_ACTV_REG CK1_ACTV_REG
R
R
R
R
R
R
R
R
Reset value = 0010 0000
Bit
7:2
1
Name
Function
Reserved
CK2_ACTV_REG CK2_ACTV_REG.
Indicates if CKIN2 is currently the active clock for the DSPLL input.
0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
1: CKIN2 is the active input clock.
0
CK1_ACTV_REG CK1_ACTV_REG.
Indicates if CKIN1 is currently the active clock for the DSPLL input.
0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.
1: CKIN1 is the active input clock.
Register 129.
Bit
D7
D6
D5
D4
D3
D2
LOS2_INT
R
D1
LOS1_INT
R
D0
LOSX_INT
R
Name
Type
R
R
R
R
R
Reset value = 0000 0110
Bit
7:3
2
Name
Function
Reserved
LOS2_INT LOS2_INT.
Indicates the LOS status on CKIN2.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN2 input.
1
0
LOS1_INT LOS1_INT.
Indicates the LOS status on CKIN1.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN1 input.
LOSX_INT LOSX_INT.
Indicates the LOS status of the external reference on the OSC pins.
0: Normal operation.
1: Internal loss-of-signal alarm on OSC reference clock input.
46
Rev. 1.0
Si5376
Register 130.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
DIGHOLDVALID
R
FOS2_INT FOS1_INT LOL_INT
R
R
R
R
R
R
R
Reset value = 0000 0001
Bit
7
Name
Function
Reserved
6
DIGHOLDVALID Digital Hold Valid.
Indicates if the digital hold circuit has enough samples of a valid clock to meet dig-
ital hold specifications.
0: Indicates digital hold history registers have not been filled. The digital hold out-
put frequency may not meet specifications.
1: Indicates digital hold history registers have been filled. The digital hold output
frequency is valid.
5:3
2
Reserved
FOS2_INT
CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
1
0
FOS1_INT
LOL_INT
CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
PLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.
Rev. 1.0
47
Si5376
Register 131.
Bit
D7
D6
D5
D4
D3
D2
LOS2_FLG LOS1_FLG LOSX_FLG
R/W R/W R/W
D1
D0
Name
Type
R
R
R
R
R
Reset value = 0001 1111
Bit
7:3
2
Name
Function
Reserved
LOS2_FLG CKIN2 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (IRQ_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to
this bit.
1
0
LOS1_FLG CKIN1 Loss-of-Signal Flag.
0: Normal operation
1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (IRQ_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to
this bit.
LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag.
0: Normal operation
1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is
enabled (IRQ_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to
this bit.
48
Rev. 1.0
Si5376
Register 132.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
FOS2_FLG FOS1_FLG LOL_FLG
R
R
R
R
R/W
R/W
R/W
R
Reset value = 0000 0010
Bit
7:4
3
Name
Function
Reserved
FOS2_FLG CLKIN_2 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (IRQ_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to
this bit.
2
1
0
FOS1_FLG CLKIN_1 Frequency Offset Flag.
0: Normal operation
1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (IRQ_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to
this bit.
LOL_FLG
Reserved
PLL Loss of Lock Flag.
0: PLL locked
1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is
enabled (IRQ_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to
this bit.
Rev. 1.0
49
Si5376
Register 134.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
PARTNUM_RO [11:4]
R
Type
Reset value = 0000 0001
Bit
Name
Function
7:0
PARTNUM_RO [11:0] Device ID (1 of 2).
0000 0100 1100: Si5376
Others: Reserved
Register 135.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
PARTNUM_RO [3:0]
R
REVID_RO [3:0]
R
Type
Reset value = 1010 0010
Bit
Name
Function
7:4
PARTNUM_RO [11:0] Device ID (2 of 2).
0000 0100 1010: Si5376
Others: Reserved
3:0
REVID_RO [3:0]
Indicates Device Revision Level.
0010: Revision C
Others: Reserved.
50
Rev. 1.0
Si5376
Register 136.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name RST_REG
ICAL
R/W
Type
R/W
R
R
R
R
R
R
Reset value = 0000 0000
Bit
Name
Function
7
RST_REG
Internal Reset (Same as Pin Reset).
Note: The I2C port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset all internal logic. Outputs disabled or tristated during reset.
6
ICAL
Start Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence.
ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibra-
tion is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm)
must be present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take
effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-cali-
bration, LOL will go low.
5:0
Reserved
Register 137.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
FASTLOCK
R/W
Name
Type
R
R
R
R
R
R
R
Reset value = 0000 0000
Bit
7:1
0
Name
Function
Reserved
FASTLOCK
Do not modify.
This bit must be set to 1 to enable FASTLOCK.
This improves initial lock time by dynamically changing the loop bandwidth during
PLL lock acquisition.
Rev. 1.0
51
Si5376
Register 138.
Bit
D7
D6
D5
D4
D3
D2
D1
LOS2_EN [1:1]
R/W
D0
LOS1_EN [1:1]
R/W
Name
Type
R
R
R
R
R
R
Reset value = 0000 1111
Bit
7:2
1
Name
Function
Reserved
LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual
for details.
0
LOS1_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual
for details.
52
Rev. 1.0
Si5376
Register 139.
Bit
D7
D6
D5
LOS2_EN [0:0] LOS1_EN [0:0]
R/W R/W
D4
D3
D2
D1
D0
Name
Type
FOS2_EN FOS1_EN
R/W R/W
R
R
R
R
Reset value = 1111 1111
Bit
7:6
5
Name
Function
Reserved
LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details.
4
LOS_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details.
3:2
1
Reserved
FOS2_EN
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
0
FOS1_EN
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
Rev. 1.0
53
Si5376
Register 142.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
INDEPENDENTSKEW1 [7:0]
R/W
Type
Reset value = 0000 0000
Bit
Name
INDEPENDENTSKEW1 [7:0] INDEPENDENTSKEW1.
Function
7:0
Eight-bit field that represents a 2s complement of the phase offset in
terms of clocks from the high speed output divider. Default = 0.
Register 143.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
INDEPENDENTSKEW2 [7:0]
R/W
Type
Reset value = 0000 0000
Bit
Name
INDEPENDENTSKEW2 [7:0] INDEPENDENTSKEW2.
Function
7:0
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider. Default = 0.
54
Rev. 1.0
Si5376
7.1. ICAL
The device registers must be configured for the device operation. After device configuration, a calibration
procedure must be performed once a stable clock is applied to the selected CKINn input. The calibration process is
triggered by writing a “1” to bit D6 in register 136. See the Family Reference Manual for details. In addition, after a
successful calibration operation, changing any of the registers indicated in Table 9 requires that a calibration be
performed again by the same procedure (writing a “1” to bit D6 in register 136).
Table 9. ICAL-Sensitive Registers
Address
0
Register
BYPASS_REG
CKOUT_ALWAYS_ON
CK_PRIOR1
CK_PRIOR2
BSWEL_REG
RATE_REG
HIST_DEL
ICMOS
0
1
1
2
2
4
5
7
FOSREFSEL
HIST_AVG
DSBL1_REG
DSBL2_REG
PD_CK1
9
10
10
11
11
19
19
19
19
25
31
34
40
40
43
46
55
55
PD_CK2
FOS_EN
FOS_THR
LOCKT
VALTIME
N1_HS
NC1_LS
NC2_LS
N2_HS
N2_LS
N31
N32
CLKIN1RATE
CLKIN2RATE
Rev. 1.0
55
Si5376
8. Pin Descriptions: Si5376
9
8
7
6
5
4
3
2
1
CKOUT1P_B
GND
VDD_B
CS_CA_B
CKOUT2P_A CKOUT2N_A
GND
CKOUT1N_A
A
B
C
D
E
F
CKOUT1N_B
GND
GND
CKIN1P_B
CKIN2P_B
CKIN1N_B
CKIN2N_B
VDD_A
LOL_B
IRQ_A
GND
GND
CKOUT1P_A
VDD_A
GND
VDD_A
CKIN2P_A
CKIN1P_A
CKOUT2N_B
CKOUT2P_B
CS_CA_C
IRQ_B
LOL_C
VDD_B
VDD_C
RSTL_B
OSC_N
RSTL_C
VDD_B
OSC_P
VDD_C
RSTL_A
GND
CKIN2N_A
VDD_D
CKIN1N_A
LOL_A
CS_CA_A
CKOUT2P_D
CKOUT2N_D
CKIN1N_C
CKIN2N_C
RSTL_D
VDD_D
IRQ_D
G
VDD_C
GND
CKIN1P_C
GND
CKIN2P_C
GND
SDA
SCL
CKIN2N_D
CKIN1N_D
CS_CA_D
CKIN2P_D
CKIN1P_D
VDD_D
GND
GND
GND
GND
CKOUT1N_D
CKOUT1P_D
IRQ_C
LOL_D
H
J
CKOUT1P_C CKOUT1N_C
GND
CKOUT2N_C CKOUT2P_C
Bottom View
Figure 9. Si5376 Pin Configuration (Bottom View)
56
Rev. 1.0
Si5376
Table 10. Si5376 Pin Descriptions
Pin #
Pin Name
I/O
Signal
Level
Description
D4
D6
F6
F4
RSTL_A
RSTL_B
RSTL_C
RSTL_D
I
LVCMOS
External Reset.
Active low input that performs external hardware reset of all four
DSPLLs. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are tri-stated
during reset. The part must be programmed after a reset or
power-on to get a clock output. This pin has a weak pull-up.
B4
D8
H6
F2
IRQ_A
IRQ_B
IRQ_C
IRQ_D
O
LVCMOS
DSPLLq Interrupt Indicator.
This pin functions as a device interrupt output. The interrupt out-
put, IRQ_PINn must be set to 1. The pin functions as a maskable
interrupt output with active polarity controlled by the IRQ_POLn
register bit.
0 = CKINn present
1 = LOS (FOS) on CKINn
The active polarity is controlled by CK_BAD_POL. If no function
is selected, the pin tri-states.
C1, C4, B5
A7, D5, D7
E7, F5, G9
E3, F3, J3
VDD_A
VDD_B
VDD_C
VDD_D
V
Supply
Analog
Supply.
DD
The device operates from a 1.8 or 2.5 V supply. A 0.1 µF bypass
capacitive is required for every VDD_9 pin. Bypass capacitors
should be associated with the following VDD_q pins:
0.1 µF per VDD pin.
Four 1.0 µF should also be placed as close to each VDD domain
as is practical. See recommended layout.
E5
E6
OSC_P
OSC_N
I
External OSC.
An external low jitter reference clock should be connected to
these pins. See the any-frequency precision clocks family refer-
ence manual for oscillator selection details.
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5376 Register Map.
Rev. 1.0
57
Si5376
Table 10. Si5376 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal
Level
Description
B2
A3
B3
E4
C8
A8
B8
C9
H7
J7
H8
H9
G1
H2
J2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Supply
Ground for each DSPLLq.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. See
recommended layout.
G2
C2
D2
C3
D3
CKIN1P_A
CKIN1N_A
CKIN2P_A
CKIN2N_A
I
Multi
Clock Inputs for DSPLLq.
Differential input clocks. This input can also be driven with a sin-
gle-ended signal.
B7
B6
C7
C6
CKIN1P_B
CKIN1N_B
CKIN2P_B
CKIN2N_B
G8
F8
G7
F7
CKIN1P_C
CKIN1N_C
CKIN2P_C
CKIN2N_C
H3
H4
G3
G4
CKIN1P_D
CKIN1N_D
CKIN2P_D
CKIN2N_D
E2
C5
E8
H5
LOL_A
LOL_B
LOL_C
LOL_D
O
LVCMOS
DSPLLq Loss of Lock Indicator.
These pins function as the active high PLL loss of lock indicator if
the LOL_PIN register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PINn = 0, this pin will tri-state. Active polarity is controlled
by the LOL_POLn bit. The PLL lock status will always be
reflected in the LOL_INTn read only register bit.
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5376 Register Map.
58
Rev. 1.0
Si5376
Table 10. Si5376 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal
Level
Description
D1
A6
F9
J4
CS_CA_A
CS_CA_B
CS_CA_C
CS_CA_D
I/O
LVCMOS DSPLLq Input Clock Select/Active Clock Indicator.
Input: In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this
function and this input tristates. If configured for input, must be
tied high or low.
Output: In automatic clock selection mode, this pin indicates
which of the two input clocks is currently the active clock. If
alarms exist on both clocks, CK_ACTV will indicate the last active
clock that was used before entering the digital hold state. The
CK_ACTV_PIN register bit must be set to 1 to reflect the active
clock status to the CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status
will always be reflected in the CK_ACTV_REG read only register
bit.
2
G5
G6
SCL
SDA
I
LVCMOS
LVCMOS
I C Serial Clock.
This pin functions as the serial clock input.
This pin has a weak pull-down.
2
I/O
I C Serial Data.
2
I C pin functions as the bi-directional serial data port.
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5376 Register Map.
Rev. 1.0
59
Si5376
Table 10. Si5376 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal
Level
Description
B1
A2
A5
A4
CKOUT1P_A
CKOUT1N_A
CKOUT2P_A
CKOUT2N_A
O
Multi
Output Clock for DSPLLq.
Differential output clocks. Output signal format is selected by
SFOUT_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both out-
put pins drive in phase single-ended clock outputs at the same
frequency.
A9
B9
E9
D9
CKOUT1P_B
CKOUT1N_B
CKOUT2P_B
CKOUT2N_B
J9
CKOUT1P_C
J8
J5
J6
CKOUT1N_C
CKOUT2P_C
CKOUT2N_C
J1
H1
E1
F1
CKOUT1P_D
CKOUT1N_D
CKOUT2P_D
CKOUT2N_D
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5376 Register Map.
60
Rev. 1.0
Si5376
9. Ordering Guide
Ordering Part
Number
Input/Output
PLL
Package
RoHS6
Temperature
Range
Clocks
Bandwidth
Range
Pb-Free
Si5376B-A-GL
Si5376B-A-BL
Si5376-EVB
8/8
60 Hz to 8.4 kHz
10x10 mm
80-PBGA
Yes
No
–40 to 85 °C
–40 to 85 °C
8/8
60 Hz to 8.4 kHz
10x10 mm
80-PBGA
Evaluation Board
Rev. 1.0
61
Si5376
10. Package Outline
Figure 10 illustrates the package details for the Si5376. Table 11 lists the values for the dimensions shown in the
illustration. Visit www.silabs.com/support/quality/pages/RoHSInformation.aspx for more environmental information
about the package.
Figure 10. 80-Pin Plastic Ball Grid Array (PBGA)
Table 11. Package Dimensions
Symbol
Min
Nom
Max
Min
Nom
Max
A
1.22
1.39
1.56
E1
e
8.00 BSC
A1
A2
0.40
0.32
0.46
0.50
0.50
0.36
0.60
0.40
0.60
0.70
1.00 BSC
0.10
aaa
bbb
ccc
ddd
eee
A3
0.53
0.10
b
0.60
0.12
D
10.00 BSC
10.00 BSC
8.00 BSC
0.15
E
0.08
D1
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-192.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
62
Rev. 1.0
Si5376
11. Recommended PCB Layout
Figure 11. PBGA Card Layout
Table 12. Layout Dimensions
Symbol
X
MIN
NOM
0.45
8.00
8.00
1.00
1.00
MAX
0.40
0.50
C1
C2
E1
E2
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.0
63
Si5376
12. Top Markings
12.1. Si5376 Top Marking (PBGA, Lead-Free)
12.2. Top Marking Explanation (PBGA, Lead-Free)
Mark Method:
Logo Size:
Laser
6.1 x 2.2 mm
Center-Justified
Font Size:
0.80 mm
Right-Justified
Line 1 Marking:
Line 2 Marking:
Device Part Number
Si5376B-A-GL, Pb-free
YY = Year
WW = Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the mold date.
TTTTTT = Mfg Code
Pin 1 Identifier
Manufacturing Code from the
Assembly Purchase Order form.
Line 3 Marking:
Circle = 0.75 mm Diameter
Lower-Left Justified
“e1” Lead-Free Finish Symbol
(Pb-Free BGA Balls)
Circle = 1.4 mm Diameter
Center-Justified
Country of Origin
TW
64
Rev. 1.0
Si5376
12.3. Si5376 Top Marking (PBGA, Lead-Finish)
12.4. Top Marking Explanation (PBGA, Lead-Finish)
Mark Method:
Logo Size:
Laser
6.1 x 2.2 mm
Center-Justified
Font Size:
0.80 mm
Right-Justified
Line 1 Marking:
Line 2 Marking:
Device Part Number
Si5376B-A-BL, Pb finish
YY = Year
WW = Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the mold date.
TTTTTT = Mfg Code
Pin 1 Identifier
Manufacturing Code from the
Assembly Purchase Order form.
Line 3 Marking:
Circle = 0.75 mm Diameter
Lower-Left Justified
“e0” Lead Finish Symbol
(SnPb BGA Balls)
Circle = 1.4 mm Diameter
Center-Justified
Country of Origin
TW
Rev. 1.0
65
Si5376
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
66
Rev. 1.0
相关型号：
©2020 ICPDF网 联系我们和版权申明