SM4040DSK [SINOPWER]
Dual N-Channel Enhancement Mode MOSFET;
| 型号： | SM4040DSK |
| 厂家： | 
Sinopower Semiconductor Inc |
| 描述： | Dual N-Channel Enhancement Mode MOSFET |
| 文件： | 总10页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM4040DSK
®
Dual N-Channel Enhancement Mode MOSFET
Features
Pin Description
D1
D1
D2
•
40V/7A,
RDS(ON) = 22mΩ (max.) @ VGS = 10V
D2
RDS(ON) = 27mΩ (max.) @ VGS = 4.5V
100% UIS + Rg Tested
S1
G1
S2
G2
•
•
•
Reliable and Rugged
Lead Free andGreenDevicesAvailable
(RoHS Compliant)
Top View of SOP-8
(6) (5)
D2 D2
(8) (7)
D1 D1
Applications
•
•
•
•
Power Management in Note book.
Battery Powered System.
DC/DC Converter.
(2)
G1
(4)
G2
Load Switch.
S1
(1)
S2
(3)
N-ChannelMOSFET
Ordering and Marking Information
Package Code
SM4040DS
K : SOP-8
Operating Junction Temperature Range
Assembly Material
Handling Code
C : -55 to 150 oC
Handling Code
Temperature Range
TR : Tape & Reel
Assembly Material
Package Code
G : Halogen and Lead Free Device
4040DS
XXXXX
SM4040DS K :
XXXXX - Lot Code
Note : SINOPOWER lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS. SINOPOWER lead-free products meet or exceed the lead-
free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. SINOPOWER
defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight
in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
SINOPOWER reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Absolute Maximum Ratings (TA = 25°C unless otherwise noted)
Symbol
Parameter
Rating
Unit
Common Ratings
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
40
±20
150
-55 to 150
2
V
V
TJ
Maximum Junction Temperature
°C
°C
A
TSTG Storage Temperature Range
IS
Diode Continuous Forward Current
TA=25°C
TA=25°C
TA=70°C
TA=25°C
TA=25°C
TA=70°C
Steady State
t ≤ 10s
7
ID
Continuous Drain Current
A
A
5.8
a
IDM
PD
RθJL
Pulse Drain Current Tested
Maximum Power Dissipation
Thermal Resistance-Junction to Lead
28
2
W
1.28
50
°C/W
°C/W
62.5
110
10
RθJA Thermal Resistance-Junction to Ambient
Steady State b
L=0.5mH
L=0.5mH
c
IAS
Avalanche Current, Single pulse
Avalanche Energy, Single pulse
A
c
EAS
25
mJ
Note a：Pulse width limited by max. junction temperature.
Note b：Surface Mounted on 1in2 pad area, t =999sec.
Note c：UIS tested and pulse width limited by maximum junction temperature 150oC (initial temperature Tj=25oC).
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
Static Characteristics
BVDSS Drain-Source Breakdown Voltage
40
-
-
-
1
V
VGS=0V, IDS=250µA
VDS=32V, VGS=0V
-
IDSS Zero Gate Voltage Drain Current
µA
TJ =85°C
-
-
30
VGS(th) Gate Threshold Voltage
IGSS Gate Leakage Current
1.5
2
2.5
±100
22
V
VDS=VGS, IDS=250µA
VGS=±20V, VDS=0V
VGS=10V, IDS=6A
VGS=4.5V, IDS=5A
-
-
-
-
nA
17
19
c
RDS(ON) Drain-Source On-state Resistance
mΩ
27
Diode Characteristics
c
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
ISD=1A, VGS=0V
-
-
-
0.75
13
1.1
V
-
-
ns
nC
IDS=6A, dlSD /dt=100A/µs
Qrr
8.7
Dynamic Characteristics d
RG
Ciss
Coss
Crss
Gate Resistance
VGS=0V,VDS=0V,F=1MHz
-
-
-
-
-
-
-
-
2.5
815
95
-
-
-
-
-
-
-
-
Ω
Input Capacitance
VGS=0V,
VDS=20V,
Frequency=1.0MHz
Output Capacitance
Reverse Transfer Capacitance
pF
60
td(ON) Turn-on Delay Time
tr Turn-on Rise Time
td(OFF) Turn-off Delay Time
tf Turn-off Fall Time
Gate Charge Characteristics d
7.8
6.9
22.4
4.8
VDD=20V, RL=20Ω,
IDS=1A, VGEN=10V,
RG=6Ω
ns
VDS=20V, VGS=10V,
IDS=6A
Qg
Total Gate Charge
-
15.7
22
Qg
Total Gate Charge
-
-
-
-
7.5
10.5
nC
Qgth
Qgs
Qgd
Threshold Gate Charge
Gate-Source Charge
Gate-Drain Charge
1.85
3.24
2.75
-
-
-
VDS=20V, VGS=4.5V,
IDS=6A
Note c：Pulse test ; pulse width≤300µs, duty cycle≤2%.
Note d：Guaranteed by design, not subject to production testing.
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Typical Operating Characteristics
Drain Current
Power Dissipation
2.4
8
7
6
5
4
3
2
1
0
2.0
1.6
1.2
0.8
0.4
TA=25oC,VG=10V
TA=25oC
0.0
0
20 40 60 80 100 120 140 160
0
20 40 60 80 100 120 140 160
Tj - Junction Temperature (°C)
Tj - Junction Temperature (°C)
Safe Operation Area
Thermal Transient Impedance
100
10
2
1
Duty = 0.5
0.2
0.1
0.05
0.1
0.01
1E-3
0.02
0.01
300µs
1
1ms
10ms
Single Pulse
0.1
Mounted on 1in2 pad
100ms
1s
θJA :110 oC/W
TA=25oC
DC
10
R
0.01
0.01
0.1
1
100 300
1E-4 1E-3 0.01 0.1
1
10 100 1000
Square Wave PulseDuration (sec)
VDS - Drain - Source Voltage (V)
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Typical Operating Characteristics (Cont.)
Drain-Source On Resistance
Output Characteristics
30
25
20
15
10
5
30
25
20
15
10
5
VGS=4,5,6,7,8,9,10V
3.5V
VGS=4.5V
VGS=10V
3V
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
15
20
25
30
VDS - Drain - Source Voltage (V)
ID -Drain Current (A)
Gate-Source On Resistance
Gate Threshold Voltage
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
70
60
50
40
30
20
10
0
IDS=6A
IDS =250µA
-50 -25
0
25 50 75 100 125 150
2
3
4
5
6
7
8
9
10
Tj - Junction Temperature (°C)
VGS - Gate - Source Voltage (V)
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Typical Operating Characteristics (Cont.)
Drain-Source On Resistance
Source-Drain Diode Forward
30
10
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
VGS = 10V
IDS = 6A
Tj=150oC
Tj=25oC
1
RON@Tj=25oC: 17mΩ
0.1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
-50 -25
0
25 50 75 100 125 150
Tj - Junction Temperature (°C)
VSD - Source - Drain Voltage (V)
Capacitance
Gate Charge
1200
1000
800
600
400
200
0
10
Frequency=1MHz
VDS=20V
IDS=6A
9
8
7
6
5
4
3
2
1
0
Ciss
Coss
Crss
0
5
10 15 20 25 30 35 40
0
2
4
6
8
10 12 14 16
QG -Gate Charge (nC)
VDS - Drain - Source Voltage (V)
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Avalanche Test Circuit and Waveforms
VDS
L
VDSX(SUS)
tp
DUT
VDS
IAS
RG
VDD
VDD
IL
tp
EAS
0.01Ω
tAV
Switching Time Test Circuit and Waveforms
VDS
RD
VDS
90%
DUT
VGS
RG
VDD
10%
VGS
tp
td(on) tr
td(off) tf
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Disclaimer
Sinopower Semiconductor, Inc. (hereinafter “Sinopower”) has been making
great efforts to development high quality and better performance products to
satisfy all customers’ needs. However, a product may fail to meet customer’s
expectation or malfunction for various situations.
All information which is shown in the datasheet is based on Sinopower’s
research and development result, therefore, Sinopower shall reserve the right
to adjust the content and monitor the production.
In order to unify the quality and performance, Sinopower has been following
JEDEC while defines assembly rule. Notwithstanding all the suppliers
basically follow the rule for each product, different processes may cause
slightly different results.
The technical information specified herein is intended only to show the typical
functions of and examples of application circuits for the products. Sinopower
does not grant customers explicitly or implicitly, any license to use or exercise
intellectual property or other rights held by Sinopower and other parties.
Sinopower shall bear no responsible whatsoever for any dispute arising from
the use of such technical information.
The products are not designed or manufactured to be used with any
equipment, device or system which requires an extremely high level of
reliability, such as the failure or malfunction of which any may result in a direct
threat to human life or a risk of human injury. Sinopower shall bear no
responsibility in any way for use of any of the products for the above special
purposes. If a product is intended to use for any such special purpose, such
as vehicle, military, or medical controller relevant applications, please contact
Sinopower sales representative before purchasing.
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Classification Profile
9
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
SM4040DSK
®
Classification Reflow Profiles
Profile Feature
Preheat & Soak
Sn-Pb Eutectic Assembly
Pb-Free Assembly
150 C
100 C
°
°
Temperature min (Tsmin
)
Temperature max (Tsmax
Time (Tsmin to Tsmax) (ts)
150 C
200 C
°
°
)
60-120 seconds
60-120 seconds
Average ramp-up rate
(Tsmax to TP)
3 C/second max.
°
3 C/second max.
°
Liquidous temperature (TL)
Time at liquidous (tL)
183 C
60-150 seconds
217 C
60-150 seconds
°
°
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
See Classification Temp in table 2
30** seconds
Time (t )** within 5 C of the specified
°
P
20** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 C/second max.
°
6 C/second max.
°
6 minutes max.
8 minutes max.
Time 25 C to peak temperature
°
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
Package
Volume mm3
Thickness
<350
≥350
<2.5 mm
235 °C
220 °C
220 °C
220 °C
≥2.5 mm
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
>2000
260 °C
245 °C
245 °C
260 °C
1.6 mm – 2.5 mm
≥2.5 mm
260 °C
250 °C
250 °C
245 °C
Reliability Test Program
Test item
Method
JESD-22, B102
JESD-22, A108
Description
SOLDERABILITY
HTRB
5 Sec, 245°C
1000 Hrs, 80% of VDS max @ Tjmax
1000 Hrs, 100% of VGS max @ Tjmax
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
HTGB
JESD-22, A108
JESD-22, A102
JESD-22, A104
PCT
TCT
Customer Service
Sinopower Semiconductor, Inc.
5F, No. 6, Dusing 1St Rd., Hsinchu Science Park,
Hsinchu, 30078, Taiwan
TEL: 886-3-5635818 Fax: 886-3-5635080
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Copyright Sinopower Semiconductor, Inc.
Rev. A.1 - December, 2015
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