SP7512BN [SIPEX]
Double-Buffered 12-Bit Multiplying DAC; 双缓冲12位乘法DAC
| 型号： | SP7512BN |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | Double-Buffered 12-Bit Multiplying DAC |
| 文件： | 总6页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Corporation
SP7512 and HS3120
SIGNAL PROCESSING EXCELLENCE
Double–Buffered 12-Bit Multiplying DAC
■ Monolithic Construction
■ 12–Bit Resolution
■ 0.01% Non-Linearity
■ Four–Quadrant Multiplication
■ Latch-up Protected
■ Low Power – 30mW
■ Single +15V Power Supply
DESCRIPTION…
The SP7512 and HS3120 are precision 12-bit multiplying DACs, double–buffered for easy
interfacing with microprocessor busses. Both unipolar and bipolar operation can be accommo-
dated with a minimum of external components. The SP7512 is available for use in commercial
and industrial temperature ranges, packaged in a 28-pin SOIC. The HS3120 is available in
commercial and military temperature ranges, packaged in a 28–pin side–brazed DIP.
(LSB)
(MSB)
Bit 1
V
2
3
4
5
6
7
8
9
10
18
11
BIT 12
REF
9
10
11
12
13
14
15
16
17
19
20
4
22
25
CE
HBE
INPUT REGISTER
INPUT REGISTER
INPUT REGISTER
CONTROL
LOGIC
24
23
21
MBE
LBE
R
5
6
7
FB
1
I
I
01
02
LDAC
DAC REGISTER
12 BIT MDAC
1
3
FB
FB
4
3
R/2
R/2
SP7512, HS3120
28
26
27
GND
8
2
V
V
GND
DD1
DD2
LDTR
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Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS
(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar, unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DIGITAL INPUT
Resolution
12
Bits
2–Quad, Unipolar Coding
Binary & Comp. Binary
The input coding is comple-
mentary binary if I02 is used.
4–Quad, Bipolar Coding
Logic Compatibility
Offset Binary
CMOS, TTL
Digital input voltage must not
exceed supply voltage or go
below –0.5V ; “0” <0.8V;
2.4V < “1” ≤VDD
Input Current
±1
µA
Data Set-up Time
250
ns
All strobes are level triggered.
See Timing Diagram; GBD*
All strobes are level triggered.
See Timing Diagram; GBD*
All strobes are level triggered.
See Timing Diagram; GBD*
Strobe Width
250
0
ns
ns
Data Hold Time
REFERENCE INPUT
Voltage Range
±25
V
Input Impedance
4
12
KOhms
ANALOG OUTPUT
Scale Factor
Scale Factor Accuracy
62.5
187.5
10
µA/VREF
±0.4
%
Using the internal feedback
resistor and an external op
amp.
At 25°C; the output leakage
current will create an offset
voltage at the external op amps
output. It doubles every 10°C
temperature increase.
Output Leakage
nA
Output Capacitance
COUT 1, all inputs high
COUT 1, all inputs low
COUT 2, all inputs high
COUT 2, all inputs low
80
40
40
80
pF
pF
pF
pF
STATIC PERFORMANCE
Integral Linearity
SP7512BN/KN, HS3120–2
Differential Linearity
SP7512BN/KN, HS3120–2
Monotonicity
±0.015
±0.024
% FSR
%FSR
SP7512BN/KN, HS3120–2
Guaranteed to 12 bits
STABILITY
Scale Factor
Integral Linearity
Differential Linearity
(TMIN to TMAX
Note 1
)
)
2
0.2
0.2
ppm FSR/°C
ppm FSR/°C
ppm FSR/°C
STABILITY
(TMIN to TMAX
Monotonicity Temp. Range
SP7512KN, HS3120C–_
SP7512BN
0
–40
–55
+70
+85
+125
°C
°C
°C
HS3120B–_
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SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS (continued)
(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DYNAMIC PERFORMANCE
Digital Small Signal Settling
Full Scale Transition Settling
Reference Feedthrough Error
@ 1kHz
1.0
2.0
µS
µS
to 0.01% (strobed)
(VREF = 20Vpp)
<1
2
mV
mV
@ 10kHz
Delay to output
from Bits input
from LDAC
from CE
100
200
120
ns
ns
ns
Delay times are twice the
amount shown at TA = +125° C
POWER SUPPLY (VDD
Operating Voltage
Voltage Range
Current
)
+15 ±5%
V
V
mA
%/%
specifications guaranteed
+5
+16
2.5
0.002
Rejection Ratio
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
SP7512K
SP7512B
HS3120–C
0
–40
0
–55
–55
–65
+70
+85
+70
+125
+125
+150
°C
°C
°C
°C
°C
°C
HS3120–B
HS3120–B/883
Storage Temperature
Package
SP7512_N
28-pin SOIC
HS3120–C
28–pin Plastic DIP
HS3120–B
28–pin Side–Brazed DIP
Notes:
1.
Using the internal feedback resistor, output leakage current creates an offset, which doubles every
10°C rise in temperature.
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Corporation
SIGNAL PROCESSING EXCELLENCE
PIN ASSIGNMENTS
FEATURES…
The SP7512 and HS3120 are precision 12-bit
multiplyingDACswithinternaltwo-stageinput
storage registers for easy interfacing with mi-
croprocessorbusses.TheDACsareimplemented
as a one-chip CMOS circuit with a resistor
ladder network designed for 0.01% linearity
without laser trimming.
Pin 1 – FB4 – Feedback Bipolar Operation
Pin 2 – LDTR – Ladder Termination
Pin 3 – FB3 – Feedback Bipolar Operation
Pin 4 – VREF – Reference Voltage Input
Pin 5 – FB1 – Feedback, Unipolar/Bipolar
Pin 6 – IO1 – Current out into virtual ground
Pin 7 – IO2 – Current out-complement of I01
Pin8–VSS–Ground, AnalogandDACRegister
Pin 9 – DB11 – MSB, Data Bit 1
Pin 10 – DB10 – Data Bit 2
The input registers are sectioned into 3 seg-
ments of 4 bits each, all individually address-
able. The DAC-register, following the input
registers, is a parallel 12-bit register for holding
the DAC data while the input registers are up-
dated. Only the data held in the DAC register
determines the analog output value of the con-
verter.
Pin 11 – DB9 – Data Bit 3
Pin 12 – DB8 – Data Bit 4
The SP7512 and HS3120 have been designed
for great flexibility in connecting to bus-ori-
ented systems. The 12 data inputs are organized
into 3 independent addressable 4-bit input reg-
isters such that the DACs can be connected to
either a 4, 8 or 16-bit data bus. The control logic
of the DACs includes chip enable and latch
enable inputs for flexible memory mapping. All
controls are level-triggered to allow static or
dynamic operation.
Pin 13 – DB7 – Data Bit 5
Pin 14 – DB6 – Data Bit 6
Pin 15 – DB5 – Data Bit 7
Pin 16 – DB4 – Data Bit 8
Pin 17 – DB3 – Data Bit 9
Pin 18 – DB2 – Data Bit 10
Pin 19 – DB1 – Data Bit 11
A total of 5 output lines are provided on the
DACs to allow unipolar and bipolar output
connection with a minimum of external compo-
nents. The feedback resistor is internal. The
resistor ladder network termination is exter-
nally available, thus eliminating an external
resistor for the 1 LSB offset in bipolar mode.
Pin 20 – DB0 – LSB, Data Bit 12
Pin 21 – LDAC – Transfers data from input to
DAC register; a logic “0” latches data into
registers; a logic “1” allows data to change
(transfer to) register.
Pin 22 – CE – Chip Enable, active low
Pin 23 – LBE – Bit 12 to Bit 9 Enable
Pin 24 – MBE – Bit 8 to Bit 5 Enable
Pin 25 – HBE – Bit 4 to Bit 1 Enable
The SP7512 is available for use in commercial
and industrial temperature ranges, packaged in
400
V
+15V
REF
V
V
DD2
DD1
FB
1
Pin 26 – VDD2 – Supply Analog and DAC
Register
R
OS
-
I
O1
DIGITAL
INPUTS
A
+
LDTR
SP7512
V
OUT
Pin 27 – VSS1 – Ground input latches
Pin 28 – VDD1 – Supply input latches
FB
FB
4
3
I
O2
NOTE: Pins 8 and 27, and pins 26 and 28 must
be connected externally.
CE
V
V
SS1
SS
HBE
MBE
LBE
LDAC
Figure 1. Unipolar Operation
116
Corporation
SIGNAL PROCESSING EXCELLENCE
-15V
+15V
TRANSFER FUNCTION (N=12)
20KΩ
BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT
400Ω
ADJUSTMENT
RANGE 0.2%
V
+15V
1
REF
–N
–(N – 1)
V
V
111...111
100...001
100...000
011...111
000...000
–VREF (1 – 2
–VREF (1/2 + 2
–VREF /2
)
–VREF (1 – 2
–VREF (2
0
)
DD1
FB
DD2
4MΩ
–N
–(N – 1)
)
)
)
R
OS1
-
I
O1
A
–N
–(N – 1)
1
DIGITAL
INPUTS
SP7512
–VREF (1/2 – 2
0
VREF (2
VREF
)
+
V
OUT
N.C.
N.C.
FB
FB
4
3
4KΩ
Table 1. Transfer Function
1KΩ
3KΩ
I
O2
LDTR
R
OS2
CE
V
V
SS
SS1
HBE
MBE
-
A
2
+
V
OUT1
, A
, LF411ACN
2
LBE
A
LDAC
1
Figure 2. Bipolar Operation
Bipolar Operation
a 28–pin SOIC. The HS3120 is available in
commercial and military temperature ranges,
packaged in a 28–pin side–brazed DIP. For
product processed and screened to the require-
ments of MIL–M–38510 and MIL–STD–883C,
please consult the factory (HS3120B only).
Figure 2 shows the interconnections for bipolar
operation. Connect IO1, IO2, FB1, FB3, FB4 as
shown in diagram. Tie LDTR to IO2. To main-
tainspecifiedlinearity, externalamplifiersmust
bezeroed. ThisisbestdonewithVREF settozero
and, the DAC register loaded with 10...0 (MSB
= 1), set ROS2 for VOUT1 = 0V. Then set ROS1 for
VOUT = 0V.
APPLICATIONS INFORMATION
Unipolar Operation
Figure 1 shows the interconnections for unipo-
lar operation. Connect IO1 and FB1 as shown in
diagram. Tie IO2 (Pin 7), FB3 (Pin 3), and FB4
(Pin 1) to Ground (Pin 8). To maintain specified
linearity, external amplifiers must be zeroed.
This is best done with VREF set to zero and, with
the DAC register loaded with all bits at zero,
adjust ROS for VOUT = 0V
Grounding
Connect all GND pins to system analog ground
and tie this to digital ground. All unused input
pins must be grounded.
117
Corporation
SIGNAL PROCESSING EXCELLENCE
TIMING
INPUT
DATA
t
3
t
2
CE
LBE
MBE
t
1
t
3
t
1
t
2
HBE
LDAC
t
2
OUTPUT
t
4
TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED.
t1: Data Setup Time, Time data must be stable before strobe (byte enable/
LDAC) goes to “0”, t1 (min) = 250ns.
t2: Strobe Width. t2 (min) = 250ns. (CE, LBE, MBE, HBE, LDAC).
t3: Hold Time. Time data must be stable after strobe goes to “0”, t3 = 0ns.
t4: Delay from LDAC to Output, t4 = 200ns.
NOTE: Minimum common active time for CE and any byte enable is 250ns.
ORDERING INFORMATION
Model .................................................................. Monotonicity ................................. Temperature Range ........................................ Package
Double–Buffered 12–Bit Multiplying DAC
SP7512BN ............................................................... 12–Bit ......................................... –40°C to +85°C ......................................28-pin, 0.3" SOIC
SP7512KN ............................................................... 12–Bit .............................................. 0°C to +70°C ......................................28-pin, 0.3" SOIC
HS3120C–2N ........................................................... 12–Bit .............................................. 0°C to +70°C ............................ 28-pin, 0.6" Plastic DIP
HS3120C–2Q ........................................................... 12–Bit .............................................. 0°C to +70°C .................. 28-pin, 0.6" Side–Brazed DIP
HS3120B–2Q ........................................................... 12–Bit ....................................... –55°C to +125°C .................. 28-pin, 0.6" Side–Brazed DIP
HS3120B–2/883 ...................................................... 12–Bit ....................................... –55°C to +125°C .................. 28-pin, 0.6" Side–Brazed DIP
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SIGNAL PROCESSING EXCELLENCE
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