CXD2436Q [SONY]
Timing Generator for LCD Panels; 时序发生器，用于LCD面板
| 型号： | CXD2436Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Generator for LCD Panels |
| 文件： | 总34页 (文件大小：2861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2436Q
Timing Generator for LCD Panels
For the availability of this product, please contact the sales office.
Description
100 pin QFP (Plastic)
The CXD2436Q is a timing signal generator for the
VGA LCD panel LCX012 driver. This chip has a
built-in serial interface circuit which allows the mode
to be switched with respect to various VGA signals
through direct control from an external
microcomputer, etc.
Features
• Generates the LCX012 drive pulse.
Absolute Maximum Ratings (Ta=25 °C)
• Supports three-panel projectors.
• Supply voltage
• Input voltage
VDD
VSS–0.5 to +7.0
V
• Built-in serial interface circuit
VI VSS–0.5 to VDD+0.5 V
VO VSS–0.5 to VDD+0.5 V
• Supports various VGA signals. (non-interlaced
mode)
• Output voltage
• Operating temperature
• Built-in 2-line pair drive circuits
• Supports NTSC and PAL systems.
• Supports up/down and/or right/left inversion.
• Supports line inversion and field inversion.
• Generates timing signal of external sample-and-
hold circuit.
Topr
–20 to +75
°C
°C
• Storage temperature
Tstg
–55 to +150
Recommended Operating Conditions
• Supply voltage
• Supply voltage
VDD
+4.5 to +5.5
–20 to +75
V
VCC
°C
Applications
LCD projectors, etc.
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E95810-TE
CXD2436Q
Block Diagram
3
28
53
78
4
15
29
40
42
45
46
47
48
49
51
52
54
65
79
90
22
PWM
32
PEO
30
31
8
EXT-CKI
XCLR
PLNT
VGAV
SLSY
SLCKI
CKI
34
DIRECT CLEAR
MASTER CLOCK
9
10
18
36
CKO 33
6
7
HPOL
VPOL
35
38
RPD
FPD
PLL PHASE COMPARATOR
5
CSYNC
H-SYNC DETECTOR
H-SKEW DETECTOR
TC
39
16
17
HD2IN
VD2IN
HDN
PLL COUNTER
68
69
73
74
1
2
HD1IN
VD1IN
XHDN
HDO
TST1 14
XHDO
TST2
20
TST3
21
SCK
SI
41
43
44
TST4
23
V-SYNC SEPARATOR
TST5
24
CS
V-RESET PULSE GENERATOR
TST6
25
TST7
26
PO0
PO1
PO2
PO3
PO4
PO5
PO6
PO7
PO8
PO9
PO10
PO11
55
56
57
58
59
60
61
62
63
64
66
67
TST8
SERIAL INTERFACE
27
TST9
V-RESET PULSE GENERATOR
37
TST10
50
92
VCK
93
VST1
72
VDO
V-POSITION COUNTER
H-POSITION COUNTER
11
SLDWN
19
SLMNB
V-TIMING PULSE
GENERATOR
&
H-TIMING PULSE
GENERATOR
DWN
71
PRG
75
XCLP1
76
PULSE ELIMINATOR
XCLP2
77
HST
84
SLRGT
RGT
12
82
83
HCK1
85
HCK2
86
XRGT
CLR
87
ENB
88
INT
89
PCG
91
SH1
94
SH2
95
FIELD & LINE CONTROLLER
AUX-VD COUNTER
SH3
96
SH4
97
FRP
XFRP
FLD
80
81
70
13
SH5
98
SH6
99
SH7
100
SLFR
—2—
CXD2436Q
Pin Description
Pin
Input pin for
Symbol
No.
I/O
Description
open status
1
2
3
4
5
HD1IN
VD1IN
VDD
I
I
Hsync input (VGA)
Vsync input (VGA)
Power supply
GND
—
—
—
—
—
—
—
I
VSS
CSYNC
Composite sync input (NTSC/PAL)
HD, CSYNC polarity identification input
(High: positive polarity, Low: negative polarity)
VD, CSYNC polarity identification input
(High: positive polarity, Low: negative polarity)
External clear (all clear when Low)
6
7
HPOL
VPOL
I
I
H
H
8
9
XCLR
PLNT
I
I
I
H
H
H
PAL/NTSC switching (High: NTSC, Low: PAL)
VGA (NTSC/PAL) switching (High: VGA, Low: NTSC/PAL)
Up/down inversion discrimination signal input
(High: Down, Low: Up)
10 VGAV
11 SLDWN
I
I
H
H
Right/left inversion discrimination signal input
(High: Normal, Low: Reverse)
12 SLRGT
13 SLFR
14 TST1
I
I
1H/1F inversion switching (High: 1H, Low: 1F)
Test pin (Not connected or High.)
H
H
15
VSS
—
I
GND
—
—
—
H
16 HD2IN
17 VD2IN
18 SLSY
19 SLMNB
20 TST2
21 TST3
22 N.C.
HD2 input (for NTSC/PAL separate-sync)
VD2 input (for NTSC/PAL separate-sync)
SYNC input switching (High: CSYNC, Low: HD2IN and VD2IN)
I
I
I
Switches mode (High: Nothing, Low: 400
Test pin (Not connected or High.)
Test pin (Connect to GND.)
N.C.
480 line conversion)
H
I
H
I
H
—
—
—
—
—
—
—
—
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
23 TST4
24 TST5
25 TST6
26 TST7
27 TST8
Test pin (Not connected or High.)
Test pin (Not connected or High.)
Test pin (Not connected or High.)
Test pin (Not connected.)
Test pin (Connect to GND.)
Power supply
28
29
VDD
VSS
GND
30 EXT-CKI
31 PEO
32 PWM
33 CKO
34 CKI
External clock input
I/O
I
Loop filter integrator output
Loop filter integrator input
Oscillation cell output (NTSC/PAL)
Oscillation cell input (NTSC/PAL)
Phase comparator output (NTSC/PAL)
I/O
I
35 RPD
O
Clock input selection (High: CKI, Low: EXT-CKI)
(NTSC/PAL mode only)
36 SLCKI
I
H
37 TST9
38 FPD
I
Test pin (Not connected or High.)
Phase comparator output (NTSC/PAL)
H
O
—
—3—
CXD2436Q
Pin
No.
Input pin for
Symbol
I/O
Description
FPD pin pulse width adjustment
open status
—
—
H
39 TC
40
41 SCK
42
I/O
—
I
VSS
GND
Serial interface clock input
GND
VSS
—
I
—
L
43 SI
Serial interface data input
Serial interface chip select
GND
44 CS
I
H
45
46
47
48
49
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
I
—
—
—
—
—
H
GND
GND
GND
GND
50 TST10
Test pin (Not connected or High.)
GND
51
52
53
54
VSS
VSS
VDD
VSS
—
—
—
—
O
O
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GND
Power supply
GND
55 PO0
56 PO1
57 PO2
58 PO3
59 PO4
60 PO5
61 PO6
62 PO7
63 PO8
64 PO9
Serial I/O data output
Serial I/O data output
Serial I/O data output
Serial I/O data output
Serial I/O data output
Serial I/O data output
Serial I/O data output
Serial I/O data output
Serial I/O data output
Serial I/O data output
GND
65
VSS
66 PO10
67 PO11
68 HDN
69 XHDN
70 FLD
Serial I/O data output
Serial I/O data output
Phase comparator output (positive polarity)
Phase comparator output (negative polarity)
Field discrimination signal output
Up/down inversion discrimination signal output
VD pulse output (positive polarity)
HD pulse output (positive polarity)
HD pulse output (negative polarity)
Precharge signal pulse (positive polarity)
Pedestal clamp pulse 1
Pedestal clamp pulse 2
Power supply
71 DWM
72 VDO
73 HDO
74 XHDO
75 PRG
76 XCLP1
77 XCLP2
78
79
VDD
VSS
GND
80 FRP
81 XFRP
82 RGT
AC drive inversion timing output
AC drive inversion timing output
Right/left inversion discrimination signal output
—4—
CXD2436Q
Pin
No.
Input pin for
Symbol
I/O
Description
open status
83 XRGT
84 HST
85 HCK1
86 HCK2
87 CLR
88 ENB
89 INT
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Right/left inversion discrimination signal output
H start pulse output (positive polarity)
H clock pulse 1 output
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H clock pulse 2 output
CLR pin output
ENB pin output
INT pin output
90
VSS
GND
91 PCG
92 VCK
93 VST1
94 SH1
95 SH2
96 SH3
97 SH4
98 SH5
99 SH6
100 SH7
PCG pin output (positive polarity)
V clock pulse output
V start pulse output
Sample-and-hold pulse 1 (positive polarity)
Sample-and-hold pulse 2 (positive polarity)
Sample-and-hold pulse 3 (positive polarity)
Sample-and-hold pulse 4 (positive polarity)
Sample-and-hold pulse 5 (positive polarity)
Sample-and-hold pulse 6 (positive polarity)
Sample-and-hold pulse 7 (positive polarity)
Electrical Characteristics
1. DC characteristics
(Temperature = 25 °C, VSS = 0 V)
Item
Symbol
VDD
Conditions
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
Applicable pins
Supply voltage
VIH1
VIL1
0.7 VDD
Input pins other than
those noted below
HDnIN, VDnIN, CSYNC,
CKI, PWM, TC, PEO,
CKO, SI, SCK, CS
Input voltage 1
CMOS input cell
V
0.3 VDD
0.2 VDD
VIH2
0.8 VDD
CMOS Schmitt
trigger input cell
Input voltage 2 VIL2
V
VT+ –VT+
0.6
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
IIL
IOH=–2 mA
IOL=4 mA
VDD–0.8
VDD–0.8
VDD–0.8
VDD/2
Output pins other than
those noted below
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
V
V
0.4
0.4
0.4
IOH=–4 mA
IOL=8 mA
VCK
IOH=–6 mA
IOL=12 mA
V
HCKn, SHn, HST
CKO, PEO
IOH=–3 mA
IOL=3 mA
V
VDD/2
–240
240
1
Input leak
current
Pull-up resistor connected
Pull-down resistor connected
High impedance
status
–40
40
–100
100
µA
IIH
SI
Output leak
current
ILZ
–40
40
µA RPD, FPD
mA At no load
Current
fclk=31 MHz
VDD=5.0 V
IDD
55
consumption
1
Input pins with pull-up resistors
HPOL, VPOL, XCLR, PLNT, VGAV, SLDWN, SLRGT, SLFR, TST1, SLSY, TST2, TST3, SLCKI, TST9, SCK, CS
—5—
CXD2436Q
2. AC characteristics
(VDD=5.0 V±0.5 V, VSS=0 V)
Item
Applicable pins
EXT-CKI, CKI
Symbol Conditions
Min.
25
Typ.
Max. Unit
ns
Clock input cycle
Cross-point time difference HCK1, 2
∆t
CL=30 pF
CL=30 pF
CL=30 pF
–10
10
20
20
ns
ns
ns
Output rise delay
Output fall delay
HCKn, SHn
tpr
tpf
HCKn, SHn
Other than
Output rise delay
Output fall delay
tpr
tpf
CL=30 pF
CL=30 pF
CL=30 pF
CL=30 pF
30
30
10
10
ns
ns
ns
ns
HCKn and SHn
Other than
HCKn and SHn
HCK1, SH1 delay
time difference
HCK2, SH1 delay
time difference
HCK1 duty
HCK1, SH1
HCK2, SH1
dt1
dt2
HCK1
HCK2
tH/tH+tL CL=30 pF
tH/tH+tL CL=30 pF
48
48
50
50
52
52
%
%
HCK2 duty
VDD
EXT-CKI/CKI
0V
VDD
90%
Output
Output
0V
tpr
tpf
VDD
10%
0V
VDD
HCK1
50%
50%
0V
VDD
50%
HCK2
50%
0V
∆t
∆t
—6—
CXD2436Q
EXT-CKI
/CKI
HCK1
HCK2
50%
t1
50%
50%
t2
tH
tL
SH1
50%
50%
dt2
dt1
(SLRGT=H, SHP0/SHP1/SHP2/SHP3=L)
3. Serial interface block AC characteristics
tw1
SCK
50%
50%
50%
50%
tw1
th1
ts1
SI (DATA)
50%
ts0
50%
th0
th1
50%
50%
CS
(VDD=5.0 V±0.5 V, VSS=0 V, Topr=–20 to +75 °C
Symbol
Item
Min.
Max.
ts1
th1
tw1
ts0
th0
th1
SI setup time with respect to rise of SCK
SI hold time with respect to rise of SCK
SCK pulse width
200 ns
200 ns
200 ns
200 ns
200 ns
200 ns
CS setup time with respect to rise of SCK
CS hold time with respect to rise of SCK
SCK high-level hold time with respect to rise of CS
2tw1
2tw1
—7—
CXD2436Q
LCD Panel Structure
The structure of LCD panels (LCX012AL) driven by this IC is shown below.
The dot arrangement is a square arrangement, and the shaded region within the diagram is not displayed.
Gate SW1
Gate SW2
Gate SW109
VSR1
VSR2
VSR3
VSR4
VSR5
VSR6
Photo-shielding
area
Display area
VSR
483
VSR
484
VSR
485
VSR
486
VSR
487
VSR
488
5
644
654
5
• The effective pixels are horizontal: 644 pixels and vertical: 484 pixels.
• The horizontal pixel start position is from Sig6 of the first-stage scanner. (Sig1 to Sig5 of the first-stage
scanner are the photo-shielding area and are not displayed.)
• The vertical pixel start position is from the third-stage scanner.
• These relationships are the same even during up/down and/or right/left inversion. (The entire area within the
panel is inverted.)
—8—
CXD2436Q
Description of Operation
• Sync input pins
The CXD2436Q has three types of sync input pins.
Pin No.
Symbol SLSY setting
Application
1
2
HD1IN
—
SYNC input pins for VGA
VD1IN
5
CSYNC
HD2IN
VD2IN
H
L
CSYNC input pin for NTSC/PAL
Separate SYNC input pins for NTSC/PAL
16
17
• Clock input pins
The CXD2436Q has two clock input pin systems to support two types of PLL circuits.
1) When using EXT-CKI (using an external PLL IC)
The 1/N frequency divider output is output from the HDN and XHDN pins for the external PLL IC.
The used pins are shown in the following table. (SLCKI = Low)
Pin No.
30
Symbol
Application
Clock input
HSYNC
EXT-CKI
Phase comparison output
(positive polarity)
68
69
HDN
HDN OUTPUT
Phase comparison output
(negative polarity)
400 clk
XHDN
2) When using CKI
This system uses the built-in phase comparator and an externally attached VCO circuit (see the Application
Circuit).
This system is used during AV mode (NTSC/PAL).
The used pins are shown in the following table. (Effective when SLCKI is set to High.)
Pin No.
31
Symbol
PEO
Application
Loop filter integrator output
Loop filter integrator input
32
PWM
CKO
CKI
33
Clock output (oscillation cell output)
Clock input (oscillation cell input)
Phase comparator output
34
35
RPD
FPD
TC
38
Phase comparator output
39
FPD pin pulse width adjustment
HSYNC
An outline of the output waveforms during
PLL lock is shown in the figure to the left.
RPD
FPD
—9—
CXD2436Q
• Connections supporting up/down and/or right/left inversion
The CXD2436Q is designed for use with three-panel projectors, and has a system configuration which
permits both normal and reverse scan. The RGT and XRGT output to the panel are switched according to
the SLRGT input, and the DWN output is switched according to the SLDWN input in the same manner.
LCX012
Normal scanning
RGT
panel
DWN
SLRGT
12
11
82
83
RGT
LCX012
RGT
DWN
Normal scanning
panel
XRGT
SLDWN
71
DWN
LCX012
Reverse scanning
panel
RGT
DWN
Example of supporting a three-panel system
• AC driving of LCD panels for no signal
The following measures have been adopted to allow AC driving of LCD panels even when there is no
signal.
• Horizontal direction pulse:
• Vertical direction pulse:
• VST cycle for no signal
The PLL is set to free running status. Therefore, the frequency of the
horizontal direction pulse is dependent on the PLL free running frequency.
The number of lines is counted by an internal counter and VST and FRP
are output at a specified cycle.
• Free running detection timing
NTSC
PAL
269H
321H
526H
NTSC
PAL
291H
339H
873H
VGA
VGA
Free running operates at the following cycles.
(No signal is judged if there is no VSYNC input for longer than the following periods.)
• Description of the MODE selector switch
• VGA/AV (NTSC/PAL) switching is performed with two pins.
VGAV
PLNT
MODE
VGA
H
H
L
H
L
VGA
H
L
NTSC
PAL
L
• The HD1IN, HD2IN, VD1IN, VD2IN and CSYNC input polarities are supported by two pins.
HD1IN
HD2IN
VD1IN
VD2IN
HPOL
VPOL
CSYNC
H
H
L
H
L
Positive polarity
Positive polarity
Positive polarity
Positive polarity Negative polarity
Negative polarity Positive polarity
—
—
H
L
L
Negative polarity Negative polarity Negative polarity
—10—
CXD2436Q
• XCLR (External clear)
Reset should be performed during startup in order to initialize the serial interface. Performing external
clear sets all serial interface modes to Low.
• Serial interface specifications
The CXD2436Q can set and switch the driving mode with the serial interface.
Set the corresponding timing data for each VGA signal according to the format in the diagram below. Be
sure to make the initial mode settings. (See the AC characteristics for detailed timing specifications.)
CS
SCK
SI
D0
D1
D2
D3
D4
D5
D6
D7
Fig. 1. Timing chart for the serial interface input block
Note) D0 to D7 internal transfer is completed by the CS signal switching from a Low to High pulse. Therefore,
the data should be transferred in 1-byte units with the CS signal reset each time.
• Description of mode switching settings using the serial interface
The CXD2436Q can set the following six modes.
(1) Frequency division ratio setting for the 1/N frequency divider of the master clock PLL circuit block.
(2) H screen center adjustment. The center changes by one dot with LSB.
(3) V screen center adjustment. The center changes by one line with LSB.
(4) Sample-and-hold circuit phase adjustment. The phase changes by a half-dot with LSB.
(See the Description of Sample-and-Hold Timing for details.)
(5) Clamp pulse timing adjustment (4-way)
(6) Data output (Serial data is held and output.)
Upper 4-bit
Lower 4-bit data
address value
Functions
D3
PHP3
PHP7
—
D2
PHP2
PHP6
PHP10
HP2
D1
PHP1
PHP5
PHP9
HP1
D0
PHP0
PHP4
PHP8
HP0
D7 to D4
0H
PLL 1/N frequency
divisions
1H
2H
HP3
—
3H
H screen center
adjustment
HP6
HP5
HP4
4H
VP3
—
VP2
VP1
VP0
5H
V screen center
adjustment
VP6
VP5
VP4
6H
SHP3
—
SHP2
—
SHP1
CLPP1
PO1
SHP0
CLPP0
PO0
7H
S/H timing
8H
Clamp timing
PO3
PO7
PO11
PO2
PO6
PO10
9H
PO5
PO4
AH
BH
Data output
PO9
PO8
PHP0, HP0, VP0, SHP0, CLPP0
—11—
CXD2436Q
• PLL 1/N frequency division ratio setting
For the frequency division ratio setting during VGA mode, set the value of the number of dots for the
horizontal period –1 in PHP0-10.
(Example) When the horizontal period is set to 800 dots
PHP setting value = 800-1
799 (01100011111 LSB)
PHP
10
0
9
1
8
1
7
0
6
0
5
0
4
1
3
1
2
1
1
1
0
1
Set the value of the number of dots fixed to 816 during NTSC/PAL.
PHP setting value = 816-1 815 (01100101111 LSB)
PHP
10
0
9
1
8
1
7
0
6
0
5
1
4
0
3
1
2
1
1
1
0
1
• Horizontal position setting
The horizontal display start position setting can be changed one dot at a time by the HP0 to 6 setting.
HSYNC
644dots
Thp
Image display period
The maximum and minimum Thp values which can be set are shown in the following table.
HP
6
1
0
5
1
0
4
1
0
3
1
0
2
1
0
1
1
0
0
1
0
VGA
NTSC
5.8 µs
PAL
Minimum value
Maximum value
110 dots
237 dots
5.8 µs
15.8 µs
15.7 µs
• Vertical position setting
The vertical display start position setting can be changed one dot at a time by the VP0 to 6 setting.
VSYNC
HSYNC
484 line
Tvp
Image display period
The maximum and minimum Tvp values which can be set are shown in the following table.
VP
6
1
0
5
1
0
4
1
0
3
1
0
2
1
0
1
1
0
0
1
0
VGA
5 H
NTSC
14 H
PAL
14 H
Minimum value
Maximum value
133 H
141 H
141 H
(This table shows the ODD field values for NTSC and PAL.)
—12—
CXD2436Q
• CLP pulse position setting
The XCLP pulse position can be changed to four different positions. Each of these positions is shown
below.
The XCLP pulse is linked with the horizontal position setting, and is indicated with the HP (1000000 LSB)
setting.
HSYNC
Wclp1
XCLP1
tclp1
XCLP2
The centers of the XCLP1
tclp2
and XCLP2 pulses match.
Wclp2
• VGA mode
CLPP1 CLPP0 tclp1 Wclp1
tclp2 Wclp2
74 dot 40 dot 61 dot 67 dot
81 dot 40 dot 68 dot 67 dot
88 dot 40 dot 75 dot 67 dot
95 dot 40 dot 82 dot 67 dot
0
0
1
1
0
1
0
1
• NTSC mode
CLPP1 CLPP0 tclp1 Wclp1
tclp2 Wclp2
0
0
1
1
0
1
0
1
4.83 µs 1.17 µs 4.36 µs 2.18 µs
5.30 µs 1.17 µs 4.83 µs 2.18 µs
5.76 µs 1.17 µs 5.30 µs 2.18 µs
6.23 µs 1.17 µs 5.76 µs 2.18 µs
• PAL mode
CLPP1 CLPP0 tclp1 Wclp1
tclp2 Wclp2
0
0
1
1
0
1
0
1
4.87 µs 1.18 µs 4.39 µs 2.20 µs
5.33 µs 1.18 µs 4.86 µs 2.20 µs
5.80 µs 1.18 µs 5.33 µs 2.20 µs
6.27 µs 1.18 µs 5.80 µs 2.20 µs
—13—
CXD2436Q
• Switching the SH pulse timing
The phase relationship between the sample-and-hold pulses and HCK can be switched in 12 different ways
with SHP0, SHP1, SHP2 and SHP3.
(This timing generator has a 0.5 DOT OFFSET function in order to ensure the phase margin.)
In addition, the timing differs according to the scanning direction (right/left scan).
Right scanning pulse (RGT = H)
HCK
SH1
SH2
SH3
SH4
SH5
SH6
SH7
SHP0=L
SHP1=L
SHP2=L
SHP3=L
SHP0=H
SHP1=L
SHP2=L
SHP3=L
SHP0=L
SHP1=H
SHP2=L
SHP3=L
SHP0=H
SHP1=H
SHP2=L
SHP3=L
HCK
SH1
SH2
SH3
SH4
SH5
SH6
SH7
SHP0=L
SHP1=L
SHP2=H
SHP3=L
SHP0=H
SHP1=L
SHP2=H
SHP3=L
SHP0=L
SHP1=H
SHP2=H
SHP3=L
SHP0=H
SHP1=H
SHP2=H
SHP3=L
—14—
CXD2436Q
HCK
SH1
SH2
SH3
SH4
SH5
SH6
SH7
SHP0=L
SHP1=L
SHP2=L
SHP3=H
SHP0=H
SHP1=L
SHP2=L
SHP3=H
SHP0H=L
SHP1=H
SHP2=L
SHP3=H
SHP0=H
SHP1=H
SHP2=L
SHP3=H
Left scanning pulse (RGT = L)
HCK
SH1
SH2
SH3
SH4
SH5
SH6
SH7
SHP0=L
SHP1=L
SHP2=L
SHP3=L
SHP0=H
SHP1=L
SHP2=L
SHP3=L
SHP0=L
SHP1=H
SHP2=L
SHP3=L
SHP0=H
SHP1=H
SHP2=L
SHP3=L
—15—
CXD2436Q
HCK
SH1
SH2
SH3
SH4
SH5
SH6
SH7
SHP0=L
SHP1=L
SHP2=H
SHP3=L
SHP0=H
SHP1=L
SHP2=H
SHP3=L
SHP0=L
SHP1=H
SHP2=H
SHP3=L
SHP0=H
SHP1=H
SHP2=H
SHP3=L
HCK
SH1
SH2
SH3
SH4
SH5
SH6
SH7
SHP0=L
SHP1=L
SHP2=L
SHP3=H
SHP0=H
SHP1=L
SHP2=L
SHP3=H
SHP0=L
SHP1=H
SHP2=L
SHP3=H
SHP0=H
SHP1=H
SHP2=L
SHP3=H
—16—
CXD2436Q
—17—
CXD2436Q
—18—
CXD2436Q
—19—
CXD2436Q
—20—
CXD2436Q
—21—
CXD2436Q
—22—
CXD2436Q
—23—
CXD2436Q
—24—
CXD2436Q
—25—
CXD2436Q
—26—
CXD2436Q
—27—
CXD2436Q
—28—
CXD2436Q
—29—
CXD2436Q
—30—
CXD2436Q
—31—
CXD2436Q
—32—
CXD2436Q
E X T - C K I
V S S
V S S
V D D
V S S
V D D
V S S
P O 0
P O 1
P O 2
P O 3
P O 4
P O 5
P O 6
P O 7
P O 8
P O 9
V S S
T S T 8
T S T 7
T S T 6
T S T 5
T S T 4
N C
T S T 3
T S T 2
S L M N B
S L S Y
V D 2 I N
H D 2 I N
V S S
P O 1 0
T S T 1
P O 1 1
H D N
S L F R
S L R G T
S L D W N
V G A V
P L N T
X C L R
V P O L
H P O L
C S Y N C
V S S
X H D N
F L D
D W N
V D O
H D O
X H D O
P R G
X C L P 1
X C L P 2
V D D
V D D
V D 1 I N
H D 1 I N
V S S
F R P
to the panel
to the RGB driver
—33—
CXD2436Q
Package Outline Unit : mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12
M
0.15
0° to 15°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
SONY CODE
EIAJ CODE
QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
1.4g
PACKAGE WEIGHT
JEDEC CODE
—34—
相关型号：
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