CXG1082EN [SONY]
Receive Dual Low Noise Amplifier/Mixer; 接收双路低噪声放大器/混频器
| 型号： | CXG1082EN |
| 厂家： | 
SONY CORPORATION |
| 描述： | Receive Dual Low Noise Amplifier/Mixer |
| 文件： | 总9页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXG1082EN
Receive Dual Low Noise Amplifier/Mixer
For the availability of this product, please contact the sales office.
Description
16 pin VSON (Plastic)
The CXG1082EN is a receive dual low noise amplifier/
mixer MMIC. This IC is designed using the Sony’s
GaAs J-FET process.
Features
• High conversion gain:Gp = 17dB (LNA Typ.)
Gc = 11 to 12dB (MIX Typ.)
• Low noise figure:
NF = 1.5dB (LNA Typ.)
NF = 4.2dB (MIX Typ.)
Absolute Maximum Ratings (Ta = 25°C)
• Single 3V power supply operation
• Low LO input power operation PLO = –15dBm
• Single CTL pin achieved by the built-in inverter
circuit
• Supply voltage
• Input power
VDD
4.5
+13
V
dBm
mA
°C
PIN
• Current consumption IDD
• Operating temperature Topr
• Storage temperature Tstg
15
–35 to +85
–65 to +150
• 16-pin VSON package
°C
Applications
Recommended Operating Voltages
800MHz Japan digital cellular telephones (PDC)
• Supply voltage
• Control voltage
VDD
2.7 to 3.3
V
V
V
VCTL (H) 2.4 to 3.3
VCTL (L) 0 to 0.3
Structure
GaAs J-FET MMIC
Block Diagram
Pin Configuration
8
6
8
7
6
5
4
3
2
1
9
LNA RFIN2
LNA RFOUT
9
LNA RFIN2
CAP
LNA RFIN1
LNA RFIN1
CAP
10
11
12
13
14
15
16
LNA RFOUT/VDD1 (LNA)
GND
GND
CTL
OPT
GND
3
1
MIX RFIN
LO IN
MIX RFIN
GND
GND
VDD2 (LO AMP)
IFOUT/VDD3 (MIX)
16
LO IN
IFOUT
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00408-PS
CXG1082EN
Electrical Characteristics
Conditions: VDD = 3.0V, VCTL (H) = 3.0V, VCTL (L) = 0V, fRF1 = 870MHz, fRF2 = 820MHz, fLO = fRF – 130MHz,
PLO = –15dBm, Ta = 25°C, unless otherwise specified
Low Noise Amplifier Block
Measurement
condition
Min.
Typ. Max. Unit
Item
Current
Symbol
Path
—
RF frequency VCTL
—
—
—
—
H
L
—
—
1.9
1.9
55
2.5
2.5
80
IDD
mA
µA
consumption
When no
signal
H
L
—
Control current
ICTL
—
–1
15
—
0
—
H
L
17
19
RFIN1 → RFOUT
RFIN2 → RFOUT
fRF1
fRF2
–20
–25
17
–15
–20
19
Power gain
Gp
dB
H
L
—
When a
small signal
15
—
RFIN1 → RFOUT
RFIN2 → RFOUT
RFIN1 → RFOUT
RFIN2 → RFOUT
RFOUT → RFIN1
RFOUT → RFIN2
fRF1
fRF2
fRF1
fRF2
fRF1
fRF2
H
L
1.5
1.5
–9
2.0
2.0
—
Noise figure
Input IP3
Isolation
NF
dB
—
H
L
–13
–13
17
18
1
IIP3
Iso
dBm
dBm
–9
—
H
L
22
—
When a
small signal
23
—
Mixer Block
Min.
—
Typ. Max. Unit Measurement condition
Item
Symbol
IDD
RF frequency
Current consumption
—
4.5
12
6.0
14
mA
When no signal
fRF1
fRF2
fRF1
fRF2
fRF1
fRF2
fRF1
fRF2
10
Power gain
Gc
dB
9
11
13
When a small signal
—
4.2
6.0
6.0
—
Noise figure
NF
IIP3
Plk
dB
—
4.2
–4.0
–3.5
—
–1.0
–0.5
–31
–31
1
Input IP3
dBm
dBm
—
–26
–26
fLO = 740MHz
fLO = 690MHz
LO to RF leak level
—
The values shown above are the specified values on the Sony’s recommended evaluation board. (When no
option pin resistor is added.)
1
Conversion from the IM3 suppression ratio for two-wave input: PRF = –30dBm (low noise amplifier block)/
–25dBm (mixer block) at fRFoffset = 100kHz.
– 2 –
CXG1082EN
Recommended Evaluation Circuit
LNA RFIN2
50Ω
LNA RFIN1
L13
L11
L14
L15
L5
L4
8
7
6
5
4
3
2
1
9
50Ω
C6
L6
10
11
12
13
14
15
16
C9
R1
LNA RFOUT
C8
CTL
50Ω
VDD1 (LNA)
MIX RFIN
L12
C7
L3
VDD2 (LO AMP)
C5
C2
C4
L8
L9
50Ω
LOIN
IFOUT
L10
L1
50Ω
C1
L7
L2
C3
VDD3 (MIX)
50Ω
L1
150nH
120nH
33nH
18nH
6.8nH
27nH
33nH
27nH
5.6nH
12nH
L11
L12
L13
L14
L15
C1
18nH
10nH
C6
C7
C8
C9
R1
18pF
L2
L3
L4
L5
L6
L7
L8
L9
L10
1000pF
100pF
56pF
22nH
5.6nH
22nH
6pF
C2
1000pF
1000pF
100pF
1000pF
C3
C4
C5
– 3 –
CXG1082EN
Example of Representative Characteristics (Ta = 25°C)
Low Noise Amplifier Block
Path RFIN1 → RFOUT
Path RFIN2 → RFOUT
Gp, NF vs. fRF
Gp, NF vs. fRF
18
17.5
17
3
18
17.5
17
3
VDD = 3V
VCTL = 0V
VDD = 3V
VCTL = 3V
Gp
2.5
2
2.5
2
Gp
16.5
16
16.5
16
15.5
15
15.5
15
1.5
1.5
NF
NF
14.5
14.5
14
14
800
1
900
1
900
820
840
860
880
800
820
840
860
880
fRF – RF frequency [MHz]
fRF – RF frequency [MHz]
Path RFIN2 → RFOUT
Path RFIN1 → RFOUT
POUT, IM3 vs. PIN
POUT, IM3 vs. PIN
20
10
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
POUT
POUT
–10
–20
–30
–40
–50
–60
–70
IM3
IM3
VDD = 3V
VCTL = 3V
fRF1 = 870MHz
fRF2 = 870.1MHz
VDD = 3V
VCTL = 0V
fRF1 = 820MHz
fRF2 = 820.1MHz
–80
–90
–80
–90
–30
–20
–10
0
10
–30
–20
–10
0
10
–40
–40
PIN – RF input power[dBm]
PIN – RF input power[dBm]
– 4 –
CXG1082EN
Mixer Block
Gc, NF vs. fRF
15
14
13
12
11
10
9
7
VDD = 3V
fLO = fRF – 130MHz
PLO = –15dBm
6.5
6
Gc
5.5
5
4.5
4
NF
8
3.5
3
7
6
2.5
2
5
800
820
840
860
880
900
fRF – RF frequency [MHz]
Gc, NF vs. PLO
Gc, NF vs. PLO
15
5.5
5.3
5.1
4.9
4.7
4.5
4.3
4.1
3.9
15
5.5
5.3
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
VDD = 3V
VDD = 3V
14 fRF1 = 870MHz
14 fRF1 = 820MHz
fRF2 = 870.1MHz
fLO = 740MHz
fRF2 = 820.1MHz
fLO = 690MHz
Gc
13
12
11
10
9
13
12
11
10
9
Gc
NF
8
8
NF
7
7
6
5
3.7
3.5
6
5
3.5
0
–20
–15
–10
–5
–20
–15
–10
–5
–25
0
–25
PLO – LO input power [dBm]
PLO – LO input power [dBm]
– 5 –
CXG1082EN
IIP3, PLK vs. PLO
IIP3, PLK vs. PLO
1
0.5
0
–25
–26
–27
–28
–29
–30
–31
–32
–33
1
0.5
0
–25
–26
–27
–28
–29
–30
–31
–32
–33
IIP3
PLK
IIP3
–0.5
–1
–0.5
–1
–1.5
–2
–1.5
–2
–2.5
–3
–2.5
–3
PLK
VDD = 3V
VDD = 3V
fRF1 = 820MHz
fRF2 = 820.1MHz
fLO = 690MHz
fRF1 = 870MHz
fRF2 = 870.1MHz
fLO = 740MHz
–3.5
–4
–34
–35
–3.5
–4
–34
–35
–20
–15
–10
–5
–20
–15
–10
–5
–25
0
–25
0
PLO – LO input power [dBm]
PLO – LO input power [dBm]
POUT, IM3 vs. PIN
POUT, IM3 vs. PIN
20
10
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
POUT
POUT
–10
–20
–30
–40
–50
–60
–70
–80
IM3
IM3
VDD = 3V
VDD = 3V
fRF1 = 820MHz
fRF2 = 820.1MHz
fLO = 690MHz
PLO = –15dBm
fRF1 = 870MHz
fRF2 = 870.1MHz
fLO = 740MHz
PLO = –15dBm
–30
–20
–10
0
10
–30
–20
–10
0
10
–40
–40
PIN – RF input power [dBm]
PIN – RF input power [dBm]
– 6 –
CXG1082EN
Example of Characteristics for Option Resistance R1 Changed (Ta = 25°C)
IDD3 (MIX) vs. R1
Mixer Block
10
VDD = 3V
8
6
4
2
1200 680 470 390 330 270
OPEN
220
R1 – Option resistance [Ω]
Gc, NF vs. R1
Gc, NF vs. R1
14
12
14
12
GC
GC
10
8
10
VDD = 3V
VDD = 3V
fRF = 870MHz
fLO = 740MHz
PLO = –15dBm
fRF = 820MHz
fLO = 690MHz
PLO = –15dBm
8
6
4
6
NF
NF
4
2
2
1200 680 470 390 330 270
1200 680 470 390 330 270
OPEN
220
OPEN
220
R1 – Option resistance [Ω]
R1 – Option resistance [Ω]
IIP3, PLK vs. R1
IIP3, PLK vs. R1
3
2
–27
–28
–29
–30
–31
–32
3
2
–27
–28
–29
–30
–31
VDD = 3V
fRF = 870MHz
fLO = 740MHz
VDD = 3V
fRF = 820MHz
fLO = 690MHz
PLO = –15dBm
IIP3
IIP3
PLO = –15dBm
1
0
1
0
PLK
PLK
–1
–2
–1
–2
OPEN
–32
220
1200 680 470 390 330 270
1200 680 470 390 330 270
OPEN
220
R1 – Option resistance [Ω]
R1 – Option resistance [Ω]
– 7 –
CXG1082EN
Recommended Evaluation Board
Front
50mm
LNA RFIN2
LNA RFIN1
LNA RFOUT
IFOUT
MIX RFIN
LO IN
CTL
VDD2
GND
VDD3
VDD1
Glass fabric-base 4-layer epoxy board (thickness: 0.2mm × 2)
GND for the whole 2nd and 3rd layers
Enlarged Diagram of Center Part
L5
L15
L6
L14
L4
L13
C9
C8
C6
L12
C7
L11
L3
C5 C4
L8
L7
L10 L9
C1
L1
L2
C3
C2
– 8 –
CXG1082EN
Package Outline
Unit: mm
16PIN VSON(PLASTIC)
0.9 MAX
0.6
3.5
0.05
S
A
S
B
2x
0.4
0.35 ± 0.1
0.2
B
S
4x
1.4
0.2
A
B
S
A-B
0.05 M S
Soldrer Plating
0.13 ± 0.025
+ 0.09
0.14
– 0.03
1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
NOTE:
TERMINAL SECTION
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SOLDER PLATING
SONY CODE
EIAJ CODE
VSON-16P-01
COPPER ALLOY
0.02 g
JEDEC CODE
– 9 –
Sony Corporation
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