CXL1502M [SONY]
CMOS-CCD Signal Processor; CMOS ， CCD信号处理器
| 型号： | CXL1502M |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS-CCD Signal Processor |
| 文件： | 总14页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL1502M
CMOS-CCD Signal Processor
For the availability of this product, please contact the sales office.
Description
30 pin SOP (Plastic)
The CXL1502M is a CMOS-CCD signal processor
designed for 8-mm video signal processing. In
combination with the 8-mm video Y/C signal
processing IC CXA1200Q, this IC configures a comb
filter for Y/C separation in recording an image,
elimination of line crawling and crosstalk in playing
back.
Features
Absolute Maximum Ratings (Ta = 25°C)
• Single power supply 5V
• Supply voltage
VDD
6
V
• Low power consumption
• Built-in peripheral circuits
• Completely adjustment free
• Built-in triple progression PLL circuit
• For PAL signals
• Operating temperature
• Storage temperature
Topr –10 to +60 °C
Tstg –55 to +150 °C
• Allowable power dissipation PD
500
mW
Recommended Operating Conditions (Ta = 25°C)
Supply voltage VDD 5 ± 5%
V
Functions
• 1H comb filter, 2H comb filter output
• Dropout compensation
• PLL circuit (triple progression)
• Clock driver
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
VCLK 0.3 to 1.0 Vp-p
(0.4Vp-p Typ.)
• Clock frequency
fCLK
4.433619 MHz
• Autobias circuit
• Input clock waveform
sine wave
• Sync tip clamp circuit
• Sample and hold circuit
• Delay time matching through output (THR)
Input Signal Amplitude
VSIG
575 mVp-p
(Max.)
Structure
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E80334-PS
CXL1502M
Y - Y D
S S V
S S V
C - C D
D D V
B G G V
A G G V
T H
Y D
A D J Y
S S V
A B N
V C O O U T
N C
S S V
S S V
S S V
D D V
N C
C L K
D D V
C C D 1
P C O U T
A D J C
V C O I N
A B P
C C D 2 - C
C C D Y
C C D 3
S S V
– 2 –
CXL1502M
Pin Description
Symbol
Pin No.
1
Description
I/O
—
I
Impedance (Ω)
VSS
GND
CCDY
CCD2-C
ADJC
CCD1
NC
2
Signal input 4 (Reverse phase signal)
Signal input 2 (Reverse phase signal)
Forward CCD bias DC output
> 100k (at no clamp)
> 100k (at no clamp)
600 to 2k
3
I
4
O
I
5
Signal input 1 (Reverse phase signal)
> 100k (at no clamp)
6
—
—
—
—
O
O
O
O
O
—
O
—
—
O
O
—
O
—
—
I
VDD
7
5V power supply
GND
VSS
8
NC
9
ABN
TH
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Reverse phase autobias DC output
THR signal output (Forward phase signal)
Gate bias (A) DC output
Gate bias (B) DC output
2H comb filter signal output
GND
2k to 200k
40 to 500
2k to 10k
2k to 10k
40 to 500
VGGA
VGGB
C-CD
VSS
Y-YD
VSS
40 to 500
1H comb filter signal output
GND
VDD
5V power supply
YD
40 to 500
600 to 2k
DOC signal output (Reverse phase signal)
Reverse phase CCD bias DC output
GND
ADJY
VSS
VCO OUT
VSS
VCO output
GND
VSS
GND
CLK
4k to 40k
Clock input
VDD
5V power supply
—
O
I
PC OUT
VCO IN
ABP
2k to 5k
Phase comparator output
VCO input
> 100k
2k to 200k
> 100k (at no clamp)
Forward phase autobias DC output
Signal input 3 (Forward phase signal)
O
I
CCD3
– 3 –
CXL1502M
– 4 –
CXL1502M
– 5 –
CXL1502M
Y - Y D
S S V
S S V
C - C D
D D V
Y D
B
A
G G V
G G V
A D J Y
T H
S S V
A B N
V C O O U T N C
S S V
S S V
S S V
D D V
N C
C L K
D D V
C C D 1
P C O U T A D J C
V C O I N
C C D 2 - C
A B P
C C D Y
C C D 3
S S V
– 6 –
CXL1502M
Notes)
1
Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an
equal value, as well as the phase difference to a precise 180°.
Also set the clock and input signal frequency accurately.
2
VIC, VIY, VID and VIT are defined as follows:
VIC, VIY, VID and VIT are input signal clamp levels. They clamps the Video signal sync tip level. They are
the pin voltages at no-input signal for pins 3, 2, 30 and 5, respectively.
VID
Input (CCD3)
30
L1502
2
3
5
Input (CCDY)
VIY
VIT
Input (CCD2-C)
VIC
Input (CCD1)
Testing of VIC, VIY, VID and VIT is executed with a voltmeter under the following SW conditions:
SW conditions
Test
point
Item
1
2
b
b
b
b
3
b
b
b
b
4
b
b
b
b
5
b
b
b
b
6
a
a
a
a
7
a
a
a
a
8
a
a
a
a
9
a
a
a
a
10 11
VIC
VIY
VID
VIT
—
—
—
—
—
—
—
—
—
—
—
—
V3
V2
V1
V4
3
4
This is the IC supply current value during clock and signal input.
GLC, GLY, GLD and GLT are output gains of C-CD, Y-YD, YD and TH pins when a 500mVp-p,
203.126kHz sine wave is simultaneously fed to CCD2-C, CCDY, CCD3 and CCD1 pins, respectively.
(Example of calculation)
C-CD pin output voltage [mVp-p]
GLC = 20 log
[dB]
500 [mVp-p]
– 7 –
CXL1502M
5
GHC, GHY, GHD and GHT are output gains of C-CD, Y-YD, YD and TH pins when a 150mVp-p,
4.437525MHz sine wave is simultaneously fed to CCD2-C, CCDY, CCD3 and CCD1 pins, respectively. Bias
at input (VBIAS1, VBIAS2, VBIAS3 and VBIAS4) is tested respectively at VID + 0.25V, VIY – 0.25V, VIC – 0.25V
and VIT – 0.25V.
(Example of calculation)
C-CD pin output voltage [mVp-p]
GHC = 20 log
[dB]
150 [mVp-p]
6
Indicates the dissipation at 4.437525MHz in relation to 203.126kHz. From the output voltage at TH, C-CD,
Y-YD and YD pins when a 150mVp-p, 203.126kHz sine wave is simultaneously fed to CCD1, CCD2-C,
CCDY and CCD3 pins, and from the output voltage at TH, C-CD, Y-YD and YD pins when a 150mVp-p,
4.437525MHz sine wave is simultaneously fed to same, calculation is made according to the following formula.
The input block bias for VBIAS1, VBIAS2, VBIAS3 and VBIAS4 is tested at VID + 0.25V, VIY – 0.25V, VIC – 0.25V
and VIT – 0.25V, respectively.
(Example of calculation)
TH pin output voltage (4.437525MHz) [mVp-p]
fT = 20 log
[dB]
TH pin output voltage (203.126kHz) [mVp-p]
7
The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure
is fed, are tested with a vector scope:
150mV
275mV
500mV
150mV
1H 64µs
CCD3 pin input waveform (the input waveform of CCD1, CCD2-C and CCDY pins is the inverted waveform
of the figure above.)
8
The noise level of output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap
mode at BPF 100kHz to 5MHz. Vn [Vrms]
The signal component is determined either by testing the output voltage (the same test system as that of
noise level) at input of 350mVp-p, 203.126kHz, or by performing calculation from the values of GLT, GLC,
GLY and GLD in accordance with the following formula. Vs [Vp-p]
(Example of VS calculation)
GLT
20
VS-T = 0.35 × 10
(VS-T: TH output voltage)
(Example of S/N ratio calculation)
VN-T (noise component) [Vrms]
VS-T (signal component) [Vp-p]
SNT = 20 log
[dB]
– 8 –
CXL1502M
9
The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. The input block bias for VBIAS1 is tested at VID + 0.5V and VIC – 0.25V.
Test value [mVp-p]
10
C-CD is calculated in accordance with the following formula from the C-CD pin output voltage when a
200mVp-p, 4.437525MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and
from the C-CD pin output voltage when a 200mVp-p, 4.441431MHz sine wave is simultaneously fed to
same. The input block bias for VBIAS1, VBIAS2, VBIAS3 and VBIAS4 is set to VID + 0.3V, VIY – 0.3V, VIC – 0.3V
and VIT – 0.3V, respectively.
C-CD pin output voltage (4.437525MHz)
C-CD = 20 log
[dB]
C-CD pin output voltage (4.441431MHz)
11
Y-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a
200mVp-p, 2.000011MHz sine wave is simultaneously fed to CCD1, CCD2-C, CCDY and CCD3 pins and
from the Y-YD pin output voltage when a 200mVp-p, 1.992198MHz sine wave is simultaneously fed to
same. The input block bias is set to the same conditions as in testing CCD.
Y-YD pin output voltage (1.992198MHz)
Y-CD = 20 log
[dB]
Y-YD pin output voltage (2.000011MHz)
CLOCK
fsc (4.433619MHz) sine wave
0.3Vp-p to 1.0Vp-p (0.4Vp-p Typ.)
– 9 –
CXL1502M
– 10 –
CXL1502M
Low frequency gain vs. Ambient temperature
High frequency gain vs. Ambient temperature
–1
–3
–4
–5
–6
–2
–3
–4
–5
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
Frequency response vs. Ambient temperature
Differential gain vs. Ambient temperature
10
8
0
–1
–2
–3
6
4
2
0
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
Chroma comb depth min. gain vs. Ambient temperature
Y comb depth min. gain vs. Ambient temperature
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
– 11 –
CXL1502M
Low frequency gain vs. Supply voltage
High frequency gain vs. Supply voltage
–1
–2
–3
–4
–5
–3
–4
–5
–6
4.75
5.00
5.25
4.75
5.00
5.25
VDD – Supply voltage [V]
VDD – Supply voltage [V]
Frequency response vs. Supply voltage
Differential gain vs. Supply voltage
10
8
0
–1
–2
–3
6
4
2
0
4.75
5.00
5.25
4.75
5.00
5.25
VDD – Supply voltage [V]
VDD – Supply voltage [V]
Chroma comb depth min. gain vs. Supply voltage
Y comb depth min. gain vs. Supply voltage
–10
–10
–20
–30
–40
–50
–20
–30
–40
–50
4.75
5.00
5.25
4.75
5.00
5.25
VDD – Supply voltage [V]
VDD – Supply voltage [V]
– 12 –
CXL1502M
Chroma comb response (C-CD output)
Y comb response (Y-YD output)
0
–10
–20
–30
–40
0
–10
–20
–30
–40
4.4285M
4.4335M
4.4385M
1.982M
1.992M
2.002M
f – Frequency [Hz]
f – Frequency [Hz]
Frequency response (TH, YD output)
0
–2
–4
–6
–8
10k
100k
1M
f – Frequency [Hz]
– 13 –
CXL1502M
Package Outline
Unit: mm
30PIN SOP (PLASTIC)
+ 0.4
2.3 – 0.15
+ 0.4
18.8 – 0.1
30
16
0.15
+ 0.2
0.1 – 0.05
15
1
+ 0.1
0.15 – 0.05
1.27
0.45 ± 0.1
0.24
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SONY CODE
EIAJ CODE
SOP-30P-L01
SOLDER PLATING
42 ALLOY
SOP030-P-0375
JEDEC CODE
PACKAGE MASS
0.7g
– 14 –
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