CXP82860Q [SONY]
8-Bit Microcontroller ; 8位微控制器\n
| 型号： | CXP82860Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | 8-Bit Microcontroller
|
| 文件： | 总22页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP82832/82840/82852/82860
CMOS 8-bit Single Chip Microcomputer
Description
100 pin QFP (Plastic)
The CXP82832/82840/82852/82860 is a CMOS 8-
bit single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time base timer, capture timer/counter, fluorescent
display panel controller/driver, remote control
reception circuit, and PWM output besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O port.
The CXP82832/82840/82852/82860 also provides
sleep/stop function that enables lower power
consumption.
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
• Incorporated ROM capacity
400ns at 10MHz operation
(122µs at 32kHz operation)
32K bytes (CXP82832)
40K bytes (CXP82840)
52K bytes (CXP82852)
60K bytes (CXP82860)
• Incorporated RAM capacity
• Peripheral functions
— A/D converter
1536 bytes (including fluorescent display area)
8 bits, 8 channels, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
— Timers
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronized type, 1 channel
8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel.
High voltage drive output port of 56 pins (40V)
Maximum of 640 segments display possible
Display timing number of 1 to 20
Dimmer function
Incorporated pull-down resistor (Mask option)
Hardware key scan function (Maximum of 16 × 8 key matrix
supportable)
— Remote control reception circuit
— PWM output
8-bit pulse measurement counter, 6-stage FIFO
14 bits, 1 channel
• Interruption
• Standby mode
16 factors, 15 vectors, multi-interruption possible
SLEEP/STOP
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP82800 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94Y08B74
CXP82832/82840/82852/82860
A T R P O B T R P O C T R P O D T R P O E T R P O F T R P O G T R P O H T R P O
S S V
D D V
T R S
A L X T
A L E X T
T X
X T E
I M / N 3 T I N
2 T I N
1 T I N
0 T I N
R E L L R O N T C T O
R E R T U N P I
F
R E A V
S S A V
– 2 –
CXP82832/82840/82852/82860
Pin Assignment (Top View)
99 98
96 95 94 93 92 91
90 89 88 87 86 85 84 83 82 81
100
97
1
2
G1/A1
G0/A0
NC
A21
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A22
3
A23
4
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5
PH7/A24
PH6/A25
PH5/A26
PH4/A27
PH3/A28
PH2/A29
PH1/A30
PH0/A31
PG7/A32
PG6/A33
PG5/A34
PG4/A35
PG3/A36
PG2/A37
PG1/A38
PG0/A39
PF7/A40
PF6/A41
PF5/A42
PF4/A43
PF3/A44
PF2/A45
PF1/A46
PF0/A47
PD7/A48
PD6/A49
PD5/A50
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PE6/PWM
PE7/TO/ADJ
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
AVREF
PA0/AN0
PA1/AN1
31
32 33
34
35
36 37 38
39
40 41 42
43 44 45 46
47
48 49 50
Note) 1. NC (Pin 3) must be connected to VDD.
2. VDD (Pins 44 and 89) must be connected to VDD.
– 3 –
CXP82832/82840/82852/82860
Pin Description
Pin code
I/O
Functions
(Port A)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistor can be set
through the software in a unit of
4 bits.
PA0/AN0
to
PA7/AN7
Analog inputs to A/D converter.
(8 pins)
I/O/
Analog input
(8pins)
Capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
I/O/Input
I/O/Input
I/O/I/O
(Port B)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistor can be set
through the software in a unit of
4 bits.
Serial data input (CH0).
I/O/Input
I/O/Output
I/O/I/O
Serial data output (CH0).
Serial clock I/O (CH1).
PB4/SO0
PB5/SCK1
PB6/SI1
(8 pins)
Serial data input (CH1).
I/O/Input
I/O/Output
Serial data output (CH1).
PB7/SO1
(Port C)
8-bit I/O port. I/O can be set in a
unit of single bits. Can drive
12mA sync current.
Incorporation of the pull-up
resistor can be set through the
software in a unit of 4 bits.
(8 pins)
Serves as key return inputs when
operating key scan with fluorescent
display panel (FDP) segment signal.
(8 pins)
PC0/KR0
to
PC7/KR7
I/O/Input
PD0/A55
to
PD7/A48
(Port D)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
Output/Output
PE0/INT0/
EC0
Input/Input/Input
External event inputs
for timer/counter.
(2 pins)
Inputs for
external
interruption
request.
(4 pins)
PE1/INT1/
EC1
Input/Input/Input
Input/Input
PE2/INT2
(Port E)
Non-maskable
interruption request input.
PE3/INT3/
NMI
8-bit port. Lower 6 bits are for
inputs; upper 2 bits are for
outputs.
Input/Input/Input
Remote control reception circuit input.
PE4/RMC
PE5
Input/Input
Input
(8 pins)
14-bit PWM output.
PE6/PWM
Output/Output
Output for the 16-bit timer/counter
rectangular waves, and 32kHz
oscillation frequency division.
Output/Output/
Output
PE7/TO/ADJ
(Port F)
8-bit output port.
(8pins)
PF0/A47
to
PF7/A40
FDP segment signal (anode
connection) outputs.
Output/Output
– 4 –
CXP82832/82840/82852/82860
Pin code
I/O
Functions
FDP segment signal (anode
PG0/A39
to
PG7/A32
(Port G)
8-bit output port.
(8 pins)
Output/Output
connection) outputs.
(8 pins)
PH0/A31
to
PH7/A24
(Port H)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
Output/Output
Output
FDP segment signal (anode connection) outputs.
(8 pins)
A16 to A23
G0/A0
to
G15/A15
Outputs for FDP timing signals (grid connection)/segment signals (anode
connection).
(16 pins)
Output/Output
FDP voltage supply when incorporated pull-down (PD) resistor is set by
mask option.
VFDP
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
EXTAL
XTAL
TEX
Input
Output
Input
Crystal connectors for 32kHz timer/counter clock oscillation. For usage
as event input, input to TEX, and open TX.
TX
Output
Input
Low-level active, system reset
NC. Under normal operation, connect to VDD.
Reference voltage input for A/D converter.
A/D converter GND.
RST
NC
Input
AVREF
AVSS
VDD
VCC supply.
VSS
GND.
– 5 –
CXP82832/82840/82852/82860
I/O Circuit Format for Pins
Pin
When reset
Circuit format
Port A
Pull-up resistor
"0" when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
"0" when reset
IP
Input protection circuit
Hi-Z
Data bus
RD (Port A)
Port A input selection
"0" when reset
Input multiplexer
A/D converter
8 pins
Pull-up transistor approx. 100kΩ
Port B
Pull-up resistor
"0" when reset
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
"0" when reset
IP
Hi-Z
Schmitt input
Data bus
RD (Port B)
CINT
CS0
SI0
SI1
Pull-up transistor approx. 100kΩ
4 pins
Port B
Pull-up resistor
"0" when reset
SCK OUT
Serial clock output enable
Port B output selection
"0" when reset
PB2/SCK0
PB5/SCK1
Hi-Z
Port B data
IP
Port B direction
"0" when reset
Schmitt input
Data
bus
RD (Port B)
Pull-up transistor approx. 100kΩ
SCK in
2 pins
– 6 –
CXP82832/82840/82852/82860
Pin
When reset
Circuit format
Port B
Pull-up resistor
"0" when reset
SO
Serial data output enable
Port B output selection
"0" when reset
PB4/SO0
PB7/SO1
Hi-Z
Port B data
IP
Port B direction
"0" when reset
Data
bus
RD (Port B)
Pull-up transistor approx. 100kΩ
2 pins
Port C
2
Pull-up resistor
"0" when reset
Port C data
PC0/KR0
to
PC7/KR7
Hi-Z
1
Port C direction
"0" when reset
IP
Data bus
RD (Port C)
1
2
Large current 12mA
Pull-up transistor approx. 100kΩ
8 pins
Key input signal
Port E
EC0/INT0
EC1/INT1
INT2
INT3/NM1
RMC
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
Schmitt input
IP
Hi-Z
Hi-Z
Data bus
RD (Port E)
5 pins
Port E
PE5
Data bus
IP
1 pin
RD (Port E)
– 7 –
CXP82832/82840/82852/82860
Pin
When reset
Circuit format
Port E
PWM
Port E output selection
"0" when reset
PE6/PWM
High level
Port E data
Output enable
"1" when reset
Data bus
1 pin
RD (Port E)
Port E
Internal reset signal
MPX
Port E data
"1" when reset
00
01
10
11
TO
High level
(with approx.
150kΩ
1
2
ADJ16K
2
ADJ2K
PE7/TO/ADJ
Port E output selection (upper)
resistor when
reset)
Port E output selection (lower)
"00" when reset
1
ADJ signal is a frequency dividing
output for 32kHz oscillation frequency adjustment.
ADJ2 can be used for buzzer output.
TO output enable
2
Pull-up transistor approx. 150kΩ
1 pin
Port D
Port F
PD0/A55
to
Segment output data
PD7/A48
PF0/A47
to
Port G
Port H
Output selection control signal
("0" when reset)
Hi-Z or Low
level (when
PD resistor is
connected)
PF7/A40
PG0/A39
to
PG7/A32
PH0/A31
to
OP
Mask
option
Port D, F, G and H data
Pull-down resistor
"0" when reset
VFDP
Data bus
High voltage drive transistor
PH7/A24
RD (Ports D, F, G and H)
32 pins
– 8 –
CXP82832/82840/82852/82860
When reset
Pin
Circuit format
Segment output data
Hi-Z or
Output selection control signal
("0" when reset)
A16 to A23
Low level
(when PD
resistor is
connected)
Mask option
OP
Pull-down resistor
VFDP
High voltage drive transistor
8 pins
Segment output data
Timing output data
Hi-Z or
G0/A0
to
G15/A15
Output selection control signal
("0" when reset)
Low level
(when PD
resistor is
connected)
Mask option
OP
Pull-down resistor
VFDP
High voltage drive transistor
16 pins
• Diagram shows circuit
composition during
oscillation.
EXTAL
XTAL
IP
EXTAL
IP
Oscillation
• Feedback resistor is
removed and XTAL
becomes High level
during stop.
XTAL
2 pins
• Diagram shows circuit
composition during
oscillation.
TEX
TX
TEX
IP
IP
• When the operation of the
oscillation circuit is
Oscillation
stopped by the software,
the feedback resistor is
removed, and TEX and
TX become Low level and
High level respectively.
TX
2 pins
Pull-up resistor
RST
1 pin
Low level
Mask option
OP
IP
Schmitt input
– 9 –
CXP82832/82840/82852/82860
Absolute Maximum Ratings
(Vss = 0V reference)
Remarks
Item
Symbol
Rating
Unit
V
Supply voltage
VDD
–0.3 to +7.0
–0.3 to +0.3
A/D converter GND voltage
AVSS
V
A/D converter reference
voltage
1
AVREF
V
–0.3 to +7.0
1
–40 2 to +7.0
–0.3 to +7.0
–0.3 to +7.0
–40 2 to +7.0
–5
FDP display supply voltage
Input voltage
VFDP
VIN
V
V
1
1
Output voltage
VOUT
VOD
IOH
V
1
Display output voltage
V
All pins excluding outputs 3 (value per pin)
Display outputs A20 to A55 (value per pin)
mA
mA
IODH1
–15
High level output current
Display outputs G0/A0 to G15/A15, and
A16 to A19 (value per pin)
IODH2
mA
–50
Total for all pins excluding display outputs
Total for all display outputs
Port (value per pin)
∑IOH
∑IODH
IOL
mA
mA
mA
mA
mA
°C
–30
–120
High level total output
current
15
Low level output current
4
Large current port (value per pin)
IOLC
∑IOL
Topr
Tstg
PD
20
Total for all output pins
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
1
100
–20 to +75
–55 to +150
600
°C
mW
VIN, VOUT, VOD and AVREF must not exceed VDD + 0.3V.
VFDP and VOD must not exceed VDD – 40V.
2
3
4
Specifies output current of general-purpose I/O ports.
The large current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 10 –
CXP82832/82840/82852/82860
Recommended Operating Conditions
(Vss = 0V reference)
Remarks
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Guaranteed operation range during
high-speed mode
(1/2 and 1/4 frequency dividing clock)
Guaranteed operation range low-speed
mode or SLEEP mode
(1/16 frequency dividing clock)
5.5
5.5
V
V
3.5
2.7
VDD
Supply voltage
Guaranteed operation range with TEX
clock
5.5
VDD
V
V
Guaranteed data hold range during STOP
2.5
0.7VDD
0.8VDD
VDD – 0.4
0
1
VIH
High level input
voltage
2
VDD
V
Hysteresis input
VIHS
VIHEX
VIL
3
VDD + 0.3
0.3VDD
0.2VDD
0.4
V
EXTAL
1
V
Low level input
voltage
2
V
Hysteresis input
VILS
VILEX
Topr
0
3
V
EXTAL
–0.3
Operating temperature
+75
°C
–20
1
Value for each pin of normal input port (PA, PB4, PB7, PC).
2
3
Value of the following pins: RST, CINT, CS0, SCK0, SCK1, SI0, SI1, EC0/INT0, EC1/INT1, INT2,
INT3/NMI, RMC.
Specifies only during external clock input.
– 11 –
CXP82832/82840/82852/82860
Electrical Characteristics
DC Characteristics
(Ta = –20 to +75°C, VSS = 0V reference)
Item
Symbol
Pins
Conditions
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V
Min.
4.0
Typ.
Max.
Unit
V
High level
output current
VOH
3.5
V
PA, PB, PC,
PE6, PE7
0.4
0.6
V
Low level
output current
V
VOL
PC
1.5
V
0.5
–0.5
0.1
40
µA
µA
µA
µA
µA
µA
µA
mA
IIHE
IILE
IIHT
IILT
IILR
EXTAL
–40
10
TEX
–0.1
–1.5
–10
–400
–50
Input current
1
RST
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
2
IIL
PA to PC
–3.3
–8
A20 to A55
VDD = 4.5V
VOH = VDD –2.5V
Display output
current
G0/A0 to
G15/A15
A16 to A19
IOH
–30
mA
µA
Open drain
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
G0/A0 to
G15/A15
A16 to A55
output leakage
current (P-CH
Tr off state)
ILOL
–20
G0/A0 to
G15/A15
A16 to A55
VDD = 5V
VOD – VFDP = 30V
Pull-down
resistor
RL
IIZ
60
100
270
±10
kΩ
3
2
PA to PC
VDD = 5.5V
VI = 0, 5.5V
I/O leakage
current
PE0 to PE5
µA
1
RST
– 12 –
CXP82832/82840/82852/82860
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
mA
High speed mode operation
(1/2 frequency dividing clock)
23
(19)
50
(40)
IDD1
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
44
(37)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
100
8
µA
IDD2
Power supply
SLEEP mode
VDD
2.3
(2.1)
4
current
IDDS1
mA
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDDS2
IDDS3
10
10
30
10
µA
µA
STOP mode
VDD = 5.5V, termination of 10MHz
and 32kHz crystal oscillation
PA to PC,
PE0 to 5,
XTAL,
Clock 1MHz
0V for all pins excluding
measured pins
Input
capacity
20
pF
CIN
EXTAL,
TEX,RST
1
RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
2
PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no
resistor has been selected.
3
4
When incorporated pull-down resistor has been selected through mask option.
When all pins are open.
Note) The values in paren thesis are for the CXP82832 and CXP82840.
– 13 –
CXP82832/82840/82852/82860
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Conditions
Fig. 1, Fig. 2
Min.
1
Typ.
Max.
10
Unit
XTAL
EXTAL
System clock frequency
fC
MHz
t
XL
Fig. 1, Fig. 2
External clock drive
System clock input pulse width
EXTAL
EXTAL
ns
ns
ns
ms
37.5
tXH
System clock input rise time,
fall time
t
CR
CF
Fig. 1, Fig. 2
External clock drive
1
tsys + 50
200
20
t
Event count input clock
pulse width
t
EH
EL
EC0,
EC1
Fig. 3
Fig. 3
t
Event count input clock
rise time, fall time
t
ER
EF
EC0,
EC1
t
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
TX
System clock frequency
fC
kHz
32.768
Event count input
pulse width
t
TL
TEX
TEX
Fig. 3
Fig. 3
µs
10
tTH
Event count input rise time,
fall time
tTR
TF
ms
20
t
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock registor (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
Fig. 1. Clock timing
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
32kHz clock applied condition
Crystal oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C2
C1
Fig. 3. Event count clock timing
0.8VDD
0.2VDD
TEX
EC0
EC1
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
– 14 –
CXP82832/82840/82852/82860
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
ns
CS0 ↓ → SCK0
Chip select transfer mode
(SCK0 = output mode)
t
t
t
DCSK
DCSKF
DCSO
tsys + 200
SCK0
delay time
CS0 ↑ → SCK0
float delay time
Chip select transfer mode
(SCK0 = output mode)
ns
ns
ns
tsys + 200
tsys + 200
tsys + 200
SCK0
SO0
CS0 ↓ → SO0
Chip select transfer mode
Chip select transfer mode
delay time
CS0 ↑ → SO0
float delay time
t
t
DCSOF
WHCS
SO0
CS0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsys + 200
CS0 High level width
Chip select transfer mode
Input mode
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
SCK0 cycle time
t
KCY
SCK0
SCK0
SI0
Output mode
Input mode
SCK0
t
t
KH
KL
High, Low level width
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SI0 input set-up time
t
t
t
SIK
(for SCK0 ↑)
200
tsys + 200
100
SI0 input hold time
KSI
SI0
(for SCK0 ↑)
tsys + 200
100
SCK0 ↓ → SO0
KSO
SO0
delay time
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock registor (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 15 –
CXP82832/82840/82852/82860
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tSIK
tKSI
0.8VDD
0.2VDD
Input data
SI0
tDCSO
tKSO
tDCSOF
0.8VDD
0.2VDD
Output data
SO0
– 16 –
CXP82832/82840/82852/82860
Serial transfer (CH1)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
SCK1
tKCY
Ouput mode
16000/fc
400
Input mode
SCK1
t
KH
KL
SCK1
SI1
High, Low level width
t
Ouput mode
8000/fc – 50
100
SCK1 input mode
SCK1 ouput mode
SCK1 input mode
SCK1 ouput mode
SCK1 input mode
SCK1 ouput mode
SI1 input set-up time
(for SCK1 ↑)
t
t
t
SIK
200
200
SI1 input hold time
(for SCK1 ↑)
SI1
KSI
100
200
100
SCK1 ↓ → SO1 delay time
SO1
KSO
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
0.8VDD
0.2VDD
SCK1
tSIK
tKSI
0.8VDD
0.2VDD
Input data
SI1
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 17 –
CXP82832/82840/82852/82860
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference)
Item
Resolution
Symbol
Pin
Condition
Min.
Typ.
Max.
8
Unit
Bits
LSB
±3
Linearity error
Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V
Zero transition
voltage
1
VZT
–10
10
70
mV
mV
Full-scale
transition voltage
2
VFT
4910
4970
5030
3
t
CONV
SAMP
160/fADC
12/fADC
µs
µs
V
Conversion time
Sampling time
3
t
AVREF
VREF
VIAN
IREF
Reference input voltage
Analog input voltage
VDD – 0.5
0
VDD
AVREF
1.0
AN0 to AN7
V
0.6
mA
Operation mode
SLEEP mode
STOP mode
32kHz operation mode
AVREF current
AVREF
IREFS
10
µA
Fig. 6. Definition of A/D converter terms
FFH
FEH
1
VZT: Value at which the digital conversion value changes
from 00H to 01H and vice versa.
2
3
VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
fADC indicates the below values due to the contents of bit 6
(CKS) of A/Dcontrol register (ADC: 00F9H) and bits 7 (PCK1)
and 6 (PCK0) of clock control register (CLC: 00FEH).
Linearity error
01H
00H
CKS
VZT
VFT
0 (φ/2 selection)
1 (φ selection)
Analog input
PCK1, PCK0
fADC = fC/2
fADC = fC/4
fADC = fC/16
00 (φ = fEX/2)
fADC = fC
01 (φ = fEX/4)
11 (φ = fEX/16)
fADC = fC/2
fADC = fC/8
– 18 –
CXP82832/82840/82852/82860
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
INT0
Condition
Min.
Max.
Unit
External interruption
High, Low level width
t
IH
IL
INT1
INT2
NMI/INT3
1
µs
t
Reset input Low level width
32/fc
µs
tRSL
RST
Fig. 7. Interruption input timing
tIH
tIL
0.8VDD
INT0
0.2VDD
INT1
INT2
tIL
tIH
NMI/INT3
(NMI specifies only for the
falling edge)
Fig. 8. RST input timing
tRSL
RST
0.2VDD
– 19 –
CXP82832/82840/82852/82860
Appendix
Fig. 9. Recommended oscillation circuit
(i) Main clock
(ii) Main clock
EXTAL
(iii) Sub clock
EXTAL
XTAL
XTAL
Rd
TEX
TX
Rd
Rd
C1
C2
C2
C1
C1 C2
Circuit
example
Manufacturer
Model
fc (MHz)
C1 (pF)
C2 (pF)
Rd (Ω)
4.19
8.00
CSA4.19MG
CSA8.00MTZ
CSA10.0MTZ
CST4.19MGW
CST8.00MTW
CST10.0MTW
(i)
MURATA
MFG
CO., LTD.
10.00
30
30
0
4.19
8.00
(ii)
10.00
4.19
RIVER
8.00
0
ELETEC
CO., LTD
HC-49/U03
12
27
12
27
10.00
4.19
(i)
8.00
HC-49/U (-S)
P3
0
KINSEKI
LTD.
10.00
32.768kHz
20
50
20
22
(iii)
1M
Models marked with an asterisk ( ) have the built-in ground capacitance (C1, C2).
Mask option table
Content
Item
Reset pin pull-up resistor
High voltage drive output port pull-down resistor
Existent
Existent
Non-existent
Non-existent
– 20 –
CXP82832/82840/82852/82860
Characteristics Curve
CXP82832/82840
IDD vs. VDD
(fc = 10MHz, Ta = 25°C, Typical)
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
1/2 dividing mode
20.0
10.0
1/4 dividing mode
20
15
10
5
1/2 dividing mode
5.0
1/16 dividing mode
SLEEP mode
1.0
0.5
32kHz mode
(instruction)
1/4 dividing mode
0.1
(100µA)
0.05
(50µA)
32kHz
SLEEP mode
1/16 dividing mode
SLEEP mode
0.01
(10µA)
2
3
4
5
6
7
0
5
10
15
fc – System clock [MHz]
VDD – Supply voltage [V]
CXP82852/82860
IDD vs. VDD
IDD vs. fc
(fc = 10MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
1/2 dividing mode
20.0
10.0
1/4 dividing mode
1/2 dividing mode
20
15
10
5
5.0
1/16 dividing mode
SLEEP mode
1.0
0.5
1/4 dividing mode
32kHz mode
(instruction)
0.1
(100µA)
0.05
(50µA)
32kHz
SLEEP mode
1/16 dividing mode
SLEEP mode
0.01
(10µA)
2
3
4
5
6
7
0
5
10
15
fc – System clock [MHz]
VDD – Supply voltage [V]
– 21 –
CXP82832/82840/82852/82860
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12
M
0.15
0° to 15°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
SONY CODE
QFP100-P-1420-A
EIAJ CODE
LEAD MATERIAL
COPPER / 42 ALLOY
1.4g
PACKAGE WEIGHT
JEDEC CODE
– 22 –
相关型号：
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