LCX009AK [SONY]
1.8cm (0.7-inch) NTSC/PAL Color LCD Panel; 1.8厘米（ 0.7英寸）的NTSC / PAL彩色液晶面板
| 型号： | LCX009AK |
| 厂家： | 
SONY CORPORATION |
| 描述： | 1.8cm (0.7-inch) NTSC/PAL Color LCD Panel |
| 文件： | 总22页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCX009AK
1.8cm (0.7-inch) NTSC/PAL Color LCD Panel
For the availability of this product, please contact the sales office.
Description
The LCX009AK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by the polycrystalline
silicon super thin film transistors with built-in
peripheral driving circuit. This panel provides full-
color representation in NTSC/PAL mode. RGB dots
are arranged in a delta pattern featuring high picture
quality of no fixed color patterns, which is inherent in
vertical stripes and mosaic pattern arrangements.
Features
• The number of active dots: 180,000 (0.7-inch; 1.8cm in diagonal)
• Horizontal resolution: 400 TV lines
• High optical transmittance: 3.5% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible)
• High quality picture representation with RGB delta arranged color filters
• Full-color representation
• NTSC/PAL compatible
• Right/left inverse display function
Element Structure
• Dots
Total dots
: 827 (H) × 228 (V) = 188,556
: 800 (H) × 225 (V) = 180,000
Active dots
• Built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94212C64-PS
LCX009AK
Block Diagram
13
6
12 11 10
9
8
7
5
4
3
2
1
15 14
16
H Level
Shifter
H Shift Register
V Level
Shifter
CS
LC
COM
Pad
– 2 –
LCX009AK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
• V driver supply voltage
• H driver input pin voltage
HVDD
–1.0 to +17
–1.0 to +17
–1.0 to +17
V
V
V
VVDD
HST, HCK1, HCK2
RGT
• V driver input pin voltage
VST, VCK1, VCK2
CLR, EN
–1.0 to +17
V
• Video signal input pin voltage GREEN, RED, BLUE –1.0 to +15
V
°C
°C
• Operating temperature
• Storage temperature
Topr
Tstg
–10 to +70
–30 to +85
Operating Conditions (Vss = 0V)
Supply voltage
HVDD
VVDD
13.5 ± 0.5
13.5 ± 0.5
V
V
Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin
3.0V or more
Pin Description
Pin
Pin
No.
Symbol
No.
Description
Symbol
Description
Drive direction pulse for H shift
register (H: normal, L: reverse)
1
2
3
4
5
6
7
8
COM
GREEN
RED
Common voltage of panel
Video signal (G) to panel
Video signal (R) to panel
Video signal (B) to panel
Power supply for H driver
9
RGT
Improvement pulse
for uniformity
10
11
12
13
14
15
16
CLR
EN
Enable pulse for gate selection
Clock pulse for
V shift register drive
BLUE
HVDD
HCK1
HCK2
HST
VCK1
VCK2
VST
Vss
Clock pulse for
V shift register drive
Clock pulse for
H shift register drive
Start pulse for
V shift register drive
Clock pulse for
H shift register drive
GND (H, V drivers)
Start pulse for
H shift register drive
VVDD
Power supply for V driver
– 3 –
LCX009AK
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is
shown below. (The resistor value: typ.)
(1) Video signal input
From H driver
HVDD
Input
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Level conversion
circuit
(2-phase input)
250Ω
HCK1
250Ω
HCK2
(3) HST
HVDD
250Ω
250Ω
Level conversion
circuit
Input
(single-phase input)
(4) RGT
HVDD
2.5kΩ
2.5kΩ
Level conversion
circuit
Input
(single-phase input)
(5) VCK1, VCK2
VVDD
2.5kΩ
2.5kΩ
Level conversion
circuit
VCK1
VCK2
(2-phase input)
1kΩ
1kΩ
(6) VST, CLR, EN
VVDD
2.5kΩ
2.5kΩ
Level conversion
circuit
Input
(single-phase input)
(7) COM
Input
LC
1MΩ
– 4 –
LCX009AK
Level Conversion Circuit
The LCX009AK has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit
voltage is stepped up to 13.5V. This level conversion circuit meets the specifications of a 3.0V to 5.0V power
supply of the externally-driven IC mainly. However, this circuit can operate even with a 12V power supply of
the IC.
1. I/O characteristics of level conversion circuit
HVDD
(For a single-phase input unit)
Example of single-phase
I/O characteristics
An example of the I/O voltage characteristics of a
level conversion circuit is shown in the figure to the
right. The input voltage value that becomes half the
output voltage (after voltage conversion) is defined
as Vth.
HVDD
2
The Vth value varies depending on the HVDD and
VVDD voltages.
Vth
Input voltage [V]
The Vth values under standard conditions are
indicated in the table below. (HST, VST, EN, CLR, and RGT in the case of a single-phase input)
HVDD = VVDD = 13.5V
Item
Symbol
Vth
Min.
0.35
Typ.
1.50
Max. Unit
2.70
Vth voltage of circuit
V
(For a differential input unit)
An example of I/O voltage characteristics of a
level conversion circuit for a differential input is
shown in the figure to the right. Although the
characteristics, including those of the Vth voltage,
are basically the same as those for a single-
phased input, the two-phased input phase is
defined. (Refer to clock timing conditions.)
HVDD
Example of differential
I/O characteristics
HVDD
2
2. Current characteristics at the input pin of level
conversion circuit
Vth
Input voltage [V]
VDD
A slight pull-in current is generated at the input
pin of the level conversion circuit. (The equivalent
circuit diagram is shown to the right.) The current
volume increases as the voltage at the input pin
decreases, and is maximized when the pin is
grounded.) (Electrical characteristics are defined
by the grounded input.)
Output
Input pin voltage [V]
0
10
0
HCK1
input
HCK2
input
Pull-in current
characteristics at the
input pin
Max. value
Level conversion equivalent circuit
– 5 –
LCX009AK
Input Signals
1. Input signal voltage conditions (Vss = 0V)
Item
Symbol
Min.
–0.3
Typ.
0.0
5.0
0.0
5.0
6.0
Max.
0.3
Unit
V
(Low)
(High)
(Low)
(High)
VHIL
VHIH
VVIL
VVIH
VVC
Vsig
H driver input voltage
3.0
5.5
V
–0.3
0.3
V
V driver input voltage
3.0
5.5
V
5.8
6.2
V
Video signal center voltage
1
VVC – 4.5
VVC + 4.5
V
Video signal input range
Vcom
VVC – 0.55 VVC – 0.40 VVC – 0.25
V
Common voltage of panel
1
Video input signal should be symmetrical to VVC.
2. Clock timing conditions (Ta = 25°C)
Item
Symbol
trHst
Min.
Typ.
Max.
30
Unit
Hst rise time
Hst fall time
HST
tfHst
30
Hst data set-up time
Hst data hold time
Hckn 2 rise time
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trClr
–100
–200
60
100
–50
30
–120
Hckn 2 fall time
HCK
30
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Clr rise time
–15
–15
0
0
15
ns
15
100
100
3600
2050
100
100
50
Clr fall time
CLR
tfClr
Clr pulse width
twClr
3400
1850
3500
1950
Clr fall to Hst rise time
Vst rise time
toHst
trVst
Vst fall time
VST
tfVst
Vst data set-up time
Vst data hold time
Vckn 2 rise time
tdVst
–50
–50
32
µs
ns
thVst
–32
–20
100
100
20
trVckn
tfVckn
to1Vck
to2Vck
trEn
2
Vckn fall time
VCK
Vck1 fall to Vck2 rise time
–20
–20
0
0
Vck1 rise to Vck2 fall time
En rise time
20
100
100
20
En fall time
EN
tfEn
Vck2 rise to En fall time
tdVck2
tdVck1
–20
–20
0
0
Vck1 rise to En rise time
20
2
Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 2.75MHz, fVckn = 7.81kHz)
– 6 –
LCX009AK
<Horizontal Shift Register Driving Waveform>
Item
Symbol
trHst
Waveform
Conditions
2
90%
90%
Hckn
Hst rise time
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hst
10%
50%
10%
tfHst
Hst fall time
tfHst
trHst
3
HST
HCK
CLR
50%
Hst data set-up time
tdHst
Hst
2
Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hck1
50%
50%
Hst data hold time
thHst
tdHst
thHst
90%
10%
2
Hckn
90%
10%
Hckn*2 rise time
Hckn*2 fall time
trHckn
tfHckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 60ns
thHst = –120ns
2
Hckn
trHckn
tfHckn
3
50%
50%
Hck1 fall to
Hck2 rise time
Hck1
to1Hck
to2Hck
tdHst = 60ns
thHst = –120ns
50%
50%
Hck2
Clr
Hck1 rise to
Hck2 fall time
to2Hck
to1Hck
90%
90%
2
Clr rise time
Clr fall time
trClr
tfClr
Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
10%
10%
trClr
tfClr
Hst
Clr
50%
Clr pulse width
twClr
toHst
2
Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
50%
50%
Clr fall to
Hst rise time
twClr
toHst
– 7 –
LCX009AK
<Vertical Shift Register Driving Waveform>
Item
Symbol
Waveform
Conditions
2
90%
90%
Vckn
Vst rise time
trVst
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
Vst
10%
50%
10%
50%
Vst fall time
tfVst
trVst
tfVst
3
VST
VCK
EN
Vst data set-up time
tdVst
Vst
2
50%
50%
Vckn
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
Vck1
Vst data hold time
thVst
tdVst
thVst
90%
2
Vckn
90%
10%
Vckn*2 rise time
Vckn*2 fall time
trVckn
tfVckn
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
10%
Vckn
trVckn
tfVckn
3
50%
50%
Vck1 fall to
Vck2 rise time
Vck1
to1Vck
to2Vck
tdVst = 32µs
thVst = –32µs
50%
50%
Vck2
Vck1 rise to
Vck2 fall time
to2Vck
to1Vck
90%
90%
2
En rise time
En fall time
trEn
tfEn
Vckn
10% 10%
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
En
tfEn
trEn
3
50%
50%
Vck2 rise to
En fall time
Vck2
tdVck2
tdVck1
2
Vckn
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
50%
50%
Vck1 rise to
En rise time
En
tdVck2
tdVck1
3
Definitions: The right-pointing arrow (
The left-pointing arrow (
) means +.
) means –.
The black dot at an arrow (
) indicates the start of measurement.
– 8 –
LCX009AK
Electrical Characteristics
(Ta = 25°C, HVDD = 13.5V, VVDD = 13.5V)
1. Horizontal drivers
Item
Input pin capacitance Hckn
Hst
Symbol
CHckn
CHst
Min.
Typ.
5
Max.
10
Unit
pF
Condition
5
10
pF
Input pin current
Hck1
Hck2
Hst
IHck1
IHck2
IHst
–200
–500
–300
–100
–60
–260
–100
–15
45
µA
µA
µA
µA
pF
Hck1 = GND
Hck2 = GND
Hst = GND
Rgt = GND
Rgt
IRgt
Video signal input pin capacitance Csig
60
4
Current consumption
IH
3
mA
Hckn: Hck1, Hck2 (2.75MHz)
2. Vertical drivers
Item
Input pin capacitance Vckn
Vst
Symbol
CVckn
CVst
Min.
Typ.
5
Max.
10
Unit
pF
Condition
5
10
pF
Input pin current
Vck1
Vck2
IVck1
IVck2
–100
–400
–30
–200
µA
µA
Vck1 = GND
Vck2 = GND
Vst
En
Clr
IVst,
IEn,
IClr
–100
–15
400
µA
µA
Vst, En, Clr=GND
Current consumption
IV
1000
Vckn: Vck1, Vck2 (7.87kHz)
3. Total power consumption of the panel
Item
Symbol
Min.
Typ.
Max. Unit
70 mW
Total power consumption of the panel (NTSC) PWR
45
4. COM input resistance
Item
Symbol
Rcom
Min.
0.5
Typ.
1
Max. Unit
COM – Vss input resistance
MΩ
– 9 –
LCX009AK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Measurement
method
Max.
Unit
Item
Symbol
CR25
Min.
Typ.
80
80
200
200
3.5
—
—
25°C
60°C
Contrast ratio
—
%
1
2
CR60
T
Optical transmittance
R
2.7
—
0.560
0.300
0.275
0.541
0.120
0.040
1.1
0.630
0.345
0.310
0.595
0.148
0.088
1.6
0.670
0.390
0.347
0.650
0.187
0.122
2.2
X
Y
Rx
Ry
X
Gx
CIE
standards
Chromaticity
G
B
3
Y
Gy
X
Bx
Y
By
25°C
60°C
25°C
60°C
25°C
60°C
R vs. G
B vs. G
0°C
V90-25
V90-60
V50-25
V50-60
V10-25
V10-60
V50RG
V50BG
ton0
ton25
toff0
toff25
F
V90
V50
V10
1.0
1.3
2.1
1.5
2.0
2.5
V – T
characteristics
4
V
1.4
1.8
2.4
2.2
2.7
3.2
2.1
2.5
3.1
—
–0.10
0.10
25
–0.25
0.45
100
40
Half tone color
5
6
V
reproduction range
—
—
ON time
—
8
25°C
0°C
Response time
Flicker
ms
—
65
150
60
OFF time
—
20
25°C
60°C
60min.
7
8
9
—
—
–40
20
dB
s
Image retention time
—
—
YT60
Vcomopt
Optimum Vcom voltage
5.45
5.60
5.75
V
– 10 –
LCX009AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 13.5V, VVDD = 13.5V
VVC = 6.0V, Vcom = 5.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) RGB input signal voltage (Vsig)
Vsig = 6 ± VAC (V)
(VAC: signal amplitude)
Measurement system Ι
Luminance
Meter
Measurement
Equipment
Back light: color temperature 6500K, +0.004uV (25°C)
Back light spectrum (reference) is listed on another page.
3.5mm
LCD panel
Measurement system II
Optical fiber
Measurement
Equipment
Light receptor lens
Light Detector
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
L (Black)
CR =
... (1)
L (White): Surface luminance of the TFT-LCD panel at the RGB signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V
Both luminosities are measured by System I.
– 11 –
LCX009AK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
L (White)
T =
× 100 (%) ... (2)
Luminance of Back Light
L (White) is the same expression as defined in the 'Contrast Ratio' section.
3. Chromaticity
Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses
Chromaticity of x and y on the CIE standards here.
Signal amplitudes (VAC) supplied to each input
R input
0.5
G input
4.5
B input
4.5
R
G
B
0.5
4.5
4.5
4.5
4.5
0.5
(Unit: V)
4. V – T Characteristics
V – T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond
to the each voltage which defines 90%, 50% and 10%
of transmittance respectively.
90
50
10
5. Half Tone Color Reproduction Range
V90 V50 V10
Half tone color reproduction range of the LCD panels is
characterized by the differences between the V – T
characteristics of R, G and B. The differences of these V – T
characteristics are measured by System II. System II
defines signal voltages of each R, G, B raster modes
which correspond to 50% of transmittance, V50R, V50G
and V50B respectively. V50RG and V50BG, the voltage
differences between V50R and V50G, V50B and V50G, are
simply given by the following formula (3) and (4)
respectively.
VAC – Signal amplitude [V]
100
50
0
V50RG
V50BG
G raster
B raster
R raster
V50RG = V50R – V50G ... (3)
V50BG = V50B – V50G ... (4)
V50R V50B
V50G
VAC – Signal amplitude [V]
– 12 –
LCX009AK
6. Response Time
Input signal
0.5V
Response time ton and toff are defined by
the formula (5) and (6) respectively.
ton = t1 – tON ... (5)
4.5V
6V
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance of
the panel.
0V
t2: time which gives 90% transmittance of
the panel.
Light transmission
output waveform
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
100%
90%
10%
0%
tON t1
ton
tOFF t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
component
AC
F (dB) = 20log
{
}
... (7)
DC component
R, G, B input signal condition for gray raster mode is given by
Vsig = 6 ± V50 (V)
where:V50 is the signal amplitude which gives 50% of
transmittance in V – T curve.
8. Image Retention Time
Image retention time is given by the following procedures:
Apply monoscope signal to the LCD panel for 60 minutes and then change monoscope signal to gray scale
signal (Vsig = 6 ± VAC (V); VAC = 3 to 4V) so as to give the maximum image retention. Hold input signal VAC.
The time of the residual image to disappear gives the image retention time.
Monoscope signal conditions:
Black level
Vsig = 6 ± 4.5 or 6 ± 2.0 (V)
4.5V
White level
(shown in the right figure)
Vcom = 5.6V
2.0V
6V
0V
2.0V
4.5V
Vsig waveform
– 13 –
LCX009AK
9. Method of Measuring the Optimum Vcom
There are two methods of measuring the optimum Vcom using the photoelectric element.
9-1. Method of Measuring Flicker
In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the
photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value at
this time is taken to be the optimum Vcom.
9-2. Method of Measuring Contrast
In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V) so
that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom.
Example of Back Light Spectrum (Reference)
0.4
0.3
0.2
0.1
0
400
500
600
700
Wave length 380 – 780 [nm]
– 14 –
LCX009AK
Description of Operation
1. Color Coding
Color filters are coded in a delta arrangement.
The shaded area is used for the dark border around the display.
Gate SW
dummy 1 to 4
Gate SW
dummy 5 to 8
Gate SW
Gate SW
Gate SW
Gate SW
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
R
G
B
R
G
B
R
G
B
B
R
R
G
B
R
G
B
R
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
G
B
R
G
G
B
B
R
R
G
G
B
B
R
R
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
G
B
B
R
R
G
G
B
B
R
R
G
G
Active area
B
R
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
R
G
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
Photo-shielding
R
G
B
827
14
800
13
– 15 –
LCX009AK
2. LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 225 gate lines sequentially in every single horizontal scanning period. A vertical shift register scans
the gate lines from the top to bottom of the panel.
• The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by
controlling the enable and VCK1, VCK2 pins. The enable pin should be High when not in use.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuit,
applies selected pulses to every 800 signal electrodes sequentially in a single horizontal scanning period.
• Scanning direction of horizontal shift register can be switched with RGT pin.Scanning direction is left to right
for RGT pin at High level; and right to left for RGT pin at Low level.(These scanning directions are from a
front view.) Normally, set to High level.
• Vertical and horizontal drivers address one pixel, and then dot Thin Film Transistors (TFTs; two TFTs for one
dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 225 × 800 dots to
display a picture in a single vertical scanning period.
• Pixels are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot offset against
juxtaposed horizontal line. For this reason, 1.5-dot offset of a horizontal driver output pulse against horizontal
synchronized pulse is required to apply a video signal to each dot properly. 1 H reversed displaying mode is
required to apply video signal to the panel.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 8.5V. This pin should be
grounded when not in use.
• The video signal must be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle
are shown below.
Hck1 and Hck2 should be exchanged to display the left-direction horizontal scanning (RGT = Low level). This
exchange enables the center of the image to be fixed by eliminating offsets.
(1) Vertical display cycle
VD
Vst
Vck1
Vck2
1
2
224
225
Vertical display 225H (14.3ms)
(2) Horizontal display cycle (right-direction scanning)
BLK
Hst
270
271
Hck1
Hck2
1
2
3
4
5
6
Horizontal display cycle (48.4µs)
The horizontal display cycle consists of 800/3 = 267 clock pulses because of RGB simultaneous sampling .
Refer to Description of Operation "3. RGB Simultaneous Sampling''
– 16 –
LCX009AK
3. RGB Simultaneous Sampling
Horizontal driver performs R, G and B signal sampling simultaneously, which requires the phase matching
between R, G, B signals to prevent horizontal resolution from deteriorating. The phase matching by an
external signal delaying circuit is needed before applying video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block
diagrams are as follows.
The LCX009 has a right/left inverse function. The following phase relationship diagram indicates the phase
setting for the right-direction scanning (RGT = High level). For the left-direction scanning (RGT = Low level),
the phase setting should be inverted for B and G signals.
(1) Sample-and-hold (right-direction scanning)
S/H
S/H
AC Amp
BLUE
RED
4
3
2
B
CKG
S/H
CKB
S/H
AC Amp
AC Amp
R
G
CKR
CKG
S/H
GREEN
CKG
<Phase relationship of delaying sample-and-hold pulses> (right-direction scanning)
HCKn
CKB
CKR
CKG
(2) Delay circuit (right-direction scanning)
Delay
Delay
Delay
AC Amp
BLUE
B
4
3
2
AC Amp
AC Amp
RED
R
G
GREEN
– 17 –
LCX009AK
Example of Color Filter Spectrum (Reference)
100
Color Filter Spectrum
R
80
G
B
60
Transmittance [%]
40
20
0
400
500
600
700
Wavelength [nm]
– 18 –
LCX009AK
Color Display System Block Diagram (1)
An example of single-chip display system is shown below.
+12V
+5V
+13.5V
RED
Composite video
Y/C
GREEN
BLUE
Y/color difference
VCOM
LCD panel
NTSC/PAL
LCX009AK
CXA1854R
HST
HCK1
HCK2
VST
VCK1
VCK2
EN
CLR
(Refer to CXD1845R data sheet.)
RGT
– 19 –
LCX009AK
Color Display System Block Diagram (2)
An example of dual-chip display system is shown below.
+12V
+5V
+13.5V
RED
Composite video
Y/C
GREEN
BLUE
Decoder/Driver
CXA1785AR
Y/color difference
Vcom
SYNC
FRP
+5V
LCD Panel
NTSC/PAL
LCX009AK
Hst
Hck1
Hck2
Vst
Vck1
Vck2
En
TG
CXD2411R
Clr
(Refer to CXD2411R data sheet.)
Rgt
– 20 –
LCX009AK
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective
sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily
deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in high temperature or in high humidity, which results in panel damages.
– 21 –
LCX009AK
Package Outline
Unit: mm
18.4 ± 0.2
Thickness of the connector 0.3 ± 0.05
1.3 ± 0.3
8.5 ± 0.05
4
1
3
5
2
CK1
sc
6
Incident
light
Active Area
Active Area
6
No
1
Description
F P C
(14.4)
2.9 ± 0.15
Molding material
Outside frame
Reinforcing board
11.0 ± 0.25
2
22.0 ± 0.15
3
P 0.5 ± 0.02
× 15 = 7.5 ± 0.03
4
+ 0.04
– 0.03
0.35
5
Reinforcing material
Polarizing film
0.5 ± 0.1
PIN1
PIN16
6
weight 2g
electrode (enlarged)
– 22 –
相关型号：
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