LCX012BL [SONY]
3.3cm (1.3-inch) Black-and-White LCD Panel; 3.3厘米（ 1.3英寸）的黑白LCD面板
| 型号： | LCX012BL |
| 厂家： | 
SONY CORPORATION |
| 描述： | 3.3cm (1.3-inch) Black-and-White LCD Panel |
| 文件： | 总21页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCX012BL
3.3cm (1.3-inch) Black-and-White LCD Panel
Description
The LCX012BL is a 3.3cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral
driving circuit. Use of three panels in combination
with the LCX012BL provides a full-color represen-
tation. The striped arrangement suitable for data
projectors is capable of displaying fine text and
vertical lines.
The adoption of advanced on-chip black matrix
realizes high picture quality without cross talk by
incorporating high luminance screen and cross talk
free circuit.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.
Using Sony’s timing generator “CXD2442Q” sends
timing signal necessary for LCD panel drive by
identificating computer supporting VGA automati-
cally, and supports double-speed processed
NTSC/PAL.
Features
• The number of active dots: 312,000 (1.3-inch; 3.3cm in diagonal)
• Accepts the computer requirements of VGA platform (640 x 480)
• High optical transmittance: 25% (typ.)
• Supports NTSC/PAL by processing the video signal at double speed
• Built-in cross talk free circuit
• High contrast ratio with normally white mode: 250 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
Element Structure
• Dots: 644 (H) × 484 (V) = 311,696
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.
Applications
• Liquid crystal data projectors
• Liquid crystal projectors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E96512-ST
LCX012BL
Block Diagram
13
19 18
6
1
2
11 12
17 10
21 20 16 15
9
22
14
8
7
5
4
3
23
Input Signal
Level
Shifter
H Shift Register (Bidrectional Scanning)
COM
PAD
– 2 –
LCX012BL
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
• V driver supply voltage
• Common pad voltage
HVDD
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
VVDD
COM
• H shift register input pin voltage
HST, HCK1, HCK2,
RGT
• V shift register input pin voltage
• Video signal input pin voltage
VST, VCK, PCG,
CLR, ENB, DWN
SIG1, SIG2, SIG3, SIG4,
SIG5, SIG6, PSIG
Topr
–1.0 to +17
–1.0 to +15
V
V
• Operating temperature
• Storage temperature
–10 to +70
–30 to +85
°C
°C
Tstg
Operating Conditions (VSS = 0V)
Supply voltage
HVDD
VVDD
15.5 ±0.5 V
15.5 ±0.5 V
Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin
5.0 ±0.5 V
Pin Description
Pin
Pin
No.
Symbol
No.
Description
Symbol
HCK2
VSS
Description
Clock pulse for H shift register
drive
1
2
NC
13
14
15
16
17
18
19
20
21
22
23
24
NC; Open
PSIG
SIG6
SIG5
SIG4
SIG3
SIG2
SIG1
HVDD
RGT
HST
GND (H, V drivers)
Uniformity improvement signal
Video signal 6 to panel
Video signal 5 to panel
Video signal 4 to panel
Video signal 3 to panel
Video signal 2 to panel
Video signal 1 to panel
Power supply for H driver
Improvement pulse (1) for
uniformity
3
CLR
4
ENB
Enable pulse for gate selection
NC; Open
5
NC
Clock pulse for V shift register
drive
6
VCK
Start pulse for V shift register
drive
7
VST
Drive direction pulse for V shift
register (H: normal, L: reverse)
8
DWN
PCG
VVDD
COM
TEST
Improvement pulse (2) for
uniformity
9
Driver direction pulse for H shift
register (H: normal, L: reverse)
10
11
12
Power supply for V driver
Common voltage of panel
Test; Open
Start pulse for H shift register
drive
Clock pulse for H shift register
drive
HCK1
– 3 –
LCX012BL
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. All pins are connected to VSS with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
250Ω
Level conversion circuit
(2-phase input)
250Ω
1MΩ
Input
1MΩ
(3) RGT
HVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
(4) HST
HVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
(6) VST, CLR, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
(7) COM
VVDD
Input
LC
1MΩ
– 4 –
LCX012BL
Input Signals
1. Input signal voltage conditions
(VSS = 0V)
Item
Symbol
VHIL
VHIH
VVIL
Min.
–0.5
Typ.
0.0
5.0
0.0
5.0
7.0
7.0
Max.
0.4
Unit
V
(Low)
H driver input voltage
(High)
4.5
5.5
V
(Low)
V driver input voltage
(High)
–0.5
0.4
V
VVIH
VVC
4.5
5.5
V
6.8
7.2
V
Video signal center voltage
Video signal input range 1 (SIG1 to 6)
Vsig
VVC – 4.5
VVC + 4.5
V
2
Vcom
VVC – 0.5 VVC – 0.4 VVC – 0.3
VVC ± 3.3 VVC ± 3.5 VVC ± 3.7
V
Common voltage of panel
Uniformity improvement signal
Vpsig
V
3
input voltage (PSIG)
1
input signal shall be symmetrical to VVC.
2
The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the
typical value is lowered, the maximum and minimum values may lower.
3
Input a uniformity improvement signal PSIG in the same polarity with video signals SIG1 to 6 and which is
symmetrical to VVC. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and
the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below).
Input waveform of uniformity improvement signal PSIG
90%
VVC
PSIG
10%
trPSIG
tfPSIG
PCG
Level Conversion Circuit
The LCX012BL has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
– 5 –
LCX012BL
2. Clock timing conditions
(Ta = 25°C) (VGA mode: fHCKn = 2.5MHz, fVCK = 15.7kHz)
Item
Symbol
trHst
Min.
—
Typ.
—
Max.
30
Unit
Hst rise time
Hst fall time
HST
tfHst
—
—
30
Hst data set-up time
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trClr
30
100
100
—
170
170
30
Hst data hold time
30
4
Hckn rise time
—
4
Hckn fall time
—
—
30
HCK
CLR
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Clr rise time
–15
–15
—
0
15
ns
0
15
—
100
100
100
2600
100
100
25
Clr fall time
tfClr
—
—
Vck rise/fall → Clr fall time
Clr pulse width
Tdclr
twClr
trVst
–100
2400
—
0
2500
—
Vst rise time
Vst fall time
tfVst
—
—
VST
VCK
ENB
Vst data set-up time
Vst data hold time
Vck rise time
tdVst
thVst
trVck
tfVck
trEnb
tfEnb
toEnb
twEnb
trPcg
tfPcg
toVck
twPcg
5
15
µs
5
15
25
—
—
100
100
100
100
600
2600
30
Vck fall time
—
—
Enb rise time
—
—
Enb fall time
—
—
Vck rise/fall to Enb rise time
Enb pulse width
Pcg rise time
400
2400
—
500
2500
—
ns
Pcg fall time
—
—
30
PCG
Pcg rise to Vck rise/fall time
Pcg pulse width
500
900
800
1000
1000
1100
4
Hckn means Hck1 and Hck2.
– 6 –
LCX012BL
<Horizontal Shift Register Driving Waveform>
Item
Symbol
Waveform
Conditions
90%
90%
4
O Hckn
Hst rise time
trHst
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hst
10%
50%
10%
tfHst
Hst fall time
tfHst
trHst
5
HST
50%
Hst data set-up time
tdHst
Hst
4
O Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hck1
50%
50%
thHst
90%
10%
Hst data hold time
thHst
tdHst
90%
10%
4
4
Hckn rise time
trHckn
tfHckn
O Hckn
4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hckn
4
Hckn fall time
trHckn
tfHckn
5
HCK
50%
50%
Hck1
Hck1 fall to Hck2 rise time to1Hck
Hck1 rise to Hck2 fall time to2Hck
50%
50%
Hck2
Clr
to2Hck
to1Hck
90%
90%
4
Clr rise time
Clr fall time
trClr
tfClr
O Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
10%
10%
trClr
tfClr
CLR
Vck
50%
twClr
tdClr
Clr pulse width
50%
Clr
50%
Vck rise/fall → Clr fall time
tdClr
5
twClr
5
Definitions: The right-pointing arrow (
The left-pointing arrow (
) means +.
) means –.
The black dot at an arrow (
) indicates the start of measurement.
– 7 –
LCX012BL
<Vertical Shift Register Driving Waveform>
Item
Symbol
Waveform
Conditions
90%
90%
Vst rise time
trVst
Vst
10%
50%
10%
50%
Vst fall time
tfVst
trVst
tfVst
5
VST
Vst data set-up time
tdVst
Vst
50%
50%
Vck
Vst data hold time
thVst
tdVst
thVst
90%
10%
90%
10%
Vck rise time
Vck fall time
Enb rise time
Enb fall time
trVck
tfVck
trEnb
tfEnb
Vck
VCK
trVckn
tfVckn
90%
90%
10% 10%
Enb
tfEn
trEn
Vck
50%
ENB
Vck rise/fall to
Enb rise time
tdEnb
twEnb
50%
50%
Enb
twEnb
to3Vck
5
Enb pulse width
tdEnb
90%
10%
90%
10%
Pcg rise time
Pcg fall time
trPcg
tfPcg
Pcg
trPcg
tfPcg
PCG
Vck
Pcg rise to Vck rise/fall
time
50%
toVck
twPcg
toVck
50%
50%
Pcg pulse width
Pcg
twPcg
5
– 8 –
LCX012BL
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Symbol
CHckn
CHst
Min. Typ.
Max. Unit
Condition
Input pin capacitance
HCKn
HST
—
—
10
10
15
15
—
—
—
—
pF
pF
Input pin current
HCK1
HCK2
HST
–500 –250
–1000 –300
–500 –150
–150 –25
µA HCK1 = GND
µA HCK2 = GND
µA HST = GND
µA RGT = GND
RGT
Video signal input pin capacitance Csig
—
—
100
4.0
150 pF
6.0 mA HCKn: HCK1, HCK2 (2.5MHz)
Current consumption
IH
2. Vertical drivers
Item
Symbol
CVck
Min.
—
Typ. Max. Unit
Condition
Input pin capacitance
VCK
VST
VCK
10
10
15
15
—
pF
pF
µA
CVst
—
Input pin current
–1000 –150
VCK = GND
PCG, VST, ENB, CLR,
DWN = GND
PCG, VST, ENB, CLR, DWN
Current consumption
–150
—
–25
2.0
—
µA
IV
3.0
mA
VCK: (15.7kHz)
3. Total power consumption of the panel
Item
Symbol
Min.
—
Typ.
100
Max. Unit
150
Total power consumption of the
panel (VGA)
PWR
mW
4. Pin input resistance
Item
Symbol
Rpin
Min.
0.4
Typ. Max. Unit
Pin – VSS input resistance
1
—
MΩ
5. Uniformity improvement signal
Item
Symbol
Min.
—
Typ.
6.5
Max. Unit
7.0 nF
Input pin capacitance for
uniformity improvement signal
CPSIGon
– 9 –
LCX012BL
Electro-optical Characteristics
(Ta = 25°C, VGA mode)
Typ. Max. Unit
Item
Contrast ratio
Symbol
CR
Measurement method Min.
150
1
250
25
—
—
—
%
25°C
25°C
22
1.1
1.2
1.3
1.0
1.1
1.1
1.5
1.6
1.7
1.5
1.5
1.6
2.0
2.1
2.1
2.1
2.1
2.2
—
Optical transmittance
2
T
1.5
1.7
1.8
1.4
1.5
1.6
1.9
2.0
2.1
1.8
1.9
2.0
2.4
2.5
2.5
2.3
2.4
2.5
36
1.8
2.0
2.1
1.7
1.8
1.9
2.2
2.3
2.4
2.1
2.2
2.3
2.7
2.8
2.8
2.6
2.7
2.8
80
RV90-25
GV90-25
BV90-25
RV90-60
GV90-60
BV90-60
RV50-25
GV50-25
BV50-25
RV50-60
GV50-60
BV50-60
RV10-25
GV10-25
BV10-25
RV10-60
GV10-60
BV10-60
ton0
25°C
60°C
25°C
60°C
25°C
60°C
V90
V-T
characteristics
V50
3
V
V10
0°C
25°C
0°C
ON time
Response time
—
14
40
ton25
4
ms
—
106
30
200
70
toff0
OFF time
—
25°C
60°C
25°C
25°C
toff25
—
–74
0
–40
0
Flicker
5
6
7
dB
s
F
—
Image retention time
Cross talk
YT60
—
—
5
%
CTK
Reflection Preventive Processing
When a phase substrate which rotates polarization axis is used to adjust to the polarization direction of
polarization screen or prism, use the phase substrate with reflection preventive processed on the surface.
This prevents characteristic deterioration caused by luminous reflection.
– 10 –
LCX012BL
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two typed of measurement system are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ±VAC [V] (VAC: signal amplitude)
• Measurement system I
approx. 2000mm
Luminance
Meter
Measurement
Equipment
LCD Projector
Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or an equivalent
Projection lens: The focal distance 80mm, F1.9
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)
(× 24, Sensor area: 7mmφ)
Polarizer: Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T or equivalent
• Measurement system II
Optical fiber
Measurement
Light Detector
Light receptor lens
Equipment
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
...
L (Black)
CR =
(1)
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 4.5V.
Both luminosities are measured by System Ι.
– 11 –
LCX012BL
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
White luminance
Luminance of light source
...
x 100 [%] (2)
T =
"White luminance" means the maximum luminance at the input signal amplitude VAC = 0.5V on Mesurement
System II.
3. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50, and V10 correspond
to the each voltage which defines 90%, 50%, and 10%
of transmittance respectively.
90
50
10
V90 V50 V10
VAC – Signal amplitude [V]
4. Respons Time
Input signal voltage (Waveform applied to the measured pixels)
Response time ton and toff are defined by
the formula (5) and (6) respectively.
4.5V
7.0V
0.5V
...
ton = t1 – tON (5)
...
toff = t2 – tOFF (6)
t1: time which gives 10% transmittance of
the panel.
0V
t2: time which gives 90% transmittance of
the panel.
Optical transmittance output waveform
100%
90%
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
10%
0%
tON t1
ton
tOFF t2
toff
– 12 –
LCX012BL
5. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC VGA: 30Hz, rms, PAL: 25Hz, rms) components of
the panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analizer in
System II.
AC component
DC component
...
F [dB] = 20log {
}
(7)
Each input signal condition for gray raster mode is given by
Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T characteristics.
6 Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure
the time till the residual image becomes indistinct.
Black level
Monoscope signal conditions:
Vsig = 7.0 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
4.5V
White level
2.0V
7.0V
0V
2.0V
4.5V
Vsig waveform
7. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented Wi' and Wi (i =
1 to 4) around black window (Vsig = 4.5V/1V)
W1 W1’
W2
W4
Wi' – Wi
Wi
Cross talk value CTK =
× 100 [%]
W2’
W4’
W3 W3’
– 13 –
LCX012BL
Viewing angle characteristics (Typical Value)
90
Phi
0
180
10
30
50
70 Theta
270
θ0°
Z
θ
φ90°
Marking
Y
φ
φ0°
φ180°
X
φ270°
Measurement method
– 14 –
LCX012BL
Optical transmittance of LCD panel (Typical Value)
30
20
10
0
400
500
600
700
Wavelength [nm]
Measurement method: Measurement system II
– 15 –
LCX012BL
1. Dot Arrangement
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.
Gate SW
Gate SW
Gate SW
Active area
Photo-shielding
5 dots
644 dots
5 dots
654 dots
– 16 –
LCX012BL
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the VGA mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 484 gate lines sequentially in every horizontal scanning period. Two lines of horizontal electrodes
are sequentially selected in NTSC/PAL mode.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 644 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then Thin film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 484 × 644 dots to display a
picture in a single vertical scanning period.
• To change the combination of the horizontal electrode in NTSC/PAL mode, the phase of VCK need to be
inverted. Normally, switching every field maximizes vertical resolution.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be
grounded when not in use.
• The video signal shall be input with 1H-inverted system.
• Timing diagrams of the vertical for VGA mode and NTSC/PAL mode and the horizontal display cycle are
shown below:
(1) Vertical display cycle (VGA)
VD
VST
(DWN = High level)
VST
(DWN = Low level)
VCK
1
2
480
Vertical display cycle 480H
(2) Horizontal display cycle
HD
HST
108
109
HCK1
1
2
3
4
5
6
HCK2
Horizontal display cycle
– 17 –
LCX012BL
[Description of operating mode]
The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The setting mode is shown below.
RGT
H
Mode
Right scan
Left scan
DWN
Mode
Down scan
Up scan
H
L
L
The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin
block upside.
• To improve uniformity, the analog signals PSIG shall be input by synchronizing with SIG1 to SIG6.
• When the up-scan mode (DWN = Low level) is set, the phase of VST shall be inverted
3. 6-dot Simultaneous Sampling and Dot-inverted Drive
Horizontal driver samples SIG1 to SIG6 signal simultaneously. Which requires the phase matching between
SIG1 to SIG6 signals to prevent horizontal resolution from deteriorating. Thus phase matching between each
signal is required using an external signal delaying circuit before applying video signal to the LCD panel.
The block diagram of the delaying procedure using sample-and-hold method is as follows.
The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For
the left scan (RGT = Low level), the phase setting shall be inverted between SIG1 to SIG6 signals.
AC Amp
AC Amp
S / H
S / H
SIG1
SIG2
S / H
CK1
8
7
SIG1
SIG2
S / H
CK2
SIG3
SIG4
AC Amp
AC Amp
S / H
CK3
S / H
S / H
6
5
SIG3
SIG4
S / H
CK4
AC Amp
AC Amp
S / H
S / H
CK5
SIG5
SIG6
SIG5
SIG6
4
3
S / H
CK6
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
– 18 –
LCX012BL
Display System Block Diagram
An example of display system is shown below.
Discrete Buff.
R
S/H
CXA2504N
RGB Driver
CXA1853Q
LCX012BL
R
G
B
FRP
S/H
CXA2504N
LCX012BL
G
S/H
CXA2504N
LCX012BL
B
HD
TG
CXD2442Q
SH
VD
C.SYNC
HCK, VCK
– 19 –
LCX012BL
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionozed air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet.
Peel off the protective sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel
damages.
g) Minimum bent radius rating for flexible substrates is 1mm.
h) Panel screw torque should not exceed 3kg · cm.
– 20 –
LCX012BL
Package Outline
Unit: mm
3.7 ± 0.1
Thickness of the connector 0.3 ± 0.05
25.0 ± 0.15
1.8 ± 0.1
4
1
3
3-φ2.3 ± 0.05
C0.8
2
5
6
Incident
light
Polarizing
Axis
Active Area
7
φ2.1 ± 0.05
(26.65)
19.0 ± 0.25
4.0 ± 0.1
30.0 ± 0.1
38.0 ± 0.15
No
1
Description
F P C
P 1.0 × 23 = 23.0 ± 0.1
1.0 ± 0.15
0.6 ± 0.05
Molding material
Outside frame
2
3
PIN1
PIN24
Reinforcing board
4
5
Reinforcing material
Polarizing film
Cover
6
7
electrode (enlarged)
weight 7.5g
The rotation angle of the active area relative to H and V is ± 1°.
– 21 –
相关型号：
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