LCX016AM [SONY]

3.3cm (1.3-inch) Black-and-White LCD Panel; 3.3厘米( 1.3英寸)的黑白LCD面板
LCX016AM
型号: LCX016AM
厂家: SONY CORPORATION    SONY CORPORATION
描述:

3.3cm (1.3-inch) Black-and-White LCD Panel
3.3厘米( 1.3英寸)的黑白LCD面板

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文件: 总22页 (文件大小:420K)
中文:  中文翻译
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LCX016AM  
3.3cm (1.3-inch) Black-and-White LCD Panel  
Preliminary  
For the availability of this product, please contact the sales office.  
Description  
The LCX016AM is a 3.3cm diagonal active matrix  
TFT-LCD panel addressed by polycrystalline silicon  
super thin film transistors with a built-in peripheral  
driving circuit. Use of three LCX016AM panels  
provides a full-color representation. The striped  
arrangement suitable for data projectors is capable  
of displaying fine text and vertical lines.  
The adoption of an advanced on-chip black matrix  
realizes high picture quality without cross talk by  
incorporating a high luminance screen and cross  
talk free circuit.  
This panel has a polysilicon TFT high-speed  
scanner and built-in function to display images  
up/down and/or right/left inverse. The built-in 5V  
interface circuit leads to lower voltage of timing and  
control signals.  
The panel contains an active area variable circuit  
which supports MAC17/SVGA/VGA/PC98 data  
signals by changing the active area according to the  
type of input signal. In addition, double-speed  
processed NTSC/PAL can also be supported.  
The adoption of a micro-lens increases the  
utilization efficiency of incident light, resulting in an  
optical transmittance of 30% or more with parallel  
incident light.  
Features  
Number of active dots: 519,000 (1.3-inch, 3.3cm in diagonal)  
Accepts the computer requirements of MAC17 (832 × 624), SVGA (800 × 600), VGA (640 × 480)  
and PC98 (640 × 400) platforms  
Supports NTSC (640 × 480) and PAL (762 × 572) by processing the video signal at double speed  
High optical transmittance: 30% or more (with parallel incident light)  
Built-in cross talk free circuit  
High contrast ratio with normally white mode: 200 (typ.)  
Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)  
Up/down and/or right/left inverse display function  
Element Structure  
Dots: 832 (H) × 624 (V) = 519,168  
Built-in peripheral driver using polycrystalline silicon super thin film transistors  
Applications  
Liquid crystal data projectors  
Liquid crystal projectors, etc.  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
PE96219-ST  
LCX016AM  
Block Diagram  
1
13 14 15 17  
9
19  
18 12  
10  
5
6
24  
20  
21 22  
11  
7
3
2
4
8
23 16  
H Shift Register (Bidirectional Scanning)  
Black Frame Control Circuit  
Input Signal  
Level Shifter  
Circuit  
COM  
PAD  
– 2 –  
LCX016AM  
Absolute Maximum Ratings (VSS = 0V)  
H driver supply voltage  
V driver supply voltage  
Common pad voltage  
HVDD  
VVDD  
COM  
–1.0 to +20  
–1.0 to +20  
–1.0 to +17  
–1.0 to +17  
V
V
V
V
H shift register input pin voltage HST, HCK1, HCK2,  
RGT  
V shift register input pin voltage VST, VCK, PCG,  
BLK, ENB, DWN  
–1.0 to +17  
–1.0 to +15  
V
V
MODE1, MODE2, MODE3  
SIG1, SIG2, SIG3, SIG4,  
Video signal input pin voltage  
SIG5, SIG6, PSIG  
Operating temperature  
Storage temperature  
Topr  
Tstg  
–10 to +70  
–30 to +85  
°C  
°C  
Operating Conditions (VSS = 0V)  
Supply voltage  
HVDD  
VVDD  
15.5 ± 0.3V  
15.5 ± 0.3V  
Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)  
Vin  
5.0 ± 0.5V  
Pin Description  
Pin  
Pin  
No.  
Symbol  
No.  
Description  
Symbol  
HST  
Description  
Start pulse for H shift register  
drive  
1
2
PSIG  
SIG4  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Uniformity improvement signal  
Video signal 4 to panel  
Video signal 3 to panel  
Video signal 5 to panel  
Video signal 2 to panel  
Video signal 6 to panel  
Video signal 1 to panel  
Power supply for H driver  
Clock pulse for H shift register  
drive  
HCK1  
HCK2  
Vss  
Clock pulse for H shift register  
drive  
3
SIG3  
4
SIG5  
GND (H, V drivers)  
5
SIG2  
BLK  
Black Frame display pulse  
Enable pulse for gate selection  
6
SIG6  
ENB  
VCK  
VST  
Clock pulse for V shift register  
drive  
7
SIG1  
Start pulse for V shift register  
drive  
8
HVDD  
RGT  
Drive direction pulse for H shift  
register (H: normal, L: reverse)  
9
PCG  
DWN  
VVDD  
COM  
Improvement pulse for uniformity  
Drive direction pulse for V shift  
register (H: normal, L: reverse)  
10  
11  
12  
MODE3  
MODE2  
MODE1  
Display area switching 3  
Display area switching 2  
Display area switching 1  
Power supply for V driver  
Common voltage of panel  
– 3 –  
LCX016AM  
Input Equivalent Circuit  
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,  
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a  
high resistor of 1M(typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)  
(1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG  
HVDD  
Input  
1M  
Signal line  
(2) HCK1, HCK2  
HVDD  
250Ω  
250Ω  
250Ω  
Level conversion circuit  
(2-phase input)  
250Ω  
1MΩ  
Input  
1MΩ  
(3) RGT  
HVDD  
2.5kΩ  
2.5kΩ  
Level conversion circuit  
(single-phase input)  
Input  
1MΩ  
(4) HST  
HVDD  
250Ω  
250Ω  
Level conversion circuit  
(single-phase input)  
Input  
1MΩ  
(5) PCG, VCK  
VVDD  
250Ω  
250Ω  
Level conversion circuit  
(single-phase input)  
Input  
1MΩ  
(6) VST, BLK, ENB, DWN, MODE1, MODE2, MODE3  
VVDD  
2.5kΩ  
2.5kΩ  
Level conversion circuit  
(single-phase input)  
Input  
1MΩ  
(7) COM  
VVDD  
Input  
LC  
1MΩ  
– 4 –  
LCX016AM  
Input Signals  
1. Input signal voltage conditions (VSS = 0V)  
Item  
Symbol  
VHIL  
Min.  
–0.5  
4.5  
Typ.  
0.0  
Max.  
0.4  
Unit  
V
(Low)  
(High)  
H shift register input voltage  
HST, HCK1, HCK2, RGT  
5.0  
5.5  
V
VHIH  
V shift register input voltage  
MODE1, MODE2, MODE3,  
BLK, VST, VCK, PCG,  
ENB, DWN  
(Low)  
(High)  
VVIL  
VVIH  
–0.5  
4.5  
0.0  
5.0  
0.4  
5.5  
V
V
Video signal center voltage  
7.0  
7.0  
V
V
V
VVC  
Vsig  
1
Video signal input range  
VVC – 4.5  
VVC + 4.5  
2
Common voltage of panel  
VVC – 0.4  
Vcom  
Uniformity improvement signal  
input voltage (PSIG)  
VVC ± 4.3 VVC ± 4.5 VVC ± 4.7  
V
Vpsig  
3
1
Input video signal shall be symmetrical to VVC.  
2
3
Common voltage of the panel shall be adjusted to VVC – 0.4V.  
Uniformity improvement signal PSIG shall be the same polarity as video signals SIG1 to 6.  
Level Conversion Circuit  
The LCX016AM has a built-in level conversion circuit in the clock input unit on the panel. The input signal level  
increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.  
– 5 –  
LCX016AM  
2. Clock timing conditions (Ta = 25°C)  
(MAC17 mode: fHCKn = 4.8MHz, fVCK = 24.9kHz)  
Item  
Symbol  
trHst  
Min.  
–15  
–15  
Typ.  
Max.  
30  
Unit  
Hst rise time  
Hst fall time  
HST  
tfHst  
30  
Hst data set-up time  
tdHst  
thHst  
trHckn  
tfHckn  
to1Hck  
to2Hck  
trVst  
50  
50  
Hst data hold time  
4
Hckn rise time  
30  
ns  
4
Hckn fall time  
30  
HCK  
Hck1 fall to Hck2 rise time  
0
15  
Hck1 rise to Hck2 fall time  
Vst rise time  
0
15  
100  
100  
Vst fall time  
VST  
tfVst  
Vst data set-up time  
tdVst  
thVst  
trVck  
tfVck  
trEnb  
tfEnb  
tdEnb  
twEnb  
trPcg  
tfPcg  
toVck  
twPcg  
trBlk  
10  
10  
µs  
ns  
µs  
Vst data hold time  
Vck rise time  
VCK  
100  
100  
100  
100  
Vck fall time  
Enb rise time  
Enb fall time  
ENB  
Vck rise/fall to Enb rise time  
500  
2500  
Enb pulse width  
Pcg rise time  
30  
Pcg fall time  
PCG  
30  
Pcg fall to Vck rise/fall time  
1000  
1200  
Pcg pulse width  
Blk rise time  
Blk fall time  
100  
100  
tfBlk  
5
BLK  
Blk fall to Vst rise time  
Blk pulse width  
toVst  
twBlk  
33  
21  
4
Hckn means Hck1 and Hck2.  
5
Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz).  
– 6 –  
LCX016AM  
<Horizontal Shift Register Driving Waveform>  
Item  
Symbol  
trHst  
Waveform  
Conditions  
90%  
90%  
3
Hckn  
Hst rise time  
duty cycle 50%  
to1Hck = 0ns  
to2Hck = 0ns  
Hst  
10%  
50%  
10%  
tfHst  
Hst fall time  
tfHst  
trHst  
6
HST  
50%  
Hst data set-up time  
tdHst  
Hst  
3
Hckn  
duty cycle 50%  
to1Hck = 0ns  
to2Hck = 0ns  
Hck1  
50%  
50%  
thHst  
Hst data hold time  
thHst  
tdHst  
90%  
10%  
90%  
10%  
3
3
Hckn rise time  
trHckn  
tfHckn  
Hckn  
3
duty cycle 50%  
to1Hck = 0ns  
to2Hck = 0ns  
Hckn  
3
Hckn fall time  
trHckn  
tfHckn  
HCK  
6
50%  
50%  
Hck1 fall to Hck2 rise time to1Hck  
Hck1 rise to Hck2 fall time to2Hck  
Hck1  
50%  
50%  
Hck2  
to2Hck  
to1Hck  
6
Definitions: The right-pointing arrow (  
) means +.  
The left-pointing arrow (  
) means –.  
) indicates the start of measurement.  
The black dot at an arrow (  
– 7 –  
LCX016AM  
<Vertical Shift Register Driving Waveform>  
Item  
Symbol  
trVst  
Waveform  
Conditions  
90%  
90%  
Vst rise time  
Vst  
10%  
50%  
10%  
50%  
Vst fall time  
tfVst  
trVst  
tfVst  
6
VST  
Vst data set-up time  
tdVst  
Vst  
50%  
50%  
Vck  
Vck  
Vst data hold time  
thVst  
tdVst  
thVst  
90%  
10%  
90%  
10%  
Vck rise time  
Vck fall time  
Enb rise time  
Enb fall time  
trVck  
tfVck  
trEnb  
tfEnb  
VCK  
trVckn  
tfVckn  
90%  
90%  
10% 10%  
Enb  
tfEn  
trEn  
ENB  
Vck rise/fall to Enb rise  
time  
tdEnb  
twEnb  
Vck  
50%  
50%  
twEnb  
50%  
Enb  
Enb pulse width  
6
tdEnb  
Pcg rise time  
Pcg fall time  
trPcg  
tfPcg  
Vck  
50%  
toVck  
50%  
7
Pcg rise to Vck rise/fall  
time  
PCG  
toVck  
trPcg  
50%  
Pcg  
twPcg  
Pcg pulse width  
6
Blk rise time  
Blk fall time  
twBlk  
tfBlk  
Vst  
50%  
BLK  
toVst  
twBlk  
Blk fall to Vst rise time  
Blk pulse width  
Blk  
50%  
50%  
toVst  
twBlk  
6
7
Input the pulse obtained by taking the OR of the above pulse (PCG) and BLK to the PCG input pin.  
– 8 –  
LCX016AM  
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)  
1. Horizontal drivers  
Item  
Symbol Min.  
Typ. Max. Unit  
Condition  
Input pin capacitance  
HCKn  
HST  
CHckn  
CHst  
12  
12  
pF  
pF  
µA  
µA  
µA  
µA  
pF  
mA  
Input pin current  
HCK1  
HCK2  
HST  
–250  
–300  
–150  
–30  
140  
5.0  
HCK1 = GND  
HCK2 = GND  
HST = GND  
RGT = GND  
RGT  
Video signal input pin capacitance  
Current consumption  
Csig  
IH  
HCKn: HCK1, HCK2 (4.8MHz)  
2. Vertical drivers  
Item  
Symbol Min. Typ. Max. Unit  
Condition  
Input pin capacitance  
VCK  
VST  
VCK  
CVck  
CVst  
12  
12  
pF  
pF  
µA  
Input pin current  
–150  
VCK = GND  
PCG, VST, ENB, DWN,  
BLK, MODE1, MODE2,  
MODE3 = GND  
PCG, VST, ENB, DWN, BLK, MODE1,  
MODE2, MODE3  
–30  
2.0  
µA  
Current consumption  
IV  
mA  
VCK: (24.9kHz)  
3. Total power consumption of the panel  
Item  
Symbol Min. Typ. Max. Unit  
PWR 100 mW  
Total power consumption of the  
panel (MAC17)  
4. Pin input resistance  
Item  
Symbol Min. Typ. Max. Unit  
Rpin 0.4 MΩ  
Pin – VSS input resistance  
1
5. Uniformity improvement signal  
Item  
Symbol Min. Typ. Max. Unit  
Input pin capacitance for uniformity  
improvement signal  
CPSIGo  
12  
nF  
– 9 –  
LCX016AM  
Electro-optical Characteristics  
Item  
(Ta = 25°C, MAC17 mode)  
Symbol Measurement method Min. Typ. Max. Unit  
Contrast ratio  
25°C  
25°C  
%
1
2
CR  
200  
20  
0
Optical transmittance  
T
RV90-25  
GV90-25  
BV90-25  
RV90-60  
GV90-60  
BV90-60  
RV50-25  
GV50-25  
BV50-25  
RV50-60  
GV50-60  
BV50-60  
RV10-25  
GV10-25  
BV10-25  
RV10-60  
GV10-60  
BV10-60  
ton0  
1.41  
1.55  
1.67  
1.33  
1.46  
1.58  
1.75  
1.85  
1.94  
1.67  
1.75  
1.84  
2.25  
2.34  
2.43  
2.15  
2.23  
2.31  
30.6  
12.0  
99.4  
28.4  
–68  
25°C  
60°C  
25°C  
60°C  
25°C  
60°C  
V90  
V-T  
V50  
3
V
characteristics  
V10  
0°C  
25°C  
0°C  
ON time  
Response time  
ton25  
toff0  
4
ms  
OFF time  
25°C  
60°C  
25°C  
25°C  
toff25  
F
Flicker  
5
6
7
dB  
s
Image retention time  
Cross talk  
YT60  
%
CTK  
5
Reflection Preventive Processing  
When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a  
polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This  
prevents characteristic deterioration caused by luminous reflection.  
– 10 –  
LCX016AM  
<Electro-optical Characteristics Measurement>  
Basic measurement conditions  
(1) Driving voltage  
HVDD = 15.5V, VVDD = 15.5V  
VVC = 7.0V, Vcom = 6.6V  
(2) Measurement temperature  
25°C unless otherwise specified.  
(3) Measurement point  
One point in the center of the screen unless otherwise specified.  
(4) Measurement systems  
Two types of measurement systems are used as shown below.  
(5) Video input signal voltage (Vsig)  
Vsig = 7.0 ± VAC [V]  
(VAC = signal amplitude)  
Measurement system I  
Approx. 2000mm  
Luminance  
Meter  
Measurement  
Equipment  
LCD Projector  
Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent  
Projection lens: Focal distance 80mm, F1.9  
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)  
(× 24, Sensor area: 7mmφ)  
Measurement system II  
Optical fiber  
Measurement  
Equipment  
Light receptor lens  
Light Detector  
Drive Circuit  
LCD panel  
Light  
Source  
1. Contrast Ratio  
Contrast Ratio (CR) is given by the following formula (1).  
L (White)  
L (Black)  
CR =  
... (1)  
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.  
L (Black): Surface luminance of the center of the screen at VAC = 4.5V.  
Both luminosities are measured by System I.  
– 11 –  
LCX016AM  
2. Optical Transmittance  
Optical Transmittance (T) is given by the following formula (2).  
White luminance  
T =  
× 100 [%] ... (2)  
Luminance of light source  
"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V  
on Measurement System I.  
3. V-T Characteristics  
V-T characteristics, or the relationship between signal  
amplitude and the transmittance of the panels, are  
measured by System II by inputting the same signal  
amplitude VAC to each input pin. V90, V50, and V10  
correspond to the voltages which define 90%, 50%,  
and 10% of transmittance respectively.  
90  
50  
10  
V90 V50 V10  
VAC – Signal amplitude [V]  
4. Response Time  
Response time ton and toff are defined by  
formulas (5) and (6) respectively.  
ton = t1 – tON ...(5)  
Input signal voltage (Waveform applied to the measured pixels)  
toff = t2 – tOFF ...(6)  
4.5V  
0.5V  
t1: time which gives 10% transmittance of  
7.0V  
the panel.  
t2: time which gives 90% transmittance of  
the panel.  
0V  
The relationships between t1, t2, tON and  
tOFF are shown in the right figure.  
Optical transmittance output waveform  
100%  
90%  
10%  
0%  
tON t1  
ton  
tOFF t2  
toff  
– 12 –  
LCX016AM  
5. Flicker  
Flicker (F) is given by formula (7). DC and AC (MAC17/SVGA/VGA/PC98/NTSC: 30Hz, rms, PAL: 25Hz,  
rms) components of the panel output signal for gray raster mode are measured by a DC voltmeter and a  
spectrum analyzer in System II.  
AC component  
DC component  
Each input signal voltage for gray raster mode  
is given by Vsig = 7.0 ± V50 [V]  
F [dB] = 20log  
...(7)  
{
}
where: V50 is the signal amplitude which gives  
50% of transmittance in V-T characteristics.  
6. Image Retention Time  
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale  
of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,  
measure the time till the residual image becomes indistinct.  
Black level  
Monoscope signal conditions:  
Vsig = 7.0 ± 4.5 or ± 2.0 [V]  
(shown in the right figure)  
Vcom = 6.6V  
4.5V  
White level  
2.0V  
7.0V  
0V  
2.0V  
4.5V  
Vsig waveform  
7. Cross Talk  
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and  
Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V).  
Wi' – Wi  
Cross talk value CTK =  
× 100 [%]  
Wi  
W1'  
W3'  
W1  
W3  
W2  
W4  
W2'  
W4'  
– 13 –  
LCX016AM  
1. Dot Arrangement  
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.  
Gate SW  
Gate SW  
Gate SW  
Photo-Shielding  
Active area  
832 dots  
840 dots  
4 dots  
4 dots  
– 14 –  
LCX016AM  
2. LCD Panel Operations  
[Description of basic operations]  
A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse  
to every 624 gate lines sequentially in a single horizontal scanning period. (in MAC17 mode)  
A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,  
applies selected pulses to every 832 signal electrodes sequentially in a single horizontal scanning period.  
These pulses are used to supply the sampled video signal to the row signal lines.  
Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn  
on to apply a video signal to the dot. The same procedures lead to the entire 624 × 832 dots to display a  
picture in a single vertical scanning period.  
The data and video signals shall be input with the 1H-inverted system.  
[Description of operating mode]  
This LCD panel can change the active area by displaying a black frame to support various computer or video  
signals. The active area is switched by MODE1, 2 and 3. The active area setting modes are shown below.  
MODE1  
L
MODE2  
L
MODE3  
L
Display mode  
MAC17  
832 × 624  
SVGA  
800 × 600  
L
L
L
H
H
L
H
L
PAL  
762 × 572  
VGA/NTSC  
640 × 480  
L
H
L
PC98  
640 × 400  
H
This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting  
systems.  
Right/left inverse mode  
Up/down inverse mode  
These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are  
shown below.  
RGT  
H
Mode  
Right scan  
Left scan  
DWN  
Mode  
Down scan  
Up scan  
H
L
L
Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin  
block upside.  
To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for  
both the H and V systems must be varied. The phase relationship between the start pulse and the clock for  
each mode is shown on the following pages.  
– 15 –  
LCX016AM  
(1) Vertical direction display cycle  
(1.1) MAC17  
VD  
VST (DWN = H)  
VST (DWN = L)  
VCK  
1
2
3
4
621 622 623 624  
Vertical display cycle 624H  
(1.2) SVGA  
VD  
VST (DWN = H)  
VST (DWN = L)  
1
2
3
4
VCK  
597 598 599 600  
Vertical display cycle 600H  
(1.3) PAL  
VD  
VST (DWN = H)  
VST (DWN = L)  
VCK  
1
2
3
4
569 570 571 572  
Vertical display cycle 572H  
(1.4) VGA/NTSC  
VD  
VST (DWN = H)  
VST (DWN = L)  
VCK  
1
2
3
4
477 478 479 480  
Vertical display cycle 480H  
(1.5) PC98  
VD  
VST (DWN = H)  
VST (DWN = L)  
VCK  
1
2
3
4
397 398 399 400  
Vertical display cycle 400H  
– 16 –  
LCX016AM  
(2) Horizontal direction display cycle  
(2.1.1) MAC17, RGT = H  
HD  
HST  
4
137 138 139 140  
HCK1  
HCK2  
1
2
3
Horizontal display cycle  
(2.1.2) MAC17, RGT = L  
HD  
HST  
HCK1  
1
2
3
138 139 140  
137  
4
HCK2  
Horizontal display cycle  
(2.2.1) SVGA, RGT = H  
HD  
HST  
1
2
3
4
131 132 133 134  
HCK1  
HCK2  
Horizontal display cycle  
(2.2.2) SVGA, RGT = L  
HD  
HST  
HCK1  
1
2
3
4
131 132 133 134  
HCK2  
Horizontal display cycle  
– 17 –  
LCX016AM  
(2.3.1) PAL, RGT = H  
HD  
HST  
1
2
3
4
125 126 127 128  
HCK1  
HCK2  
Horizontal display cycle  
(2.3.2) PAL, RGT = L  
HD  
HST  
1
2
3
4
125 126 127 128  
HCK1  
HCK2  
Horizontal display cycle  
(2.4.1) VGA/NTSC/PC98, RGT = H  
HD  
HST  
1
2
3
4
105 106 107 108  
HCK1  
HCK2  
Horizontal display cycle  
(2.4.2) VGA/NTSC/PC98, RGT = L  
HD  
HST  
4
1
2
3
105 106 107 108  
HCK1  
HCK2  
Horizontal display cycle  
– 18 –  
LCX016AM  
3. 6-dot Simultaneous Sampling  
The horizontal shift register samples signals SIG1 to SIG6 simultaneously. This requires phase matching  
between signals SIG1 to SIG6 to prevent the horizontal resolution from deteriorating. Thus, phase matching  
between each signal is required using an external signal delaying circuit before applying the video signal to  
the LCD panel.  
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following  
phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT =  
Low level), the phase settings for signals SIG1 to SIG6 are exactly reversed.  
8
6
S/H  
SIG1  
SIG2  
SIG1  
SIG2  
S/H  
S/H  
CK1  
S/H  
CK2  
SIG3  
SIG4  
S/H  
S/H  
S/H  
SIG3  
SIG4  
4
3
CK3  
S/H  
CK4  
SIG5  
SIG6  
S/H  
5
7
S/H  
SIG5  
SIG6  
CK5  
S/H  
CK6  
<Phase relationship of delaying sample-and-hold pulses> (right scan)  
HCKn  
CK1  
CK2  
CK3  
CK4  
CK5  
CK6  
– 19 –  
LCX016AM  
Display System Block Diagram  
An example of display system is shown below.  
LCX016  
R
S/H  
S/H  
S/H  
R-IN  
G-IN  
B-IN  
CXA1853AQ  
CXA1853AQ  
CXA1853AQ  
SHA, B, C  
SH1, 2, 3, 4  
LCX016  
G
LCX016  
B
HD  
VD  
TIMING GENERATOR  
C.SYNC  
– 20 –  
LCX016AM  
Notes on Handling  
(1) Static charge prevention  
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.  
a) Use non-chargeable gloves, or simply use bare hands.  
b) Use an earth-band when handling.  
c) Do not touch any electrodes of a panel.  
d) Wear non-chargeable clothes and conductive shoes.  
e) Install conductive mats on the working floor and working table.  
f) Keep panels away from any charged materials.  
g) Use ionized air to discharge the panels.  
(2) Protection from dust and dirt  
a) Operate in a clean environment.  
b) When delivered, the panel surface (Polarizer) is covered by a protective sheet. Peel off the protective  
sheet carefully so as not to damage the panel.  
c) Do not touch the panel surface. The surface is easily scratched. When cleaning, use a clean-room  
wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.  
d) Use ionized air to blow dust off the panel.  
(3) Other handling precautions  
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is  
easily deformed.  
b) Do not drop the panel.  
c) Do not twist or bend the panel or panel frame.  
d) Keep the panel away from heat sources.  
e) Do not dampen the panel with water or other solvents.  
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel  
damages.  
– 21 –  
LCX016AM  
Package Outline  
Unit: mm  
3.7 ± 0.1  
Thickness of the connector 0.3 ± 0.05  
25.0 ± 0.15  
1.8 ± 0.1  
4
1
3
5
6
8
3-φ2.3 ± 0.05  
C0.8  
2
Incident  
light  
Polarizing  
Axis  
Active Area  
7
φ2.1 ± 0.05  
(26.6)  
19.0 ± 0.25  
4.0 ± 0.1  
30.0 ± 0.1  
38.0 ± 0.15  
No  
1
Description  
P 1.0 × 23 = 23.0 ± 0.1  
F P C  
1.0 ± 0.15  
0.6 ± 0.05  
Molding material  
Outside frame  
Reinforcing board  
2
3
PIN1  
PIN24  
4
5
Reinforcing material  
Polarizing film  
6
7
Cover 1  
Cover 2  
electrode (enlarged)  
8
The rotation angle of the active area relative to H and V is ± 1°.  
weight 7.6g  
– 22 –  

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