MB15E06SRPV [SPANSION]
PLL Frequency Synthesizer, PBCC16, PLASTIC, BCC-16;
| 型号： | MB15E06SRPV |
| 厂家： | 
SPANSION |
| 描述： | PLL Frequency Synthesizer, PBCC16, PLASTIC, BCC-16 |
| 文件： | 总19页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
2003.Sep Edition 0.2
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-chip 3.0 GHz Prescaler
MB15E06SR
DESCRIPTION
The Fujitsu MB15E06SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 3.0 GHz prescaler.
The 3.0 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation.
The MB15E06SR uses the BiCMOS process, as a result, the low phase noise achieved. The phase noise
MB15E06SR was drastically improved comparing with the former single PLL, MB15E06. A refined charge pump
supplies well-balanced output currents of 4.0mA.The supply voltage range is between 2.7 V and 4.0 V.
The data format of serial data and the pin assignments exept for φP and φR pins are same as the former one,
so it is easy to replace the former one.
MB15E06SR is ideally suited for the ETC (Electronic Toll Collection).
FEATURES
• High frequency operation: 3.0 GHz max
• Low power supply voltage: VCC = 2.7 to 4.0 V
• Ultra Low power supply current:ICC = 8.0 mA typ. (VCC = Vp = 3.0 V, Ta = +25°C, SW=1 in locking state)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = Vp = 3.0 V, Ta = +25°C)
• Dual modulus prescaler: 64/65 or 128/129
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• On-chip phase comparator achieving fast tuning and low phase noise.
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
PACKAGES
16-pin, Plastic TSSOP
16-pad, Plastic BCC
(LCC-16P-M06)
(FPT-16P-M07)
1
MB15E06SR
PIN ASSIGNMENTS
16-pin TSSOP
16-pad BCC
NC
16
15
1
2
3
OSCIN
OSCIN NC
NC
OSCOUT
LD/fout
Vp
Vcc
Do
16
15
14
OSCOUT
1
14
NC
NC
PS
13
12
11
10
4
5
6
7
8
2
13
12
Vp
LD/fout
NC
3
Vcc
TOP
TOP
VIEW
VIEW
11 PS
Do
GND
Xfin
4
5
6
GND
Xfin
fin
LE
10
9
LE
Data
Data
7
8
9
Clock
fin Clock
(FPT-16P-M07)
LCC-16P-M06
2
MB15E06SR
PIN DESCRIPTIONS
Pin no.
Pin
TSSOP BCC
I/O
Descriptions
name
1
2
3
4
16
1
OSCIN
OSCOUT
VP
I
Programmable reference divider input. Connection to a TCXO.
Oscillator output
–
–
–
2
Power supply voltage input for the charge pump.
Power supply voltage input.
3
VCC
Charge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
5
4
DO
O
6
7
5
6
GND
Xfin
–
I
Ground.
Prescaler complementary input, which should be grounded via a capacitor.
Prescaler input.
8
9
7
8
fin
Clock
Data
LE
I
I
I
I
Connection to an external VCO should be done via AC coupling.
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
10
11
9
Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
10
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
12
13
14
11
12
13
PS
NC
I
-
PS = “H”; Normal mode
PS = “L”; Power saving mode
No connection
Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LD/fout
O
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
15
16
14
15
NC
NC
-
-
No connection.
No connection.
3
MB15E06SR
BLOCK DIAGRAM
(16)
OSCin 1
fr
(15)
16
NC
Phase
Reference
Oscillator
circuit
comparator
Binary 14-bit
reference counter
(1)
15 NC
SW
FC
LDS
2
(14)
OSCOUT
4-bit latch
14-bit latch
(11)
12
Intermittent
mode control
(power save)
lock
detector
PS
C
N
T
19-bit shift register
(13)
14
LD/fr/fp
selector
(10)
11
LD/
fout
1-bit
control
latch
LE
(9)
10
Data
fp
7 bit latch
11 bit latch
(8)
9
Clock
(2)
3
VP
Binary 11-bit
programmable
counter
Binary 7-bit
swallow
counter
Charge
pump
(4)
5
Do
MD
(6)
7
XfIN
fIN
Prescaler
64/65
(7)
8
SW
128/129
(5)
6
GND
(3)
4
VCC
TSSOP
BCC
( )
4
MB15E06SR
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Condition
Unit
Remark
Min.
–0.5
VCC
Max.
5.0
VCC
VP
–
V
V
Power supply voltage
Input voltage
–
6.0
VI
–
–0.5
GND
GND
–55
VCC +0.5
VCC
V
VO
Except Do
V
Output voltage
VO
Do
–
VP
V
Storage temperature
Tstg
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.7
Typ.
3.0
–
Max.
4.0
VCC
VP
VI
V
V
Power supply voltage
VCC
5.5
Input voltage
GND
–40
–
VCC
+85
V
Operating temperature
Ta
–
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15E06SR
ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 4.0 V, Ta = –40 to +85°C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
fin=3000 MHz, VCC = VP = 3.0 V
Power supply current*1
Power saving current
*1
ICC
–
8.0
–
mA
IPS
fIN
PS=L
–
700
3
0.1*2
–
20
3000
40
µA
fin
–
–
MHz
MHz
Operating frequency
OSCIN OSCIN
–
50 Ω system
fin*3
Vfin (Refer to the measurement
circuit.)
–10
–
+2
dBm
Vp-p
V
Input sensitivity
*3
OSCIN
VOSC
–
–
0.5
–
–
VCC
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
Data,
Clock,
LE,PS,
VIH
VCC × 0.7
–
VIL
–
–
–
–
–
–
–
VCC × 0.3
+1.0
*4
Data,
Clock,
LE
IIH
–1.0
–1.0
µA
*4
IIL
+1.0
*4
“H” level input current
“L” level input current
“H” level output voltage
“L” level output voltage
“H” level output voltage
“L” level output voltage
IIH
–
–
0
–100
VCC – 0.4
–
–
–
–
–
–
–
100
0
OSCin
LD/fout
µA
*4
IIL
VOH
VOL
VCC = VP = 3.0V, IOH = –1 mA
VCC = VP = 3.0V, IOL = 1 mA
–
V
0.4
–
VDOH
VDOL
VCC = VP = 3.0V, IDOH = –0.5 mA VP – 0.4
Do
Do
V
VCC = VP = 3.0V, IDOL = 0.5 mA
–
–
0.4
High impedance cutoff
current
VCC = VP = 3.0V,
VOFF = 0.5 V to VP – 0.5 V
IOFF
–
2.5
nA
mA
“H” level output current
“L” level output current
“H” level output current
“L” level output current
IOH
–
–
–
1.0
-5.2
2.8
–
–
–
–1.0
–
LD/fout
IOL
*4
IDOH
-4.0
4.0
5
-2.8
5.2
–
VCC =VP =3.0V VDO = VP/2
mA
Ta = +25°C
IDOL
*5
IDOL/IDOH
vs VDO
vs Ta
VDO = VP/2
%
%
%
IDOMT
IDOVD
Charge pump current
rate
*6
*7
0.5 V ≤ VDO ≤ VP – 0.7 V
– 40°C ≤ Ta ≤ +85°C,VDo=Vp/2
–
10
5
–
–
–
IDOTA
6
MB15E06SR
*1: Conditions; fosc = 13 MHz, Ta = +25°C, Vosc=1.2Vpp locking state.
*2: VCC = VP = 3.0V, fosc = 13 MHz, Vosc=1.2Vpp, Ta = +25°C, in power saving mode
*3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency.
*4: The symbol “–” (minus) means direction of current flow.
*5: VCC = VP = 3.0V, Ta = +25°C (||I3| – |I4||) / [(|I3| + |I4|) /2] × 100(%)
*6: VCC = VP = 3.0V, Ta = +25°C [(||I2| – |I1||) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)
*7: VCC=VP= 3.0V,VDO=VP/2,(||IDO(85°C)|–|IDO(–40°C)||/2)/(|IDO(85°C)|+|IDO(–40°C)| /2)×100(%) (Applied to each IDOL, IDOH)
I2
I3
I1
I1
I4
I2
0.5
VP/2
VP-0.7
VP
Output Voltage(V)
7
MB15E06SR
FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(P × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
A
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
P
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
: Preset divide ratio of modulus prescaler (64 or 128)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider
and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high,
stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT)
Destination of serial data
For the programmable reference divider
For the programmable divider
H
L
(1) Shift Register Configuration
Programmable Reference Counter
LSB
1
MSB
LDS
Data Flow
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
10 11 12 13 14 SW FC
CNT
: Control bit
[Table 1]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
SW
FC
LDS
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
: Phase control bit for the phase comparator
: LD/fOUT signal select bit
[Table 5]
[Table 7]
[Table 6]
Note: Start data input with MSB first.
8
MB15E06SR
Programmable Counter
MSB
LSB
1
Data Flow
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
10 11
CNT
: Control bit
[Table 1]
[Table 3]
[Table 4]
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
Note: Data input with MSB first.
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
R
R
R
R
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
ratio
(R)
14
13
12
11
10
3
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
1
⋅
1
0
⋅
1
0
⋅
4
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide
N
N
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
(N)
11
10
3
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
1
⋅
1
0
⋅
1
0
⋅
4
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
9
MB15E06SR
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide
A
7
A
6
A
5
A
4
A
3
A
2
A
1
ratio
(A)
0
1
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
0
⋅
0
1
⋅
⋅
127
1
1
1
1
1
1
1
Table 5. Prescaler Data Setting
SW
1
Prescaler divide ratio
64/65
0
128/129
Table 6. LD/fout Output Select Data Setting
LDS
LD/fOUT output signal
1
0
fout signal
LD signal
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level (DO)
is reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The relationship
between the FC bit and DO output is shown below.
Table 7. FC Bit Data Setting (LDS = “1”)
FC = 1
LD/fout
FC = 0
LD/fout
DO
H
DO
L
fr > fP
fr < fP
fr = fP
L
fout = fr
H
fout = fp
Z*
Z*
* : High impedance
10
MB15E06SR
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
(1)
* : When the LPF and VCO characteristics are similar to
(1), set FC bit high.
* : When the VCO characteristics are similar to (2), set
FC bit low.
VCO
Output
Frequency
(2)
PLL
LPF
VCO
LPF Input Voltage
3.Power Saving Mode (Intermittent Mode Control Circuit)
Table 8. PS Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
11
MB15E06SR
Note: PS pin must be set “L” for Power-ON.
OFF
ON
tv > 1µs
Vcc
Clock
Data
LE
tps > 100ns
(3)
PS
(1)
(2)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: L → H) 100 nS later after setting serial data.
12
MB15E06SR
SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit
LSB
Invalid data
Data
MSB
Clock
t6
LE
t1
t2
t3
t4
t5
t0
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit
t0
t1
t2
t3
100
20
–
–
–
–
–
–
–
–
ns
ns
ns
ns
t4
t5
t6
30
100
20
–
–
–
–
–
–
ns
ns
ns
20
30
Note: LE should be “L” when the data is transferred into the shift register.
13
MB15E06SR
PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWL
tWU
LD
[FC = “1”]
H
Do
Z
L
[FC = “0”]
H
Do
Z
L
Notes: 1. Phase error detection range: –2π to +2π
2. Pulses on Do signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cycles or more.
4. tWU and tWL depend on OSCIN input frequency.
tWU > 2/fosc (s) (e. g. tWU > 153.8 ns, fosc = 13 MHz)
tWU < 4/fosc (s) (e. g. tWL < 307.7 ns, fosc = 13 MHz)
5. LD becomes high during the power saving mode (PS = “L”).
14
MB15E06SR
MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
VCC VP
0.1µF
1000pF
1000pF
1000pF
S • G
S • G
0.1µF
50Ω
50Ω
8
7
6
5
4
3
2
1
9 10 11 12 13 14 15 16
Oscilloscope
Controller
(setting divide ratio)
Vcc
NOTE : TSSOP-16
15
MB15E06SR
APPLICATION EXAMPLE
Output
LPF
VCO
From
a controller
NC
16
NC
LD/fout NC
14 13
PS
12
LE
Data
10
Clock
15
11
6
9
8
MB15E06SR
1
2
3
4
5
7
OSCIN OSCOUT
VP
VCC
Do
GND
XfIN
fIN
1000pF
TCXO
1000pF
1000pF
0.1µF 0.1µF
VP: 5.5 V Max
Notes: 1. TSSOP-16
2. Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent
ꢀꢀꢀ oscillation when open-circuited in the input)
3: In case of using a crystal resonator, it is necessary to optimize matching between the crysta and this LSI.
and perform detailed system evaluation. It is recommended to consakut with a supplier of the crystal.
Reference oscillator circuit provides its own bias, feed back resistor is 100kohm(typ.)
16
MB15E06SR
USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting device into or removing device from a socket.
-Protect leads with a conductive sheet when transporting a board-mounted device.
ORDERING INFORMATION
Part number
MB15E06SRPFT
MB15E06SRPV
Package
Remarks
16-pin, Plastic TSSOP
(FPT-16P-M07)
16-pad, Plastic BCC
(LCC-16P-M06)
17
MB15E06SR
PACKAGE DIMENSIONS
16-pin, Plastic SSOP
(FPT-16P-M07)
* : These dimensions do not include resin protrusion.
*
5.00±0.10(.197±.004)
0.17±0.05
(.007±.002)
16
9
*
4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(Mounting height)
(.041±.002)
1
8
LEAD No.
"A"
0.65(.026)
0.24±0.08
(.009±.003)
0~8°
M
0.13(.005)
0.07 +–00..0073 .003 –+..000031
(Stand off)
(0.50(.020))
0.25(.010)
0.45/0.75
(.018/.030)
0.10(.004)
C
1999 FUJITSU LIMITED F16020S-2C-2
Dimensions in mm (inches
)
(Continued)
18
MB15E06SR
(Continued)
16-pad, Plastic BCC
(LCC-16P-M06)
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
3.40(.134)TYP
0.65(.026)
0.325±0.10
(.013±.004)
TYP
0.40±0.10
(.016±.004)
14
9
9
14
0.80(.031)
REF
INDEX AREA
3.40±0.10
(.134±.004)
2.45(.096)
TYP
1.15(.045)
REF
"B"
"A"
0.075±0.025
(.003±.001)
(Stand off)
1.725(.068)
REF
1
6
6
1
Details of "A" part
0.75±0.10
Details of "B" part
0.60±0.10
(.024±.004)
(.030±.004)
0.05(.002)
0.40±0.10
0.60±0.10
(.016±.004)
(.024±.004)
Dimensions in mm (inches).
C
1999 FUJITSU LIMITED C16017S-1C-1
19
相关型号：
MB15E07SLWQN
PLL Frequency Synthesizer, BICMOS, PQCC16, 4 X 4 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFN-16
FUJITSU
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