SS6383 [SSC]
1.5A DDR Termination Regulator; 1.5A DDR终端稳压器
| 型号： | SS6383 |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | 1.5A DDR Termination Regulator |
| 文件： | 总7页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SS6383(G)
1.5A DDR Termination Regulator
FEATURES
DESCRIPTION
Source and sink current capability of 1.5A
The SS6383 linear regulator is designed to
provide 1.5A source and sink current while
regulating an output voltage to within 25mV.
Low output voltage offset, ±20mV
High accuracy output voltage at full-load
VOUT adjustable by external resistors
Low external component count
Current limit protection
The SS6383 converts voltage supplies ranging
from 1.6V to 6V into an output voltage that
is set by two external voltage-divider resistors.
It provides an excellent voltage source for
active termination schemes for high-speed
transmission lines such as those seen in high-
speed memory buses.
Thermal protection
SO-8 package
APPLICATIONS
Mother Board
The built-in current-limiting in source and sink
mode, together with thermal shutdown, provides
maximum protection to the SS6383 against
fault conditions.
Graphic Cards
DDR Termination Voltage Supply - supports
DDR1 (1.25VTT), DDR2 (0.9VTT), and meets
JEDEC SSTL-2 and SSTL-3 term. specifications
TYPICAL APPLICATION CIRCUIT
8
1
V
V =3.3V
CNTL
VIN
IN=2.5V
VCNTL
VCNTL
VCNTL
VCNTL
R1
+
+
100K
C
7
6
5
IN
470µF
2
3
C
CNTL
47µF
GND
VREF
VOUT
V
=1.25V
+
C1
100pF
OUT
R2
100K
4
EN
SSM7002EN
SS6383
C
OUT
220µF
This device is available with Pb-free lead finish (second-level interconnect) as SS6383GS
10/07/2004 Rev.1.01
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SS6383(G)
ORDERING INFORMATION
PIN CONFIGURATION
SS6383XX XX
SO-8
TOP VIEW
Packing
TR: Tape and reel
1
VCNTL
VIN
8
7
6
VCNTL
VCNTL
VCNTL
2
3
GND
VREF
VOUT
Package type
CS: SO-8, Commercial
GS: SO-8, Commercial with
Pb-free lead finish
5
4
Example:
SS6383GSTR
ꢀ in SO-8 package with Pb-free lead finish
shipped on tape and reel
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-0.4V to 7V
-40°C~85°C
125°C
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Solder, 10sec)
Storage Temperature Range
260°C
-65°C ~150°C
Thermal Resistance .JC
SO-8
SO-8
40°C /W
Thermal Resistance θJA
160°C /W
(Assumes no ambient airflow, no heatsink)
Note1: Any stress beyond these Absolute Maximum Ratings may cause permanent damage to the device.
TEST CIRCUIT
8
7
6
5
1
2
3
4
VCNTL
VCNTL
VCNTL
VCNTL
VIN
2.5V/1.8V
3.3V
GND
VREF
VOUT
1.25V/0.9V
V
OUT
+
C
OUT
SS6383
10µF
10/07/2004 Rev.1.01
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SS6383(G)
ELECTRICAL CHARACTERISTICS
VCNTL=3.3V, VIN=2.5V, VREF=0.5VIN, C OUT=10µF, TA=25°C, unless otherwise specified) (Note 1)
PARAMETER
TEST CONDITIONS
SYMBOL
VIN
MIN.
1.6
TYP.
2.5/1.8
3.3
MAX.
UNIT
Keep VCNTL≥VIN during
power on and off sequences
Input Voltage (DDR1/2)
V
VCNTL
VOUT
VOS
3.0
6
Output Voltage
IOUT = 0mA
VREF
V
Output Voltage Offset
IOUT = 0mA (Note 2)
IOUT =0.1mA ~ +1.5A
-20
20
25
25
30
10
1
mV
10
10
8
Load Regulation (DDR1/2)
∆VLOR
mV
I
OUT = 0.1mA ~ -1.5A
(Note 3)
Quiescent Current
VREF<0.2V, VOUT = OFF
IQ
µA
mA
µA
A
Operating Current of VCNTL No load
ICNTL
3
VREF Bias Current
Current Limit
VREF=1.25V
(Note 4)
IIL
2.1
3
4.5
THERMAL PROTECTION
Thermal Shutdown
Temperature
3.3V≤VCNTL≤5V
TSD
125
150
30
°C
°C
Thermal Shutdown
Hysteresis
Guaranteed by design
SHUTDOWN SPECIFICATIONS
Output ON (VREF=0Vꢀ1.25V)
Output OFF (VREF=1.25Vꢀ0V)
0.8
Shutdown Threshold
V
0.2
Note 1: Specifications are production-tested at TA=25°C. Specifications over the -40°C to 85°C operating
temperature range are assured by design, characterization and correlation with Statistical Quality
Controls (SQC).
Note 2: VOS is the difference between VOUT and VREF
.
Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low duty cycle.
Note 4: Current limit is measured using a low duty cycle.
Note 5: To operate safely, VCNTL must always be greater than VIN.
10/07/2004 Rev.1.01
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SS6383(G)
TYPICAL PERFORMANCE CHARACTERISTICS
0.55
0.50
0.45
0.40
0.35
0.30
0.55
0.50
0.45
0.40
0.35
0.30
VCNTL=3.3V
VIN=2.5V
VCNTL=5V
VIN=2.5V
-40
-20
0
20
40
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (6°C0 )
Temperature (°C)
Fig. 2 Turn-On Threshold vs. Temp
Fig. 1 Turn-On Threshold vs. Temp.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5
4
3
2
1
0
V
V
VCNTL=3.3V
VIN=2.5V
V
No Load
REF
=1.25V
VCNTL=3.3V
VIN=2.5V
VOUT=1.25V
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature(oC)
Temperature (°C)
Fig. 4 Current-Limit (Sourcing) vs. Temperature
Fig. 3 Output Voltage Offset vs. Temperature
5
4
3
2
1
0
VCNTL=3.3V
VIN=2.5V
OUT
V
=1.25V
-40
-20
0
20
40
80
100
120
Temperature (6°C0 )
Fig. 5 Current-Limit (Sinking) vs. Temperature
10/07/2004 Rev.1.01
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SS6383(G)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
V =2.5V
V =2.5V
IN
V
IN
V
=3.3V
=3.3V
CNTL
V
CNTL
V
=1.25V
=1.25V
REF
REF
I
: 1A/DIV
I
: 1A/DIV
OUT
OUT
Fig. 6 Output Short-Circuit (Sinking)
: 50mV/DIV
Fig. 7 Output Short-Circuit Protection (Sourcing)
V
I
V
OUT
: 50mV/DIV
OUT
V =1.8V
V =2.5V
IN
CNTL
REF
IN
V
V
=3.3V
V
V
=3.3V
CNTL
REF
I
: 1A/DIV
OUT
=0.9V
: 1A/DIV
=1.25V
OUT
Fig. 9 Transient Response at 0.9VTT/1.5A
Fig. 8 Transient Response at 1.25VTT/1.5A
BLOCK DIAGRAM
VCNTL
VIN
+
Control
-
VOUT
VREF
Thermal
Current
Limit
Shutdown
VOUT
Shutdown
GND
10/07/2004 Rev.1.01
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SS6383(G)
PIN DESCRIPTIONS
PIN 1: VIN
- Input supply pin - provides
PIN 4: VOUT - Output pin.
power to create the external
reference voltage using a
resistor divider for regulating
PIN 5~8: VCNTL - Input supply pin - supplies all
the internal control circuitry.
V
REF and VOUT
.
PIN 2: GND - Ground pin.
PIN 3: VREF - Reference voltage input. Pull this
pin low to shut the device down.
APPLICATION INFORMATION
The large copper area around the VCNTL pins can
be used to assist the heat dissipation. Vias to lead
heat into the bottom layer are also recommended.
Layout Consideration
The SS6383 is in an SO-8 package and is unable
to dissipate heat easily when operating with high
currents. In order to avoid exceeding the maximum
junction temperature, an appropriate area of copper
must be used.
All capacitors should be placed as close to the
relative IC pin as possible.
Fig. 10. Top layer
Fig. 11. Bottom layer
Fig. 12. Placement
10/07/2004 Rev.1.01
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SS6383(G)
PHYSICAL DIMENSIONS (unit: mm)
SO-8
D
SYMBOL
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
A
A1
B
C
D
E
e
H
E
e
h x 45°
1.27BSC
A
H
h
L
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
0.25
C
Gauge Plane
Seating Plane
B
L
Q
Q
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
10/07/2004 Rev.1.01
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