SSM2313GN [SSC]
P-channel Enhancement-mode Power MOSFET; P沟道增强型功率MOSFET
| 型号： | SSM2313GN |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | P-channel Enhancement-mode Power MOSFET |
| 文件： | 总5页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM2313GN
P-channel Enhancement-mode Power MOSFET
Low gate-charge
BVDSS
R DS(ON)
ID
-20V
D
S
Simple drive requirement
Fast switching
120mW
-2.5A
G
Pb-free; RoHS compliant.
DESCRIPTION
D
The SSM2313GN is in a SOT-23-3 package, which is widely used for lower
power commercial and industrial surface mount applications. This device is
suitable for low-voltage applications such as DC/DC converters and and
general switching applications.
S
SOT-23-3
G
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Drain-Source Voltage
Rating
-20
Units
V
VDS
VGS
Gate-Source Voltage
V
± 12
ID @ TA=25°C
ID @ TA=70°C
IDM
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1,2
-2.5
A
-1.97
A
-10
A
PD @ TA=25°C
Total Power Dissipation
1.38
W
Linear Derating Factor
0.01
W/°C
°C
°C
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
THERMAL DATA
Symbol
Parameter
Value
Unit
R
ΘJA
Maximum Thermal Resistance, Junction-ambient3
90
°C/W
4/16/2005 Rev.2.1
www.SiliconStandard.com
1 of 5
SSM2313GN
(at Tj = 25°C unless otherwise specified)
ELECTRICAL CHARACTERISTICS
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=-250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
-20
-
-0.01
-
-
-
V
∆BVDSS/∆Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA
-
-
V/°C
RDS(ON)
Static Drain-Source On-Resistance2 VGS=-10V, ID=-2.8A
120 mΩ
VGS=-4.5V, ID=-2.5A
VGS=-2.5V, ID=-2A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
160 mΩ
300 mΩ
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=-250uA
VDS=-5V, ID=-2A
VDS=-20V, VGS=0V
VDS=-16V, VGS=0V
VGS=±12V
-
-1.2
V
Forward Transconductance
4
-
S
Drain-Source Leakage Current (T=25oC)
IDSS
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
-
-1
j
Drain-Source Leakage Current (T=70oC)
-
-25
j
IGSS
Qg
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
-
±100
ID=-2A
5
8
Qgs
Qgd
td(on)
tr
VDS=-16V
1
-
VGS=-4.5V
2
-
VDS=-10V
6
-
ID=-1A
17
16
5
-
td(off)
tf
Turn-off Delay Time
Fall Time
RG=3.3Ω , VGS=-10V
RD=10Ω
-
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
270
70
55
430
VDS=-20V
-
-
f=1.0MHz
Source-Drain Diode
Symbol
Parameter
Forward On Voltage2
Reverse Recovery Time2
Test Conditions
IS=-1.2A, VGS=0V
IS=-2A, VGS=0V,
Min. Typ. Max. Units
VSD
trr
-
-
-
-
-1.2
V
ns
nC
20
15
-
-
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
Notes:
1.Pulse width limited by maximum junction temperature.
2.Pulse width <300us, duty cycle <2%.
3.Surface-mounted on 1 in2 copper pad on FR4 board , t <10sec ; 270°C/W when mounted on minimum copper pad.
4/16/2005 Rev.2.1
www.SiliconStandard.com
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SSM2313GN
15
12
9
15
12
9
-5.0V
-4.5V
-5.0V
-4.5V
T A = 150 o
C
T A =25 o C
-3. 5 V
-3.5V
-2.5V
-2.5V
6
6
3
3
V G = - 1. 5 V
V
G = - 1. 5 V
0
0
0
1
2
3
4
5
0
1
2
3
4
5
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.6
1.4
1.2
1.0
0.8
0.6
200
I D =-2A
T A =25 o C
I D = - 2.5 A
V
G = -4.5V
160
120
80
2
4
6
8
10
-50
0
50
100
150
T j , Junction Temperature ( o C)
-V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
1.6
3
1.2
0.8
0.4
2
T j =150 o
C
T j =25 o C
1
0
0
0.2
0.4
0.6
0.8
1
1.2
-50
0
50
100
150
-V SD , Source-to-Drain Voltage (V)
T j , Junction Temperature ( o C)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
4/16/2005 Rev.2.1
www.SiliconStandard.com
3 of 5
SSM2313GN
f=1.0MHz
10
1000
100
10
I D =- 2 A
8
V
DS =-16V
C iss
6
C oss
C rss
4
2
0
1
5
9
13
17
21
25
0
2
4
6
8
-V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
0.2
10
0.1
0.1
1ms
0.05
1
PDM
t
10ms
0.01
T
0.01
Single Pulse
Duty factor = t/T
100ms
Peak Tj = PDM x Rthja + Ta
T A =25 o C
0.1
R Θja = 270°C/W
1s
DC
Single Pulse
0.001
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
0.1
1
10
100
-V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
-4.5V
QGD
QGS
10%
VGS
tr
td(on)
td(off)tf
Q
Charge
Fig 11. Switching Time Circuit
Fig 12. Gate Charge Circuit
4/16/2005 Rev.2.1
www.SiliconStandard.com
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SSM2313GN
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
4/16/2005 Rev.2.1
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