SSM9980GJ [SSC]

N-channel Enhancement-mode Power MOSFET; N沟道增强模式功率MOSFET
SSM9980GJ
型号: SSM9980GJ
厂家: SILICON STANDARD CORP.    SILICON STANDARD CORP.
描述:

N-channel Enhancement-mode Power MOSFET
N沟道增强模式功率MOSFET

文件: 总6页 (文件大小:721K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SSM9980GH,J  
N-channel Enhancement-mode Power MOSFET  
PRODUCT SUMMARY  
DESCRIPTION  
The SSM9980Gx acheives fast switching performance  
with low gate charge without a complex drive circuit. It is  
suitable for low voltage applications such as DC/DC  
converters and general load-switching circuits.  
BVDSS  
RDS(ON)  
ID  
80V  
45mW  
21A  
The SSM9980GH is in a TO-252 package, which is  
widely used for commercial and industrial surface-mount  
applications.  
Pb-free; RoHS-compliant TO-251 (IPAK)  
and TO-252 (DPAK)  
The through-hole version, the SSM9980GJ in TO-251,  
is available for vertical mounting, where a small footprint  
is required on the board, and/or an external heatsink is  
to be attached.  
G
G
D
D
These devices are manufactured with an advanced process,  
providing improved on-resistance and switching performance.  
S
S
TO-251 (suffix J)  
TO-252 (suffix H)  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VDS  
Parameter  
Value  
80  
Units  
Drain-source voltage  
Gate-source voltage  
V
V
VGS  
±25  
21  
Continuous drain current, T = 25°C  
ID  
A
C
T = 100°C  
13.4  
80  
A
C
IDM  
PD  
Pulsed drain current1  
A
Total power dissipation, T = 25°C  
41  
W
C
Linear derating factor  
0.33  
W/°C  
TSTG  
TJ  
Storage temperature range  
-55 to 150  
-55 to 150  
°C  
°C  
Operating junction temperature range  
THERMAL CHARACTERISTICS  
Symbol  
Parameter  
Value  
Units  
°C/W  
°C/W  
R
ΘJC  
ΘJA  
Maximum thermal resistance, junction-case  
Maximum thermal resistance, junction-ambient  
3.0  
R
110  
Notes:  
1.Pulse width must be limited to avoid exceeding the safe operating area.  
9/19/2006 Rev.3.1  
www.SiliconStandard.com  
1 of 6  
SSM9980GH,J  
(at Tj = 25°C, unless otherwise specified)  
ELECTRICAL CHARACTERISTICS  
Symbol  
BVDSS  
Parameter  
Test Conditions  
VGS=0V, ID=250uA  
Min. Typ. Max. Units  
Drain-source breakdown voltage  
80  
-
-
-
V
BVDSS/Tj  
Breakdown voltage temperature coefficient Reference to 25°C, ID=1mA  
0.07  
-
-
V/°C  
m  
RDS(ON)  
Static drain-source on-resistance  
VGS=10V, ID=12A  
-
45  
VGS=4.5V, ID=8A  
VDS=VGS, ID=250uA  
VDS=5V, ID=12A  
-
1
-
-
-
-
-
-
-
-
-
-
55  
mΩ  
V
VGS(th)  
gfs  
Gate threshold voltage  
3
Forward transconductance  
Drain-source leakage current  
20  
-
-
S
IDSS  
V
uA  
uA  
nA  
nC  
nC  
nC  
ns  
ns  
ns  
DS=80V, VGS=0V  
10  
VDS=64V ,VGS=0V, Tj = 150°C  
VGS=±25V  
-
100  
IGSS  
Qg  
Gate-source leakage current  
Total gate charge 2  
Gate-source charge  
Gate-drain ("Miller") charge  
Turn-on delay time 2  
Rise time  
-
±100  
ID=12A  
18  
5
30  
-
Qgs  
Qgd  
td(on)  
tr  
VDS=64V  
VGS=4.5V  
11  
11  
20  
29  
30  
-
VDS=40V  
-
ID=12A  
-
-
td(off)  
tf  
Turn-off delay time  
Fall time  
RG=3.3, VGS=10V  
RD=3.3Ω  
-
-
-
-
ns  
Ciss  
Coss  
Crss  
Input capacitance  
VGS=0V  
-
1810 2900 pF  
Output capacitance  
Reverse transfer capacitance  
VDS=25V  
-
-
135  
96  
-
pF  
pF  
f=1.0MHz  
-
Rg  
Gate resistance  
f=1.0MHz  
1.6  
Source-Drain Diode  
Symbol  
Parameter  
Forward voltage 2  
Reverse-recovery time 2  
Reverse-recovery charge  
Test Conditions  
Min. Typ. Max. Units  
VSD  
trr  
IS=20A, VGS=0V  
IS=12A, VGS=0V,  
dI/dt=100A/µs  
-
-
1.2  
V
-
57  
140  
-
-
ns  
Qrr  
-
nC  
Notes:  
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C.  
2.Pulse width <300us, duty cycle <2%.  
9/19/2006 Rev.3.1  
www.SiliconStandard.com  
2 of 6  
SSM9980GH,J  
60  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
10V  
6.0V  
5.0V  
4.5V  
10V  
6.0V  
5.0V  
4.5V  
T C =25 o C  
T C =150 o C  
V G =3.0V  
V G =3.0V  
0
3
6
9
12  
15  
18  
0
3
6
9
12  
15  
18  
V DS , Drain-to-Source Voltage (V)  
V DS , Drain-to-Source Voltage (V)  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
54  
50  
46  
42  
38  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
I D = 12 A  
V G =10V  
I D = 8 A  
T C =25 o C  
Ω
Ω
Ω
Ω
-50  
0
50  
100  
150  
3
5
7
9
11  
T j , Junction Temperature ( o C)  
V GS , Gate-to-Source Voltage (V)  
Fig 3. On-Resistance vs. Gate Voltage  
Fig 4. Normalized On-Resistance  
vs. Junction Temperature  
8
6
4
2
0
3
2.5  
2
T j =150 o C  
T j =25 o C  
1.5  
1
0.5  
0
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
-50  
0
50  
100  
150  
T j , Junction Temperature ( o C)  
V SD , Source-to-Drain Voltage (V)  
Fig 5. Forward Characteristic of  
Reverse Diode  
Fig 6. Gate Threshold Voltage vs.  
Junction Temperature  
9/19/2006 Rev.3.1  
www.SiliconStandard.com  
3 of 6  
SSM9980GH,J  
f=1.0MHz  
12  
10  
8
10000  
1000  
100  
I D = 12 A  
C iss  
V DS = 4 0V  
V DS = 50 V  
V DS = 64 V  
6
C oss  
C rss  
4
2
0
10  
0
10  
20  
30  
40  
1
5
9
13  
17  
21  
25  
29  
Q G , Total Gate Charge (nC)  
V DS , Drain-to-Source Voltage (V)  
Fig 7. Gate Charge Characteristics  
Fig 8. Typical Capacitance Characteristics  
1
100  
10  
1
Duty factor=0.5  
10us  
100us  
0.2  
0.1  
1ms  
0.1  
0.05  
PDM  
10ms  
100ms  
t
0.02  
0.01  
T
T C =25 o C  
Duty factor = t/T  
DC  
Single Pulse  
Peak Tj = PDM x Rthjc + TC  
Single Pulse  
0.1  
0.01  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
0.1  
1
10  
100  
1000  
V DS , Drain-to-Source Voltage (V)  
t , Pulse Width (s)  
Fig 9. Maximum Safe Operating Area  
Fig 10. Effective Transient Thermal Impedance  
VG  
VDS  
90%  
QG  
4.5V  
QGD  
QGS  
10%  
VGS  
tr  
td(on)  
td(off) tf  
Q
Charge  
Fig 11. Switching Time Waveform  
Fig 12. Gate Charge Waveform  
9/19/2006 Rev.3.1  
www.SiliconStandard.com  
4 of 6  
SSM9980GH,J  
PHYSICAL DIMENSIONS: TO-251 (I-PAK)  
D
Millimeters  
A
SYMBOLS  
D1  
MIN  
NOM MAX  
c1  
A
A1  
B1  
B2  
c
2.20  
0.90  
0.50  
0.60  
0.45  
0.45  
6.40  
5.20  
6.80  
5.40  
1.40  
--  
2.30  
1.20  
0.60  
0.72  
0.50  
0.50  
6.60  
5.35  
7.00  
5.60  
1.50  
2.30  
7.50  
1.60  
2.40  
1.50  
0.70  
0.90  
0.60  
0.55  
6.80  
5.50  
7.20  
5.80  
1.60  
--  
E2  
E
E1  
c1  
D
D1  
E
A1  
B2  
B1  
E1  
E2  
e
F
F1  
F
7.20  
1.50  
7.80  
1.80  
F1  
c
1.All dimensions are in millimeters.  
2.Dimensions do not include mold protrusions.  
e
e
PHYSICAL DIMENSIONS: TO-252 (D-PAK)  
E
b3  
A
S
Y
M
B
O
L
TO-252-3L  
c2  
MILLIMETERS  
MIN.  
MAX.  
A
1.80  
2.80  
A1  
b
0.00  
0.40  
4.80  
0.35  
0.13  
1.00  
5.90  
0.65  
b3  
c
c2  
D
0.40  
5.10  
0.89  
6.30  
A
A
e
E
e
6.00  
7.00  
SEE VIEW B  
b
2.30 BSC  
H
7.80  
11.05  
WITH PLATING  
L
1.00  
2.20  
2.55  
3.05  
L1  
BASE METAL  
L2  
L3  
L4  
0.35  
0.50  
0.50  
0.65  
2.03  
1.20  
SECTION A-A  
GAUGE PLANE  
SEATING PLANE  
0°  
8°  
θ
L
L1  
VIEW B  
9/19/2006 Rev.3.1  
www.SiliconStandard.com  
5 of 6  
SSM9980GH,J  
PART MARKING  
PART NUMBER: 9980GH or 9989GJ  
XXXXXX  
DATE/LOT CODE: (YWWSSS)  
Y = last digit of the year  
WW = week  
YWWSSS  
SSS = lot code sequence  
PACKING: Moisture sensitivity level MSL3  
TO-252: 3000 pcs in antistatic tape on a reel packed inside a moisture barrier bag (MBB).  
TO-251: 1000pcs in tubes packed inside a moisture barrier bag (MBB).  
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no  
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no  
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its  
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including  
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to  
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of  
Silicon Standard Corporation or any third parties.  
9/19/2006 Rev.3.1  
www.SiliconStandard.com  
6 of 6  

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