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74LVQ138M [STMICROELECTRONICS]

3 TO 8 LINE DECODER INVERTING; 3至8线译码器反相
74LVQ138M
型号： 74LVQ138M
厂家： ST    ST
描述：

3 TO 8 LINE DECODER INVERTING
3至8线译码器反相
文件： 总9页 (文件大小：72K)
中文：  中文翻译
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74LVQ138  
3 TO 8 LINE DECODER (INVERTING)  
■
■
■
HIGH SPEED:tPD =5.5ns (TYP.) atVCC = 3.3V  
COMPATIBLEWITH TTL OUTPUT  
LOW POWER DISSIPATION:  
o
µ
I
CC =4 A (MAX.) at TA =25 C  
LOWNOISE:  
■
■
■
M1  
T
VOLP =0.2 V (TYP.)at VCC = 3.3V  
(Micro Package)  
(TSSOPPackage)  
Ω
75 TRANSMISSIONLINEDRIVING  
ORDER CODES :  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 12 mA (MIN)  
74LVQ138M  
74LVQ138T  
■
■
PCI BUSLEVELSGUARANTEED AT 24mA  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
If the device is enabled, 3 binary select inputs (A,  
B and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either  
G2A or G2B is held high, the decoding function is  
inhibited and all the 8 outputsgo high.  
Three enable inputs are provided to ease  
cascade connection and application of address  
decodersfor memory systems.  
■
■
■
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V(1.2VDataRetention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES138  
IMPROVED LATCH-UP IMMUNITY  
It has better speed performance at 3.3V than 5V  
LSTTL family combinad with the true CMOS low  
power consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The LVQ138 is a low voltage CMOS 3 TO 8 LINE  
DECODER  
(INVERTING)  
fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
It is ideal for low power and low noise 3.3V  
applications.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/9  
February 1999  
74LVQ138  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
PIN DESCRIPTION  
PIN No  
1, 2, 3  
4, 5  
SYMBOL NAME AND FUNCTION  
A, B, C Address Inputs  
G2A, G2B Enable Inputs  
G1 Enable Input  
Y0 to Y7 Outputs  
6
15, 14, 13,  
12, 11, 10,  
9, 7  
8
GND  
VCC  
Ground (0V)  
Positive Supply Voltage  
16  
TRUTH TABLE  
INPUTS  
OUTPUTS  
ENABLE  
SELECT  
G2B  
X
X
H
L
G2A  
X
H
X
L
G1  
L
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0  
H
H
H
L
Y1  
Y2  
H
H
H
H
H
L
Y3  
H
H
H
H
H
H
L
Y4  
H
H
H
H
H
H
H
L
Y5  
H
H
H
H
H
H
H
H
L
Y6  
H
H
H
H
H
H
H
H
H
L
Y7  
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
L
L
H
H
H
H
L
L
H
H
X:Don’t Care  
LOGIC DIAGRAM  
Thislogic diagram has notbe used to esimate propagation delays  
2/9  
74LVQ138  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VCC  
VI  
Parameter  
Value  
-0.5 to +7  
-0.5 to VCC + 0.5  
-0.5 to VCC + 0.5  
± 20  
Unit  
V
Supply Voltage  
DC Input Voltage  
V
VO  
DC Output Voltage  
DC Input Diode Current  
DC Output Diode Current  
DC Output Current  
V
IIK  
mA  
mA  
mA  
mA  
oC  
IOK  
± 20  
IO  
50  
±
ICC or IGND DC VCC or Ground Current  
200  
±
Tstg  
TL  
Storage Temperature  
-65 to +150  
300  
Lead Temperature (10 sec)  
oC  
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.  
(*)500mW: 65oCderatedto 300 mW by10mW/oC:65oC to85oC  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
VI  
Parameter  
Supply Voltage (note 1)  
Value  
2 to 3.6  
0 to VCC  
0 to VCC  
-40 to +85  
0 to 10  
Unit  
V
Input Voltage  
V
VO  
Output Voltage  
V
oC  
Top  
Operating Temperature:  
dt/dv  
Input Rise and Fall Time (VCC = 3V) (note 2)  
ns/V  
1) Truth Table guaranteed: 1.2V to 3.6V  
2)VIN from0.8Vto2V  
3/9  
74LVQ138  
DC SPECIFICATIONS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
-40 to 85 oC  
VIH  
VIL  
High Level Input Voltage  
Low Level Input Voltage  
2.0  
2.0  
V
V
3.0 to  
3.6  
0.8  
0.8  
VOH  
High Level Output  
Voltage  
3.0  
VI(*)  
VIH or  
VIL  
=
IO=-50 µA  
2.9  
2.99  
2.9  
2.48  
2.2  
V
IO=-12 mA 2.58  
IO=-24 mA  
IO=50 µA  
VOL  
Low Level Output  
Voltage  
3.0  
VI(*)  
VIH or  
VIL  
=
0.002 0.1  
0.1  
0.44  
0.55  
±1  
V
IO=12 mA  
0
0.36  
IO=24 mA  
II  
Input Leakage Current  
VI = VCC or GND  
±0.1  
µA  
3.6  
3.6  
ICC  
Quiescent Supply  
Current  
VI = VCC or GND  
4
40  
A
µ
IOLD  
IOHD  
Dynamic Output Current  
(note 1, 2)  
3.6  
VOLD = 0.8 V max  
VOHD = 2 V min  
36  
mA  
mA  
-25  
1) Maximum test duration 2ms, one output loaded attime  
2)Incident wave switchingis guaranteed ontransmission lines withimpedances aslowas50 Ω.  
(*) All outputs loaded.  
DYNAMIC SWITCHING CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Unit  
VCC  
-40 to 85 oC  
(V)  
Min. Typ. Max. Min. Max.  
VOLP Dynamic Low Voltage  
3.3  
0.2  
0.8  
Quiet Output (note 1, 2)  
VOLV  
-0.8  
-0.2  
VIHD  
VILD  
Dynamic High Voltage  
Input (note 1, 3)  
3.3  
3.3  
2
CL = 50 pF  
V
Dynamic Low Voltage  
Input (note 1, 3)  
0.8  
1)Worstcase package  
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto3.3V, (n -1)outputs switching andone outputatGND  
3)max number ofdatainputs (n)switching.(n-1)switching 0Vto3.3V. Inputsunder testswitching: 3.3Vtothreshold (VILD),0V tothreshold (VIHD).f=1MHz  
4/9  
74LVQ138  
AC ELECTRICAL CHARACTERISTICS  
(CL = 50 pF, RL = 500 Ω, Input tr = t =3 ns)  
f
Symbol  
Parameter  
Test Condition  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
-40 to 85 oC  
tPLH  
tPHL  
Propagation Delay Time  
A, B, C to Y  
2.7  
3.3(*)  
2.7  
7.0  
5.5  
7.0  
5.5  
7.0  
5.5  
0.5  
0.5  
17.0  
12.0  
17.0  
12.0  
17.0  
12.0  
1.5  
20.0  
14.0  
20.0  
14.0  
20.0  
14.0  
1.5  
ns  
ns  
tPLH  
tPHL  
Propagation Delay Time  
G1 to Y  
3.3(*)  
tPLH  
tPHL  
Propagation Delay Time  
G2A or G2B to Y  
2.7  
ns  
ns  
3.3(*)  
2.7  
tOSLH Output to Output Skew  
tOSHL  
3.3(*)  
1.5  
1.5  
Time (note 1, 2)  
1) Skewis defined astheabsolute value ofthe difference between theactual propagation delay for any twooutputs of thesame device switching inthe  
same direction, either HIGHor LOW (tOSLH = |tPLHm -tPLHn|,tOSHL =|tPHLm -tpHLn|)  
2) Parameter guaranteed bydesign  
(*) Voltagerangeis3.3V ± 0.3V  
CAPACITIVE CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Unit  
VCC  
-40 to 85 oC  
(V)  
Min. Typ. Max. Min. Max.  
CIN  
Input Capacitance  
3.3  
3.3  
5
pF  
pF  
CPD  
Power Dissipation  
fIN = 10 MHz  
50  
Capacitance (note 1)  
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto  
TestCircuit).Average operting current can beobtained bythe followingequation. ICC(opr)= CPD VCC  
fIN + ICC  
•
•
TEST CIRCUIT  
CL = 50 pF or equivalent (includes jigand probe capacitance)  
RL =R1 =500Ω orequivalent  
RT = ZOUT ofpulse generator (typically50Ω)  
5/9  
74LVQ138  
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; duty cycle 50%)  
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz;  
duty cycle 50%)  
6/9  
74LVQ138  
SO-16 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
1.75  
0.2  
MIN.  
MAX.  
0.068  
0.007  
0.064  
0.018  
0.010  
A
a1  
a2  
b
0.1  
0.004  
1.65  
0.46  
0.25  
0.35  
0.19  
0.013  
0.007  
b1  
C
0.5  
0.019  
c1  
D
45 (typ.)  
9.8  
5.8  
10  
0.385  
0.228  
0.393  
0.244  
E
6.2  
e
1.27  
8.89  
0.050  
0.350  
e3  
F
3.8  
4.6  
0.5  
4.0  
5.3  
0.149  
0.181  
0.019  
0.157  
0.208  
0.050  
0.024  
G
L
1.27  
0.62  
M
S
8 (max.)  
P013H  
7/9  
74LVQ138  
TSSOP16 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
1.1  
MIN.  
MAX.  
0.433  
0.006  
0.374  
0.0118  
0.0079  
0.201  
0.256  
0.176  
A
A1  
A2  
b
0.05  
0.85  
0.19  
0.09  
4.9  
0.10  
0.9  
0.15  
0.95  
0.30  
0.20  
5.1  
0.002  
0.335  
0.0075  
0.0035  
0.193  
0.246  
0.169  
0.004  
0.354  
c
D
5
6.4  
0.197  
0.252  
E
6.25  
4.3  
6.5  
E1  
e
4.4  
4.48  
0.173  
0.65 BSC  
4o  
0.0256 BSC  
4o  
K
0o  
8o  
0o  
8o  
L
0.50  
0.60  
0.70  
0.020  
0.024  
0.028  
A2  
A
K
L
b
e
A1  
c
E
D
E1  
PIN 1 IDENTIFICATION  
1
8/9  
74LVQ138  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is  
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are  
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products  
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a trademark of STMicroelectronics  
1999 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
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Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.  
http://www.st.com  
.
9/9  

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