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74VHC174T [STMICROELECTRONICS]

HEX D-TYPE FLIP FLOP WITH CLEAR; HEX D型触发器与Clear FLOP
74VHC174T
型号： 74VHC174T
厂家： ST    ST
描述：

HEX D-TYPE FLIP FLOP WITH CLEAR
HEX D型触发器与Clear FLOP

触发器
文件： 总10页 (文件大小：73K)
中文：  中文翻译
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74VHC174  
HEX D-TYPE FLIP FLOP WITH CLEAR  
PRELIMINARY DATA  
■
■
■
HIGH SPEED:  
MAX =175MHz (TYP.)atVCC =5V  
LOW POWER DISSIPATION:  
ICC =4 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
f
M
T
VNIH = VNIL =28% VCC (MIN.)  
(Micro Package)  
(TSSOPPackage)  
■
■
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
ORDER CODES :  
74VHC174M  
74VHC174T  
■
■
■
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES174  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
transfered to the Q outputs on the positive going  
edge of the clock pulse.  
When the CLEAR input is held low, the Q outputs  
are held low independentlyof the other inputs.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
■
■
DESCRIPTION  
The 74VHC174 is an advanced high-speed  
CMOS HEX D-TYPE FLIP FLOP WITH CLEAR  
fabricated with sub-micron silicon gate and  
double-layermetal wiring C2MOS technology.  
Information signals applied to D inputs are  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
June 1999  
74VHC174  
INPUT EQUIVALENT CIRCUIT  
PIN DESCRIPTION  
PIN No  
SYMBOL NAME AND FUNCTION  
1
CLEAR  
Asyncronous Master Reset  
(Active LOW)  
2, 5, 7, 10,  
12, 15  
Q0 to Q5 Flip-Flop Outputs  
3, 4, 6, 11,  
13, 14  
D0 to D5 Data Inputs  
9
CLOCK  
Clock Input (LOW-to-HIGH,  
Edge- Triggered)  
8
GND  
VCC  
Ground (0V)  
16  
Positive Supply Voltage  
TRUTH TABLE  
INPUTS  
OUTPUTS  
FUNCTION  
CLEAR  
D
X
L
CLOCK  
Q
L
L
H
H
H
X
CLEAR  
L
H
X
H
Qn  
NO CHANGE  
X:Don’t Care  
LOGIC DIAGRAM  
Thislogic diagram has notbe used to estimate propagation delays  
2/10  
74VHC174  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VCC  
VI  
Parameter  
Value  
-0.5 to +7.0  
-0.5 to +7.0  
-0.5 to VCC + 0.5  
- 20  
Unit  
V
Supply Voltage  
DC Input Voltage  
V
VO  
DC OutputVoltage  
DC Input Diode Current  
DC OutputDiode Current  
DC OutputCurrent  
V
IIK  
mA  
mA  
mA  
mA  
oC  
IOK  
± 20  
IO  
25  
50  
±
±
ICC or IGND DC VCC or Ground Current  
Tstg  
TL  
Storage Temperature  
-65 to +150  
300  
Lead Temperature (10 sec)  
oC  
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
VI  
Parameter  
Value  
2.0 to 5.5  
0 to 5.5  
Unit  
V
Supply Voltage  
Input Voltage  
V
VO  
Output Voltage  
0 to VCC  
-40 to +85  
V
oC  
Top  
Operating Temperature  
dt/dv  
0 to 100  
0 to 20  
ns/V  
ns/V  
Input Rise and Fall Time (see note 1) (VCC = 3.3 ± 0.3V)  
(VCC = 5.0 0.5V)  
±
1)VIN from30% to70%of VCC  
DC SPECIFICATIONS  
Symbol  
Parameter  
Test Conditions  
VCC  
Value  
TA = 25 oC  
Unit  
-40 to 85 oC  
(V)  
Min. Typ. Max. Min. Max.  
VIH  
VIL  
High LevelInput Voltage  
Low Level Input Voltage  
2.0  
3.0 to 5.5  
2.0  
1.5  
1.5  
V
V
0.7VCC  
0.7VCC  
0.5  
0.5  
3.0 to 5.5  
2.0  
0.3VCC  
0.3VCC  
VOH  
High LevelOutput  
Voltage  
I =-50  
A
1.9  
2.9  
2.0  
3.0  
4.5  
1.9  
2.9  
µ
O
3.0  
IO=-50 µA  
IO=-50 µA  
IO=-4 mA  
IO=-8 mA  
V
V
4.5  
4.4  
4.4  
3.0  
2.58  
3.94  
2.48  
3.8  
4.5  
VOL  
Low Level Output  
Voltage  
2.0  
I =50  
O
A
A
0.0  
0.0  
0.0  
0.1  
0.1  
0.1  
0.1  
µ
µ
3.0  
I =50  
O
4.5  
IO=50 µA  
IO=4 mA  
0.1  
0.1  
3.0  
0.36  
0.36  
0.44  
0.44  
4.5  
IO=8 mA  
II  
Input Leakage Current  
0 to 5.5  
5.5  
VI = 5.5V or GND  
VI = VCC or GND  
0.1  
1.0  
A
A
±
±
µ
µ
ICC  
Quiescent Supply  
Current  
4
40  
3/10  
74VHC174  
AC ELECTRICAL CHARACTERISTICS  
(Input tr = tf =3 ns)  
Symbol  
Parameter  
Test Condition  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
CL  
(pF)  
-40 to 85 oC  
tPLH  
tPHL  
Propagation Delay Time  
CKto Q  
3.3(*)  
3.3(*)  
15  
50  
7.2  
9.7  
4.9  
6.4  
7.4  
9.9  
5.1  
6.6  
11.0  
14.5  
7.2  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
13.0  
16.5  
8.5  
ns  
ns  
5.0(**)  
5.0(**)  
3.3(*)  
3.3(*)  
5.0(**)  
5.0(**)  
3.3(*)  
5.0(**)  
3.3(*)  
5.0(**)  
3.3(*)  
5.0(**)  
3.3(*)  
5.0(**)  
3.3(*)  
5.0(**)  
3.3(*)  
3.3(*)  
5.0(**)  
5.0(**)  
15  
50  
15  
50  
15  
50  
9.2  
10.5  
13.5  
17.0  
9.0  
tPHL  
Propagation Delay Time  
CLR to Q  
11.4  
14.9  
7.6  
9.6  
11.0  
5.0  
tw  
tw  
CLR pulseWidth  
LOW  
5.0  
ns  
ns  
ns  
ns  
ns  
5.0  
5.0  
CKpulse Width  
HIGH r LOW  
5.0  
5.0  
5.0  
5.0  
ts  
Setup Time D to CK  
HIGH or LOW  
5.0  
4.5  
0.0  
0.5  
3.0  
2.5  
6.0  
4.5  
0.0  
0..5  
3.0  
2.5  
th  
Hold TimeD to CK  
HIGH or LOW  
tREM  
fMAX  
Removal Time  
CLR to CK  
Maximum Clock  
Frequency  
15  
50  
15  
50  
95  
55  
150  
85  
80  
50  
MHz  
130  
90  
175  
120  
110  
80  
(*) Voltagerangeis3.3V ± 0.3V  
(**) Voltagerange is 5V± 0.5V  
CAPACITIVE CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Unit  
-40 to 85 oC  
Min. Typ. Max. Min. Max.  
CIN  
Input Capacitance  
4
10  
10  
pF  
pF  
CPD  
Power Dissipation  
29  
Capacitance (note 1)  
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto  
TestCircuit).Average operating current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/6(per Flip-Flop)  
4/10  
74VHC174  
DYNAMIC SWITCHING CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
VCC  
(V)  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
-40 to 85 oC  
VOLP Dynamic Low Voltage  
5.0  
0.3  
0.8  
Quiet Output (note 1, 2)  
VOLV  
-0.8  
3.5  
-0.3  
VIHD  
VILD  
Dynamic High Voltage  
Input (note 1, 3)  
5.0  
5.0  
CL = 50 pF  
V
Dynamic Low Voltage  
Input (note 1, 3)  
1.5  
1)Worstcase package.  
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto5.0V, (n -1)outputs switching andone outputatGND.  
3)Max number ofdatainputs (n)switching.(n-1)switching 0Vto5.0V. Inputsunder testswitching: 5.0Vtothreshold (VILD),0V tothreshold (VIHD),f=1MHz.  
TEST CIRCUIT  
CL = 15/50 pF or equivalent (includes jig and probe capacitance)  
RT = ZOUT ofpulse generator (typically50Ω)  
5/10  
74VHC174  
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES  
(f=1MHz; 50% duty cycle)  
6/10  
74VHC174  
WAVEFORM 2: PROPAGATION DELAYS  
(f=1MHz; 50% duty cycle)  
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)  
7/10  
74VHC174  
Plastic DIP-16 (0.25) MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
0.51  
0.77  
TYP.  
MAX.  
MIN.  
0.020  
0.030  
MAX.  
a1  
B
b
1.65  
0.065  
0.5  
0.020  
0.010  
b1  
D
E
e
0.25  
20  
0.787  
8.5  
0.335  
0.100  
0.700  
2.54  
17.78  
e3  
F
7.1  
5.1  
0.280  
0.201  
I
L
3.3  
0.130  
Z
1.27  
0.050  
P001C  
8/10  
74VHC174  
SO-16 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
1.75  
0.2  
MIN.  
MAX.  
0.068  
0.007  
0.064  
0.018  
0.010  
A
a1  
a2  
b
0.1  
0.004  
1.65  
0.46  
0.25  
0.35  
0.19  
0.013  
0.007  
b1  
C
0.5  
0.019  
c1  
D
45 (typ.)  
9.8  
5.8  
10  
0.385  
0.228  
0.393  
0.244  
E
6.2  
e
1.27  
8.89  
0.050  
0.350  
e3  
F
3.8  
4.6  
0.5  
4.0  
5.3  
0.149  
0.181  
0.019  
0.157  
0.208  
0.050  
0.024  
G
L
1.27  
0.62  
M
S
8 (max.)  
P013H  
9/10  
74VHC174  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is  
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are  
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products  
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a trademark of STMicroelectronics  
1999 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - Canada - China -France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -  
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.  
http://www.st.com  
.
10/10  

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