EMIF10-COZ01F3 [STMICROELECTRONICS]
EMI FILTER INCLUDING ESD PROTECTION; EMI滤波器，它包括ESD保护
| 型号： | EMIF10-COZ01F3 |
| 厂家： | 
ST |
| 描述： | EMI FILTER INCLUDING ESD PROTECTION |
| 文件： | 总7页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EMIF10-COM01F2
®
EMI FILTER
INCLUDING ESD PROTECTION
IPAD™
MAIN PRODUCT CHARACTERISTICS
EMI filtering and ESD protection for:
■
Computers and printers
Communication systems
Mobile phones
■
■
DESCRIPTION
The EMIF10-COM01F2 is a highly integrated
device designed to suppress EMI / RFI noise in all
systems subjected to electromagnetic interfer-
ences. The EMIF10 Flip-Chip packaging means
the package size is equal to the die size.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
Flip-Chip
(25 Bumps)
Table 1: Order Code
Part Number
Marking
EMIF010-COM01F2
FE
Figure 1: Pin Configuration (Ball side)
BENEFITS
C
E
D
B
A
■
■
■
■
■
EMI symmetrical (I/O) low-pass filter
Lead free package
I5
I4
I3
I2
I1
1
2
3
4
5
Very low PCB space consuming: < 6mm2
Very thin package: 0.65 mm
I10
GND
010
05
I9
GND
09
I8
GND
08
I7
GND
07
I6
GND
06
High efficiency in ESD suppression on both
input & output pins
■
High reliability offered by monolithic integration
04
03
02
01
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2 level 4
15kV (air discharge)
8kV (contact discharge)
Figure 2: Basic cell configuration
Low-pass Filter
Input
Output
RI/O = 200Ω
Cline = 45 pF
TM: IPAD is a trademark of STMicroelectronics.
April 2005
REV. 2
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EMIF10-COM01F2
Table 2: Absolute Ratings (Tamb = 25°C)
Symbol
Parameter and test conditions
Value
Unit
15
8
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
VPP
kV
Tj
Junction temperature
125
°C
°C
°C
Top
Tstg
Operating temperature range
Storage temperature range
- 40 to + 85
- 55 to + 150
Table 3: Electrical Characteristics (Tamb = 25°C)
I
Symbol
Parameter
Breakdown voltage
VBR
IRM
VRM
VCL
Rd
Leakage current @ VRM
Stand-off voltage
VCL VBR VRM
Clamping voltage
V
IRM
IR
Dynamic impedance
Peak pulse current
IPP
Series resistance between Input &
Output
RI/O
slope :1 / R
d
IPP
Cline
Input capacitance per line
Symbol
Test conditions
Min.
Typ.
Max.
10
Unit
V
VBR
IR = 1 mA
6
8
IRM
Rd
VRM = 3V per line
500
nA
Ω
IPP = 10A, tp = 2.5µs
1
RI/O
Cline
tLH
180
200
45
220
50
Ω
At 0V bias
pF
ns
Vinput = 2.8V
Rload = 100kΩ
25
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EMIF10-COM01F2
Figure 3: S21(db) attenuation measurement
Figure 4: Analog crosstalk
0.00
dB
EMIF10-COM01F2: Typical S21(dB) measurement on line I10/O10
0.00
dB
-10.00
-5.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
-40.00
-45.00
-50.00
1.0M
3.0M
10.0M 30.0M
100.0M 300.0M
f/Hz
1.0G
3.0G
100.0k
1.0M
10.0M
100.0M
1.0G
f/Hz
Note: Spikes at high frequencies are induced by the PCB layout
Figure 5: ESD response to IEC61000-4-2
(+15kV air discharge) on one input V(in) and on
one output (Vout)
Figure 6: ESD response to IEC61000-4-2 (-15kV
air discharge) on one input V(in) and on one
output (Vout)
V(in1)
V(in1)
V(out1)
V(out1)
Figure 7: Rise time measurement
EMIF10-COM01F2
In
Out
Vout
Square signal
Generator Vc = 2.8V
100k
Vout
Vin
Vin
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EMIF10-COM01F2
Figure 8: Capacitance versus reverse applied
voltage
C(pF)
50
F=1MHz
Vosc=30mV
40
30
20
10
0
1
2
3
4
5
VR(V)
Figure 9: Aplac model
200R
out
in
Demif10 model
BV = 7
IBV = 1m
CJO = 25p
M = 0.3333
RS = 1
MODEL = demif10
MODEL = demif10
VJ = 0.6
TT = 100n
sub
PCB grounding recommendations
In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we recommend to
implement microvias (100 µm dia.) between the GND bumps and the GND layer. GND bumps can be con-
nected together in PCB layer 1, and in addition, if possible, use through hole vias (200 µm dia.) in both
sides of filter to improve contact to GND (layer). This layout will minimize the distance to the ground and
thus parasitic inductances. In addition, we recommend to have GND plane wherever possible.
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EMIF10-COM01F2
Figure 10: Ordering Information Scheme
EMIF yy
-
xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x
= 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
= 3: Leadfree Pitch = 400µm, Bump = 250µm
Figure 11: FLIP-CHIP Package Mechanical Data
500ꢀm 50
650ꢀm 65
315ꢀm 50
2.42mm 50ꢀm
Figure 12: Foot print recommendations
Figure 13: Marking
545
400
Dot, ST logo
xx = marking
z = packaging location
yww = datecode
(y = year
Copper pad Diameter :
250ꢀm recommended , 300ꢀm max
ww = week)
E
Solder stencil opening : 330ꢀm
x x z
Solder mask opening recommendation :
340ꢀm min for 315ꢀm copper pad diameter
y
w w
All dimensions in µm
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EMIF10-COM01F2
Figure 14: FLIP-CHIP Tape and Reel Specification
Dot identifying Pin A1 location
Ø 1.5 +/- 0.1
4 +/- 0.1
ST
ST
ST
0.73 +/- 0.05
4 +/- 0.1
User direction of unreeling
All dimensions in mm
Table 4: Ordering Information
Ordering code
Marking
Package
Weight
Base qty
5000
Delivery mode
EMIF10-COM01F2
FE
Flip-Chip
8.3 mg
Tape & reel
Note: More informations are available in the application notes:
AN1235: “Flip-Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
Table 5: Revision History
Date
Revision
Description of Changes
14-Dec-2004
12-Apr-2005
1
2
First issue.
Die clearance reduction.
6/7
EMIF10-COM01F2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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