ESDALC6V1P6 [STMICROELECTRONICS]
QUAD LOW CAPACITANCE TRANSIL⑩ ARRAY FOR ESD PROTECTION; 四路低电容的Transil ™阵列的ESD保护
| 型号： | ESDALC6V1P6 |
| 厂家： | 
ST |
| 描述： | QUAD LOW CAPACITANCE TRANSIL⑩ ARRAY FOR ESD PROTECTION |
| 文件： | 总9页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESDALC6V1P6
®
QUAD LOW CAPACITANCE TRANSIL™ ARRAY
FOR ESD PROTECTION
ASD™
MAIN APPLICATIONS
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
■
■
■
■
Computers
Printers
Communication systems and cellular phones
Video equipment
This device is particularly adapted to the
protection of symmetrical signals.
SOT-666IP
(Internal Pad)
FEATURES
■
4 Unidirectional Transil™ functions
■
Breakdown voltage V = 6.1 V min.
BR
FUNCTIONAL DIAGRAM
■
■
Low diode capacitance (12pF @ 0V)
Low leakage current < 500 nA
2
■
Very small PCB area < 2.6 mm
DESCRIPTION
The ESDALC6V1P6 is
designed to protect up to 4 lines against ESD
transients.
I/O1
GND
I/O2
I/O4
GND
I/O3
a
monolithic array
The device is ideal for situations where board
space saving is required.
BENEFITS
■
■
■
High ESD protection level
High integration
Suitable for high density boards
COMPLIES WITH THE FOLLOWING STANDARDS:
■
IEC61000-4-2 level 4:
15kV (air discharge)
8kV (contact discharge)
■
MIL STD 883E-Method 3015-7: class3
25kV HBM (Human Body Model)
Order Codes
Part Number
Marking
ESDALC6V1P6
D
July 2004
REV. 3
1/9
ESDALC6V1P6
ABSOLUTE RATING (T
= 25°C)
amb
Symbol
Parameter
Value
Unit
V
ESD discharge
15
8
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
PP
kV
P
Peak pulse power (8/20µs) (see note 1) T initial = T
30
125
W
°C
°C
°C
°C
PP
j
amb
T
Junction temperature
j
T
Storage temperature range
-55 to +150
260
stg
T
Maximum lead temperature for soldering during 10 s at 5mm for case
Operating temperature range
L
T
-40 to +125
op
Note 1: for a surge greater than the maximum values, the diode will fail in short-circuit.
THERMAL RESISTANCES
Symbol
Parameter
Value
Unit
R
220
°C/W
Junction to ambient on printed circuit on recommended pad layout
th(j-a)
ELECTRICAL CHARACTERISTICS (T
= 25°C)
amb
I
Symbol
Parameter
Stand-off voltage
IF
V
RM
V
Breakdown voltage
Clamping voltage
Leakage current
Peak pulse current
BR
VF
V
CL
VCLVBR VRM
V
IRM
I
RM
I
PP
αT
Voltage temperature coefficient
Forward voltage drop
Capacitance
Slope: 1/Rd
IPP
V
F
C
Rd
Dynamic resistance
V
@ I
I
@
V
R
d
αT
C
BR
R
RM
RM
min.
max.
max.
typ.
max.
typ.
@ 0V
pF
Part Number
-4
V
V
mA
µA
V
3
Ω
10 /°C
ESDALC6V1P6
6.1
7.2
1
0.5
1.5
4.5
12
2/9
®
ESDALC6V1P6
Fig. 1: Peak power dissipation versus initial
Fig. 2: Peak pulse power versus exponential pulse
junction temperature.
duration (Tj initial = 25°C).
P
(W)
PP
P [T initial] / P [T initial=25°C]
PP j PP j
1000
100
10
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Tj initial = 25°C
T initial (°C)
j
t (µs)
p
0
25
50
75
100
125
150
1
10
100
Fig. 3: Clamping voltage versus peak pulse
current (Tj initial = 25°C). Rectangular waveform
tp = 2.5µs.
Fig. 4: Peak forward voltage drop versus peak
forward current (typical values).
I
(A)
I
(A)
FM
PP
1.E+00
1.E-01
1.E-02
1.E-03
100.0
10.0
1.0
tp = 2.5µs
Tj = 125°C
Tj = 25°C
V (V)
CL
V
(V)
FM
0.1
0
10
20
30
40
50
60
70
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Fig. 5: Capacitance versus reverse applied
Fig. 6: Relative variation of leakage current versus
voltage (typical values).
junction temperature (typical values).
I [T ] / I [T =25°C]
C(pF)
R
j
R
j
1000
100
10
13
F=1MHz
VOSC=30mVRMS
Tj=25°C
12
11
VR = 3V
10
9
8
7
6
5
4
3
2
1
T (°C)
j
V (V)
R
0
1
0
1
2
3
4
5
6
25
50
75
100
125
3/9
®
ESDALC6V1P6
TECHNICAL INFORMATION
Fig. A: Application example.
1. ESD protection by ESDALC6V1P6
I/O2
I/O1
With the focus of lowering the operation levels, the
problem of malfunction caused by the environment
is critical. Electrostatic discharge (ESD) is a major
cause of failure in electronic systems.
IC
to be
protected
I/O4
I/O3
As a transient voltage suppressor, ESDALC6V1P6
is an ideal choice for ESD protection by
suppressing ESD events. It is capable of clamping
the incoming transient to a low enough level such
that any damage is prevented on the device
protected by ESDALC6V1P6.
ESDALC6V1P6 serves as a parallel protection
elements, connected between the signal line and
ground. As the transient rises above the operating
voltage of the device, the ESDALC6V1P6 becomes a low impedance path diverting the transient current
to ground.
The clamping voltage is given by the following formula:
V
= V + R .I
BR d PP
CL
As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A2: ESD clamping behavior.
R
G
I
PP
R
d
R
LOAD
V
G
V(i/o)
V
BR
Device
to be
ESD surge
ESDALC6V1P6
protected
I
1
slope =
R
d
I
PP
V
= V +R x I
PP
CL
BR
d
V
V
BR
V
CL
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical
dynamical resistance value R . By taking into account the following hypothesis:
d
RG > Rd""and""Rload > Rd
we have:
VG
-------
V(i ⁄ o)= VBR + Rd ×
RG
The results of the calculation done V = 8kV, R = 330Ω (IEC61000-4-2 standard), V = 6.4V (typ.) and
G
G
BR
R = 1.5Ω (typ.) give:
d
V(i ⁄ o) = 42.8 Volts
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few ns at the Vi/o side.
4/9
®
ESDALC6V1P6
Fig. A3: ESD test board.
Fig. A4: ESD test condition.
15kV ESD
Air discharge
I/O1, I/O2, I/O3 or I/O4
V(i/o)
15kV ESD
V(i/o)
Air discharge
GND
ESDALC6V1P6
The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection:
the clamping voltage V(i/o) becomes very close to V (positive way, figure A5a) and -V (negative way,
BR
F
figure A5b).
Fig. A5: Remaining voltage during ESD surge.
a: Response in the positive way
b: Response in the negative way
One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative
ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b.
5/9
®
ESDALC6V1P6
2. Crosstalk behavior
Fig. A6: Crosstalk phenomenon.
RG1
Line 1
Line 2
VG1
RL1
α1VG1 + β12VG2
RG2
V
G2
RL2
α2VG2 + β21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( β12 or β21 ) increase
when the gap across lines decreases, particularly in silicon dice. In the example above, the expected
signal on load R is α V , in fact the real voltage at this point has got an extra value β V . This part
L2
2
G2
21 G2
of the V signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This
G1
phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals. The perturbed line will be more affected if it works with low voltage signal or high load
impedance (few kΩ).
Fig. A7: Analog crosstalk test configuration.
Fig. A8: Typical analog crosstalk response.
0.00
dB
-10.00
I/O1
50Ω
unloaded
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
VG
Port 1
GND
50Ω
Port 2
I/O4
100.0k
1.0M
10.0M
100.0M
1.0G
f/Hz
Figure A7 gives the measurement circuit for the analog crosstalk application. In figure 8, the curve shows
the effect of the cell I/O1 on the cell I/O4. In usual frequency range of analog signals (up to 100 MHz) the
effect on disturbed line is less than -55dB.
6/9
®
ESDALC6V1P6
Fig. A9: Digital crosstalk test configuration.
Fig. A10: Typical digital crosstalk response.
I/O1
unloaded
VG1
VG1
0 - 5V
pulse generator
F= 100kHz
GND
β21VG1
tR = 20ns
β21VG1
unloaded
I/O4
Figure A9 shows the measurement circuit used to quantify the crosstalk effect in a classical digital
application.
Figure A10 shows that in such a condition, ie signal from 0 to 5V and rise time of a few ns, the impact on
the disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line.
The measurements performed with falling edges give an impact within the same range.
3. PCB layout recommendations
As ESD is a fast event, the dI/dt caused by this surge is about 30A/ns (risetime=1ns, Ipeak=30A), that
means each nH causes an overvoltage of 30V.
Thus, the circuit board layout is a critical design step in the suppression of ESD induced transients by
reducing parasitic inductances. To ensure that, the following guidelines are recommended :
■
■
■
■
■
The ESDALC6V1P6 should be placed as close as possible to the input terminals or connectors.
The path length between the ESD suppressor and the protected line should be minimized.
All conductive loops, including power and ground loops should be minimized.
The ESD transient return path to ground should be kept as short as possible.
The connections from the ground pins to the ground plane should be the shortest possible.
4. Comparison with varistors
Varistors
TRANSIL™
Leakage current
--
--
--
+++
++
Protection efficiency
Ageing
++
Low leakage current for Transil™ device
■
Improve the autonomy of portable equipments as mobile
Better efficiency in terms of ESD protection by using Transil™ device
■
Varistors are bidirectional devices and so are not suitable to protect sensitive ICs, because they will be
submitted to high voltages in the negative way.
■
■
Ratio V /V lower for Transil™ device
CL BR
Less dispersion in terms of V
BR
No ageing phenomena regarding ESD events with Transil™ device
■
Higher efficiency in terms of ESD protection
7/9
®
ESDALC6V1P6
ORDER CODE
ESDA LC 6V1 P6
ESD ARRAY
PACKAGE: SOT-666IP
VBR min
LOW CAPACITANCE
ORDERING INFORMATION
Delivery
mode
Part Number
Marking
Package
Weight
Base qty
ESDALC6V1P6
D
SOT-666IP
2.9 mg
3000
Tape & reel
REVISION HISTORY
Table 1: Revision history
Date
Revision
Description of Changes
January-2004
25-May-2004
05-Jul-2004
1
2
3
First issue
SOT-666 Internal Pad version package change
Stylesheet update. No content change.
8/9
®
ESDALC6V1P6
PACKAGE MECHANICAL DATA
SOT-666IP (internal Pad)
b
e
DIMENSIONS
Millimeters Inches
Min.
L3
L1
REF.
Min.
0.53
0.13
1.50
1.05
1.50
1.10
0.23
0.11
0.10
0.05
Max.
Max.
0.024
0.007
0.067
0.049
0.067
0.051
0.017
0.010
0.012
-
A
A3
D
0.60
0.18
1.70
1.25
1.70
1.30
0.43
0.26
0.30
-
0.021
0.005
0.059
0.041
0.059
0.043
0.009
0.004
0.004
0.002
L4
b1
e1
D2
E
Θ(4x)
E1
E2
L1
L2
L3
L4
b
A
A3
D
0.83 Ref
0.032
0.14
-
0.25
0.34
0.006
0.010
0.013
b1
e
E
E1
0.50 Bsc
0.020
e1
Θ
0.20
8°
-
0.008
12°
L2
12°
8°
FOOT PRINT DIMENSIONS (in millimeters)
0.36
0.30
0.62
2.30
0.84
0.20
0.20
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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9/9
®
相关型号：
ESDALC6V1PX
ASD (Application Specific Devices) Low capacitance TRANSIL⑩ arrays for ESD protection
STMICROELECTR
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