L6238SQA [STMICROELECTRONICS]
12V SENSORLESS SPINDLE MOTOR CONTROLLER; 12V无传感器锭子马达控制器
| 型号： | L6238SQA |
| 厂家： | 
ST |
| 描述： | 12V SENSORLESS SPINDLE MOTOR CONTROLLER |
| 文件： | 总31页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6238S
12V SENSORLESS SPINDLE MOTOR CONTROLLER
PRODUCT PREVIEW
12V OPERATION
3A, THREE-PHASE DMOS OUTPUT
(TOTAL Rdson 0.52Ω)
PLCC44
PQFP44
NO HALL SENSORS REQUIRED
DIGITAL BEMF PROCESSING
LINEAR OR PWM CONTROL
STAND ALONE OR EXT. DRIVER
SHOOT-THROUGH PROTECTION
THERMAL SHUTDOWN
DESCRIPTION
TQFP64
The L6238S is a Three-Phase, D.C. Brushless
Spindle Motor Driver system. This device features
both the Power and Sequence Sections.
Higher Power Applications can be activied with
the addition of an external Linear Driver, or by op-
erating the Internal Drivers in PWM.
ORDERING NUMBERS: L6238S (PLCC44)
L6238SQA (PQFP44)
L6238SQT (TQFP64)
Motor Start-Up, without the use of Hall Sensors,
can be achieved either by an internal start-up al-
gorithm or by manually sequencing the Output
Drivers, using a variety of User-Defined Start-UP
Algorithms.
Protection features include Stuck Rotor\Backward
Rotation Detection and Automatic Thermal Shut-
down.
BLOCK DIAGRAM
OUTPUT
ENABLE
RUN/
BRAKE SLEW
PWM/
PWM
LIN
PWM
COMP
PWM
TIM
VL
FALIGN
CPUMP1
CPUMP2
CPUMP3
CHARGE
PUMP
VANALOG
BIAS
ONE-SHOT
SLEW-CTRL
POWER
STAGE
VPOWER
SYSTEM
CLOCK
ALIGN + GO
START-UP
SYS CLOCK
SEQ INCR
BRAKE
DELAY
MONO/SEQ
CTRL
SEQUENCER
TDLY(0)
TDLY(1)
+
OUT A
OUT B
ZERO
CROSSING
DETECTOR
DIGITAL
DELAY
+
+
-
BEMF
SENSE
MONO
DET
TDLY(2)
OUT C
MASK DLY
CTR TAP
RSENSE1
RSENSE2
SPIN
SENSE
DIVIDE
BY N
TOGGLE
+
-
DRV
CNTL
GND
THERMAL
SHUTDOWM
OT-WARN
AV=4V/V
CSA
CSA INPUT
D95IN232
SEL POL
FMTR
VCTRL GM COMP GATE DRIVE
1/31
October 1995
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6238S
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
17
Unit
V
BVdss
VPower
VLogic
VAnalog
Vin
Output Brakdown Voltage
Motor Supply Voltage
Logic Supply Voltage
Analog Supply Voltage
Input Voltage
15
V
7
V
15
V
-0.3 to 7
4.7
V
Cstorage
Imdc
Charge Pump Storage Capacitor
µF
Motor Current (DC) (TQFP64 only)
3
2.5
A
A
(PLCC44 and PQFP44)
Impk
Ptot
Peak Motor Current (Pulsed: Ton = 5ms, d.c. = 10%)
5
A
Power Dissipation at Tamb = 50 °C(PLCC44)
2.3
1.7
1.3
W
W
W
(TQFP64)
(PQFP44)
Ts
Storage and Junction Temperature
-40 to 150
°C
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-Ambient
PLCC44
PQFP44
45
TQFP64
Unit
Rth (j-amb)
34
45
°C/W
Those Thermal Data are valid if the package is mounted on Mlayer board in stillair
PIN CONNECTION PLCC44 (Top view)
6
5
4
3
2
1 44 43 42 41 40
GND
CHARGE PUMP 1
CHARGE PUMP 3
OUTPUT A
VPOWER
7
39
38
37
36
35
34
33
32
31
30
29
GND
8
GATE DRIVE
GM COMP
OUTPUT C
RSENSE 2
CSA INPUT
VCONTROL
N.C.
9
10
11
12
13
14
15
16
17
VANALOG
N.C.
TDLY(0)
TDLY(1)
FMOTOR
VLOGIC
TDLY(2)
GND
GND
18 19 20 21 22 23 24 25 26 27 28
D95IN245
2/31
L6238S
PIN CONNECTION PQFP44 (10x10) (Top view)
11 10
9
8
7
6
5
4
3
2
1
OTWARN
SELECT POLE
PWM LIMIT TIMER
PWM/LINEAR
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
GND
CHARGE PUMP 2
RSENSE 1
BRAKE DELAY
SPIN SENSE
OUTPUT B
PWM/SLEW
CENTER TAP
VPOWER
OUTPUT ENABLE
RUN/BRAKE
SEQ. INCREMENT
SYSTEM CLOCK
MONO/SEQINC CTRL
FALING
MASK/DELAY
GND
PWM COMP.
23 24 25 26 27 28 29 30 31 32 33
D95IN243
PIN CONNECTION TQFP64 (Top view)
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
GND
N.C.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
GND
GND
N.C.
CHARGE PUMP 2
RSENSE 1
RSENSE 1
BRAKE DELAY
SPIN SENSE
OUTPUT B
OUTPUT B
PWM/SLEW
CENTER TAP
VPOWER
VPOWER
MASK DELAY
GND
OTWARN
SELECT POLE
PWM LIMIT TMR
PWM/LINEAR
OUTPUT ENABLE
RUN/BRAKE
SEQ. INCREMENT
SYSTEM CLOCK
MONO/SEQINC CTRL
FALIGN
PWM COMP
N.C.
GND
GND
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
D95IN244
3/31
L6238S
PIN FUNCTIONS
PLCC44 PQFP44 TQFP64
Name
OUTPUT B
SPIN SENSE
BRAKE DELAY
Rsense 1
I/O
Function
1
2
3
4
39
40
41
42
56, 57
58
I/O DMOS Half Bridge Output and Input B for Bemf sensing.
O
I
Toggless at each Zero Crossing of the Bemf.
59
Energy Recovery time constant, defined by external R-C to ground.
60, 61
O
Outputs A+B connections for the Motor Current Sense Resistor
to ground
5
43
62
*
CHARGE
PUMP 2
I
Negative Terminal of Pump Capacitor.
6, 7,
1, 11,
GROUND
S
Ground terminals.
17, 29, 23, 33,
39, 40 34, 44
8
9
2
3
4
5
CHARGEPUMP 1
CHARGEPUMP 3
OUTPUT A
I
Positive terminal of Pump Capacitor.
Positive terminal of Storage Capacitor.
O
10
4
6, 7
I/O DMOS Half Bridge Output and Input A for Bemf sensing.
11, 42
5, 36
9, 10,
52, 53
Vpower
S
Power Section Supply Terminal.
12
6
11
Vanalog
N.C
S
12V supply.
13, 32
7, 26
8, 18,
19, 31,
41
N.C Open Terminal
14
15
16
18
19
8
12
13
14
20
21
Tdly(0)
Tdly(1)
I
I
Three bits that set the Delay between the detection of the Bemf
zero crossing, and the commutation of the next Phase.
9
10
12
13
Tdly(2)
I
OTWARN
SELECT POLE
O
I
Overtemperature Warning Output
Selects # of Motor Poles. A zero selects 8, while a one selects 4
poles.
20
14
22
PWM TIMER
PWM/LINEAR
I
Capacitor connected to this pin sets the maximum time allowed
for 100% duty cycle during PWM operation
21
22
15
16
23
24
I
I
Selects PWM or Linear Output Current Control
Tristates Power Output Stage when a logic zero.
OUTPUT
ENABLE
23
24
17
18
25
26
SEQUENCE
I
I
Rising edge will initiate start-up. A Braking rountine is started
when this input is brought low.
SEQ
INCREMENT
A low to high transition on this pin increments the Output State
Sequencer.
25
26
19
20
27
28
SYSTEM CLK
I
I
Clock Frequency for the system timer/counters.
MONO/SEQ.
INC. CONTROL
A logic one will disable the Monotonicity Detector and Sequence
Increment functions.
27
21
29
Falign
I
Reference Frequency for the opt. Auto-Start Algorithm. If int.
start up is not used, this pin must be connected to the System
Clock.
28
30
31
33
34
35
22
24
25
27
28
29
30
35
PWM COMP
Vlogic
O
S
O
I
Output of the PWM Comparator
5V Logic Supply Voltage.
36
Fmotor
Motor Once-per-Revolution signal.
Voltage at this input controls he Motor Current
Input to the Current Sense Amplifier.
37
Vcontrol
38
CSA INPUT
Rsense 2
I
39, 40
O
Output C connection for the Motor Current Sense Resistor to
ground.
36
37
30
31
42, 43 OUTPUT C
44 gm COMP
I/O DMOS Half Bridge Output and Input C for Bemf sensing.
I
A series RC network to ground that defines the compensation of
the Transconductance Loop.
4/31
L6238S
PIN FUNCTIONS
PLCC44 PQFP44 TQFP64
Name
I/O
Function
38
32
45
GATE DRIVER I/O Drivers the Ext. PFET Gate Driver for Higher Power applications.
This pin must be grounded if an external driver is not used.
41
43
44
35
37
38
51
54
55
MASK/DELAY
CENTER TAP
PWM/SLEW
O
I
Internal Logic Signals used for production Testing
Motor Center Tap used for differential BEMF sensing.
R/C at this input set the Linear Slew Rate and PWM OFF-Time
I
Figure 1: Brake Delay Timeout vs Cbrake
Figure 2: Linear Slew Rate vs Rslew
(Rbrake = 1Meg)
T
(s)
BD
D95IN274
S
VR
(V/µs)
D95IN275
3.0
3.0
1.0
0.3
0.0
1.0
0.3
0.0
10
30
100
300
Rs(KΩ)
0.0
0.3
1.0
3.0
Cb(µF)
Figure 3: PWM Off - Time vs Rslew/Coff
Figure 4: PWM Limit Time - Out vs Ctimer
PWM
D95IN276
PWM
D95IN277
(µs)
30
10
3
(µs)
30
10
1
100
300
Ctimer(pF)
100
300
Coff(pF)
5/31
L6238S
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C; VA = VPwr = 12V; Vlogic = 5V; unless otherwise
specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
GENERAL
Vanalog
Analog Supply Voltage
Analog Supply Current
10.5
1.5
13.5
4.5
V
Ianalog
Run Mode VA = 13.5V
Brake Mode VA = 13.5V
2.7
280
5.0
2
mA
µA
V
800
5.5
Vlogic
Ilogic
Logic Supply Voltage
Logic Supply Current
4.5
1
Run Mode Vlogic = 5.5V
Brake Mode
3.2
mA
µA
100
500
1000
THERMAL SHUTDOWN
* Tsd
Shut Down Temperature
150
180
°C
°C
* Thys
Recovery Temperature
Hysteresis
30
* Tew
Early Warning Temperature
Tsd-25
°C
POWER STAGE
RDS(on)
Output ON Resistance per FET
Tj = 25°C; VA = 10.5V
Tj = 125°C; VA = 10.5V
0.20
0.30
0.7
0.26
0.40
Ω
Ω
Io(leak)
VF
Output Leakage Current
Body Diode Forward Drop
Output Slew Rate (Linear)
Output Slew Rate (PWM)
Vpwr = 15V
Im = 2.0A
1
mA
V
1.5
dVo/dt
Rslew = 100KΩ
0.15
10
0.45
150
V/µs
V/µs
mA
Igt
Gate Drive for Ext. Power
DMOS
Vcontrol = 1V; Vsns = 0V;
VA = 10.5V
4.5
VGate-Drive
VCtrl-Range
Iin(VCtrl)
Ext Driver Disable Voltage
Voltage Control Input Range
Voltage Control Input Current
V
V
0
5.0
10
µA
PWM OFF-TIME CONTROLLER (Rslew = 100KΩ, Coff = 120pF)
Toff
Vchrg
Vtrip
OFF Time
9
11
14
µs
V
Capacitor Charge Voltage
Lower Trip Threshold
VA = 10.5V
2.31
2.65
1.25
3.1
V
PWM LIMIT TIMER
Ichrg
Vchrg
Vtrip
Capacitor Charge Current
VPWM Timer = 0V; VA = 10.5V
VA = 10.5V
10.0
3.0
20.0
3.5
30
4.0
400
µA
mV
V
Capacitor Charge Voltage
Lower Trip Threshold
100
BEMF AMPLIFIER
ZinCT
Center Tap Imput Impedance
20
60
30
40
KΩ
VBemf
Minimum Bemf (Pk-Pk)
mV
CURRENT SENSE AMPLIFIER
Isnsin
Input Bias Current
Voltage Gain
Slew Rate
VA = 13.5V
10
µA
V/V
V/µs
Gv
3.8
4.0
0.8
4.2
SR
0.33
6/31
L6238S
ELECTRICAL CHARACTERISTICS (Continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
BRAKE DELAY
Vchrg
Iin
Iout3
VThres
Capacitor Charge Voltage
Input Current
RT = 50K
8.8
9.6
10.5
500
V
nA
mA
V
Vin = 5.0V
Source Current
VA = 10.5V
0.5
1.2
Delay Timer Low Trip Threshold
1.8
2.8
CHARGE PUMP
Vout
Storage Capacitor Output
VA = 10.5V; Iout = 500µA
17
V
Voltage
Fcp
Iin
Charge Pump Frequency
140
450
25
KHz
Vstorage Input Current (Run
Mode)
Vstorage = 12V; VA = Vlogic = 0
Vstorage = 12V; VA = Vlogic = 0
Vstorage = 12V; VA = Vlogic = 0
µA
Ibrkdly
Ibrake
Vstorage Leakage Current
(Brake Delay Mode)
0.4
0.1
1
1
µA
µA
Vstorage Leakage Current
(Brake Mode)
SEQUENCE INCREMENT
tseq
Time Between Rising Edges
1
µs
OUTPUT TRANSCONDUCTANCE AMPLIFIER Note: Measure at OTA Comp. pin.
Voh
VoutL
Isource
Isink
Voltage Output High
Output Voltage
VA = 10.5V
10
V
V
2.0
0.5
Output Voltage
40.0
40.0
V
Output Sink Current
µA
LOGIC SECTION
VinH
VinL
Input Voltage (All Inputs
Except Run/Brake
Vlogic = 4.5 to 5.5V
Vlogic = 4.5 to 5.5V
3.5
2.0
V
V
1.5
VinH
VinL
Run/Brake Input Voltage
V
V
1.0
1.0
IinH
IinL
Input Current
µA
mA
-1.0
VoutL
VinL
Output Voltage
Vsink = 2.0mA
0.5
V
V
V
source = 2.0mA
4.5
8.0
20
Fsys
System Clock Frequency
Clock ON/OFF Time
12.0
MHz
ns
toff/ton
Phase Delay Truth Table
Commutation Phase Delay,
in Electrical Degrees
Tdelay (2)
Tdelay (1)
Tdelay (0)
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
2.0
9.4
18.80
20.68
22.56
24,44 (*)
26.32
28.20
(*) Input Default
7/31
L6238S
shown in Fig. 1-1.
This configuration requires a minimum amount of
external components.
FUNCTIONAL DESCRIPTION
1.0 INTRODUCTION
1.1 Typical Application
1.2 Input Default States
In a typical application, the L6238S will operate in
conjunction with the L6244 Voice Coil Driver as
Figure 1-2 depicts the two possible input struc-
tures for the logic inputs. If a particular pin is not
Figure 1-1
9D5IN728
F µ 0 . 1
F µ
0 . 0 6 8
8/31
L6238S
reaches the nominal speed.
Figure 1-2
4) Park
When Run/Brake is brought low, energy to park
the heads may be derived from the rectified Bemf.
The energy recovery time is a function of the
Brake Delay Time Constant. In this state, the qui-
escent current of the device is minimized (sleep
mode).
VLOGIC
VLOGIC
5) Brake
10µA
After the Energy Recovery Time-Out, the device
is in Brake, with all lower Drivers in full conduc-
tion.
330
330
10µA
There are two mutually exclusive conditions
which may be present during the Tristate Mode
(wake up):
PULL-UP
D95IN279
PULL-DOWN
a)the spindle is stopped.
b)the system is still running at a speed that
allows for resynchronization.
In order to minimize the ramp up time, the micro-
controllerhas the possibility to:
used in an application, it may either be connected
to ground or VLOGIC as required, It may also be
simply left unconnected.
If no connection is made, the pin is either pulled
high or low by internal constant current gener-
ators as shown above.
check the SPIN SENSE pin, (which toggles at
the Bemf zero crossing frequency)
enable the power to the motor based on the
previous information. Otherwise the µP may is-
sue a Brake command, followed by the start-
up procedure after the motor has stopped spin-
ning.
A listing of the logic and clock inputs is shown in
Table 1 with the correspondingdefault state.
Table 1
Pin Function
Tdly (0,1,2)
Configuration
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Up
2.0 STATE DIAGRAMS
2.1 State Diagram
Figure 2-1 is a complete State Diagram of the
controller depicting the operationalflow as a func-
tion of the control pins and motor status. The flow
can be separatedinto four distinct operations.
Select Pole
PWM/Linear
Output Enable
Run/Brake
Sequence Increment
System Clock
Faling
Pull-Down
Pull-Up
2.2 Align + Go
Pull-Up
Figure 2-2 represent the normal flow that will
achieve a spin-up of the spindle motor using the
internally generated start up algorithm.
Upon power up, or from any state with
Run/Brake low the controller first sets the state
machine for State=1 with the Outputs Tristated.
1.3 Modes of Operation
There are 5 basicmodes of operation.
1) Tristate
When Output Enable is low, the output power
The period counter that monitors the time be-
tween zero crossing is stopped, analog with the
phase and mask delay counters.
drivers are tristated.
2) Start-Up
When Run/Brake is brought high, the motor is in
the first part of the align mode at State 2 (Output
A high and Output C low). If Output Enable is
high, the controller first checks to determine if the
motor is still spinning for a time of 21Ω (with
Sys_Clk = 10MHz). The drivers are now enabled
and after the align time-out, (64/Falign), the se-
quencer double increments the outputs to State 4
(Output B high and Output A low). The first part
of this align mode is used to reduce the effects of
stiction
With Output Enable high, bringing Run/Brake
from a low to a high will energize the motor and
the system will be driven by the Fully-Integrated
StartUp Algorithm.
A user-defined Start-Up Algorithm, under control
of a MicroProcessor, can also be achieved via the
sequence incrementinput.
3) Run
Run mode is achieved when the motor speed
(controlled by the external microprocessor)
9/31
L6238S
Figure 2-1
POR=0
FROM ANY STATE
(FOR IS GENERATED INTERNALLY
BY MONITORING VLOGIC)
SEQLNC=1 &
OUTENA=0
RUN/BRK=X
STATE = 1
RUN/BRK=1 &
OUTENA=1
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
DELAY STOP
INT. START-UP DISABLED
MIN. CLOCK DELAY
LOAD MIN. DELAY
DRIVERS ON
PERIOD COUNT
DELAY COUNT
RUN/BRAKE=0
FROM ANY STATE
LOAD MIN. MASK***
MASK STOP
RUN/BRAKE=1
SEQINC=0
SEQINC=1
STATE=STATE+1*
MASK COUNT
MASK COUNT
SEQINC=0
BEMF
BEMF
SEQINC=1
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT**
SEQINC=1
STATE=STATE+1
RETURN TO
FROM ANY STATE
WITH SEQ_INC=0
PREVIOUS STATE
(CHANGING SEQINC=1)
BEMF
DRIVERS OFF
MIN CLOCK DELAY
LOAD MIN MASK***
PERIOD STOP
DELAY COUNT
STATE=STATE+1
MASK COUNT
LOAD MIN. DELAY
LOAD MIN. MASK***
DELAY COUNT
STATE=STATE+1
MASK COUNT
* VALID IF SEQINC=0, AND DELAY TIMES OUT
** CLOCK DELAY=F(TDLY_[2:0])
WHEN BEMF PERIOD <3.3ms @ 10MHz
(SPEED >12.7Hz FOR 8 POLES)
STATE=STATE+2
BEMF
OUTENA=1
OUTENA=1
OUTENA=1
BEMF
OUTENA=1
OUTENA=0
OUTENA=1
BEMF
CHECK FOR Zc
DRIVERS OFF
221
SYS_CLK
STATE=STATE+1
MIN CLOCK DELAY
LOAD MIN DELAY
LOAD MAX MASK
DELAY COUNT
221
DRIVERS ON
LOAD DELAY=MIN
LOAD MASK=MIN
RESET PERIOD
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT
SYS_CLK
PERIOD STOP
DELAY STOP
MASK STOP
STATE=STATE+1
MASK COUNT
64/FALIGN
RUN/BRK=0
DRIVERS OFF
MIN CLOCK DELAY
STATE=STATE+2
OUTENA=1
PERIOD STOP
BEMF
192/FALIGN
DRIVERS OFF
MONO=0**
OUTENA=0
RUN/BRK=0
STATE=STATE+1
LOAD DELAY=MIN
LOAD MASK=MAX
PERIOD COUNT
DELAY COUNT
221
DRIVERS ON
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
SYS_CLK
OUTENA=0
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT
DRIVERS OFF
BEMF
STATE=STATE+1
MASK COUNT
BEMF
RUN
MODE
ALIGN &
GO MODE
RESYNCHRONIZATION
MODE
BEMF
D95IN280
* CLOCK DELAY=F(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES)
BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0
BEMF1: BEMF RISINGWITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1
**MONO=0 WHEN FREQ(BEMF)=2*FREQ(PHASE)
***MIN MASK=192/SYS_CLK(I.E. WITH SYS_CLK=10MHz,MIN MASK=19.2µs)
After the next align time-out 192/Falign), the con-
troller enters the Go mode, were the sequencer
again double increments the output phase upon
detectionof the motor’s Bemf.
The align time-out may be optimized for the appli-
cation by changing the Faling reference fre-
quency.
Without this feature, the output would remain in
the first phase under high current conditions, if
the clock were not present.
If the external sequencer is used to provide start
up, the system clock may be tied to the Falign pin
to satisfy the requirements of the Watch-Dog
Timer.
A Watch-Dog Timer protection feature is built into
the control logic to monitor the Falign pin for a
clocking signal. This circuitry, shown in Figure 2-3
will prevent start up the device if the Falign clock
is not present.
2.3 Resynchronization
If power is momentarily lost, the sequencer can
automatically resynchronize to the monitored
10/31
L6238S
Bemf. This resychronization can either occur
whenever Output Enable or Run/Brake is first
brought low then high.
Figure 2.2
Referring to figure 2-4, the ”Hold for Resync”
state is brought low. The controller leaves this
state and enters ”Start Resync” when Output En-
able is high.
POR=0
FROM ANY STATE
STATE=1
DRIVERS ON
PERIOD STOP
DELAY STOP
MASK STOP
RUN/BRK=0
FROM ANY STATE
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
DELAY STOP
MASK STOP
Figure 2.3: Watch-Dog Timer
64/FALIGN
RUN/BRAKE=1
CHECK FOR Zc
192/FALIGN
OVER TEMP SHUTDOWN
DRIVERS OFF
MIN CLOCK DELAY
LOAD MIN DELAY
LOAD MIN MASK
PERIOD STOP
DELAY COUNT
STATE=STATE+1
MASK COUNT
STATE=STATE+1
LOAD DELAY=MIN
LOAD MASK=MAX
PERIOD COUNT
DELAY COUNT
STATE=STATE+1
MASK COUNT
BEMF
OUTENA=1
BEMF
S
TO START-UP
LOGIC
CHECK FOR Zc
Q
Q
DRIVERS ON
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT
221
SYS_CLK
BEMF
S
D95IN310
BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0
BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1
***MIN MASK=192/SYS_CLK (I.E. WITH SYS_CLK=10MHz, MIN MASK=19.2µs)
D95IN311
OUTPUT
ENABLE
RUN/
BRAKE
FALIGN
Figure 2-4
LOAD MIN DELAY
LOAD MIN MASK***
DELAY COUNT
STATE=STATE+1
MASK COUNT
BEMF
OUTENA=1
BEMF
CHECK FOR Zc
BEMF
LOAD DELAY=MIN
LOAD MASK=MIN
PERIOD COUNT
DELAY COUNT*
STATE=STATE+1
MASK COUNT
BEMF
RUN/BRK=0
OUTENA=1
DRIVERS OFF
MONO=0**
BEMF
DRIVERS ON
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAYH COUNT*
STATE=STATE+1
MASK COUNT
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
OUTENA=0
BEMF
RUN
MODE
HOLD FOR RESYNC
RESYNCHRONIZATION MODE
D95IN312
*CLOCK DELAY=(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES)
BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0
BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1
** MONO=0 WHEN FREQ (BEMF)=2*FREQ(PHASE)
*** MIN MASK=192/SYS_CLK(I.E.WITH SYS_CLK=10MHz, MIN MASK=19.2µs)
11/31
L6238S
Figure 2-5
POR=0
FROM ANY STATE
STATE=1
DRIVERS OFF
MIN CLOCK DELAY
PERIOD STOP
DELAY STOP
MASK STOP
SEQINC=1 &
OUTENA=0
RUN/BRK=X
INT START-UP DISABLED
MIN CLOCK DELAY
LOAD MIN DELAY
LOAD MIN MASK
RUN/BRK=1 &
OUTENA=1
DRIVERS ON
PERIOD COUNT
DELAY COUNT
SEQINC=0
SEQINC=1
STATE=STATE+1
MASK COUNT
MASK COUNT
BEMF
BEMF
SEQINC=0
SEQINC=1
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT**
SEQINC=1
STATE=STATE+1
FROM ANY STATE
WITH SEQ_INC=0
RETURN TO
PREVIOUS STATE
(CHANGING SEQINC=1)
D95IN313
*VALID IF SEQINC=0, AND DELAY TIMES OUT
**CLOCK DELAY=F(TDLY_[2:0])
WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES)
CREMENT pin. During the time that this pin is
high, all Bemf information is masked out. When it
is low, the Bemf information can be detected nor-
mally after the internal mask time. The minimum
mask time is 192/Sys_Clk (i.e. with Sys_Clk =
10MHz, min. mask = 19.2µs) Therefore to insure
that the sequencer is under complete control of
the state machine, the time that the SEQUENCE
INCREMENT pin is held low should be much less
then the min. mask time, but greater then 1µs.
If zero crossings are detected, the sequencer will
automatically lock on to the proper phase.
This resynchronization will take effect with the
motor speed running as low as typically 30% of
it’s nominal value.
2.5 External Sequencing
Although the user-defined Start-Up Algorithm is
flexible and will consistently spin up a motor with
no external interaction, the possibility exists
where certain applications might require complete
microprocessor control of start-up.
The L6238S offers this capability via the SE-
QUENCE INCREMENT input. Referring to figure
2-5, during initial power-up with Output Enable
low, the controller is in the ”Hold and Wait for De-
cision” state. If the SEQUENCE INCREMENT pin
is brought high during this state, the Auto StartUp
Algorithm is disabled and the sequencer can be
controlledexternally.
When the motor has reached a predetermined
speed, the SEQUENCE INCREMENT pin can be
left low and the L6238S Motor Control logic will
take over and automatically spin up the motor to
the desired speed
.
3.0 START-UP ALGORITHMS
3.1 Spin-Up Operation
The spinoperation can be separated into 3 parts:
1) Open Loop Start-Up - The object is to create
motion in the desired direction so that the Bemf
voltages at the 3 motor terminals can provide reli-
able information enabling a transition to closed
loop operation.
When Output Enable and Run/Brake are
brought high, the sequencer is incremented on
each positive transition o the SEQUENCER IN-
12/31
L6238S
Figure 3-1: Align+Go
RUN/BRAKE
SEQUENCER
ALIGNMENT
GO
DOUBLE INCREMENTS
*2.133s
*0.711s
A
OUT
10V
1
2
3
B
OUT
10V
C
OUT
10V
STATE 4
STATE 6
A=FLOAT
B=LOW
A=LOW
B=HIGH
C=FLOAT
STATE 2
A=HIGH
B=FLOAT
C=LOW
C=HIGH
D95IN314
* FALIGN=90Hz
500ms/DIV
per drivers are OFF.
2) Closed Loop Start-Up - The Bemf voltage
zerocrossings provide timing information so that
the motor can be accelerated to steady state
speed.
3) Steady-State Operation - The Bemf voltage
zero-crossings provide timing information for pre-
cision speed control.
The L6238S contains features that offer flexible
control over the start-up procedure. Either the on-
board Auto-Start Algorithm can be used to control
the start-up sequence or more sophisticated ex-
tenal start-up algorithms can be developed using
the Serial Port and key control/sense functions
brought out to pins.
The Auto-Start Algorithm is based on an Align &
Go approachand can be visualized by referring to
Figure 3-1. Shown are the Run/Brake control sig-
nals, sequencer function, and the three output
voltage waveforms.
Referring to figure 3-1, the following is the se-
quence of events during Auto-Start:
With Output Enable = 1, Run/Brake = 0
- State Machine is set to State 1 with the drivers
Trisatted.
Alignment Phase (1)
Run/Brake = 1
- Output Stage is sequenced to State 2 and the
drivers energized with OUTPUT A high and
OUTPUT C low for 64/Falign seconds.
3.2 Auto-Start Algorithm
When initially powered up, the controller defaults
to the internal AutoStart Mode. When Run/Brake
is low, the L6238S is in brake mode, and the
Auto-Start Algorithm is reset. In the brake mode,
all of the lower DMOS drivers are ON, and the up-
Alignment Phase (2)
- Output Stage is double sequenced to State 4
with OUTPUT B high and OUTPUT A low for
13/31
L6238S
192/Falign seconds.
The Auto-Start algorithm described earlier is an
Align & Go approach. The main advantages of
the integrated Auto-Start are that the µP is not in-
volved real-time, and there are a minimum of in-
terface pins required to the spindle control sys-
tem.
- During the alignment phase, the SEQ INCRE-
MENT signal is ignored.
Go Phase
- The internal sequencer double increments the
output stage to State 6, which should produce
torque in the desired direction.
- with SEQ INCREMENT held low, the se-
quencer is now controlled by the Bemf zero
crossings, and the motor should ramp up to
speed.
Stepper Motor Approach This approach mini-
mizes backward rotation by sequencing SEQ
INCR at an initial rate that the rotor can follow.
Thus, it is driven in a similar fashion to a stepper
motor. The rate is continually increased until the
Bemf voltage is large enough to reliably use the
zero-crossings for commutation timing. SEQ
INCR is held low, causing control to be passed to
the L6238S’sinternal sequencer as in the Align &
Go approach.
3.3 Externally Controlled Start-Up Algorithms
Enhanced Start-Up Algorithms can be achieved
by using a µProcessor to interact with the
L6238S.’ The L6238S has the ability to transition
to Closed Loop Start-Up at very low speeds, re-
ducing the uProcessor task to monitoring status
rather than real time interaction. Thus, it is a per-
fect application for an existing µProcessor.
The Stepper Motor approach takes longer than
the Align & Go approach because the initial com-
mutation frequency and subsequent ramp rate
must be low enough so that the motor can follow
without slipping. This implies that to have a reli-
able algorithm, the initial frequency and ramp rate
must be chosen for the worst case motor under
worst case conditions.
The following control and status signals allow for
very flexible algorithm development:
SEQ_INCR A low to high transitionat thisinput
is used to increment the state of the power out-
put stage. It is useful during start-up, because
the µProcessor can cycle to any desired state,
or cycle through the states at any desired rate.
When held high, it inhibits the BEMF zero
crossings from incrementing the internal se-
quencer.
4.0 MOTOR DRIVER
4.1 Output Stage
The output stage forms a 3-Phasefullwave bridge
consisting of six Power DMOS FET High output
currents are allowed for bbrief periods. High out-
put currents are allowed for brief periods. Output
Power exceeding the stand-alone power dissipa-
tion capabilities of the L6238S can be increased
with the addition of an external P-FET or by the
use of Pulse-Width-Modulation.
SPIN SENSE This output is low until the first
detected Bemf zero crossing occurs. It then
toggles at each successive zero crossing. This
signal serves as a motion detector and gives
useful timing information as well as the slope
of the Bemf.
Table 4-1 is a reference diagram that lists the pa-
rameters associated with 8-pole motors operating
at 3600 and 5400 RPM.
Figure 4-1 represents the waveforms associated
with the output stage. The upper portion of figure
4-1 shows the flow of current in the motor wind-
ings for each of the 24 phase increments. A rota-
tional degree index is shown as a referencealong
with a base line to indicate the occurrence of a
zero crosing. The output waveforms are a digitally
reproduced voltage signals as measured on sam-
ples.The feedback Input is multiplexed between
the internal Bemf Zero Crossing Detector and an
externally provided sync pulse (EXT INDEX)
3.4 Start Up Approaches
Align & Go Approach The Align & Go approach
provides a very time efficient algorithm by ener-
gizing the coils to align the rotor and stator to a
known phase. This approach can be achieved via
the sequencing SEQ INCR. SPIN SENSE can be
monitored to assure that motion occurred. Once
ample time is given for alignment to occur, SEQ
INCR can be double incremented, and the SPIN
SENSE pin can be monitored to detect motion.
Shown in figure 10 is the classical state diagram
for a phase detector along with waveform exam-
ples.
When SEQ INCR is pulled low, control is trans-
ferred to the internal sequencer, and the L6238S
finishes the spinup operation. If no motion is de-
tected, SEQ INCR can be incremented to a differ-
ent phase and the process can be repeated. The
alignment phase may cause backward rotation,
which on the average will be greater than the
StepperMotor approach.
A typical sequence starts when the outputs
switch states. Referring to figure 4-1, during
phase 1, output A goes high, while outputB is low.
During this phase, output C is floating, and the
Bemf is monitored. The outputs remain in this
state for 60 electrical degrees as indicated by the
first set of dashed lines. After this period the out-
14/31
L6238S
Table 4-1
Rotational Speed
Rotational Frequency
Rotational Period
Electrical Period
Phase Period
3600rpm
60Hz
5400rpm
90Hz
16.667ms
4.167ms
694.5µs
11.111ms
2.778ms
463.0
Figure 4-1: Waveforms
15/31
L6238S
put switched to phase 2 with output A high and C
low with the Bemf amplifier monitoring output B.
torque. The spin sense waveform at the bottom of
the figure indicates that this output signal toggles
with each zero crossing.
In order to prevent commutation current noise be-
ing detectedm as a false zero crossing, a mask-
ing circuit automatically blanks out all incoming
signals as soon as a zero crossing is detected.
When the next commutation occurs an internal
counter starts counting down to set the time that
the masking pulse remains.
The counter is initially loaded with a number that
is equal to time that is always 25% of the previous
phase period or 15 electrical degrees. The time-
out of the masking pulse shown for reference at
the bottom of figure 4-1. Thus the actual masking
period is the total of the time from the detected
zero crossing to the phase commutation, plus
25% of the previous period. The mask pulse op-
eration is further discussed in section 4.6, Slew
Rate Control and PWM operation.
4.2 Brake Delay
When Run/Brake is brought low, a brake is initi-
ated. Referring to figure 4-2, SW1 is opened and
the brake delay capacitor, Cbrake, is allowed to
discharge towards groun via Rbrake
.
At the same time, switches SW2 through SW7
bring the gates of the output FETs to ground halt-
ing conduction, causing the motor to coast. While
the motor is coasting, the Bemf is used to park
the heads. When Cbrake reaches a voltage that
is below the turn ON threshold of Q1, Switches
SW8, 9, and 10 bring the gates of the lower driv-
ers to Vbrake potential. This enables the lower
FETs causing a braking action.
After the masking period, the Bemf voltage at out-
put B is monitored for a zero crossing. Upon de-
tection of the crossing, the output is commutated
after the selected phase delay insuring maximum
The analog and logic supplies are not monitored
in the L6238S, since the L6244 already monitors
this voltage and initiates a Park function when
either supply drops to a predeterminated level.
Figure 4-2
16/31
L6238S
Figure 4-3
4.3 Charge Pump
A capacitor, Cpump, is used to retrieve energy
from the analog supply and then ”pumps” it into
The charge pump circuitry is used as a means of
doubling the analog supply voltage in order to al-
low the upper N-channel DMOS transistors to be
driven like P-channel devices. The energy stored
in the reservoir capacitor is also used to drive the
lower drivers in a brake mode if the analog supply
is lost. Figure 4-3 is a simplified schematioc of the
charge pump circuitry.
the storage capacitor, Cresvr
.
An internal 300KHz oscillator first turns ON Q2 to
quickly charge Cpump to approximately the rail
voltage. The oscillator then turns ON Q1 while
turning OFF Q2. Since the bottom plate of Cpump
,
is now effectively at the rail voltage via D2.
A zener-referencedseries-pass regulator supplies
Figure 4-4
OUTPUT
VPOWER
B
C
VPUMP
L1
L2
SW2
1
0
UPPER A
Q1
Cfet
VCTRL
+
-
L3
A2
I1
Islew
SW3
OUTA
1
0
LOWER A
Q2
RSENSE
Cfet
I2
Islew
A3
CSA
RS
X4
VANALOG
Q3
Q4
Q5
PWM SLEW/RC
RSLW
SLEW RATE
REFERENCE CURRENT
3.1V
D95IN315
17/31
L6238S
a voltage, Vbrake, during brake mode.
The pole/zero locations are adjusted such that a
few dB of gain (typ. 20dB) remains in the tran-
sconductance loop at frequencies higher than the
zero.
The maximum capacitance specified for the Stor-
age Capacitor is 4.7µF.For applications requiring
a larger value, an external diode should be con-
nected between Vanalog and the Storage Ca-
pacitor to prevent excessive inrush current from
damaging the charge pump circuitry. A small
value resistor (i.e. 50W) may instead be inserted
in series with the Storage Capacitor to limit the in-
rush current.
The inductive characteristic of the load provides
the pole necessary for loop stability. Thus the
loop bandwidth is actually limited by the motor it-
self.
Figure 4-5 shows the complete transconductance
loop including compensation, plus the response.
The Bode plot depicts the normal way to achieve
stability in the loop. The pole andzero are used to
set a gain of 20dB at a higher frequency and the
pole of the motor cuts the gain to achieve stabil-
ity.
4.4 Linear Motor Current Control
The output current is controlled in a linear fashion
via a transconductance loop. Referring to Figure
4-4 the sourcing FET of one phase is forced into
Loop instability may be caused by two factors:
full conduction by connecting the gate to Vpump
,
while the sinking transistor of an appropriate
phase operates as a transconductance element.
To understand the current control loop, it will be
assumed that Q2 in figure 4-4 is enabled via SW3
by the sequencer. During a run condition, the cur-
rent in Q2 is monitored by a resistor Rs connected
to the Rsense input.
The resulting voltage that appears across Rs is
amplified by a factor of four by A3 and is sent to
A2 where it is compared to the Current Command
Signal. A2 provides sufficient drive to Q2 in order
to maintain the motor speed at the proper level as
commanded by the Speed Controller.
1)The motor pole is too close to the zero. Refer-
ring to figure 4.6, the zero is not able to dec-
rement the shift of phase, and when the effect
of the pole is present, the phase shift may
reach 180° and the loop will oscillate. To rec-
tify this situation, the pole/zero must be
shifted at lower frequencies by increasing the
compensationcapacitor.
Figure 4-6
4.5 Transconductance Loop Stability
The RC network connected to the Compensation
pin provides for a single pole/zero compensation
scheme. The pole/zero compensation scheme.
Figure 4-5
Figure 4-7
18/31
L6238S
turbance when one motor phase turns OFF and
another turns ON because the FET turn-OFF time
is much shorter than the L/R rise time. Abrupt
FET turn-OFF without a proper snubbing circuit
can even cause current recirculation back into the
supply.
Figure 4-8
However, the need for a snubber circuit can be
eliminated by controlling the turn-OFF time of the
FETs.
The rate at which the upper and lower drivers turn
OFF is programmable via an external resistor,
Sslew connected to the SLEW RATE pin. This re-
sistor defines an internal current source that is
utilized to limit the voltage slew rate at the outputs
during transition, thus minimizing the load change
that the power supply sees.
To insure proper operation the range of resistor
values indicated should not be exceeded and in
some applications values near the end points
should be avoided as discussed below.
Low Values of Rslew - If a relativelylow value of
Rslew is selected, the resultant fast slew rate will
result in increased commutation cross-over cur-
rent, higher EMI, and large amount of commuta-
tion current.
2)The motor capacitance, CM, itself can inter-
fere with the loop, creating double poles. If
the gain at higher frequencies is sufficiently
high, the double pole slope of 40dB/decade
can cause the phase shift to reach 180°,
re sulting in oscillation.
This last case can cause voltage spikes at the
output that can go as much as lV below ground
level. This situation must be avoided in this inte-
grated circuit (as in most) since it causes unpre-
dictable operation.
Figure 4-8 is a Bode plot showing how to correct
this situation. The bold line indicates the response
with relatively high gain at the higher frequencies.
By leaving the pole unchangedand increasing the
zero, the response indicated by the dashed lines
can be achieved.
High Values of Rslew - Higher values of Rslew
result of course in slow slew rates at the outputs
which is, under most conditions, the desired case
since the problems associated with fast rates are
reduced. The additional advantage is lower
acoustical noise.
4.6 Slew Rate Control
A 3-phase motor appears as an inductive load to
the power supply. The power supply sees a dis-
Problems can occur though if the slew rate for a
Figure 4-9: Effect of Slow Slew Rate.
19/31
L6238S
Figure 4-10: External P-Fet.
given application is too slow. Figure 4-9 is an os-
cillograph taken on a device that had a fairly large
value for Rslew and failed to spin up and phase
lock a motor.
The problem manifests itself as the motor begins
to spin up. At lower RPMs, the Bemf of the motor
is relatively small resulting in higher amounts of
commutation current. In figure 4-9, the upper
waveform is the voltage appearing at OUTPUT
relative to the CENTER TAP input. The lower
waveform is the actual output of the Bemf ampli-
fier available on special engineering prototypes.
Figure 4-10 shows the Ext FET connection and
demonstrates how the L6238S automatically
senses the FETs presence. When the voltage at
the Gate Drive pin is ≥ 0.7V, the output of com-
parator A3 goes high, removing the variable drive
A1 from the internal FETs and connects them in-
stead to Vanalogvia the commutation switches to
facilitate full conduction.
The upper FETs drive paths are not shown for
clarity. A3 also closes SW2 allowing A1 to linearly
drive the external P-Channel FET Q1 via inverter
A2.
The oscillograph was taken just as the problem
occured. The period between zero crossings was
~800µs resulting in a mask time period of 200µs.
As can be seen, the excessively long slew rate
actually exceeded the mask period and was de-
tected as a zero crossing.
This resulted in improper sequencing of the out-
puts relative to the proper phases and caused the
motor to spin down.
4.8 Bemf Ampolifier
Since no Hall Effect Sensors are required, the
commutation information is derived from the Bemf
voltage zero-crossings of the undriven phase with
respect to the center tap. The Bemf comparator
and associated signal levels are depicted in figure
4-11. For reliable operation, the Bemf signal am-
plitude should be a minimum of ± 60 mV to be
properly detected. In order to provide for noise
immunity, internal hysteresis is incorporated in
the detection circuitry to prevent false zero cross-
ing detection.
4.7 Ext PFET Driver
The power handling capabilities of the 3 phase
output stage can be extended with the addition of
a single P-ChannelFET.
For laboratory evaluation purposes, a simple re-
20/31
L6238S
Figure 4-11: Bemf Amplifier.
VoBEMF
ViBEMF(mV)
-35
-25
0
25
35
D95IN316
SLOPE=0
SLOPE=1
sistive network as shown in figure 4.12 can be
used to emulate the Bemf of the motor.
will not be optimal until the desired commutation
interval is less than the dynamic range of the
counter.
The actual Bemf zero-crossing is 30 electrical de-
grees (50% of a commutation interval) away from
the optimal switch point. A digital counter circuit
measures 50% of the previous interval to deter-
mine the next interval’s commutation delay from
the zero crossing. During the low RPM stages of
start up the long commutation intervals may
cause the counter to overflow, in which case 50%
of the max count will be less than 50% of the
ideal commutation interval. Therefore, the torque
4.9 Center Tap Protection
Spindle Motors with a high number of windings
exhibit a transformer coupling effect that in some
cases can cause relatively high currents to flow
through the center tap input.
Current flowing out of the center tap pin as high
as 25mA has been observed with certain motors.
Figure 4-12: Bemf Emulator
Figure 4-13
TO CENTER
TAP INPUT
R1 1K
DS1
D95IN317
21/31
L6238S
The high current flows from the grounded sub-
strate of the integrated circuit (p-type material),
through one or more epitaxial pockets(n-type ma-
terial) and out the center par pin.
When the motor current reaches this commanded
level, the output drivers turn OFF and remain
OFF for a Constant-OFF time. After this OFF time
the drivers turn back ON to repeat the cycle.
This current can cause adverse operation of the
controllet due to substrate injection and might
possibility damage the internal metalization runs.
The normal current for this input is in the 200µA
range.
Figure 5.1 is a block diagram of the PWM control
circuitry. When using PWM as opposed to linear
control, two changes are made to the control
loop:
Referring to figure 4-13, a simple protection
scheme consisting of a 1K resistor and a low cur-
rent Schottky diode should be added if the appli-
cation causes excessive current (i.e. >1mA) to
flow through the center tap pin.
1.The slew rate control is disabled, allowing the
outputs to slew at a minimum rate of 10V/µs.
This is accomplished by closing SW3 and
SW5.
2.The OTA amplifier is taken out of the control
loop via SW6. The lower drivers are now
driven into hard conduction by tying the gates
to the analog supply during the On time of the
PWM cycle.
5.0 PWM MOTOR CURRENT CONTROL
A unique feature of the L6238S in the optional
Pulse Width Modulation (PWM) control of motor
current.
Using Variable-frequency, Constant-OFF time
Current-Mode control, the L6238S can drive
higher power motors without the need for external
drivers, while minimizing internal power dissipa-
tion.
The current in the motor windings is monitored via
the voltage dropped in the sensing resistor,
Rsense
.
This voltage is multiplied by a factor of 4 in the
Current Sense Amplifier (CSA) and sent to nega-
tive input of the PWMComparator (A2).
Additional benefits include reduced power supply
consumption (up to 50% savings) and lower watt-
age requirements for the current sensingresistor.
Constant-OFF time Current-Mode control, oper-
ates on the principle of monitoring the motor cur-
rent and comparison it to a reference or control
level.
The control voltage, Vcontrol, is applied to the posi-
tive input of A2. When the output of the CSA
reaches a level that is equal to the commanded
level, the output of A2 switches low, toggling the
latch comprised of N1 and N2. This causes the
upper drivers to turn off and opens SW1. Q3 turns
OFF allowing the Constant-OFF time capacitors,
Figure 5-1
OUTPUT
VPOWER
B
C
VPUMP
VANALOG
SW2
L1
L2
UPPER A
1
0
Q1
Q2
N3
Q4
Cfet
PWM/LIN
CONTROL
SW3
I1
Islew
SLEW RATE
REFERENCE
CURRENT
L3
Q3
SW1
OUTA
LOWER A
SW4
1
0
Q5
3.1V
RSENSE
Cfet
SW5
I2
Islew
VANALOG
A3
PWM/SLEW
SW6
1
0
+
-
A1
N1
N2
1.2V
FROM TRANS. LOOP
+
VCTRL
CSA
A2
-
X4
RSLEW
COFF
CSA
RSLW
D95IN318
22/31
L6238S
Coff to discharge to dischargte through Rslew, initi-
ating the Constant-OFF time-out. When the volt-
age on Coff reaches 1.2V, comparator A1switches
state toggling the latch in the opposite state, turn-
ing the upper driver back ON. SW1 also closed
quickly charging up Coff for the next cycle.
Figure 5-2
VPOWER
Q1
Q3
Q4
D1
D3
5.1 PWM Design Considerations
In order to select the parameters associated with
PWM operation, the following factors must be
taken into consideration:
1. PWM Switching Frequency
2. Duty Cycle
L1
L2
OUTPUTA
D2
OUTPUTB
D4
Q2
3. Motor Currents
4. Minimum ON Time
5. Noise Blanking
RSENSE
RSNS
6. Bemf Masking/Sampling
D95IN319
5.1.1. PWM Switching Frequency
The PWM switching frequency Fpwm is found
from:
Figure 5-3
VPOWER
1
Fpwm
=
(5.1.1)
T
on + Toff
Q1
Q3
Q4
where:
D1
D3
Ton = The time required for the motor current
to reach the commanded level.
Toff = The programmedOFF time.
L1
L2
The two main considerations for this parameter
are the minimum and maximum switching fre-
quency.
OUTPUTA
D2
OUTPUTB
D4
Q2
The maximum switching frequency occurs during
the Start-up and should be kept below 50KHz due
tointentional bandwidth limitations and output
switching losses.
RSENSE
RSNS
D95IN320
5.1.2 Duty Cycle
Besides reducing the power dissipation of the
controller output stage, running in PWM offers 2
additional ”free” benefits:
for both the Power Supply and the Power Rating
for the sensing resistor.
A. Reduced Powe Supply Current at Start Up
5.1.3 Motor Currents
B. Lower PowerRating for the Motor Current
SenseResistor.
Note: It is not the objective of thissection to describe the principles
of brushless DCmotor, but to provide sufficient informationabout the
parameters associated with PWM operation in order to optimize an
application.
Figure 5-2 is the current path during the ON time
of a phase period. The current from the supply
passes through the upper sourcing DMOS, Q3
transistor through the two driven winding, the
lower DMOS, Q2 and finally through the current
sensing resistor Rsns. Since both Q3 and Q4 are
ON, while Q3 is turned OFF. The voltage, causing
the current to continue to flow through Q2, and
Q4.
If the duty cycle is nearor at 50%, then for 1/2 the
PWM cycle, no current is flowing from the power
supply or the sense resistor while current is still
flowing in the motor. This lowers the requirement
A simplified model of a motor is shown in figure 5-
4. For this discussion, lower order effects due to
mutual inductance between windings, resistance
due to losses in the magnetic circuit, etc. are not
shown.
The motor at stall is equal to a resistance, Rmtr,
in serieswith an inductance, Lmtr. When the mo-
tor is rotating, there is an induced emf that ap-
pears across the armaure terminals and is shown
in figure 5-4 as an internally generated voltage
Ibemf), Eg.
23/31
L6238S
The additional resistance associated with the out-
put stage and sensing resistor are also in series
with the motor. If we let Rs equal the total series
resistence:
Figure 5-4
Lmtr
Rmtr
Rs = 2*RdsON + Rmtr + Rsense
(5.1.5)
then (5.1.4) becomes:
dimtr
+
-
Eg
D95IN321
V = L
Rs imtr + Eg
(5.1.6)
mtr
dt
The relation between these variables is given by:
dimtr
Figure 5-6
V = L
R
i
mtr mtr + Eg
(5.1.2)
mtr
dt
where:
V
Lmtr
=
=
=
Applied Voltage
Motor Current
imtr
Rmtr
-
Lmtr
Total inductance of the motor
windings
KEW
Rmtr
Eg
=
=
Resistance in series with the motor
+
The internally generated voltage of
the motor, proportional to the motor
velocity
LOWER
Rdson
LOWER
Rdson
D95IN323
Since:
Eg
= KEω
(5.1.3)
Figure 5-6 is an equivalent circuit of the output
stage during the Constant-OFF period. During the
OFF time the lower driver for the particular phase
beign driven remains ON.
The internally generated voltage forces the path
of current though the motor, its series resistance,
the RdsON of the Lower Driver and finally through
the opposite lower driver.
The above equations can be combined to form
the basic electrical equation for a motor:
dimtr
dt
V = L
R
i
mtr mtr + KEω
(5.1.4)
mtr
Figure 5.5 is a simplified electrical equivalent of
the output stage of the L6238S along with the
model of the motor during the time that the Out-
put Drives are conducting.
PWM Example (Refer to Figure 5-7)
The following is an example on how to select the
timing parameters.
Figure 5-5
Given:
UPPER
Rdson
DCStart Current
Ripple Current
=
=
=
=
=
1.25A
100mA
50%
Lmtr
Rmtr
Duty Cycle
Motor Interface (L)
Total Series Resistance (Rs)
880µH
4.8Ω
+
KEW
-
LOWER
Rdson
If the worst case start current is 1.25A and the
duty cycle is 50%, then the Peak Current, It will
be:
0.1
it = 1.25+
2
Rsense
D95IN322
it = 1.30A
24/31
L6238S
the voltage drop remains constant across the
windings.
The Valley current, Ib will thereforebe:
The time required for the inductor current to reach
the valley current is given by:
ib = 1.30 - 0.1A
ib = 1.20A
I
Ib
L
R
t
toff
=
ln
(5.1.9)
During the Align and Go Phase (where the power
dissipation requirements are highest, Eg is zero.
The initial time required to reach the Peak current
is:
Substituting values:
880e±6
4.8
1.3
1.2
toff
=
ln
± L
R
I,R
V
tinit
=
ln 1 ±
(5.1.7)
toff = 14.67µs
Substitutingvalues:
Note: that the parameters for this example were selected to arrive at
a 50%duty cycle. This will notalways be the case due tofactors such
as fixed motor parameters, etc.
± 880e ± 6
1.3 4.8
12
tinit
=
ln 1 ±
The Constant Off timer period can be determined
from:
4.8
t
init = 134.6µs
Vchrg
Vtrip
The ON time can be calculated from:
t
off = Rslew Coff ln
(5.1.10)
V
Rs
V
Rs
± ib
Where:
L
Rs
ton
=
ln
(5.1.8)
Toff
=
Constant-OFF Time
Slew Rate Resistor
Off Time Capacitor
± it
Rslew
Coff
=
=
=
=
Substitutingvalues:
Vchrg
Vtrip
Initial Capacitor Charge Voltage
Capacitor Lower Trip Threshold
12
4.8
12
± 1.2
± 1.3
880E ± 6
ton
=
ln
4.8
Substituting nominal valuesgiven:
Toff = 0.75 Rslew Coff
4.8
t
on = 14.67µs
Solving for Coff
Toff
Figure 5-7
D95IN324
Coff
=
0.75Rslew
It=1.3A
In the example, to set the OFF timer for a 50%
duty cycle:
Ib=1.2A
Given:
Toff
=
=
14.67µs
Iavg=1.25A
Rslew
100KΩ (typical Value)
14.67e±6
100e3
Coff
=
Iout A
200mA
4
Coff ≈ 146pF
20µs/DIV
5.1.4 Minimum ON Time
The bandwidth of the PWM loop was optimized to
reject unwanted switching noise while providing
During the OFF time, the motor current continues
to flow through the DMOS transistors and threfore
25/31
L6238S
sufficient response, commensurate with the
switching speed of the output drivers. At higher
frequencies the switching losses inherent in the
drivers start to negative any of the power dissipa-
tion savings gained with PWM operation.
Figure 5-9 is an additional block diagram of the
PWM control loop including the noise blanking cir-
cuit. The output of A3 goes high when ever the
voltage at the CSA input is more positive then the
Control Voltage.
The current sense amplifier has a minimum slew
rate of 0.31V/µs. With a worst case Motor peak
start-up current of 2.5A and Sense Resistor of
0.33, the resultant Rsense voltage would be equal
to 825mV. With a minimum gain of 3.8V/V, the
CSA output voltage would have to slew to 3.14V.
Therefore it would require approximately 10µs for
the output voltage to reach the required com-
manded level.
If an ON time were selected that was less than
this time, the motor current would overshoot the
desired level resulting in incorrect current control
possibly exceeding the output capabilities of the
drivers.
This is the case when either the motor current or
the turn-ON transient has reached the com-
manded level. The output of A3 is gates by N11.
In order to provide a blankingperiod, Q1 is turned
Figure 5-8
D95IN325
3µs BLANKING PULSE
COMMANDED
CURRENT LEVEL
5.1.5 Noise Blanking
Vrsense
Referring to Figure 5-8, when operating with
lower levels of current (i.e. < 700mA, with Rsense
= 0.33Ω), the possibility exiss where the noise
due to output Turn-ON can exceed the Com-
manded Current Level causing prematire Turn-
OFF.
1
In order to provide noise immunity from this
switching noise, a blanking circuit automatically
rejects any signal appearing at the output of the
CSA for a 3µs period.
10µs/DIV
Figure 5-9
2.4V
SW1
N12
N1
Q3
PWM_SLEW
Q1
+
C1
N6
N7
A2
N9
-
1.2V
R1
8pF
C3
I1
5µA
X4
CSA INPUT
N8
N10
+
N11
A3
-
VCONTROL
PWM COMP
PWM TIMER
DELAY
N3
I2
20µA
TO OUPUT
DRIVERS
CLK_BEMF
N2
N4
N5
Q2
C4
PWM/LIN
N12
D95IN326
RUN/BRAKE
26/31
L6238S
ON during the Constant-OFFtime, charging C1 to
the internal rail. At the end of the OFF time, Q1 is
turned OFF allowing current source I1 to dis-
charge the capacitor towards ground. While the
voltage on C1 is above the low input threshold of
N1, the output of N1 is low, preventing any
change of state at the output of N11 due to a high
A3 output. When the capacitor reaches the low in-
put threshold of N1, N1 chnges state allowing A3
to control the state of N11.
smpled, preventing further commutation of the
output.
The PWM Limit Timer is used to set up a maxi-
mum ON time. When this limit is exceeded the
method of sensing the bemf is essentially the
same as in the case of operating in linearmode.
Figure 5-10 is an oscillograph of the controller op-
erating in PWM mode. The top trace is Aout. The
2nd trace is the voltage seen at the PWM/SLEW
pin indicating the exponential discharging of the
timing capacitor during the OFF time. Trace 3 is
the voltage appearing on the PWM Timer capaci-
tor, while trace 4 is the motor current.
Referring again to Figure 5-9, and 5-10 transistor
Q2 is turned ON at the beginningof the OFF time,
discharging the external capacitor C4 to near
ground level. At the end of the OFF-Time, Q2 is
turned off and C4 starts charging linearly via I2.
C4 is again discharged at the beginning of the
OFF time and the cycle repeats. As long as C4
does not reach the threshold of A1 (typically
3.5V), the bemf is only sampled just before turn-
off of the output. As the motor is starting up in fig-
ure 5-10, the duty cycle is roughly 50%. The
PWM limit timer is reset to ground by the start of
the OFF timer before reaching the 3.5V threshold.
In figure 5-11, as the motor spins up, the on time
of the output increases and the PWM limit timer
reaches the 3.5V. Eventually the duty cycle
reaches 100% and the sampling of the bemf is
essentially the same as in the linear mode.
The selectionof componentsfor the PWMtimer is
not critical. Since the objective is to sample the
bemf only at turn OFF to maximize the signal to
noise ratio, the PWM timer slope can be set up to
convert to the full bemf sampling after a few revo-
lutions of the motor when the bemf has reached
an appropriatevoltage output.
5.1.6 Masking/Bemf Sampling in PWM
The method of sampling the floating phase for the
bemf zero crossing defers between Linear and
PWM operation. In Linear Mode, the bemf is sam-
pled continuously after the mask time-out, until
the zero crossing is detected. Then the mask is
enabled for a time based on the commutation
phase delay plus the additional time based on the
previous period as explained earlier.
With PWM operation however, the switching
noise at turn ON (after the Constant-OFF time)
can be significant, especially at low RPMs where
the bemf is the lowest. In order to provide the
greatest noise immunity in PWM, the floating
phase is monitored only at the point where the
output is about to be turned OFF.
In operation, when the motor current reaches the
commanded level, the floating phase is first moni-
tored to determine if the bemf has crossed the
zero. The output is then turned OFF for the Con-
stant-OFF time out.
As the motor current increases through, the in-
creasing bemf causes the motor current to natu-
rally decrease. Eventually a point is reached
where the PWM is running at 100% duty cycle
and the motor current cannot reach the com-
manded level. At this time the bemf is no longer
Figure 5-10
Figure 5-11
D95IN327
D95IN328
Aout
Aout
10v
10V
1
1
PWM/Slew
PWM/Slew
2V
2
2V
2
PWM Limit
PWM Limit
Timer
Timer
500mV
500mV
3
3
Iout A
Iout A
Fpwm=50KHz
Coff=120pF
Ctmr=220pF
Fpwm=12KHz
Coff=120pF
Ctmr=220pF
1A
1A
4
4
20µs/DIV
50µs/DIV
27/31
L6238S
PLCC44 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
17.4
16.51
3.65
4.2
TYP.
MAX.
17.65
16.65
3.7
MIN.
0.685
0.650
0.144
0.165
0.102
MAX.
0.695
0.656
0.146
0.180
0.108
A
B
C
D
4.57
2.74
d1
d2
E
2.59
0.68
0.027
14.99
16
0.590
0.630
e
1.27
12.7
0.46
0.71
0.050
0.500
0.018
0.028
e3
F
F1
G
0.101
0.004
M
M1
1.16
1.14
0.046
0.045
28/31
L6238S
PQFP44 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
MIN.
MAX.
A
A1
A2
B
3.40
0.134
0.25
2.55
0.010
0.100
0.0138
0.005
0.667
0.547
2.80
3.05
0.50
0.110
0.120
0.0197
0.009
0.687
0.555
0.35
C
0.13
0.23
D
16.95
13.90
17.20
14.00
10.00
1.00
17.45
14.10
0.677
0.551
0.394
0.039
0.677
0.551
0.394
0.0315
0.063
D1
D3
e
E
16.95
13.90
17.20
14.00
10.00
0.80
17.45
14.10
0.667
0.547
0.687
0.555
E1
E3
L
0.65
0.95
0.026
0.0374
L1
K
1.60
0°(min.), 7°(max.)
D
D1
D3
A
A2
A1
33
23
22
34
0.10mm
.004
SeatingPlane
44
12
11
1
C
e
K
PQFP44
29/31
L6238S
TQFP64 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.60
0.15
1.45
0.28
0.20
MIN.
MAX.
0.063
0.006
0.057
0.011
0.0079
A
A1
A2
B
0.05
1.35
0.18
0.12
0.002
0.053
0.007
0.0047
1.40
0.23
0.055
0.009
0.0063
0.472
0.394
0.295
0.0197
0.472
0.394
0.295
0.0236
0.0393
C
0.16
D
12.00
10.00
7.50
D1
D3
e
0.50
E
12.00
10.00
7.50
E1
E3
L
0.40
0.60
0.75
0.0157
0.0295
L1
K
1.00
0°(min.), 7°(max.)
D
D1
D3
A
A2
A1
48
33
49
32
0.10mm
Seating Plane
17
64
1
16
C
e
K
TQFP64
30/31
L6238S
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-
THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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