L6911D [STMICROELECTRONICS]
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION; 采用同步整流5位可编程降压控制器
| 型号： | L6911D |
| 厂家： | 
ST |
| 描述： | 5 BIT PROGRAMMABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION |
| 文件： | 总17页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6911D
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
■
OPERATING SUPPLY IC VOLTAGE FROM 5V
TO 12V BUSES
■
■
UP TO 1.3A GATE CURRENT CAPABILITY
TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 9.0 :
1.100V TO 1.850V WITH 0.025V BINARY
SO-20
STEPS
ORDERING NUMBERS: L6911D
■
■
VOLTAGE MODE PWM CONTROL
EXCELLENT OUTPUT ACCURACY: ±1%
L6911DTR (Tape and Reel)
OVER LINE AND TEMPERATURE
DESCRIPTION
VARIATIONS
The device is a power supply controller specifically de-
VERY FAST LOAD TRANSIENT RESPONSE:
■
signed to provide a high performance DC/DC conver-
sion for high current microprocessors. A precise 5-bit
digital to analog converter (DAC) allows adjusting the
output voltage from 1.30V to 2.05V with 50mV binary
steps and from 2.10V to 3.50V with 100mV binary steps.
FROM 0% TO 100% DUTY CYCLE
POWER GOOD OUTPUT VOLTAGE
OVERVOLTAGE PROTECTION AND
MONITOR
■
■
■
OVERCURRENT PROTECTION REALIZED
USING THE UPPER MOSFET'S R
200KHz INTERNAL OSCILLATOR
dsON
The high precision internal reference assures the se-
lected output voltage to be within ±1%. The high peak
current gate drive affords to have fast switching to the
external power mos providing low switching losses.
■
■
OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50KHz TO 1MHz
SOFT START AND INHIBIT FUNCTIONS
■
The device assures a fast protection against load
overcurrent and load overvoltage. An external SCR is
triggered to crowbar the input supply in case of hard
over-voltage. An internal crowbar is also provided
turning on the low side mosfet as long as the over-
voltage is detected. In case of over-current detection,
the soft start capacitor is discharged and the system
works in HICCUP mode.
APPLICATIONS
■
POWER SUPPLY FOR ADVANCED
MICROPROCESSOR CORE
DISTRIBUTED POWER SUPPLY
HIGH POWER DC-DC REGULATORS
■
■
BLOCK DIAGRAM
Vcc 5 to 12V
Vin 5V to12V
VCC
OCSET
PGOOD
SS
BOOT
MONITOR and
PROTECTION
UGATE
OVP
RT
Vo
1.100V to 1.850V
PHASE
LGATE
PGND
GND
OSC
VD0
VD1
VD2
VD3
VD4
-
D/A
+
PWM
+
-
VSEN
VFB
E/A
D98IN957_2
COMP
November 2001
1/17
L6911D
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
V
CC
to GND, PGND
15
V
-V
Boot Voltage
15
V
BOOT PHASE
V
-V
15
V
HGATE PHASE
OCSET, LGATE, PHASE
-0.3 to Vcc+0.3
V
RT, SS, FB, PGOOD, VSEN, VID0-4
OVP, COMP
7
V
6.5
V
THERMAL DATA
Symbol
Parameter
Value
110
Unit
R
Thermal Resistance Junction to Ambient
Maximum junction temperature
Storage temperature range
°
C/W
th j-amb
T
j
150
°
C
°
C
°
C
T
-40 to 150
0 to 125
stg
T
Junction temperature range
J
PIN CONNECTION (Top view)
VSEN
OCSET
SS/INH
VID0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
OVP
VCC
LGATE
PGND
BOOT
UGATE
PHASE
PGOOD
GND
VID1
VID2
VID3
VID4
COMP
FB
D98IN958
2/17
L6911D
PIN FUNCTION
Pin
Name
Description
Num.
1
VSEN
Connected to the output voltage is able to manage over-voltage conditions and the PGOOD
signal.
2
OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection.
µ
The internal 200 A current generator sinks a current from the drain through the external resistor.
The Over-Current threshold is due to the following equation:
I
ROCSET
IP = --O----C----S----E---T----------------------------
RDSon
3
SS/INH
The soft start time is programmed connecting an external capacitor from this pin and GND. The
µ
internal current generator forces through the capacitor 10 A.
This pin can be used to disable the device forcing a voltage lower than 0.4V
4 - 8
VID0 - 4 Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They
are used to program the output voltage as specified in Table 1 and to set the overvoltage and
power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
9
COMP This pin is connected to the error amplifier output and is used to compensate the voltage control
feedback loop.
10
FB
This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop.
11
12
GND
All the internal references are referred to this pin. Connect it to the PCB signal ground.
PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds.
If not used may be left floating.
13
PHASE This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver. This pin monitors the drop across the upper mosfet for the current limit
14
15
UGATE High side gate driver output.
BOOT
Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet.
Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot).
16
PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to
reduce the noise injection into the device
17
18
LGATE This pin is the lower mosfet gate driver output
VCC
Device supply voltage. The operative nominal supply voltage ranges from 5 to 12V.
DO NOT CONNECT V TO A VOLTAGE GREATER THAN V
.
CC
IN
19
20
OVP
Over voltage protection. If the output voltage reaches the 17% above the programmed voltage
this pin is driven high and can be used to drive an external SCR that crowbar the supply voltage.
If not used, it may be left floating.
RT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
4.94 106
f S = 200kHz + -------------------------
RT(kΩ)
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
4.306 107
f S = 200kHz – ----------------------------
RT(kΩ)
If the pin is not connected, the switching frequency is 200KHz.
µ
The voltage at this pin is fixed at 1.23V (typ). Forcing a 50 A current into this pin, the built in
oscillator stops to switch.
3/17
L6911D
ELECTRICAL CHARACTERISTCS (V = 12V, T
= 25°C unless otherwise specified)
CC
amb
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
SUPPLY CURRENT
CC
Icc
Vcc Supply current
UGATE and LGATE open
5
mA
POWER-ON
Turn-On Vcc threshold
Turn-Off Vcc threshold
VOCSET=4.5V
VOCSET=4.5V
4.6
V
V
V
3.6
Rising V
threshold
1.24
10
OCSET
I
Soft start Current
OSCILLATOR
Free running frequency
µ
A
SS
R = OPEN
T
180
-15
200
1.9
220
15
KHz
%
Total Variation
Ω
Ω
6 K < RT to GND < 200 K
∆
Ramp amplitude
R = OPEN
T
Vp-p
V
osc
REFERENCE AND DAC
DACOUT Voltage
Accuracy
-1
1
%
V
VID0, VID1, VID2, VID3, VID4
°
see Table1; Tamb = 0 to 70 C
VID Pull-Up voltage
ERROR AMPLIFIER
4
DC Gain
88
10
10
dB
GBWP Gain-Bandwidth Product
MHz
SR
GATE DRIVERS
High Side Source
Slew-Rate
COMP=10pF
µ
V/ S
1
1.3
2
A
I
V
V
- V
=12V,
PHASE
UGATE
BOOT
Current
- V
= 6V
UGATE
PHASE
High Side Sink
Resistance
4
3
Ω
R
V
-V
=12V,
UGATE
BOOT PHASE
I
= 300mA
UGATE
Low Side Source
Current
0.9
1.1
1.5
A
Ω
I
Vcc=12V, V
= 6V
LGATE
LGATE
Low Side Sink
Resistance
R
Vcc=12V, I
= 300mA
LGATE
LGATE
Output Driver Dead Time
PHASE connected to GND
120
ns
PROTECTIONS
Over Voltage Trip
(V /DACOUT)
SEN
V
Rising
117
200
120
230
%
SEN
I
OCSET Current Source
OVP Sourcing Current
V = 4.5V
OCSET
170
60
µ
A
OCSET
I
V
> OVP Trip, V =0V
OVP
mA
OVP
SEN
POWER GOOD
Upper Threshold
(V /DACOUT)
V
V
Rising
Falling
110
86
112
88
2
114
90
%
%
%
V
SEN
SEN
SEN
Lower Threshold
(V /DACOUT)
SEN
Hysteresis
(V /DACOUT)
Upper and Lower threshold
= -5mA
SEN
V
PGOOD Voltage Low
I
0.5
PGOOD
PGOOD
4/17
L6911D
Table 1. VID Settings
Output
Voltage (V)
VID4 VID3 VID2 VID1 VID0
Output Voltage
(V)
VID4 VID3 VID2 VID1 VID0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Output OFF
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
Device Description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed
to drive N-Channel Mosfets in a synchronous-rectified buck topology. The device works properly with Vcc rang-
ing from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The
output voltage of the converter can be precisely regulated, programming the VID pins, from 1.100V to 1.850V
with 25mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The
device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator
that is adjustable from 50kHz to 1MHz.
The error amplifier features a 15MHz gain-bandwidth product and 10V/ s slew rate which permits high convert-
µ
er bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The device
protects against over-current conditions entering in HICCUP mode. The device monitors the current by using
the r
of the upper MOSFET which eliminates the need for a current sensing resistor.
DS(ON)
The device is available in SO20 package
Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
µ
oscillator is typically 50 A (Fsw=200KHz) and may be varied using an external resistor (R ) connected between
T
RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied
proportionally to the current sunk (forced) from (into) the pin.
In particular connecting it to GND the frequency is increased (current is sunk from the pin), according to the
following relationship:
6
4.94 10
=
+ -------------------------
200kHz
f
S
( Ω)
R
k
T
Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according
to the following relationships:
5/17
L6911D
7
4.306 10
+ ----------------------------
=
f
200kHz
V
CC
= 12V
S
( Ω)
R
k
T
7
15 10
+ --------------------
=
f
200kHz
V
CC
= 5V
S
( Ω)
R
k
T
Switching frequency variations vs. R are reported in Fig.1.
T
µ
Note that forcing a 50 A current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 1.
10000
1000
100
RT to G N D
10
RT to V CC =12V
RT to V CC =5V
10
100
1000
Frequency [kH z]
Digital to Analog Converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.30V to 2.05V with
50mV binary steps and from 2.10V to 3.50V with 100mV binary steps as shown in the previous table 1. The
internal reference is trimmed to ensure the precision of 1%.
The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These
are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a par-
tition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise
point of the divider. The DAC output is delivered to an amplifier obtaining the V
voltage reference (i.e. the
PROG
µ
set-point of the error amplifier). Internal pull-ups are provided (realized with a 5 A current generator); in this
way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short
the pin to GND.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-
voltage protection (OVP) thresholds.
The VID code "11111" disable the device (as a short on the SS pin) and no output voltage is regulated.
Soft Start and Inhibit
At start-up a ramp is generated charging the external capacitor C by means of a 10µA constant current, as
SS
shown in figure 1.
When the voltage across the soft start capacitor (V ) reaches 0.5V the lower power MOS is turned on to dis-
SS
6/17
L6911D
charge the output capacitor. As V reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper
SS
MOS begins to switch and the output voltage starts to increase.
The V growing voltage initially clamps the output of the error amplifier, and consequently V
linearly in-
OUT
SS
creases, as shown in figure 2. In this phase the system works in open loop. When V is equal to V
the
SS
COMP
clamp on the output of the error amplifier is released. In any case another clamp on the input of the error ampli-
fier remains active, allowing to V to grow with a lower slope (i.e. the slope of the V voltage, see figure 2).
OUT
SS
In this second phase the system works in closed loop with a growing reference. As the output voltage reaches
the desired value V , also the clamp on the error amplifier input is removed, and the soft start finishes. Vss
PROG
increases until a maximum value of about 4V.
The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins
are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of
the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept
off.
Figure 2. Soft Start
Vcc Turn-on threshold
Vcc
Vin
Vin Turn-on threshold
1V
Vss
LGATE
Vout
to GND
0.5V
Timing Diagram
Aquisition: CH1 = PHASE; CH2 = V
;
OUT
CH3 = PGOOD; CH4 = V
SS
Driver Section
The driver capability on the high and low side drivers allows using different types of power MOS (also multiple
MOS to reduce the R ), maintaining fast switching transition.
DSON
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the
low side turn-off.
The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 4nF capacitive
load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak
current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V.
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ Vboot-
Vphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
7/17
L6911D
Figure 3. High Side driver peak current. Vboot-Vphase=12V (left) Vboot-Vphase=5V (right)
CH1 = High Side Gate
CH4 = Gate Current
Figure 4. Low Side driver peak current. Vcc=12V (left) Vcc=5V (right)
CH1 = Low Side Gate
CH4 = Gate Current
Monitoring and Protections
The output voltage is monitored by means of pin 1 (VSEN). If it is not within ±12% (typ.) of the programmed
value, the powergood output is forced low.
The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) grater than the
nominal one. If the output voltage exceeds this threshold, the OVP pin is forced high, triggering an external SCR
to shuts the supply (VIN) down, and also the lower driver is turned on as long as the over-voltage is detected.
To perform the overcurrent protection the device compares the drop across the high side MOS, due to the
RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of
the upper MOS. Thus the overcurrent threshold (I ) can be calculated with the following relationship:
P
I
R
OCS
OCS
= --------------------------------
I
P
R
DSON
µ
is 200 A. To calculate the ROCS value it must be considered the maximum
Where the typical value of I
OCS
R
DSON
(also the variation with temperature) and the minimum value of I
. To avoid undesirable trigger of
OCS
8/17
L6911D
overcurrent protection this relationship must be satisfied:
∆
2
l
≥
+ ---- =
I
PEAK
I
I
P
OUTMAX
∆
Where I is the inductance ripple current and I
is the maximum output current.
OUTMAX
µ
In case of output short circuit the soft start capacitor is discharged with constant current (10 A typ.) and when
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-
ways active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is dis-
charged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,
as shown in figure 5a. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
Figure 5.
9
L=1.5µH, Vin=12V
8
µ
L=2 H,
7
6
5
4
3
2
1
0
Vin=12V
µ
L=3 H,
Vin=12V
µ
L=1.5 H,
Vin=5V
µ
L=2 H,
Vin=5V
L=3µH, Vin=5V
0.5
1.5
2.5
3.5
Output Voltage [V]
a: Hiccup Mode
b: Inductor Ripple Current vs. Vout
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
∆
the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
–
V
V
V
OUT OUT
IN
------------------------------ --------------
=
L
∆
f
I
V
IN
S
L
Where f
is the switching frequency, V is the input voltage and V
is the output voltage. Figure 5b shows
OUT
SW
IN
the ripple current vs. the output voltage for different values of the inductor, with V = 5V and V = 12V.
IN
IN
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-
rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
∆
imate response time for I load transient in case of enough fast compensation network response:
9/17
L6911D
∆
∆
I
L
I
L
V
= ------------------------------
= --------------
t
t
removal
application
–
V
V
IN
OUT
OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
Output Capacitor
Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the
µ
range of tenth A/ sec, the output capacitor is a basic component for the fast response of the power supply. In
fact for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
∆
V
∆
I
OUT
=
· ESR
OUT
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
2
∆
I
L
OUT
∆
= ---------------------------------------------------------------------------------------------
V
OUT
(
–
V
)
OUT
2 C
V
D
OUT
INMIN
MAX
Where D
is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
MAX
during load transient and the lower is the output voltage static ripple.
Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
=
( –
1
)
D
I
I
D
OUT
rms
Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:
2
=
P
ESR I
rms
Compensation network design
The control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM
module, reducing the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current: at light load the output voltage will be higher than the nom-
inal level, while at high load the output voltage will be lower than the nominal value.
10/17
L6911D
Figure 6. Output transient response without (a) and with (b) the droop function
ESR DROP
ESR DROP
VMAX
VDROOP
VNOM
VMIN
(a)
(b)
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor-
tional to the output current. Since a sense resistor is not present, the output DC current is measured by using
Ω
the intrinsic resistance of the inductance (a few m ). So the low-pass filtered inductor voltage (that is the induc-
tor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the
schematic in figure 7, the static characteristic of the closed loop system is:
R
R8 // R9
+
R3 R8 // R9
L
----------------------------------
I
OUT
=
+
------------------------------------- –
V
V
V
OUT
PROG
PROG
R2
R8
Where V
is the output voltage of the digital to analog converter (i.e. the set point) and R is the inductance
L
PROG
+
∆
resistance. The second term of the equation allows a positive offset at zero load ( V ); the third term introduces
∆
the droop effect ( V
). Note that the droop effect is equal the ESR drop if:
DROOP
R
R8 // R9
L
---------------------------------- =
ESR
R8
Figure 7. Compensation network
V
IN
V
C
O
M
P
V
P
H
A
S
E
L 2
R
L
V
O U T
P W M
E S R
R 8
C 1 8
Z F
C 6 - 1 5
C 2 0
R 4
R 9
R 3
C 2 5
P
R
O
G
Z I
V
R 2
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired
droop effect as follow:
■
Ω
Choose a value for R2 in the range of hundreds of K to obtain realistic values for the other
components.
11/17
L6911D
■
From the above equations, it results:
R8
+
R
I
MAX
∆
V
V
R2
L
----------------------- --------------------------
=
;
∆
V
DROOP
PROG
∆
V
1
DROOP
-------------------------- ------------------------------------
=
R9 R8
;
∆
V
DROOP
R
I
L
MAX
+ --------------------------
1
R
I
MAX
L
Where I
is the maximum output current.
MAX
■
The component R3 must be chosen in order to obtain R3<<R8//R9 to permit these and successive
simplifications.
Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output
impedance is equal to a resistance R . It is easy to verify that the output voltage deviation under load tran-
OUT
sient is minimum when the output impedance is constant with frequency.
To choose the other components of the compensation network, the transfer function of the voltage loop is con-
sidered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9).
Figure 8. Compensation network definition
|A v|
2
fLC
fC E
fEC
fC C
f
f
|R |
R 0
f
D
f
2
f
1
f
3
|G loo p|
G
0
fc
f
CompensationNetworkS ingularity
f
=
π
R
C
1/ 2
4
20
ConverterSingularity
f
f
= 1 / 2π
LC
doublepole
ESRzero
1
LC
f
f
f
=
π
π
R
+ R
C
4) 20
1 / 2
1 / 2
(
3
=
=
π
ESR C
OUT
1/ 2
2
3
d
CE
=
=
R
C
C
3
25
25
f
π
ESR Cceramic
Introducedby
1 / 2
1 / 2
EC
π
1/ 2
Rd
f
=
π
Rceramic Cceramic
CeramicCapacitor
CC
The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later,
this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this as-
sumption, the voltage loop has the following transfer function:
12/17
L6911D
( )
Z
s
( )
Zf s
( )
Zi s
Vin
C
-------------
--------------- ------------------------------------
( ) =
Gloop s
( )
( ) =
( )
Av s
( ) =
Where Av s
Av s R s
∆
( ) + ( )
V
Z
s
Z
s
osc
C
L
Where Z (s) and Z (s) are the output capacitor and inductor impedance respectively.
C
L
The expression of Z (s) may be simplified as follow:
I
2 R3
1
--
s
1
s
-------
+
(τ + τ ) +
s
τ
τ
1
Rd 1
s
+
R4
C20 R3
--
Rd
C25
1
d
d
R
d
( ) = --------------------------------- + ----------------------------------------------------- = --------------------------------------------------------------------------------------------------
Z s
=
I
( +
τ ) ( +
τ )
s
d
1
s
1
1
1
+ --
s
2
+ --
Rd
C25
+
R3
R4
C20
s
R3
+ ------- τ
( +
τ )
1
s
1
s
d
1
R
d
--------------------------------------------------------------------
=
Rd
( +
τ ) ( +
τ )
s
d
1
s
1
2
τ
τ
τ
d
Where: = R4×C20, = (R4+R3)×C20 and = Rd×C25.
1
2
The regulator transfer function became now:
( +
τ ) ( +
τ )
s
d
1
s
1
2
-------------------------------------------------------------------------------------------------------
( ) ≈
R s
R3
-------
+
τ
( +
τ )
s
1
s C18 R
1
s
1
d
d
R
d
Figure 8 shows a method to select the regulator components (please note that the frequencies f and f cor-
EC
CC
responds to the singularities introduced by additional ceramic capacitors in parallel to the output main electro-
lytic capacitor).
■
τ
To obtain a flat frequency response of the output impedance, the droop time constant has to be equal
d
to the inductor time constant (see the note at the end of the section):
L
L
τ
=
= ------ = τ
= -----------------------
C25
R
C25
d
d
L
(
)
R
L d
R
R
L
■
To obtain a constant -20dB/dec Gloop(s) shape the singularity f and f are placed in proximity of f
CE
1
2
and f respectively. This implies that:
LC
f
f
f
LC
LC
2
--------
--- =
=
-------- –
R4
R3
1
1
f
f
f
CE
1
CE
=
= -- π
f1
f
C20
R4 f
CE
CE
2
■
To obtain a Gloop bandwidth of f , results:
C
f C
G0 = A0 R0 = ----------------- ----------------------------- = -------
∆Vosc C18 f LC
f LC
C20 C25
VIN C20 // C25
VIN
C18 = ----------------- ---------------------------- -------
∆Vosc C20 + C25 fC
G0 fLC = 1 fC
Note.
To understand the reason of the previous assumption, the scheme in figure 9 must be considered.
In this scheme, the inductor current has been substituted by the load current, because in the frequencies range
of interest for the Droop function these current are substantially the same and it was supposed that the droop
network don't represent a charge for the inductor.
13/17
L6911D
Figure 9. Voltage regulation with droop function block scheme
Vcomp
Vout
Av(s)
R(s)
1 + s
1 + s
τ
τ
L
d
Iout
R
OUT
It results:
+ τ
+ τ
s
L
1
s
G
1
V
L
LOOP
o
------------------ ----------------------------
------------------
= --------------- =
=
R
Z
R
OUT
d
OUT
+ τ
s
+
+ τ
1 s
d
I
1
1
G
d
LOOP
LOAD
Because in the interested range |Gloop|>>1.
To obtain a flat shape, the relationship considered will naturally follow.
Application Idea: 1.100V to 1.850V / 25A
Figure 10 shows an application schematic for a 1.100V to 1.850V conversion with 25A of current capability.
Since the device's high gate drive, more than one mosfet for both high side and low side can be used: three
STS11NF30L (30V, 9mW typ @ Vgs=10V) mosfet are suggested for high side while four of them are suggested
as low side switch.
Figure 10. Schematic Circuit
L1
F1
+5 VIN
C1-3
C21-22
D1
C23
R7
C24
BOOT
OVP
19
15
R10
VCC
GND
VID0
VID1
VID2
VID3
VID4
OSC
SS
OCSET
+12Vcc
18
11
4
2
14
13
17
16
12
1
C17
UGATE
PHASE
LGATE
PGND
R13
R14
VID0
Q1,Q2, Q3
L2
VOUTCORE
VID1
5
U1
L6911D
VID2
6
Q4,Q5,Q6
D2
C4-9
R15
R6
VID3
7
Vss
VID25mV
8
PGOOD
VSEN
R1
PWRGD
20
3
9
10
VFB
C16
R8
COMP
C18
R3
R9
C20
C17
C19
R5
R4
R2
14/17
L6911D
Part List
Resistor
R1
Not Mounted
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
R2
470
1%
R3
1k
R4
82
R5
Not Mounted
R6
1k
R7
1k
R8
13k
R9
100k
R10
Not Mounted
20k
R12
R13, R14
Capacitor
C1-C3
C4-C9
Short Circuit
680µF - 6.3V
OSCON 6SP680M
Radial 10x10.5
820µF - 4V
680µF - 6.3V
OSCON 6SP680M
OSCON 4SP820M
Radial 10x10.5
Radial 10x10.5
C16
100n
100n
2.2n
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
C17
C18
C19
Not Mounted
100n
1n
C20
C23
C24
100n
47n
C25
Magnetics
L1
µH
T44-52 Core, 7T-18AWG
T50-52B Core, 7T-16AWG
1.5
L2
1.8µH
Transistors
Q1-Q5
Diodes
D1
STS12NF30L
STMicroelectronics
SO8
1N4148
STMicroelectronics
STMicroelectronics
SOT23
SMB
D2
STPS3L25U
Ics
U1
L6911D
STMicroelectronics
Littlefuse
SO20
Fuse
F1
251015A-15A
AXIAL
15/17
L6911D
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
B
C
D
E
e
2.35
0.1
2.65 0.093
0.3 0.004
0.104
0.012
0.020
0.013
0.512
0.299
0.33
0.23
12.6
7.4
0.51 0.013
0.32 0.009
13
0.496
0.291
7.6
1.27
0.050
H
h
10
0.25
0.4
10.65 0.394
0.75 0.010
0.419
0.030
0.050
L
1.27 0.016
SO20
K
0˚ (min.)8˚ (max.)
L
h x 45˚
A
B
A1
K
C
e
H
D
20
1
11
E
01
SO20MEC
16/17
L6911D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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17/17
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