L9823 [STMICROELECTRONICS]

Octal Low-Side Driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic; 八路低端驱动器的灯泡，电阻和电感负载，串行输入控制，输出保护及诊断


型号：	L9823
厂家：	ST
描述：	Octal Low-Side Driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic 八路低端驱动器的灯泡，电阻和电感负载，串行输入控制，输出保护及诊断驱动器
文件：	总12页 (文件大小：170K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L9823

Octal Low-Side Driver for bulb, resistive and inductive loads with

serial input control, output protection and diagnostic

■ OUTPUTS CURRENT CAPABILITY UP TO

0.5A

■ CASCADABLE SPI CONTROL FOR

OUTPUTS

■ RESET FUNCTION WITH RESET SIGNAL OR

UNDERVOLTAGE AT V

■ PROGRAMMABLE INTRINSIC OUTPUT

VOLTAGE CLAMPING AT TYP. 50V FOR

INDUCTIVE SWITCHING

SO24 (20+2+2)

ORDERING NUMBER: L9823

■

OVERCURRENT SHUTDOWN WITH LATCH-

OFF FOR EVERY WRITE CYCLE (SFPD = LOW)

■ INDEPENDENT THERMAL SHUTDOWN OF

OUTPUTS (-1,5V OR -3,0A)

OUTPUTS (SOA PROTECTION)

■ OUTPUT MODE PROGRAMMABLE FOR

SUSTAINED CURRENT LIMIT OR

SHUTDOWN

■

OUTPUT STATUS DATA AVAILABLE ON THE

SPI USING 8-BIT I/O PROTOCOL UP TO 3.0MHZ

■ LOW STANDBY CURRENT WITH RESET =

LOW (TYP 35µA @ VDD)

DESCRIPTION

■ OPEN LOAD DETECTION (OUTPUTS OFF)

L9823 is a Octal Low-Side Driver Circuit, dedicated

for automotive applications. Output voltage clamping

is provided for flyback current recirculation, when in-

ductive loads are driven. Chip Select and cascadable

Serial 8-bit Interface for outputs control and diagnos-

tic data transfer.

■ SINGLE V

LOGIC SUPPLY

■ HIGH EMS IMMUNITY AND LOW EME

(CONTROLLED OUTPUT SLOPES)

■ FULL FUNCTIONALITY OF THE REMAINING

DEVICE AT NEGATIVE VOLTAGE DROP ON

BLOCK DIAGRAM

SFPD

OUT0

OL0

CSB

Gate

Control

SCB

Over

Temperature

Detect

OT0

CH0

SCLK

Diag0

Diag1

Diag2

Diag3

Diag4

Diag5

Diag6

Diag7

OUT1

CH1

CH2

CH3

CH4

CH5

CH7

Diag1

Diag2

OUT2

OUT3

Diag3

OUT4

Diag4

OUT5

Diag5

OUT6

Diag6

Reset

OUT7

Diag7

Undervoltage

RESET

5 -8

17 - 20

GND

April 2003

1/12

L9823

PIN FUNCTION

N°

Description

Out 7

Out 6

SCLK

Output 7

Output 6

SCLK. The system clock pin (SCLK) clocks the internal shift registers of the L9823. The serial

input pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while

the serial output pin (SO) shifts data information out of the shift register on the rising edge of the

SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It

is essential that the SCLK pin be in a logic low state whenever chip select bar pin (CSB) makes

any transition. For this reason, it is recommended though not necessary, that the SCLK pin be

kept in a low logic state as long as the device is not accessed (CSB in logic high state). When

CSB is in a logic high state, any signal at the SCLK and SI pin is ignored and SO is tri-stated

(high-impedance).

SI. This pin is for the input of serial instruction data. SI information is read in on the falling edge

of SCLK. A logic high state present on this pin when the SCLK signal rises will program a

specific output OFF, and in turn, turns OFF the specific output on the rising edge of the CSB

signal. Conversely, a logic low state present on the SI pin will program the output ON, and in

turn, turns ON the specific output on the rising edge of the CSB signal. To program the eight

outputs of the L9823 ON or OFF, an eight bit serial stream of data is required to be entered into

the SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For each rise

of the SCLK signal, with CSB held in a logic low state, a databit instruction (ON or OFF) is

loaded into the shift register per the databit SI state. The shift register is full after eight bits of

information have been entered. To preserve data integrity, care should be taken to not transition

SI as SCLK transitions from a low-to-high logic state.

GND

SO. The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin

remains in a high impedance state until the CSB pin goes to a logic low state. The SO data

reports the drain status, either high or low. The SO pin changes state on the rising edge of SCLK

and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the

corresponding SO databit is a high state. When SO an output is ON, and there is no fault, the

corresponding databit on the SO pin will be a low logic state. The SI / SO shifting of data follows

a first-in-first-out protocol with both input and output words transferring the Most Significant Bit

(MSB) first. The SO pin is not affected by the status of the Reset pin.

CSB

CSB. The system MCU selects the L9823 to be communicated with through the use of the CSB

pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823

and vise versa. Clocked-in data from the MCU is transferred from the L9823 shift register and

latched into the power outputs on the rising edge of the CSB signal. On the falling edge of the

CSB signal, drain status information is transferred from the power outputs and loaded into the

device's shift register. The CSB pin also controls the output driver of the serial output pin.

Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowing

information to be transferred from the L9823 to the MCU. To avoid any spurious data, it is

essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic low

state.

Out 5

Out 4

Out 3

Output 5

Output 4

Output 3

2/12

L9823

PIN FUNCTION (continued)

N°

Description

Out 2

SFPD

Output 2

SFPD. The Short Fault Protect Disable (SFPD) pin is used to disable the overcurrent latch-OFF.

This feature allows control of incandescent loads where in-rush currents exceed the device's

analog current limits. Essentially the SFPD pin determines whether the L9823 output(s) will

instantly shutdown upon sensing an output short or remain ON in a current limiting mode of

operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is

tied to V

the L9823 output(s) will remain ON in a current limited mode of operation upon

encountering a load short to supply. If the SFPD pin is grounded, a short circuit will immediately

shutdown only the output affected. Other outputs not having a fault condition will operate

normally.

VDD

GND

VDD

GND

Not Connected

Reset

Reset. The Reset pin is active low and used to clear the SPI shift register and in doing so sets all

output switches OFF. With the device in a system with an MCU; upon initial system power up,

the MCU holds the Reset pin of the device in a logic low state ensuring all outputs to be OFF

until the VDD pin voltages are adequate for predictable operation. After the L9823 is Reset, the

MCU is ready to assert system control with all output switches initially OFF. The Reset pin is

active low and has an internal pull-down incorporated to ensure operational predictability

should the external pull-down of the MCU open circuit. The internal pull-up is to afford safe and

easy interfacing to the MCU. The Reset pin of the L9823 should be pulled to a logic low state for

a duration of at least 160ns to ensure reliable Reset.

Out 1

Out 0

Output 1

Output 0

ABSOLUTE MAXIMUM RATINGS

For voltages and currents applied externally to the device. Exceeding limits may cause damage to the device

Symbol

Parameter

Value

Unit

Supply voltage

-0.3 to 7

Inputs and data lines

(CSB, SCLK, SI, Reset, SFPD, SO)

Voltage

-0.3 to 7

(CSB, SCLK, SI, Reset, SFPD)

SDO

Voltage (SO)

-0.3 to V +0.3

Protection diodes current

Outputs (Out0 ... Out7)

Continuous output voltage

T ≤ 1ms

-20 to 20

-1.5 to 45

OUT Cont

3/12

L9823

ABSOLUTE MAXIMUM RATINGS (continued)

Symbol

Parameter

Value

-3 to I

Unit

Continuous output current

Output current

OUT Cont

OUT LIM

OUT PEAK

-10 to 2

OUTclamp

OUT LIM

Output clamp energy

Output current (self limit)

Note

1) All inputs are protected against ESD according to MIL 883C; tested with HBM C = 100pF, R = 1500Ω at ±2KV. It corresponds to

a dissipated energy E ≤ 0.2mJ (data available upon request).

2) Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.

3) Max. output clamp energy at T = 150°C, using single non-repetitive pulse of 500mA

THERMAL DATA

Symbol

Parameter

Value

Unit

Thermal shutdown

Thermal shutdown threshold

Thermal resistance (junction-to-Lead)

Single output (junction lead)

155 (Min.), 180 (Typ.)

°C

LIM

25 (Max.)

20 (Max.)

-55 to 150

°C/W

°C

thjL-one

thjL-all

All outputs (junction lead)

Storage Temperature

stg

ELECTRICAL CHARACTERISTCS (4.5V

≤

V ≤ 5.5V; -40°C ≤ T ≤ 150°C; unless otherwise specified

DD J

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply voltage

Standby current

leakage current

Reset = LOW and / or

µA

DDSTB

>V > 0.5V

DDRES DD

DDleak

< 0.5V

Operating mode

= 500mA

DDOPM

OUT0 ... 7

SPI - SCLK = 3MHz

CSB = LOW

SO no load

∆I

∆I during reverse output

current

I = -2.5A

out rev

DD rev

Undervoltage Reset

Reset of all registers and disable

of all outputs

2.5

3.95

DD RES

Inputs (CSB, SCLK, SI, Reset, SFPD)

Low level

-0.3

0.2·V

INL

INH

hyst

High level

0.7·V

V +0.3

Hysteresis voltage

0.5

1.2

0.5·V

4/12

L9823

ELECTRICAL CHARACTERISTCS (continued)

Symbol Parameter

Test Condition

Min.

-10

Typ.

Max.

Unit

µA

Input current

= V

Pullup resistance

(CSB, SI)

250

kΩ

Pulldown resistance

(SFPD, Reset, SCLK)

Input capacitance

Serial data outputs

High output level

= -4mA

V -0.4

SOH

Low output level

= 3,2mA

0.4

SOL

Tristate leakage current

Output capacitance

CSB = high; 0V ≤ V ≤ V

-10

µA

SOL

= 300kHz, 0V ≤ V ≤ V

SO SO DD

Outputs OUT 0 ... 7

Leakage current

OUTx = OFF; V

= 16V;

-10

µA

OUTL0 - 7

OUTx

≤

and / or Reset = Low

DD RES

<1µA

Tj ≤ 85°C

OUT

clamp

Output clamp voltage

On resistance OUT 0 ... 7

Output capacitance

2mA ≤ I

≤ I

OUT clamp OUT LIM

= 20mA with correlation

OUT test

= 500mA;T = +150°C

0.8

1.5

1.25

Ω

DSon

OUT

T = +25°C

= 16V; f = 1MHz

OUT

300

OUT

Outputs short circuit protection

Overcurrent shutoff threshold

Short circuit current limitation

Short circuit shutdown delay

SFPD = Low, V

≥ V

0.5

1.6

2.5

SCB

OUT

OUT LIM

SFPD = Low, V

CSB = 50% to

150

250

µs

dly SCB

OUT

≤ 1/2 I

OUT

OUT LIM

Diagnostics

Diagnostic threshold voltage

0.5

·V

0.55

·V

0.6·V

Open load detection sink current

= V

100

250

µA

OUT OL

out

Output programmed OFF

Diagnostic detection filter time

SFPD = Low, V

CSB = 50% to

≥ V

150

µs

dly SFPD

OUT

valid data at SO

Outputs timing

Turn ON delay

CSB = 50% to R = 50Ω

µs

don

= 0,9V , V = 16V

bat bat

OUT

5/12

L9823

ELECTRICAL CHARACTERISTCS (continued)

Symbol

Parameter

Turn OFF delay

Test Condition

Min.

Typ.

Max.

Unit

CSB = 50% to R = 50Ω

µs

doff

= 0,1·V

, V = 16V

bat bat

OUT

Turn ON voltage slew-rate

Turn OFF voltage slew-rate

90% to 30% of V

;

bat

0.7

2.1

3.5

5.5

V/µs

on/dt

off/dt

R = 50Ω; V = 16V

bat

30% to 90% of V

;

bat

R = 50Ω; V = 16V

bat

off

clamp/dt

Turn OFF voltage clamp slew-rate 30% to 80% of V

OUT clamp

R = 500Ω

Serial diagnostic link (Load capacitor at SO = 200pF)

Clock frequency

50% duty cycle

MHz

sclk

Minimum time SCLK = HIGH

Minimum time SCLK = LOW

160

clh

cll

Propagation delay

SCLK to data at SO valid

4.9V ≤ V ≤ 5.1V

100

pcld

CSB = LOW to data at SO active

SCLK low before CSB low

csdv

Setup time SCLK to CSB change

H/L

100

sclch

SCLK change L/H after CSB =

Low

Setup time CSB to SCLK change

L/H

hclcl

SI input setup time

SCLK change H/L after SI data

valid

scld

hcld

sclcl

SI input hold time

SI data hold after SCLK change

H/L

SCLK low before CSB high

SCLK high after CSB high

150

15,

hclch

CSB L/H to output data float

Minimum Reset time Reset = Low

100

160

pchdz

Reset

Outputs Control Tables :

Outputs:

SI-bit

Output

off

6/12

L9823

Output Control register structure :

MSB

LSB

Q6 Q5 Q4 Q3 Q2 Q1 Q0

Control-bit output 7

Control-bit output 6

Control-bit output 5

Control-bit output 4

Control-bit output 3

Control-bit output 2

Control-bit output 1

Control-bit output 0

Power outputs characteristics

for flyback current, outputs short circuit protection and diagnostics

For output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V.

This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is

absorbed in the chip.

Output short circuit protection SFPD = Low (dedicated for loads without inrush current): when the output current

exceeds the short circuit threshold, the corresponding output overload latch is set after a delay time t

and

dly SCB

the output is switched off. The delay timer is started after each rise of CSB and valid datas are transfered to the

output control register. If the short takes place after the delay time has elapsed the shutdown is immediate (with-

in 15µs).

Output short circuit protection SFPD = High (dedicated for loads with inrush current, as lamps): when the load

current would exceed the short circuit limit value, the corresponding output goes in a current regulation mode.

The output current is determined by the output characteristics and the output voltage depends on the load re-

sistance. In this mode high power is dissipated in the output transistor and its temperature increases rapidly.

When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set and

the corresponding output switched off.

For the load diagnostic in output off condition each output features a diagnostic current sink, of typ 60µA.

FUNCTIONAL DESCRIPTION

General

The L9823 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using

the Serial Peripheral Interface = SPI protocol. The power outputs features voltage clamping function for flyback

current recirculation and are protected against short circuit to Vbat.

The diagnostics recognizes two outputs fault conditions: 1) overcurrent and thermal overload in switch-ON con-

dition and 2) open load or short to GND in switch-OFF condition for all outputs. The outputs status can be read

out via the serial interface.

The chip internal Reset is a OR function of the external Reset signal and internally generated undervoltage Re-

set signal.

7/12

L9823

Output Stages Control

Each output is controlled with its latch and with a common Reset line, which enables all outputs.

The control data are transmitted via the SI input, the timing of the serial interface is shown in Fig. 1.

The device is selected with low CSB signal and the input data are transferred into the 8 bit shift register at every

falling SCLK edge. The rising edge of the CSB latches the new data from the shift register to the drivers.

Figure 1. Timing of the Serial Interface

CSB

tsclch

tcsdv

thclcl

tclh

tcll

tsclcl

thclch

SCLK

tpcld

tpchdz

not defined

thcld

tscld

The SPI register data are transferred to the output latch at rising CSB edge. The digital filter between CSB and

the output latch ensures that the data are transferred only after 8 SCLK cycles or multiple of 8 SCLK cycles

since the last CSB falling edge. The CSB changes only at low SCLK.

Diagnostics

The output voltage at all outputs is compared with the diagnostic threshold, typ 0,55

Diagnostic Table for outputs:

•

= V

Output

off

Output-voltage

> DG-threshold

< DG-threshold

> DG-threshold

Status-bit

high

Output-mode

correct operation

fault condition 2)

correct operation

fault condition 1)

off

low

high

Fault condition 1) "output short circuit to Vbat" : For SFPD = Low the output was switched on and the voltage at

the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the

output has been switched off. The diagnostic bit is high.

: For SFPD = High the output was switched on and the voltage at the output exceeds the diagnostics threshold.

The output operates in current regulation mode or has been switched off due to thermal shutdown. The status

bit is high.

Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the

output drops below the diagnostics threshold, because the load current is lower than the output diagnostic cur-

rent source, the load is interrupted. The diagnostic bit is low.

At the falling edge of CSB the output status data are transferred to the shift register. When SCB is low, data bits

contained in the shift register are transferred to SO output at every rising SCLK edge.

8/12

L9823

Figure 2. Pulse Diagram to Read the Outputs Status Register

CSB

SCLK

MSB

LSB

MSB

LSB

Figure 3. Structure of the Outputs Status Register

MSB

LSB

Diag7Diag6Diag5Diag4Diag3Diag2Diag1Diag0

Diagnostic-bit ou

9/12

L9823

APPLICATIONS INFORMATION

The typical application diagram for parallel Input SPI control is shown in Figure 4.

Figure 4. Typical Application Circuit Diagram for the L9823 Circuit.

BAT

VOLTAGE

REGULATOR

SFPD

OUT0

OL0

CSB

Gate

Control

SCB

Over

Temperature

Detect

OT0

CH0

SCLK

Diag0

Diag1

Diag2

Diag3

Diag4

Diag5

Diag6

Diag7

OUT1

OUT2

OUT3

CH1

CH2

Diag1

Diag2

Diag3

CH3

OUT4

Diag4

CH4

OUT5

Diag5

CH5

OUT6

Diag6

Reset

CH7

Reset

OUT7

Diag7

CH7

Undervoltage

RESET

µP

U459

R, L loads

5 -8

17 - 20

GND

U459

For higher current driving capability more outputs of the same kind can be paralleled. In this case the maximum

flyback energy should not exceed the limit value for single output.

The immunity of the circuit with respect to the transients at the output is verified during the characterization for

Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with

200pF series capacitor. The correct function of the circuit with the Test Pulses coupled to the outputs is verified

during the characterization for the typical application with R = 16Ω to 200Ω, L= 0 to 600mH loads. All outputs

withstand testpulses without damage.

10/12

L9823

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN.

2.35

0.10

0.33

0.23

15.20

TYP. MAX. MIN.

2.65 0.093

0.30 0.004

0.51 0.013

0.32 0.009

15.60 0.598

TYP. MAX.

0.104

0.012

0.200

Weight: 0.60gr

0.013

(1)

0.614

7.40

7.60 0.291

1.27

0.299

0.050

10.0

0.25

0.40

10.65 0.394

0;75 0.010

1.27 0.016

0˚ (min.), 8˚ (max.)

0.10

0.419

0.030

0.050

ddd

0.004

SO24

(1) “D” dimension does not include mold flash, protusions or gate

burrs. Mold flash, protusions or gate burrs shall not exceed

0.15mm per side.

0070769 C

11/12

L9823

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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http://www.st.com

12/12

L9823 [STMICROELECTRONICS]

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