M24M01 [STMICROELECTRONICS]
1 Mbit Serial IC Bus EEPROM; 1兆位串行I²C总线EEPROM
| 型号： | M24M01 |
| 厂家： | 
ST |
| 描述： | 1 Mbit Serial IC Bus EEPROM |
| 文件： | 总19页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24M01
1 Mbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■ 400 kHz High Speed Two Wire I C Serial
2
Figure 1. Packages
Interface
■ Single Supply Voltage:
– 2.7V to 3.6V for M24M01-V
– 1.8V to 3.6V for M24M01-S
■ Write Control Input
■ BYTE and PAGE WRITE (up to 128 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ More than 100000 Erase/Write Cycles
■ More than 40 Year Data Retention
LGA
LGA8 (LA)
January 2003
1/19
M24M01
SUMMARY DESCRIPTION
The M24M01 is a 1 Mbit (131,072 x 8) electrically
erasable programmable memory (EEPROM) ac-
cessed by an I C-compatible bus.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9 bit time,
th
2
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 2. Logic Diagram
V
CC
Figure 3. LGA Connections
2
E1-E2
SCL
WC
SDA
M24M01
M24M01
V
DU
E1
E2
8
7
6
5
1
2
3
4
CC
WC
SCL
SDA
V
SS
V
SS
AI04051C
AI04048B
Note: 1. DU = Don’t Use (should be left unconnected, or tied to
V
)
SS
Table 1. Signal Names
E1, E2
SDA
SCL
Chip Enable
Power On Reset: V
Lock-Out Write Protect
CC
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
voltage, below the POR threshold value, all oper-
WC
has reached the POR
CC
V
V
CC
SS
drops from the operating
CC
ations are disabled and the device will not respond
to any command. A stable and valid V
applied before applying any logic signal.
must be
CC
2
These devices are compatible with the I C memo-
ry protocol. This is a two wire serial interface that
uses a bi-directional data bus and serial clock. The
devices carry a built-in 4-bit Device Type Identifier
When the power supply is turned on, V
rises
CC
from V to V (min), passing through a value V
SS
CC
th
in between. The device ignores all instructions un-
til a time delay of t has elapsed after the mo-
2
code (1010) in accordance with the I C bus defini-
PU
tion.
ment that V
rises above the V threshold.
CC
th
2
However, the correct operation of the device is not
guaranteed if, by this time, V is still below
The device behaves as a slave in the I C protocol,
CC
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.
V
(min).No instructions should be sent until the
CC
later of:
– t after V
passed the V threshold
PU
CC
th
– V passed the V (min) level
CC
CC
These values are specified in Table 9.
2/19
M24M01
SIGNAL DESCRIPTION
Serial Clock (SCL)
Chip Enable (E1, E2)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con-
These input signals are used to set the value that
is to be looked for on bits b3 and b2 of the 7-bit De-
vice Select Code. These inputs must be tied to
V
or V , to establish the Device Select Code.
CC
SS
When unconnected, the Chip Enable (E1, E2) sig-
nected from Serial Clock (SCL) to V . (Figure 4
nals are internally read as V (see Tables 10 and
CC
IL
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
11).
Write Control (WC)
This input signal is useful for protecting the entire
contents of the memory from inadvertent write op-
erations. Write operations are disabled to the en-
tire memory array when Write Control (WC) is
driven High. When unconnected, the signal is in-
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
ternally read as V , and Write operations are al-
lowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
IL
be connected from Serial Data (SDA) to V . (Fig-
CC
ure 4 indicates how the value of the pull-up resistor
can be calculated).
2
Figure 4. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
3/19
M24M01
DEVICE OPERATION
2
The device supports the I C protocol. This is sum-
marized in Figure 2. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The M24M01 device is always a
slave in all communication.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 2-bit Chip Enable “Address”
(E1, E2). To address the memory array, the 4-bit
Device Type Identifier is 1010b.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Up to four memory devices can be connected on a
2
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
single I C bus. Each one is given a unique 2-bit
code on the Chip Enable (E1, E2) inputs. When
the Device Select Code is received on Serial Data
(SDA), the device only responds if the Chip Enable
Address is the same as the value on the Chip En-
able (E1, E2) inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
Acknowledge Bit (ACK)
th
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
on Serial Data (SDA) during the 9 bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
(SDA) after sending eight bits of data. During the
th
9
clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
1
Table 2. Device Select Code
Device Type Identifier
Chip Enable Address
RW
b0
b7
1
b6
0
b5
1
b4
0
b3
E2
b2
E1
b1
A16
Device Select Code
RW
Note: 1. The most significant bit, b7, is sent first.
4/19
M24M01
2
Figure 5. I C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 3. Operating Modes
Mode
1
RW bit
Bytes
Initial Sequence
START, Device Select, RW = 1
WC
X
Current Address Read
Random Address Read
1
0
1
1
0
0
1
1
X
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 128
START, Device Select, RW = 0
Note: 1. X = VIH or VIL.
5/19
M24M01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120C
nificant Byte. Bits A16 to A0 form the address of
the byte in memory.
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10 bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
th
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 6.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
Each data byte in the memory has a 17-bit ad-
dress. The most significant bit, A16, is sent with
the Device Select Code, and the remaining bits,
A15-A0, in the two address bytes. The Most Sig-
nificant Byte is sent first, followed by the Least Sig-
6/19
M24M01
terminates the transfer by generating a Stop con-
dition, as shown in Figure 7.
Page Write
The bus master sends from 1 to 128 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 7 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
The Page Write mode allows up to 128 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits
(b16-b7) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. This should be avoided, as
data starts to become overwritten in an implemen-
tation dependent way.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01106C
7/19
M24M01
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
The maximum Write time (t ) is shown in Table
w
12, but the typical time is shorter. To make use of
this, a polling sequence can be used by the bus
master.
The sequence, as shown in Figure 8, is:
– Initial condition: a Write cycle is in progress.
8/19
M24M01
Figure 9. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
must not acknowledge the byte, and terminates
the transfer with a Stop condition.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but
without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device Se-
lect Code with the RW bit set to 1. The device ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The bus master terminates the
9/19
M24M01
transfer with a Stop condition, as shown in Figure
9, without acknowledging the byte.
Sequential Read
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9.
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
th
9 bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
The output data comes from consecutive address-
es, with the internal address counter automatically
10/19
M24M01
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
°C
°C
V
TSTG
Storage Temperature
–65
150
1
TLEAD
VIO
Lead Temperature during Soldering
Input or Output range
LGA: 20 seconds (max)
235
4.2
–0.6
–0.3
VCC
Supply Voltage
4.2
V
2
VESD
–3000
3000
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
11/19
M24M01
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 5. Operating Conditions (M24M01-V)
Symbol
Parameter
Min.
2.7
Max.
3.6
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 6. Operating Conditions (M24M01-S)
Symbol
Parameter
Min.
1.8
Max.
3.6
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
Table 7. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
Input Pulse Voltages
50
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Voltages
V
CC
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 10. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
0.2V
CC
CC
0.7V
CC
0.3V
CC
AI00825B
Table 8. Capacitance
Symbol
Parameter
Test Condition
Min.
Max.
Unit
pF
CIN
CIN
Input Capacitance (SDA)
8
6
Input Capacitance (other pins)
pF
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
50
ns
Note: 1. T = 25 °C, f = 400 kHz
A
2. Sampled only, not 100% tested.
12/19
M24M01
Table 9. Power-Up Timing and V Threshold
th
1
Symbol
Parameter
Time delay to Read or Write instruction
Threshold Voltage
Min.
Max.
Unit
Test Condition
200
1.4
µs
tPU
Vth
1.1
V
Note: 1. These parameters are characterized only.
Table 10. DC Characteristics (M24M01-V)
Test Condition
(in addition to those in Table 5)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA, E1, E2, WC)
ILI
VIN = VSS or VCC
± 1
µA
ILO
ICC
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
Output Leakage Current
Supply Current
± 2
2
µA
mA
µA
V
CC =3.6V, f =400kHz (rise/fall time < 30ns)
c
ICC1
Stand-by Supply Current
VIN = VSS or VCC , 2.7 V ≤ VCC ≤ 3.6 V
2
Input Low Voltage
(E1, E2, SCL, SDA, WC)
VIL
0.3VCC
– 0.3
V
Input High Voltage
(E1, E2, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.4
V
V
VOL
Output Low Voltage
IOL = 2.5 mA, 2.7 V ≤ VCC ≤ 3.6 V
Table 11. DC Characteristics (M24M01-S)
Test Condition
(in addition to those in Table 6)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA, E1, E2, WC)
ILI
VIN = VSS or VCC
± 1
µA
ILO
ICC
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
Output Leakage Current
Supply Current
± 2
2
µA
mA
µA
V
CC =3.6V, f =400kHz (rise/fall time < 30ns)
c
ICC1
Stand-by Supply Current
VIN = VSS orVCC , VCC=3.6 V
2
Input Low Voltage
(E1, E2, SCL, SDA, WC)
VIL
VIH
0.3VCC
VCC+1
– 0.3
V
V
Input High Voltage
(E1, E2, SCL, SDA, WC)
0.7VCC
IOL = 2.5 mA, 2.7 V ≤ VCC ≤ 3.6 V
RL = 2.2 kΩ, 1.8 V ≤ VCC ≤ 3.6 V
0.4
V
V
VOL
Output Low Voltage
0.2VCC
13/19
M24M01
Table 12. AC Characteristics
Test conditions specified in Table 7 and Table 5 or Table 6
Symbol
fC
Alt.
fSCL
Parameter
Min.
Max.
400
300
300
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Frequency
Clock Rise Time
Clock Fall Time
tCH1CH2
tCL1CL2
tCHCL
tR
20
20
tF
tHIGH
tLOW
tR
Clock Pulse Width High
Clock Pulse Width Low
SDA Rise Time
600
1300
20
tCLCH
2
300
300
tDH1DH2
2
tF
SDA Fall Time
20
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
100
0
Data In Hold Time
Data Out Hold Time
200
205
600
600
600
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
900
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tCHDX
tDLCL
tCHDH
Time between Stop Condition and Next Start
Condition
tDHDL
tW
tBUF
tWR
1300
ns
Write Time
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
14/19
M24M01
Figure 11. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
STOP
tCHDX
START
Condition
tW
Write Cycle
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
15/19
M24M01
PACKAGE MECHANICAL
LGA8 - 8 lead Land Grid Array, Package Outline
CONTACT 1
D
D1
T3
E1
k
E
E2
T1
T2
E3
A
A2
A1
ddd
LGA-Z01B
Notes: 1. Drawing is not to scale.
LGA8 - 8 lead Land Grid Array, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
Max.
Typ.
Min.
Max.
A
A1
A2
D
1.040
0.340
0.700
8.000
0.100
5.000
1.270
3.810
0.390
0.100
0.410
0.670
0.970
0.100
0.940
1.140
0.0409
0.0134
0.0276
0.3150
0.0039
0.1969
0.0500
0.1500
0.0154
0.0039
0.0161
0.0264
0.0382
0.0039
0.0370
0.0449
0.300
0.380
0.0118
0.0150
0.640
0.760
0.0252
0.0299
7.900
8.100
0.3110
0.3189
D1
E
–
–
–
–
4.900
5.100
0.1929
0.2008
E1
E2
E3
k
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
T1
T2
T3
ddd
16/19
M24M01
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M24M01
–
V
LA
6
T
Device Type
2
M24 = I C serial access EEPROM
Device Function
M01 = 1 Mbit (131,072 x 8)
Operating Voltage
V = V = 2.7 to 3.6V
CC
S = V = 1.8 to 3.6V
CC
Package
LA = LGA8 (Land Grid Array)
Temperature Range
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
17/19
M24M01
REVISION HISTORY
Table 14. Document Revision History
Date
Rev.
Description of Revision
LGA8 Package mechanical data updated
Datasheet released as Product Preview
02-Oct-2001
1.0
Table added on Power-up Timing
Full Datasheet released
21-Jun-2002
08-Jan-2003
1.1
1.2 Added LGA maximum rating for soldering temperature
18/19
M24M01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2003 STMicroelectronics - All Rights Reserved
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19/19
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