PM6681A_08 [STMICROELECTRONICS]
Dual synchronous step-down controller with adjustable LDO; 可调LDO的双同步降压控制器
| 型号： | PM6681A_08 |
| 厂家： | 
ST |
| 描述： | Dual synchronous step-down controller with adjustable LDO |
| 文件： | 总47页 (文件大小：2765K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PM6681A
Dual synchronous step-down controller with adjustable LDO
Features
■ 6 V to 36 V input voltage range
■ Adjustable output voltages
■ 0.9 - 3.3 V LDO adjustable delivers 100 mA
peak current
■ 5 V LDO delivers 100 mA peak current
■ 1.237 V 1 % reference voltage available
VFQFPN-32 (5 mm x 5 mm)
■ No R
current sensing using low side
SENSE
MOSFETs' R
DS(on)
Description
■ Negative current limit
PM6681A is a dual step-down controller
■ Soft-start internally fixed at 2 ms
■ Soft output discharge
specifically designed to provide extremely high
efficiency conversion, with lossless current
sensing technique. The constant on-time
architecture assures fast load transient response
and the embedded voltage feed-forward provides
nearly constant switching frequency operation. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
Pulse skipping technique increases efficiency at
very light load. Moreover a minimum switching
frequency of 33 kHz is selectable to avoid audio
noise issues. The PM6681A provides a selectable
switching frequency, allowing three different
values of switching frequencies for the two
switching sections. The output voltages OUT1
and OUT2 can be adjusted from 0.9 V to 5 V and
from 0.9 V to 3.3 V respectively. The device
provides also 2 LDOs, 5 V fixed and 0.9 V - 3.3 V
adjustable.
■ Latched UVP
■ Not-latched OVP
■ Selectable pulse skipping at light loads
■ Selectable minimum frequency (33 kHz) in
pulse skip mode
■ 5 mW maximum quiescent power
■ Independent Power Good signals
■ Output voltage ripple compensation
Applications
■ Embedded computer system
■ FPGA system power
■ Industrial applications on 24 V
■ High performance and high density DC-DC
modules
■ Notebook computer
Table 1.
Order codes
Order codes
Package
Packaging
PM6681A
Tray
VFQFPN-32 (5 mm x 5 mm)
exposed pad
PM6681ATR
Tape and reel
June 2008
Rev 3
1/47
www.st.com
47
Contents
PM6681A
Contents
1
2
Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
4
5
6
7
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 20
Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.10 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28
8
Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1
8.2
8.3
8.4
Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/47
PM6681A
Contents
9
Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.8.7
9.8.8
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Output feedback divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10
11
12
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/47
Simplified application schematic
PM6681A
1
Simplified application schematic
Figure 1.
Application schematic
4/47
PM6681A
Pin settings
2
Pin settings
2.1
Connections
Figure 2.
Pin connection (top view)
32
31
30
29
28
27
26
25
1
24
SKIP
SGND
2
3
4
23
22
21
COMP2
FSEL
BOOT1
HGATE1
PHASE1
CSENSE1
EN2
PM6681A
5
6
20
19
SHDN
FB2
VIN
7
8
18
17
LDO
LDO5
V5SW
OUT2
9
10
11
12
13
14
15
16
2.2
Functions
Table 2.
N°
Pin functions
Pin
Function
Signal ground. Reference for internal logic circuitry. It must be connected to
the signal ground plan of the power supply. The signal ground plan and the
power ground plan must be connected together in one point near the PGND
pin.
1
SGND
2
3
COMP2
FSEL
DC voltage error compensation pin for the switching section 2
Frequency selection pin. It provides a selectable switching frequency,
allowing three different values of switching frequencies for the switching
sections.
5/47
Pin settings
PM6681A
Table 2.
N°
Pin functions (continued)
Pin
Function
Enable input for the switching section 2.
– The section 2 is enabled applying a voltage greater than 2.4 V to this pin.
– The section 2 is disabled applying a voltage lower than 0.8 V.
4
EN2
When the section is disabled the high side gate driver goes low and Low
Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin
is high the device enters in standby mode.
Shutdown control input.
– The device switch off if the SHDN voltage is lower than the device off
threshold (shutdown mode)
– The device switch on if the SHDN voltage is greater than the device on
threshold.
5
6
SHDN
FB2
The SHDN pin can be connected to the battery through a voltage divider to
program an undervoltage lockout. In shutdown mode, the gate drivers of the
two switching sections are in high impedance (high-Z).
Feedback input for the switching section 2 This pin is connected to a
resistive voltage-divider from OUT2 to PGND to adjust the output voltage
from 0.9 V to 3.3 V.
Adjustable internal regulator output. It can be set from 0.9 V to 3.3 V.
LDO pin can provide a 100 mA peak current.
7
8
LDO
Output voltage sense for the switching section 2. This pin must be directly
connected to the output voltage of the switching section.
OUT2
Bootstrap capacitor connection for the switching section 2. It supplies the
high-side gate driver.
9
BOOT2
HGATE2
PHASE2
High-side gate driver output for section 2. This is the floating gate driver
output.
10
11
Switch node connection and return path for the high side driver for the
section 2. It is also used as negative current sense input.
Positive current sense input for the switching section 2. This pin must be
connected through a resistor to the drain of the synchronous rectifier
(RDS(on) sensing) to obtain a positive current limit threshold for the power
supply controller.
12
CSENSE2
13
14
15
LGATE2
PGND
Low-side gate driver output for the section 2.
Power ground. This pin must be connected to the power ground plan of the
power supply.
LGATE1
Low-side gate driver output for the section 1.
Feedback input for the adjustable internal linear regulator. This pin is
connected to a resistive voltage-divider from LDO to SGND to adjust the
output voltage from 0.9 V to 3.3 V.
16
LDO FB
V5SW
Internal 5 V regulator bypass connection.
– If V5SW is connected to OUT5 (or to an external 5 V supply) and V5SW is
greater than 4.9 V, the LDO5 regulator shuts down and the LDO5 pin is
directly connected to OUT5 through a 3 W (max) switch.
17
If V5SW is connected to GND, the LDO5 linear regulator is always on if the
device is not in shutdown mode.
6/47
PM6681A
Pin settings
Table 2.
N°
Pin functions (continued)
Pin
Function
5 V internal regulator output. It can provide up to 100 mA peak current.
LDO5 pin supplies embedded low side gate drivers and an external load.
18
19
LDO5
VIN
Device supply voltage input and battery voltage sense. A bypass filter
(4 W and 4.7 µF) between the battery and this pin is recommended.
Positive current sense input for the switching section 1. This pin must be
connected through a resistor to the drain of the synchronous rectifier
(RDS(on) sensing) to obtain a positive current limit threshold for the power
supply controller.
20
CSENSE1
Switch node connection and return path for the high side driver for the
section 1. It is also used as negative current sense input.
21
22
23
PHASE1
HGATE1
BOOT1
High-side gate driver output for section 1. This is the floating gate driver
output.
Bootstrap capacitor connection for the switching section 1. It supplies the
high-side gate driver.
Pulse skipping mode control input.
– If the pin is connected to LDO5 the PWM mode is enabled.
– If the pin is connected to GND, the pulse skip mode is enabled.
24
25
SKIP
EN1
– If the pin is connected to VREF the pulse skip mode is enabled but the
switching frequency is kept higher than 33 kHz
(No-audible pulse skip mode).
Enable input for the switching section 1.
– The section 1 is enabled applying a voltage greater than 2.4 V to this pin.
– The section 1 is disabled applying a voltage lower than 0.8 V.
when the section is disabled the high side gate driver goes low and low side
gate driver goes high.
Power Good output signal for the section 1. This pin is an open drain output
and when the output of the switching section 1 is out of +/- 10 % of its
nominal value.It is pulled down.
26
27
28
PGOOD1
PGOOD2
FB1
Power Good output signal for the section 2. This pin is an open drain output
and when the output of the switching section 2 is out of +/- 10 % of its
nominal value.It is pulled down.
Feedback input for the switching section 1. This pin is connected to a
resistive voltage-divider from OUT1 to PGND to adjust the output voltage
from 0.9 V to 5.5 V.
Output voltage sense for the switching section 1.This pin must be directly
connected to the output voltage of the switching section.
29
30
31
OUT1
COMP1
VCC
DC voltage error compensation pin for the switching section 1.
Device supply voltage pin. It supplies all the internal analog circuitry except
the gate drivers (see LDO5). Connect this pin to LDO5.
Internal 1.237 V high accuracy voltage reference. It can deliver 50 µA.
Bypass to SGND with a 100 nF capacitor to reduce noise.
32
VREF
7/47
Functional block diagram
PM6681A
3
Functional block diagram
Figure 3.
Functional block diagram
8/47
PM6681A
Maximum ratings
4
Maximum ratings
Table 3.
Absolute maximum ratings
Parameter
Value
Unit
V5SW, LDO5 to PGND
VIN to PGND
-0.3 to 6
-0.3 to 36
-0.3 to 6
V
V
V
V
V
V
V
V
V
V
W
V
HGATEx and BOOTx, to PHASEx
PHASEx to PGND
-0.6 (1) to36
-0.6 to 42
-6 to 0.3
CSENSEx, to PGND
CSENSEx to BOOTx
LGATEx to PGND
-0.3 (2) to LDO5 +0.3
-0.3 to Vcc+0.3
-0.3 to 0.3
-0.3 to 6
FBx, COMPx, SKIP, FSEL,VREF to SGND, LDO FB
PGND to SGND
SHDN, PGOODx, OUTx, VCC, ENx to SGND
Power dissipation at TA = 25 °C
2.8
Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002- “human body model” acceptance
criteria: “normal performance”
VIN
1000
Other pins
2000
1. PHASE to PGND up to -2.5 V for t < 10 ns
2. LGATEx to PGND up to -1 V for t < 40 ns
Table 4.
Symbol
Thermal data
Parameter
Value
Unit
TSTG
RthJA
TJ
Storage temperature range
-50 to 150
35
°C
°C/W
°C
Thermal resistance junction to ambient
Junction operating temperature range
Operating ambient temperature range
-40 to 125
-40 to 85
TA
°C
Table 5.
Symbol
Recommended operating conditions
Value
Parameter
Test condition
Unit
Min
Typ
Max
VIN
Input voltage range
IC supply voltage
LDO5 in regulation
5.5
4.5
36
V
V
VCC
5.5
VV5SW maximum operating
range
VV5SW
5.5
V
9/47
Electrical characteristics
PM6681A
5
Electrical characteristics
Table 6.
Electrical characteristics
(V = 24 V; T = 25 °C, unless otherwise specified)
IN
J
Symbol
Supply section
Parameter
Test condition
Min
Typ
Max
Unit
Turn-on voltage threshold
Turn-off voltage threshold
Hysteresis
4.8
4.75
50
4.9
V
V
VV5SW
4.6
20
mV
LDO5 internal bootstrap
switch resistance
RDS(on)
V5SW > 4.9 V
1.8
18
3
Ω
Ω
OUTx, OUTx
discharge-mode
25
On-resistance
OUTx, OUTx
discharge-mode
0.2
0.35
0.6
V
Synchronous rectifier
turn-on level
Operating power
consumption
FBx > VREF, Vref in regulation,
V5WS to 5 V
Pin
Ish
Isb
4
mW
µA
Operating current sunk by
VIN
SHDN connected to GND
ENx to GND, V5SW to GND
20
30
Operating current sunk by
VIN
250
380
µA
Shutdown section
Device on threshold
Device off threshold
soft-start section
soft-start ramp time
Current limit and zero crossing comparator
1.2
0.8
1.5
1.7
0.9
V
V
VSHDN
0.85
2
3.5
ms
ICSENSE
Input bias current limit (1)
Comparator offset
90
-6
100
110
6
µA
VCSENSE - VPGND
VPGND - VPHASE
mV
Zero crossing comparator
offset
-1
11
mV
mV
Fixed negative current limit
threshold
VPGND - VPHASE
-120
10/47
PM6681A
Electrical characteristics
Table 6.
Symbol
Electrical characteristics
(V = 24 V; T = 25 °C, unless otherwise specified) (continued)
IN
J
Parameter
Test condition
Min
Typ
Max
Unit
On time pulse width
FSEL to GND
575
195
390
145
285
110
680
230
460
175
340
135
785
265
530
205
395
160
OUT1 = 3.3 V
OUT2 = 1.8 V
FSEL to VREF
OUT1 = 3.3 V
OUT2 = 1.8 V
On time duration_
@VIN = 24 V
Ton
ns
FSEL to LDO5
OUT1 = 3.3 V
OUT2 =1.8 V
OFF time
Minimum off time
@VIN = 24 V
TOFFMIN
350
500
ns
Voltage reference
VREF
Voltage accuracy
4 V < VLDO5 < 5.5 V
1.224
-4
1.236
1.249
4
V
Load regulation
-100 µA< IREF < 100 µA
mV
Undervoltage lockout fault
threshold
Falling edge of REF
0.95
mV
Integrator
FB
Voltage accuracy
Input bias current
Over voltage clamp
Under voltage clamp
+891
+909
mV
µA
(1)
FB
0.1
250
-150
COMP
COMP
Normal mode
mV
Line regulation
Both SMPS, 6 V < Vin < 36 V (1)
1
%
V
LDO5 linear regulator
6 V < VIN < 36 V,
0 < ILDO5 < 50 mA
VLDO5
LDO5 linear output voltage
4.9
5.0
5.1
LDO5 line regulation
LDO5 current limit
6 V < VIN < 36 V, ILDO5 = 20 mA ,
VLDO5 > UVLO
0.004
400
%/V
mA
ILDO5
ULVO
270
330
4
Under voltage lockout of
LDO5
3.94
4.13
V
LDO linear regulator
4.5 V< V5SW < 5.5 V
0.5 mA < ILDO < 50 mA
VLDO
LDO linear output voltage
0.887
0.905
0.923
V
LDO FB connected to LDO
11/47
Electrical characteristics
Table 6. Electrical characteristics
Symbol
PM6681A
(V = 24 V; T = 25 °C, unless otherwise specified) (continued)
IN
J
Parameter
Test condition
Min
Typ
Max
Unit
ILDO
LDO current limit
Input bias current
170
220
0.1
270
mA
µA
(1)
ILDO FB
High and low gate drivers
HGATE driver on-resistance
HGATEx high state (pull-up)
HGATEx low state (pull-down)
LGATEx high state (pull-up)
LGATEx low state (pull-down)
2.0
1.6
1.4
0.8
3
2.7
2.1
1.2
Ω
LGATE driver on-resistance
PGOOD pins UVP/OVP protections
Both SMPS sections with
respect to VREF, OUT1 = 5 V,
OUT2 = 3.3 V
OVP
UVP
Over voltage threshold
Under voltage threshold
112
116
120
%
65
68
71
%
%
Upper threshold
(VFB-VREF)
107
110
113
PGOOD1,2
Lower threshold
(VFB-VREF)
88
91
94
%
IPGOOD1,2 PGOOD leakage current
VPGOOD1,2 output low voltage
VPGOOD1,2 forced to 5.5 V
ISink = 4 mA
1
uA
150
250
mV
Power management pins
(1)
(1)
SMPS disabled level
EN1,2
0.8
0.5
V
V
SMPS enabled level
2.4
1.0
Frequency selection range
FSEL
Low level (1)
VLDO5
1.5
-
-
Middle level (1)
VLDO5
0.8
-
-
High level (1)
(1)
Pulse skip mode
0.5
VLDO5
1.5
(1)
Ultrasonic mode
SKIP
1.0
V
VLDO5
0.8
(1)
PWM mode
VEN1,2 = 0 to 5 V
1
1
1
1
V
SKIP = 0 to 5 V
VSHDN = 0 to 5 V
FSEL = 0 to 5 V
Input leakage current
µA
V
1. by design
12/47
PM6681A
Typical operating characteristics
6
Typical operating characteristics
(FSEL = GND (200/300 kHz), SKIP = GND (skip mode), V5SW = EXT5 V (external 5 V
power supply connected), input voltage VIN = 24 V, SHDN, EN1 and EN2 high,
OUT1 = 3.3 V, OUT2 = 1.8 V, no load, LDO = 3.3 V, (LDO_FB divider = 5.6 k and 15 k)
unless specified)
Figure 4.
Efficiency vs current load
Figure 5.
Efficiency vs current load
\
Figure 6.
PWM no load battery current Figure 7.
vs input voltage
No-audible skip no load
battery current vs input
voltage
\
Figure 8.
Skip no load battery current Figure 9.
Shutdown mode input battery
current vs input voltage
vs input voltage
\
13/47
Typical operating characteristics
PM6681A
Figure 10. Standby mode input battery Figure 11. Voltage reference vs load
current vs input voltage current
\
Figure 12. OUT1 = 3.3 V switching
frequency
Figure 13. OUT2 = 1.8 V switching
frequency
\
Figure 14. OUT1 = 3.3 V load regulation Figure 15. OUT2 = 1.8 V load regulation
\
14/47
PM6681A
Typical operating characteristics
Figure 16. LDO5 vs output current
Figure 17. LDO vs output current
\
Figure 18. SHDN, OUT1, LDO and LDO5 Figure 19. OUT1, OUT2, LDO and LDO5
power-up
power-up
\
Figure 20. OUT1 = 3.3 V load transient
0 to 2 A
Figure 21. OUT2 = 1.8 V load transient
0 to 2 A
\
15/47
Typical operating characteristics
PM6681A
Figure 22. 3.3 V soft-start (1 Ω load)
Figure 23. 1.8 V soft-start (0.6 Ω load)
\
Figure 24. OUT1 = 3.3 V
soft-end (no load)
Figure 25. OUT2 = 1.8 V
soft-end (no load)
\
Figure 26. OUT1 = 3.3 V soft-end
Figure 27. OUT2 = 1.8 V soft-end
(0.8 Ω load)
(0.6 Ω load)
\
16/47
PM6681A
Typical operating characteristics
Figure 28. 3.3 V no-audible skip mode
Figure 29. 1.8 V no-audible skip mode
\
17/47
Device description
PM6681A
7
Device description
The PM6681A is a dual step-down controller dedicated to provide logic voltages for
industrial automation application and notebook computer.
It is based on a constant on time control architecture. This type of control offers a very fast
load transient response with a minimum external component count. A typical application
circuit is shown in Figure 1. The PM6681A regulates two adjustable output voltages: OUT1
and OUT2. The switching frequency of the two sections can be adjusted to three different
values. In order to maximize the efficiency at light load condition, a pulse skipping mode can
be selected. The PM6681A includes also a 5 V linear regulator (LDO5) that can power the
switching drivers. If the output OUT1 regulates 5 V, in order to maximize the efficiency in
higher consumption status, the linear regulator can be turned off and their outputs can be
supplied directly from the switching outputs. Moreover, the PM6681A includes also a linear
regulator with an output voltage adjustable from 0.9 V to 3.3 V. It can provide 100 mA of
peak current. The PM6681A provides protection versus overvoltage, undervoltage and
overtemperature as well as Power Good signals for monitoring purposes.
An external 1.237 V reference is available.
7.1
Constant on time PWM control
If the SKIP pin is tied to 5 V, the device works in PWM mode. Each power section has an
independent on time control.The PM6681A employees a pseudo-fixed switching frequency,
constant on time (COT) controller as core of the switched mode section. Each power section
has an independent COT control.
The COT controller is based on a relatively simple algorithm and uses the ripple voltage due
to the output capacitor's ESR to trigger the fixed on-time one-shot generator. In this way, the
output capacitor's ESR acts as a current sense resistor providing the appropriate ramp
signal to the PWM comparator. On-time one-shot duration is directly proportional to the
output voltage, sensed at the OUT1/OUT2 pins, and inversely proportional to the input
voltage, sensed at the VIN pin, as follows:
Equation 1
Vout
Ton = K ×
Vin
This leads to a nearly constant switching frequency, regardless of input and output voltages.
When the output voltage goes lower than the regulated voltage Vreg, the on-time one shot
generator directly drives the high side MOSFET for a fixed on time allowing the inductor
current to increase; after the on time, an off time phase, in which the low side MOSFET is
turned on, follows. Figure 30 shows the inductor current and the output voltage waveforms
in PWM mode.
18/47
PM6681A
Device description
Figure 30. Constant on time PWM control
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The duty cycle of the buck converter in steady state is:
Equation 2
Vout
D =
Vin
The PWM control works at a nearly fixed frequency fSW
:
Equation 3
Vout
D
Vin
Vout
1
fsw
=
=
=
Kon
Ton
Kon
×
Vin
As mentioned the steady state switching frequency is theoretically independent from battery
voltage and from output voltage.
Actually the frequency depends on parasitic voltage drops that are present during the
charging path (high side switch resistance, inductor resistance (DCR) and discharging path
(low side switch resistance, DCR).
As a result the switching frequency increases as a function of the load current.
Standard switching frequency values can be selected for both sections by connecting pin
FSEL to SGND, VREF or LDO5 pin. The following table shows the typical switching
frequencies that can be obtained as a function of the programmed output voltage. The
measures are referred to switching sections with 2 A load, 12 V input voltage and working in
continuous conduction mode.
Table 7.
FSEL pin selection: typical switching frequency
Fsw @ OUT1 = 1.5 V (kHz)
Fsw @ OUT2 = 1.05 V (kHz)
FSEL = GND
200
290
390
325
425
590
FSEL = VREF
FSEL = LDO5
19/47
Device description
PM6681A
7.2
Constant on time architecture
Figure 31 shows the simplified block diagram of a constant on time controller. A minimum
off-time constrain (350 ns typ.) is introduced to allow inductor valley current sensing on
synchronous switch. A minimum on-time (130 ns) is also introduced to assure the start-up
switching sequence.
PM6681A has a one-shot generator for each power section that turns on the high side
MOSFET when the following conditions are satisfied simultaneously: the PWM comparator
is high, the synchronous rectifier current is below the current limit threshold, and the
minimum off-time has timed out.
Once the on-time has timed out, the high side switch is turned off, while the synchronous
switch is turned on according to the anti-cross conduction circuitry management.
When the negative input voltage at the PWM comparator (Figure 31), which is a scaled-
down replica of the output voltage (see the external R1/R2 divider in Figure 32), reaches the
valley limit (determined by internal reference Vr = 0.9 V), the low-side MOSFET is turned off
according to the anti-cross conduction logic once again, and a new cycle begins.
Figure 31. Constant on-time block diagram
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7.3
Output ripple compensation and loop stability
In a classic constant on time control, the system regulates the valley value of the output
voltage and not the average value, as shown in Figure 30. In this condition, the output
voltage ripple is source of a DC static error.
To compensate this error, an integrator network can be introduced in the control loop, by
connecting the output voltage to the COMP1/COMP2 (for the OUT1 and OUT2 sections
respectively) pin through a capacitor CINT as in Figure 32.
20/47
PM6681A
Device description
Figure 32. Circuitry for output ripple compensation
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The integrator amplifier generates a current, proportional to the DC errors between the FB
voltage and Vr, which decreases the output voltage in order to compensate the total static
error, including the voltage drop on PCB traces. In addition, CINT provides an AC path for
the output ripple. In steady state, the voltage on COMP1/COMP2 pin is the sum of the
reference voltage Vr and the output ripple (see Figure 32). In fact when the voltage on the
COMP pin reaches Vr, a fixed Ton begins and the output increases.
For example, we consider Vout = 5 V with an output ripple of ∆V = 50 mV. Considering CINT
>> CFILT, the CINT DC voltage drop VCINT is about 5 V - Vr + 25 mV = 4.125 V.
CINT assures an AC path for the output voltage ripple. Then the COMP pin ripple is a replica
of the output ripple, with a DC value of Vr + 25 mV = 925 mV.
For more details about the output ripple compensation network, see the paragraph “Closing
the integrator loop” in the design guidelines.
In steady state the FB pin voltage is about Vr and the regulated output voltage depends on
the external divider:
Equation 4
⎛
⎜
⎝
⎞
⎟
⎟
R2
R1
⎜
OUT = Vr × 1+
⎠
7.4
Pulse skip mode
If the SKIP pin is tied to ground, the device works in skip mode.
At light loads a zero-crossing comparator truncates the low-side switch on-time when the
inductor current becomes negative. In this condition the section works in discontinuous
conduction mode. The threshold between continuous and discontinuous conduction mode
is:
21/47
Device description
Equation 5
PM6681A
V − VOUT
IN
ILOAD(SKIP) =
× TON
2×L
For higher loads the inductor current doesn't cross the zero and the device works in the
same way as in PWM mode and the frequency is fixed to the nominal value.
Figure 33. PWM and pulse skip mode inductor current
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Figure 33 shows inductor current waveforms in PWM and SKIP mode. In order to keep
average inductor current equal to load current, in SKIP mode some switching cycles are
skipped. When the output ripple reaches the regulated voltage Vreg, a new cycle begins.
The off cycle duration and the switching frequency depend on the load condition.
As a result of the control technique, losses are reduced at light loads, improving the system
efficiency.
7.5
No-audible skip mode
If SKIP pin is tied to VREF, a no-audible skip mode with a minimum switching frequency of
33 kHz is enabled. At light load condition, If there is not a new switching cycle within a 30 µs
(typ.) period, a no-audible skip mode cycle begins.
Figure 34. No audible skip mode
Inductor current
No audible skip mode
∼30us
Time
0
Low side
22/47
PM6681A
Device description
The low side switch is turned on until the output voltage crosses about Vreg+1 %. Then the
high side MOSFET is turned on for a fixed on time period. Afterwards the low side switch is
enabled until the inductor current reaches the zero-crossing threshold. This keeps the
switching frequency higher than 33 kHz. As a consequence of the control, the regulated
voltage can be slightly higher than Vreg (up to 1 %).
If, due to the load, the frequency is higher than 33 kHz, the device works like in skip mode.
No-audible skip mode reduces audio frequency noise that may occur in pulse skip mode at
very light loads, keeping the efficiency higher than in PWM mode.
7.6
Current limit
The current-limit circuit employs a “valley” current-sensing algorithm. During the conduction
time of the low side MOSFET the current flowing through it is sensed. The current-sensing
element is the low side MOSFET on-resistance (Figure 35).
Figure 35. R
sensing technique
DS(on)
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An internal 100 µA current source is connected to CSENSE pin and determines a voltage
drop on RCSENSE. If the voltage across the sensing element is greater than this voltage
drop, the controller doesn't initiate a new cycle. A new cycle starts only when the sensed
current goes below the current limit.
Since the current limit circuit is a valley current limit, the actual peak current limit is greater
than the current limit threshold by an amount equal to the inductor ripple current. Moreover
the maximum output current is equal to the valley current limit plus half of the inductor ripple
current:
Equation 6
∆IL
2
ILOAD(max) = ILvalley
+
The output current limit depends on the current ripple, as shown in Figure 36:
23/47
Device description
Figure 36. Current waveforms in current limit conditions
PM6681A
Maximum load current is
Current
DC current limit = maximum load
Inductor current
influenced by the inductor
current ripple
Valley current threshold
Time
Being fixed the valley threshold, the greater the current ripple is, greater the DC output
current is:
The valley current limit can be set with resistor RCSENSE
:
Equation 7
(R
sensing technique)
DS(on)
RDSon ×ILvalley
RCSENSE
=
ICSENSE
Where ICSENSE = 100 µA, RDS(on) is the drain-source on resistance of the low side switch.
Consider the temperature effect and the worst case value in RDS(on) calculation.
The accuracy of the valley current threshold detection depends on the offset of the internal
comparator (∆VOFF) and on the accuracy of the current generator(∆ICSENSE):
Equation 8
∆ILvalley
⎡
⎢
⎣
⎤
∆ICSENSE
ICSENSE
∆VOFF
RCSENSE ×ICSENSE
∆RCSENSE ∆RSNS
=
+
×100 +
+
⎥
ILvalley
RCSENSE
RSNS
⎦
Where RSNS is the sensing element (RDS(on)).
PM6681A provides also a fixed negative peak current limit to prevent an excessive reverse
inductor current when the switching section sinks current from the load in PWM mode. This
negative current limit threshold is measured between PHASE and SGND pins, comparing
the magnitude drop on the PHASE node during the conduction time of the low side
MOSFET with an internal fixed voltage of 120 mV.
The negative valley-current limit INEG (if the device works in PWM mode) is given by:
Equation 9
120mV
INEG
=
RDSon
24/47
PM6681A
Device description
7.7
soft-start and soft-end
Each switching section is enabled separately by asserting high EN1/EN2 pins respectively.
In order to realize the soft-start, at the startup the overcurrent threshold is set 25 % of the
nominal value and the undervoltage protection (see related sections) is disabled. The
controller starts charging the output capacitor working in current limit. The overcurrent
threshold is increased from 25 % to 100 % of the nominal value with steps of 25 % every
700 µs (typ.). After 2.8 ms (typ.) the undervoltage protection is enabled. The s oft start time
is not programmable. A minimum capacitor CINT is required to ensure a soft-start without
any overshoot on the output:
Equation 10
6uA
CINT
≥
×Cout
ILvalley
∆IL
2
+
4
Figure 37. Soft-start waveforms
Switching
Current limit threshold
EN1/EN2
Time
When a switching section is turned off (EN1/EN2 pins low), the controller enters in soft-end
mode. The output capacitor is discharged through an internal 18 Ω P-MOSFET switch;
when the output voltage reaches 0.3 V, the low-side MOSFET turns on, keeping the output
to ground. The soft-end time also depends on load condition.
7.8
Gate drivers
The integrated high-current drivers allow to use different power MOSFETs. The high side
driver MOSFET uses a bootstrap circuit which is indirectly supplied by LDO5 output. The
BOOT and PHASE pins work respectively as supply and return rails for the HS driver.
The low side driver uses the internal LDO5 output for the supply rail and PGND pin as return
rail.
An important feature of the gate drivers is the adaptive anti-cross conduction protection,
which prevents high side and low side MOSFETs from being on at the same time. When the
25/47
Device description
PM6681A
high side MOSFET is turned off the voltage at the phase node begins to fall. The low side
MOSFET is turned on when the voltage at the phase node reaches an internal threshold.
When the low side MOSFET is turned off, the high side remains off until the LGATE pin
voltage goes approximately under 1 V.
The power dissipation of the drivers is a function of the total gate charge of the external
power MOSFETs and the switching frequency, as shown in the following equation:
Equation 11
Pdriver = Vdriver ×Qg × fsw
Where Vdriver is the 5 V driver supply.
Reference voltage and bandgap
The 1.237 V (typ.) internal bandgap voltage is accurate to 1 % over the temperature range.
It is externally available (VREF pin) and can supply up to 100 µA and can be used as a
voltage threshold for the multifunction pins FSEL and SKIP to select the appropriate working
mode. Bypass VREF to ground with a 100 nF minimum capacitor.
If VREF goes below 0.87 V (typ.), the system detects a fault condition and all the circuitry is
turned off. A toggle on the input voltage (power on reset) or a toggle on SHDN pin is
necessary to restart the device.
An internal divider of the bandgap provides a voltage reference Vr of 0.9 V. This voltage is
used as reference for the linear and the switching regulators outputs. The overvoltage
protection, the undervoltage protection and the Power Good signals are referred to Vr.
7.9
Internal linear regulators
The PM6681A has two linear regulators providing respectively 5 V (LDO5) and an
adjustable voltage (LDO) at 2 % accuracy. High side drivers, low side drivers and
MOSFETs of internal circuitry are supplied by LDO5 output through VCC pin (an external
RC filter may be applied between LDO5 and VCC). The linear regulator can provide an
average output current of 50 mA and a peak output current of 100mA. Bypass LDO5 output
with a minimum 1 µF ceramic capacitor and a 4,7 µF tantalum capacitor (ESR ≥ 2 Ω). If the
5 V output goes below 4 V, the system detects a fault condition and all the circuitry is turned
off. A power on reset or a toggle on SHDN pin is necessary to restart the device.
V5SW pin allows to keep the 5 V linear regulator always active or to enable the internal
bootstrap-switch over function: if the 5 V switching output is connected to V5SW, when the
voltage on V5SW pin is above 4.8 V, an internal 3.0 Ω max P-channel MOSFET switch
connects V5SW pin to LDO5 pin and simultaneously LDO5 shuts down. This configuration
allows to achieve higher efficiency. V5SW can be connected also to an external 5 V supply.
LDO5 regulator turns off and LDO5 is supplied externally. If V5SW is connected to ground,
the internal 5 V regulator is always on and supplies LDO5 output.
26/47
PM6681A
Device description
Table 8.
V5SW
GND
Switching 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and
V5SW multifunction pin
Description
The 5 V linear regulator is always turned on and supplies LDO5 output.
output
LDO5 output is supplied by the switching 5 V output.
External 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and
supply LDO5 output is supplied by the external 5 V.
The adjustable linear regulator is supplied by LDO5 output. It turns on after LDO5 power up
sequence.
It can provide up to 100 mA peak current. Set up the feedback resistor divider according to
the following formula, to regulate a voltage from 0.9 V to 3.3 V.
Equation 12
Rup
⎛
⎞
⎟
⎟
⎠
⎜
LDO = V × 1+
r
⎜
Rdown
⎝
where LDO is the desired output voltage, Vr = 0.9 V is the internal reference voltage and Rup
and Rdown are the resistors of the feedback divider, as shown in Figure 38:
Figure 38. LDO linear regulator
Bypass LDO5 and LDO output with 1-10 µF ceramic capacitor and a 4,7 µF tantalum
capacitor (ESR ≥ 2 Ω).
27/47
Device description
PM6681A
7.10
Power up sequencing and operative modes
Let’s consider SHDN, EN1 and EN2 low at the beginning. The battery voltage is applied as
input voltage. The device is in shutdown mode.
When the SHDN pin voltage is above the shutdown device on threshold (1.5 V typ.), the
controller begins the power-up sequence. All the latched faults are cleared. LDO5
undervoltage control is blanked for 4 ms and the internal regulator LDO5 turns on. If the
LDO5 output is above the UVLO threshold after this time, the device enters in standby mode
and the adjustable internal linear regulator LDO is turned on.
The switching outputs are kept to ground by turning on the low side MOSFETs. When EN1
and EN2 pins are forced high the switching sections begin their soft-start sequence.
Table 9.
Mode
Operative modes
Conditions
Description
SHDN is high,
Switching regulators are enabled; internal linear
regulators outputs are enabled.
Run
EN1/EN2 pins are high
Internal linear regulators active (LDO5 is always on). In
Standby mode LGATE1/LGATE2 pins are forced high
while HGATE1/HGATE2 pins are forced low.
Both EN1/EN2 pins are low
and SHDN pin is high
Standby
Shutdown
SHDN is low
All circuits off.
28/47
PM6681A
Monitoring and protections
8
Monitoring and protections
8.1
8.2
Power Good signals
The PM6681A provides three independent Power Good signals: one for each switching
section (PGOOD1/PGOOD2).
PGOOD1/PGOOD2 signals are low if the output voltage is out of 10 % of the designed set
point or during the soft-start, standby and shutdown mode.
Thermal protection
The PM6681A has a thermal protection to preserve the device from overheating. The
thermal shutdown occurs when the die temperature goes above +150 °C. In this case all
internal circuitry is turned off and the power sections are turned off after the discharge
mode.
A power on reset or a toggle on the SHDN pin is necessary to restart the device.
8.3
8.4
Overvoltage protection
When the switching output voltage goes over the OVP threshold (about 116 % of its nominal
value), the low side MOSFET turns on. The LS MOSFET is kept on until the output voltage
returns under the OVP threshold.
Undervoltage protection
When the switching output voltage is below 70 % of its nominal value, a latched
undervoltage protection occurs. In this case the switching section is immediately disabled
and both switches are open. The controller enters in soft-end mode and the output is
eventually kept to ground, turning low side MOSFET on. The undervoltage circuit protection
is enabled only at the end of the soft-start. Once an overvoltage protection has been
detected, a toggle on SHDN, EN1/EN2 pin or a power on reset is necessary to clear the
undervoltage fault and starts with a new soft-start phase.
Table 10. Protections and operatives modes
Mode
Conditions
Description
LGATE1/LGATE2 pin is forced high until the output
voltage is over the OVP threshold, LDO5 remains
active.
Overvoltage OUT1/OUT2 > 115 % of
protection the nominal value
LGATE1/LGATE2 is forced high after the soft-end
mode, LDO5 remains active. Exit by a power on reset
or toggling SHDN or EN1/EN2
Undervoltage OUT1/OUT2 < 70 % of the
protection
nominal value
Thermal
shutdown
All circuitry off. Exit by a POR on VIN or toggling
SHDN.
TJ > +150 °C
29/47
Design guidelines
PM6681A
9
Design guidelines
The design of a switching section starts from two parameters:
●
Input voltage range: in notebook applications it varies from the minimum battery
voltage, VINmin to the AC adapter voltage, VINmax
Maximum load current: it is the maximum required output current, ILOAD(max)
.
●
.
9.1
Switching frequency
It's possible to set 3 different working frequency ranges for the two sections with FSEL pin
(table 1).
Switching frequency mainly influences two parameters:
●
●
Inductor size: for a given saturation current and RMS current, greater frequency allows
to use lower inductor values, which means smaller size.
Efficiency: switching losses are proportional to frequency. High frequency generally
involves low efficiency.
9.2
Inductor selection
Once that switching frequency is defined, inductor selection depends on the desired
inductor ripple current and load transient performance.
Low inductance means great ripple current and could generate great output noise. On the
other hand, low inductor values involve fast load transient response.
A good compromise between the transient response time, the efficiency, the cost and the
size is to choose the inductor value in order to maintain the inductor ripple current ∆IL
between 20 % and 50 % of the maximum output current ILOAD(max). The maximum ∆IL
occurs at the maximum input voltage. With this considerations, the inductor value can be
calculated with the following relationship:
Equation 13
V − VOUT VOUT
IN
L =
×
fsw × ∆IL
V
IN
where fsw is the switching frequency, VIN is the input voltage, VOUT is the output voltage and
∆IL is the selected inductor ripple current.
In order to prevent overtemperature working conditions, inductor must be able to provide an
RMS current greater than the maximum RMS inductor current ILRMS
:
Equation 14
(∆IL(max))2
ILRMS = (ILOAD(max))2 +
12
Where ∆IL(max) is the maximum ripple current:
30/47
PM6681A
Design guidelines
Equation 15
V
− VOUT
fsw ×L
VOUT
INmax
∆IL
=
×
`
(max)
V
INmax
If hard saturation inductors are used, the inductor saturation current should be much greater
than the maximum inductor peak current Ipeak
:
Equation 16
∆IL (max)
Ipeak = ILOAD (max) +
2
Using soft saturation inductors it's possible to choose inductors with saturation current limit
nearly to Ipeak. Below there is a list of some inductor manufacturers.
Table 11. Inductor manufacturer
Inductor value
(uH)
RMS current
(A)
Saturation current
(A)
Manufacturer
Series
Coilcraft
Coilcraft
TDK
SER1360
MLC
1 to 8
0.7 to 4.5
1 to 10
6 to 9.5
7 to 31
13.6 to 17.3
7.5 to 14.4
11.5 to 26
7.5 to 18.5
RLF12560
9.3
Output capacitor
The selection of the output capacitor is based on the ESR value Rout and the voltage rating
rather than on the capacitor value Cout.
The output capacitor has to satisfy the output voltage ripple requirements. Lower inductor
value can reduce the size of the choke but increases the inductor current ripple ∆IL.
Since the voltage ripple VRIPPLEout is given by:
Equation 17
VRIPPLEout = Rout × ∆IL
A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can
work correctly even with 20 mV output ripple.
However, to reduce jitter noise between the two switching sections it's preferable to work
with an output voltage ripple greater than 30 mV. If lower output ripple is required, a further
compensation network is needed (see Closing the integrator loop paragraph).
Finally the output capacitor choice deeply impacts on the load transient response (see Load
transient response paragraph). Below there is a list of some capacitor manufacturers.
31/47
Design guidelines
PM6681A
Table 12. Output capacitor manufacturer
Capacitor value
(uF)
Manufacturer
Series
Rated voltage (V) ESR max (mΩ)
POSCAP TPB,TPD,
TPE
SANYO
100 to 470
100 to 470
2.5 to 6.3
2 to 6.3
12 to 65
7 to 18
Panasonic
SPCAP UD, UE
9.4
Input capacitors selection
In a buck topology converter the current that flows into the input capacitor is a pulsed current
with zero average value. The input RMS current of the two switching sections can be roughly
estimated as follows:
Equation 18
ICinRMS = D1 ×I12 ×(1− D1) + D2 ×I22 ×(1−D2)
Where D1, D2 are the duty cycles and I1, I2 are the maximum load currents of the two
sections.
Input capacitor should be chosen with an RMS rated current higher than the maximum RMS
current given by both sections.
Tantalum capacitors are good in term of low ESR and small size, but they occasionally can
burn out if subjected to very high current during the charge. Ceramic capacitors have
usually a higher RMS current rating with smaller size and they remain the best choice.
Below there is a list of some ceramic capacitor manufacturers.
Table 13. Input capacitor manufacturer
Manufacturer
Series
Capacitor value (uF)
Rated voltage (V)
Tayio yuden
TDK
UMK432 X5506MM-T
C3225X5R1E106M
10
10
50
25
9.5
Power MOSFETs
Logic-level MOSFETs are recommended, since low side and high side gate drivers are
powered by LDO5. Their breakdown voltage VBRDSS must be higher than VINmax
.
In notebook applications, power management efficiency is a high level requirement. The
power dissipation on the power switches becomes an important factor in switching
selections. Losses of high-side and low-side MOSFETs depend on their working conditions.
The power dissipation of the high-side MOSFET is given by:
Equation 19
PDHighSide = Pconduction + Pswitching
32/47
PM6681A
Design guidelines
Maximum conduction losses are approximately:
Equation 20
VOUT
Pconduction = RDSon
×
×ILOAD(max)2
V
INmin
where RDS(on) is the drain-source on resistance of the high side MOSFET. Switching losses
are approximately:
Equation 21
∆I
2
∆I
2
V ×(ILOAD(max) − L )× ton × fsw V ×(ILOAD(max) + L )× toff × fsw
IN
IN
Pswitching
=
+
2
2
where ton and toff are the switching times of the turn off and turn off phases of the MOSFET.
As general rule, high side MOSFETs with low gate charge are recommended, in order to
minimize driver losses.
Below there is a list of possible choices for the high side MOSFET.
Table 14. High side MOSFET manufacturer
Manufacturer
Type
Gate charge (nC)
Rated reverse voltage (V)
ST
ST
STS12NH3LL
STS17NH3LL
10
18
30
30
The power dissipation of the low side MOSFET is given by:
Equation 22
PDLowSide = Pconduction
Maximum conduction losses occur at the maximum input voltage:
Equation 23
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
×ILOAD(max)2
⎜
Pconduction = RDSon × 1−
V
INmax
Choose a synchronous rectifier with low RDS(on). When high side MOSFET turns on, the fast
variation of the phase node voltage can bring up even the low side gate through its gate
drain capacitance CRSS, causing cross-conduction problems. Choose a low side MOSFET
that minimizes the ratio CRSS/CGS (CGS = CISS - CRSS).
Below there is a list of some possible low side MOSFETs.
33/47
Design guidelines
PM6681A
Table 15. Low side MOSFET manufacturer
CRSS
CGS
Manufacturer
Type
RDS(on) (mΩ)
Rated reverse voltage (V)
ST
ST
STS17NF3LL
STS25NH3LL
5.5
3.5
0.047
0.011
30
30
Dual N-channel MOSFETs can be used in applications with a maximum output current of
about 3 A. Below there is a list of some MOSFET manufacturers.
Table 16. Dual MOSFET manufacturer
Manufacturer
Type
RDS(on) (mΩ) Gate charge (nC) Rated reverse voltage (V)
ST
ST
STS8DNH3LL
STS4DNF60L
25
65
10
32
30
60
A rectifier across the low side MOSFET is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on. It
can increase the efficiency of the switching section, since it reduces the low side switch
losses. A Schottky diode is suitable for its low forward voltage drop (0.3 V). The diode
reverse voltage must be greater than the maximum input voltage VINmax. A minimum
recovery reverse charge is preferable. Below there is a list of some Schottky diode
manufacturers.
Table 17. Schottky diode manufacturer
Forward voltage
(V)
Rated reverse voltage Reverse current
Manufacturer
Series
(V)
(uA)
ST
ST
STPS1L30M
STPS1L20M
0.34
0.37
30
20
0.00039
0.000075
9.6
Closing the integrator loop
The design of external feedback network depends on the output voltage ripple. If the ripple
is higher than approximately 30 mV, the feedback network (Figure 39) is usually enough to
keep the loop stable.
34/47
PM6681A
Design guidelines
Figure 39. Circuitry for output ripple compensation
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The stability of the system depends firstly on the output capacitor zero frequency. The
following condition should be satisfied:
Equation 24
k
fsw > k × fZout
=
2π×Cout ×Rout
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It
determinates the minimum integrator capacitor value CINT
:
Equation 25
gm
Vr
CINT
>
×
f
VOUT
⎛
⎜
⎞
⎟
sw
2π×
− fZout
k
⎝
⎠
where gm = 50 µs is the integrator trans conductance.
In order to ensure stability it must be also verified that:
Equation 26
gm
Vr
CINT
>
×
2π× fZout VOUT
In order to reduce ground noise due to load transient on the other section, it is
recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a
low pass filter (see Figure 39). The cutoff frequency fCUT must be much greater (10 or more
times) than the switching frequency of the section:
35/47
Design guidelines
Equation 27
PM6681A
1
RINT
=
CINT × Cfilt
CINT + Cfilt
2π× fCUT
×
Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:
Equation 28
CINT
VRIPPLE = VRIPPLEout
×
= VRIPPLEout × q
INT
CINT + Cfilt
Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple.
If the ripple is very small (lower than approximately 30 mV), a further compensation network,
named virtual ESR network, is needed. This additional part generates a triangular ripple
that is added to the ESR output voltage ripple at the input of the integrator network. The
complete control schematic is represented in Figure 40.
Figure 40. Virtual ESR network
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The T node voltage is the sum of the output voltage and the triangular waveform generated
by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent
ESR RESR
.
A good trade-off is to design the network in order to achieve an RESR given by:
Equation 29
VRIPPLE
RESR
=
−Rout
∆IL
36/47
PM6681A
Design guidelines
where ∆IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node
voltage. It should be chosen higher than approximately 30 mV.
The new closed loop gain depends on CINT. In order to ensure stability it must be verified
that:
Equation 30
gm
Vr
CINT
>
×
2π× fZ VOUT
Where:
Equation 31
1
fZ =
2π×Cout ×RTOT
where RTOT is the sum of the ESR of the output capacitor Rout and the equivalent ESR
given by the virtual ESR network RESR
.
Moreover CINT must meet the following condition:
Equation 32
k
fsw > k × fZ =
2π× Cout ×RTOT
Where k is a free design parameter greater than 3 and determines the minimum integrator
capacitor value CINT
:
Equation 33
gm
Vr
CINT
>
×
f
VOUT
⎛
⎜
⎞
⎟
sw
2π×
− fZ
k
⎝
⎠
C must be selected as shown:
Equation 34
C > 5× CINT
R must be chosen in order to have enough ripple voltage on integrator input:
Equation 35
L
R =
RESR ×C
R1 can be selected as follows:
37/47
Design guidelines
Equation 36
PM6681A
⎛
⎞
1
⎜
⎜
⎟
⎟
R×
C× π× fZ
1
C× π× fZ
⎝
⎠
R1=
R −
Example:
OUT1 = 1.5 V, fSW = 290 kHz, L = 2.5 µH, Cout = 330 µF with Rout ≈ 12 mΩ. We design
RESR = 12 mΩ. We choose CINT = 1 nF by equations 31, 34 and Cfilt = 47 pF, RINT = 1 kΩ by
eq.28, 29. C = 5.6 nF by Eq.35. Then R = 36 kΩ (eq.36) and R1 = 3 kΩ (eq.37).
9.7
Other parts design
●
VIN filter. A VIN pin low pass filter is suggested to reduce switching noise. The low pass
filter is shown in the next figure:
Figure 41. VIN pin filter
Typical components values are: R = 3.9 Ω and C = 4.7 µF.
●
VCC filter. A VCC low pass filter helps to reject switching commutations noise:
Figure 42. Inductor current waveforms
LDO5
VCC
R
C
38/47
PM6681A
Design guidelines
Typical components values are: R = 47 Ω and C = 1 µF.
●
VREF capacitor. A 10 nF to 100 nF ceramic capacitor on VREF pin must be added to
ensure noise rejection.
●
LDO5 output capacitors. Bypass the output of each linear regulator with 1 µF ceramic
capacitor closer to the LDO pin and a 4.7 µF tantalum capacitor (ESR = 2 Ω). In most
applicative conditions a 4.7 µF ceramic output capacitor can be enough to ensure
stability.
●
Bootstrap circuit. The external bootstrap circuit is represented in the next figure:
Figure 43. Bootstrap circuit
D
D
RRBOOOT
LDOO55
BBOOOOTT
C
CBOOT
L
PHASE
PHASE
The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high
side MOSFET during turn on phase. A typical value is 100 nF.
The bootstrap diode D must charge the capacitor during the off time phases. The maximum
rated voltage must be higher than VINmax
.
A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the phase
node rises up, working like a gate resistor for the turn on phase of the high side MOSFET.
9.8
Design example
The following design example considers an input voltage from 7 V to 16 V. The two switching
outputs are OUT1 = 1.5 V and OUT2 = 1.05 V and must deliver a maximum current of 5 A.
The selected switching frequencies are about 290 kHz for OUT1 section and about 425 kHz
for OUT2 section (see Table 1).
9.8.1
Inductor selection
OUT1: ILOAD = 2.5 A, 45 % ripple current.
3.3V ⋅(20V − 3.3V)
290KHz ⋅ 24V ⋅ 0.45⋅ 2.5
L =
≈ 8.2µH
We choose standard value L = 8.2 µH.
∆IL(max) = 1.16 A @ VIN = 24 V.
ILRMS = 2.53 A
39/47
Design guidelines
PM6681A
Ipeak = 2.5 A + 0.58 A = 3.08 A
OUT2 : ILOAD = 2.5 A, 35 % ripple current.
1.8V ⋅(24V −1.8V)
425KHz ⋅ 24V ⋅ 0.35⋅ 2.5
L =
≈ 4.76µH
We choose standard value L = 4.7 µH.
∆IL(max) = 0.89 A @ VIN = 24 V.
ILRMS = 2.513 A
Ipeak = 2.5 A + 0.443 A = 2.943 A
9.8.2
9.8.3
Output capacitor selection
We would like to have an output ripple smaller than 25 mV.
OUT1: POSCAP 4TPE150MI
OUT2: POSCAP 6TPE220M
Power MOSFETs
OUT1:High side: STS5NF60L
Low side: STS7NF60L
OUT2:High side: STS5NF60L
Low side: STS7NF60L
9.8.4
Current limit
OUT1:
∆IL(min)
ILvalley(min)= ILOAD(max)−
= 4.12A
2
4.12A
RCSENSE
≡
⋅16.25mΩ ≈ 670Ω
100µA
(Let's assume the maximum temperature Tmax = 75 °C in RDS(on) calculation)
OUT2:
∆IL(min)
ILvalley (min) = ILOAD(max) −
= 4.2A
2
40/47
PM6681A
Design guidelines
4.2A
RCSENSE
≡
⋅16.25mΩ ≈ 680Ω
100µA
(Let's assume Tmax = 75 °C in RDS(on) calculation)
9.8.5
9.8.6
9.8.7
Input capacitor
Maximum input capacitor RMS current is about 1.1 A. Then ICinRMS > 1.1 A
We can put two 10 µF ceramic capacitors with Irms = 1.5 A.
Synchronous rectifier
OUT1: Schottky diode STPS1L40M
OUT2: Schottky diode STPS1L40M
Integrator loop
(Refer to Figure 40)
OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required.
CINT = 1 nF; Cfilt = 47 pF; RINT = 1 kΩ
C = 5.6 nF; R = 36 kΩ; R1 = 3 kΩ
OUT2: The ripple is smaller than 40mV, then the virtual ESR network is required.
CINT = 1 nF; Cfilt = 110 pF; RINT = 1 kΩ
C = 5.6 nF; R = 22 kΩ; R1 = 3.3 kΩ
9.8.8
Output feedback divider
(Refer to Figure 32)
OUT1: R1 = 10 kΩ; R2 = 6.8 kΩ
OUT2: R1 = 11 kΩ; R2 = 1.8 kΩ
41/47
Layout guidelines
PM6681A
10
Layout guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is
possible to refer to the PM6681A demonstration board for a complete layout example.
For good PC board layout follows these guidelines:
●
●
Place on the top side all the power components (inductors, input and output capacitors,
MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve
a layer to PGND plan. The PGND plan is the same for both the switching sections.
AC current paths layout is very critical (see Figure 44). The first priority is to minimize
their length. Trace the LS MOSFET connection to PGND plan (with or without current
sense resistor RSENSE) as short as possible. Place the synchronous diode D near the
LS MOSFET. Connect the LS MOSFET drain to the switching node with a short trace.
●
●
Place input capacitors near HS MOSFET drain. It is recommended to use the same
input voltage plan for both the switching sections, in order to put together all input
capacitors.
Place all the sensitive analog signals (feedbacks, voltage reference and current sense
paths) on the bottom side of the board or in an inner layer. Isolate them from the power
top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in
one point (a multiple via connection is preferable to a 0 ohm resistor connection) near
the PGND device pin. Place the device on the top or on the bottom size and connect
the exposed pad and the SGND pins to the SGND plan (see Figure 44).
Figure 44. Current paths, ground connection and driver traces layout
42/47
PM6681A
Layout guidelines
●
As general rule, make the high side and low side drivers traces wide and short. The
high side driver is powered by the bootstrap circuit. It's very important to place
capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for
example on the layer opposite to the device). Route HGATE and PHASE traces as near
as possible in order to minimize the area between them. The Low side gate driver is
powered by the 5 V linear regulator output. Placing PGND and LGATE pins near the
low side MOSFETs reduces the length of the traces and the crosstalk noise between
the two sections.
●
The linear regulator output LDO5 is referred to SGND as long as the reference voltage
Vref. Place their output filtering capacitors as near as possible to the device.
●
●
Place input filtering capacitors near VCC and VIN pins.
It would be better if the feedback networks connected to COMP, FB and OUT pins are
“referred” to SGND in the same point as reference voltage Vref. To avoid capacitive
coupling place these traces as far as possible from the gate drivers and phase
(switching) paths.
●
Place the current sense traces on the bottom side. If low side MOSFET RDS(on) sensing
is enabled, use a dedicated connection between the switching node and the current
limit resistor RCSENSE.
43/47
Package mechanical data
PM6681A
11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 18. VFQFPN32 5 x 5 x 1.0 mm pitch 0.50
Databook (mm)
Dim.
Min
Typ
Max
A
A1
A3
b
0.8
0
0.9
1
0.02
0.05
0.2
0.18
4.85
0.25
0.3
D
5
5.15
D2
E
See exposed pad variations (2)
4.85
0.3
5
5.15
E2
e
See exposed pad variations (2)
0.5
0.4
L
0.5
ddd
0.05
Table 19. Exposed pad variations
(1)(2)D2
E2
Min
Typ
Max
Min
Typ
Max
3.20
2.90
3.10
3.20
2.90
3.10
1. VFQFPN stands for thermally enhanced very thin fine pitch quad flat package no lead. Very thin:
A = 1.00 mm Max.
2. Dimensions D2 and E2 are not in accordance with JEDEC.
44/47
PM6681A
Package mechanical data
Figure 45. Package dimensions
45/47
Revision history
PM6681A
12
Revision history
Table 20. Document revision history
Date
Revision
Changes
02-Nov-2006
1
Initial release
Document status promoted from Target specification to
Datasheet
03-Jun-2008
26-Jun-2008
2
3
Updated: Figure 1 on page 4, Figure 27 on page 16, Figure 16
and Figure 17 on page 15
46/47
PM6681A
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47/47
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