ST1L02XX18 [STMICROELECTRONICS]
Very low quiescent BiCMOS voltage regulator; 非常低的静态的BiCMOS稳压器
| 型号： | ST1L02XX18 |
| 厂家： | 
ST |
| 描述： | Very low quiescent BiCMOS voltage regulator |
| 文件： | 总19页 (文件大小：419K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST1L02xx
Very low quiescent BiCMOS voltage regulator
Features
■ Fixed output voltage: 1.8 V, 2.5 V, 3.3 V (1.5 V,
under customer request)
■ Output voltage tolerance: 2 ꢀ at 25 °C
■ Output current capability: 1 A minimum
■ Very low quiescent current: max 500 µA over
DFN6D (3x3 mm)
temperature range
■ Typ. dropout 0.7 V (@ I = 1 A)
O
■ Stable with low ESR ceramic capacitors
Internal protection circuitry includes thermal
protection with hysteresis and over current
limiting.
■ Available with and without the external output
voltage sense pin
■ Thermal shutdown protection with hysteresis
■ Over current protection
The ST1L02xx is especially suitable for data
storage applications such as HDDs, where can be
used to supply the read channel and memory
chips requiring 3.3 V.
■ Operating junction temperature range:
from 0 to 125 °C
The regulator is available in the small and thin
DFN6D (3x3 mm) package.
Description
The ST1L02xx is a low drop linear voltage
regulator capable to supply up to 1 A output
current.
The output voltage is fixed to 3.3 V, but under
customer request, it’s possible to have also 1.5 V,
1.8 V and 2.5 V. Thanks to the BiCMOS
technology, the quiescent current is well
controlled and maintained below 650 µA over the
whole allowed junction temperature range.
The ST1L02xx is stable with low ESR output
ceramic capacitors.
Table 1.
Device summary
Part numbers
Order codes
Package
ST1L02XX18
ST1L02XX25
ST1L02XX33
ST1L02XX
ST1L02PU18R
ST1L02PU25R
ST1L02PU33R
ST1L02PUR (1)
DFN6D (3x3 mm)
DFN6D (3x3 mm)
DFN6D (3x3 mm)
DFN6D (3x3 mm)
1. Only 3.3 V
March 2008
Rev 8
1/19
www.st.com
19
ST1L02xx
Contents
1
2
3
4
5
6
7
8
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
ST1L02xx
Diagram
1
Diagram
Figure 1. Schematic diagram
3/19
Pin configuration
ST1L02xx
2
Pin configuration
Figure 2.
Pin connections (top through view)
ST1L02PXxx
ST1L02PX *
* Only 3.3 V.
Table 2.
Pin description
Pin n° for
ST1L02PXxx ST1L02PX
Pin n° for
Symbol
Name and function
1, 3
2
1, 4, 5
6
N.C.
GND
VO
Not connected.
Ground. The exposed metallic pad of the package is connected to
GND.
4
5
6
2
-
Output voltage pin. Bypass with a 4.7 µF capacitor to GND.
VO_SENSE Sense output voltage pin. Must be connected to pin 4.
VI Supply voltage input pin. Bypass with a 4.7 µF capacitor to GND.
3
4/19
ST1L02xx
3
Maximum ratings
Maximum ratings
Table 3.
Absolute maximum ratings
Parameter
Symbol
Value
Unit
VI
PTOT
IO
DC supply voltage
10
V
W
A
Power dissipation
internally limited
internally limited
0 to 150
Output current
TOP
Operating junction temperature range
Storage temperature range (1)
Lead temperature (Soldering) 10 Sec.
°C
°C
°C
TSTG
TLEAD
-65 to 150
260
1. Storage temperature >125 °C are acceptable only if the regulator is soldered to a PCBA.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these condition is not implied.
Table 4.
Thermal data
Symbol
Parameter
Value
Unit
RthJC
RthJA
Thermal resistance junction-case
Thermal resistance junction-ambient
10
55
°C/W
°C/W
5/19
Electrical characteristics
ST1L02xx
4
Electrical characteristics
Table 5.
Electrical characteristics for ST1L02XX18
(refer to the typical application schematic, V = 4.5 V to 7 V, I = 5 mA to 1 A, C = 4.7 µF,
I
O
I
C = 4.7 µF, T = 0 to 125 °C, unless otherwise specified). Typical values are intended at
O
J
T = 25 °C unless otherwise specified.
J
Symbol
Parameter
Test
Min. Typ. Max. Unit
VO
VO
Output voltage
Output voltage
Line regulation
Load regulation
Output current limit
VI = 4.75 V to 5.25 V, T=25°C
VI = 4.75 V to 5.25 V
VI = 4.75 V to 5.25 V
VI = 4.75 V, IO = 10 mA to 1 A
VI = 5.5 V
1.764
1.746
1.8
1.8
1.836
1.854
15
V
V
ΔVO
ΔVO
IS
mV
mV
A
10
1.0
Minimum output current for
regulation
IOMIN
2
mA
IO = 0.8 A
1.6
1.6
V
Vd
Dropout voltage (1)
IO = 1 A
V
IQ
IQ
Quiescent current
VI = 5 V, IO = 2 mA to 1 A, T = 25°C
VI = 7 V, IO = 2 mA to 1 A
500
650
µA
µA
dB
Quiescent current
SVR
Supply voltage rejection (2)
VI = 5 ± ± 0.5 V, IO = 5 mA, f = 120 Hz
50
75
B = 10 Hz to 10 kHz, VI = 5 V,
IO = 5 mA
eN
RMS Output noise (2)
0.003
ꢀVO
VI = 5 V, any 200 mA step from
100 mA to 1 A, tR ≥±1 µs
ΔVO/ΔIO Load transient (rising) (3)
ΔVO/ΔIO Load transient (falling) (3)
ΔVO/ΔVI Start-up transient (3)
Short circuit removal response
5
ꢀVO
V
VI = 5 V, IO = 1 A to 10 mA, tF ≥±1 µs
3.6
3.5
VI =0 V to 5 V, IO = 10 mA to 1 A,
tR ≥±1 µs
V
ΔVO/ΔIO
VI = 5 V, IO = short to 10 mA
3.5
V
(3)
TSH
Thermal shutdown trip point (3) VI = 5 V
165
°C
1. See minimum start-up voltage, VI = 3.3 V.
2. Guaranteed by design. Not tested in production.
3. CI = 10 µF, CO = 10 µF, all X7R ceramic capacitors.
6/19
ST1L02xx
Table 6.
Electrical characteristics
Electrical characteristics for ST1L02XX25
(refer to the typical application schematic, V = 4.5 V to 7 V, I = 5 mA to 1 A, C = 4.7 µF,
I
O
I
C = 4.7 µF, T = 0 to 125 °C, unless otherwise specified). Typical values are intended at
O
J
T = 25 °C unless otherwise specified.
J
Symbol
Parameter
Test
Min.
Typ.
Max.
Unit
VO
VO
Output voltage
Output voltage
Line regulation
Load regulation
Output current limit
VI = 4.75 V to 5.25 V, T = 25°C
VI = 4.75 V to 5.25 V
VI = 4.75 V to 5.25 V
VI = 4.75 V, IO = 10 mA to 1 A
VI = 5.5 V
2.45
2.5
2.55
V
V
2.4375 2.5 2.5625
ΔVO
ΔVO
IS
15
mV
mV
A
10
1.0
Minimum output current for
regulation
IOMIN
2
mA
IO = 0.8 A
0.6
0.7
1.0
1.1
V
Vd
Dropout voltage (1)
IO = 1 A
V
IQ
IQ
Quiescent current
VI = 5 V, IO = 2 mA to 1 A, T= 25°C
VI = 7 V, IO = 2 mA to 1 A
VI = 5 ± ± 0.5 V, IO = 5 mA, f = 120 Hz
500
650
µA
µA
dB
Quiescent current
SVR
Supply voltage rejection (2)
50
75
B = 10 Hz to 10 kHz, VI = 5V,
IO = 5 mA
eN
RMS Output noise (2)
0.003
ꢀVO
VI =5 V, any 200 mA step from
100mA to 1A, tR ≥±1 µs
ΔVO/ΔIO Load transient (rising) (3)
ΔVO/ΔIO Load transient (falling) (3)
ΔVO/ΔVI Start-up transient (3)
Short circuit removal response
5
ꢀVO
V
VI = 5 V, IO = 1 A to 10 mA, tF ≥±1 µs
3.6
3.5
VI =0 V to 5 V, IO = 10 mA to 1 A,
tR ≥±1 µs
V
ΔVO/ΔIO
VI = 5 V, IO = short to 10 mA
3.5
V
(3)
TSH
Thermal shutdown trip point (2) VI = 5 V
165
°C
1. See minimum start-up voltage, VI = 3.2 V.
2. Guaranteed by design. Not tested in production
3. CI = 10 µF, CO = 10 µF, all X7R ceramic capacitors.
7/19
Electrical characteristics
ST1L02xx
Table 7.
Electrical characteristics for ST1L02XX33
(refer to the typical application schematic, V = 4.5V to 7V, I = 5mA to 1A, C = 4.7µF,
I
O
I
C = 4.7 µF, T = 0 to 125 °C, unless otherwise specified). Typical values are intended at
O
J
T = 25 °C unless otherwise specified.
J
Symbol
Parameter
Test
Min.
Typ.
Max.
Unit
VO
VO
Output voltage
Output voltage
Line regulation
Load regulation
Output current limit
VI = 4.75 V to 5.25 V, T = 25°C
VI = 4.75 V to 5.25 V
VI = 4.75 V to 5.25 V
VI = 4.75 V, IO = 10 mA to 1 A
VI = 5.5 V
3.234
3.3
3.366
V
V
3.2175 3.3 3.3825
ΔVO
ΔVO
IS
15
mV
mV
A
10
1.0
Minimum output current for
regulation
IOMIN
2
mA
I
O = 0.8 A
0.6
0.7
1.0
1.1
V
Vd
Dropout voltage
IO = 1 A
V
IQ
IQ
Quiescent current
VI = 5 V, IO = 2 mA to 1 A, T= 25°C
VI = 7 V, IO = 2 mA to 1 A
VI = 5 ± ± 0.5V, IO = 5 mA, f = 120 Hz
500
650
µA
µA
dB
Quiescent current
SVR
Supply voltage rejection (2)
50
75
B = 10 Hz to 10 kHz, VI = 5 V,
IO = 5 mA
eN
RMS Output noise (2)
0.003
ꢀVO
VI = 5 V, any 200 mA step from
100 mA to 1 A, tR ≥±1 µs
ΔVO/ΔIO Load transient (rising) (1)
ΔVO/ΔIO Load transient (falling) (1)
ΔVO/ΔVI Start-up transient (1)
Short circuit removal response
5
ꢀVO
V
VI = 5 V, IO = 1 A to 10 mA, tF ≥±1 µs
3.6
3.5
VI =0 V to 5 V, IO = 10 mA to 1 A,
tR ≥±1 µs
V
ΔVO/ΔIO
VI = 5 V, IO = short to 10 mA
3.5
V
(1)
TSH
Thermal shutdown trip point (2) VI = 5 V
165
°C
1. CI = 10 µF, CO = 10 µF, all X7R ceramic capacitors.
2. Guaranteed by design. Not tested in production.
8/19
ST1L02xx
Typical application
5
Typical application
Figure 3. Application schematic for ST1L02PM
Figure 4. Application schematic for ST1L02PMxx
Note:
The regulator is designed to be stable with either tantalum and ceramic capacitors on the
input and the output. The expected values of the input and output ceramic capacitors are
from 1 µF to 22 µF with 4.7 µF typical. The input capacitor must be connected within 0.5
inches of the V terminal. The output capacitor must also be connected within 0.5 inches of
I
output pin. There is no upper limit to the value of the input capacitor.
9/19
Typical characteristics
ST1L02xx
6
Typical characteristics
Figure 5.
Output voltage vs temperature
Line regulation vs temperature
Dropout voltage vs temperature
Figure 6.
Line regulation vs temperature
Figure 7.
Figure 8.
Load regulation vs temperature
Figure 9.
Figure 10. Quiescent current vs temperature
10/19
ST1L02xx
Typical characteristics
Figure 11. Quiescent current vs temperature Figure 12. Quiescent current vs temperature
Figure 13. Quiescent current vs temperature Figure 14. Quiescent current vs output current
Figure 15. Supply voltage rejection vs
temperature
Figure 16. Supply voltage rejection vs
frequency
11/19
Typical characteristics
ST1L02xx
Figure 17. Output noise vs frequency
Figure 18. Change of V with step load
O
change
VI=5V, IO=100mA to 300mA, CO=10μF, CI=10μF, tRISE≥1µs
Figure 19. Change of V with step load
Figure 20. Change of V with step load
O
O
change
change
VI=5V, IO=500mA to 700mA, CO=10μF, CI=10μF, tRISE≥1µs,
TJ=25°C
VI=5V, IO=300mA to 500mA, CO=10μF, CI=10μF, tRISE≥1µs
Figure 21. Change of V with step load
Figure 22. Change of V with step load
O
O
change
change
VI=5V, IO=10mA to S.C., CO=10μF, CI=10μF, tRISE≥1µs,
VI=5V, IO=700mA to 900mA, CO=10μF, CI=10μF, tRISE≥1µs,
TJ=25°C
TJ=25°C
12/19
ST1L02xx
Typical characteristics
Figure 23. Line transient
VI = 4.75 V to 5.25 V, IO = 500 mA, CO=10 µF, CI = 2.2 µF,
tRISE ≥±1 µs
13/19
Package mechanical data
ST1L02xx
7
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
14/19
ST1L02xx
Package mechanical data
DFN6D (3x3 mm) mechanical data
mm.
inch.
Dim.
Min.
0.80
0
Typ.
Max.
1.00
0.05
Min.
0.031
0
Typ.
Max.
0.039
0.002
A
A1
A3
b
0.02
0.20
0.001
0.008
0.23
2.90
2.23
2.90
1.50
0.45
3.10
2.50
3.10
1.75
0.009
0.114
0.088
0.114
0.059
0.018
0.122
0.098
0.122
0.069
D
3.00
3.00
0.118
0.118
D2
E
E2
e
0.95
0.037
L
0.30
0.40
0.50
0.012
0.016
0.020
7946637B
15/19
Package mechanical data
ST1L02xx
Tape & Reel QFNxx/DFNxx (3x3) Mechanical Data
mm.
Typ.
inch.
Typ.
Dim.
Min.
Max.
330
Min.
Max.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
18.4
0.724
Ao
Bo
Ko
Po
P
3.3
3.3
1.1
4
0.130
0.130
0.043
0.157
0.315
8
16/19
ST1L02xx
Package mechanical data
Figure 24. DFN6 (3x3 mm) footprint recommended data
17/19
Revision history
ST1L02xx
8
Revision history
Table 8.
Document revision history
Revision
Date
Changes
25-Feb-2005
10-Jan-2006
16-May-2006
05-Jul-2006
22-Feb-2007
03-Apr-2007
05-Sep-2007
12-Mar-2008
1
2
3
4
5
6
7
8
First release.
Add new order codes and tables of the electrical characteristics.
General feature has been updated and add note 3 in table 6.
Updated mechanical data DFN6 (3x3).
Add note in Figure 2 and in order codes.
Add order codes and mechanical data DFN6D.
Add Table 1 in cover page.
Removed: mechanical data DFN6.
18/19
ST1L02xx
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