STA016T [STMICROELECTRONICS]
MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM; MPEG 2.5第三层音频解码器配套光盘能力的＆ ADPCM
| 型号： | STA016T |
| 厂家： | 
ST |
| 描述： | MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM |
| 文件： | 总45页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA016T
MPEG 2.5 LAYER III AUDIO DECODER
SUPPORTING CD-ROM CAPABILITY & ADPCM
PRODUCT PREVIEW
■ SINGLE CHIP MPEG LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
TQFP64
■ DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
ORDERING NUMBER: STA016T
■ SUPPORTING ALL THE MPEG 1 & 2
SAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:48, 44.1,32,
24,22.05, 16, 12,11. 025, 8 KHz
■ EASY PROGRAMMABLE GPSO INTERFACE
(MONO/STEREO) FOR ENCODED DATA UP
TO 5Mbit/s
■ ACCEPTS MPEG 2.5 LAYER III
ELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
Kbit/s
■ DIGITAL VOLUME
■ BYPASS MODE FOR EXTERNAL AUXILIARY
■ BASS & TREBLE CONTROL
■ SERIAL BITSTREAM INPUT INTERFACE
AUDIO SOURCE
■ ADPCM ENCODING/DECODING
CAPABILITY:
■ EASY PROGRAMMABLE ADC INPUT
INTERFACE
- sample frequency from 8 kHz to 32 kHz
- sample size from 8 bits to 32 bits
- encoding algorithm: DVI, ITU-G726 pack
(G723-24, G721,G723-40)
2
■ SERIAL PCM OUTPUT INTERFACE (I S AND
OTHER FORMATS)
■ PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
■ EMBEDDED ISO9660 LAYER FOR FILE-
SYSTEM DECODING (JOLIET)
■ CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
INDICATORS
■ EMBEDDED CD-ROM DECODER BLOCKS
INCLUDING ECC/EDC CAPABILITY
2
2
■ I C CONTROL BUS
■ FLEXIBLE I S INPUT INTERFACE FOR EASY
CONNECTION WITH MOST CD-SERVO
DEVICES
■ LOW POWER 2.4V CMOS TECHNOLOGY
WITH 3.3V TOLERANT AND CAPABLE I/O
■ EMBEDDED BROWSING COMMAND
INTERPRETER FOR EASY FILE-SYSTEM
BROWSING
■ FAST FORWARD AND PAUSE CAPABILITIES
APPLICATIONS
■ CUE-SHEET CAPABILITY UP TO 100
■ AUDIO CD PLAYERS
■ MULTIMEDIA PLAYERS
■ CD-ROM PLAYERS
■ CAR RADIO PLAYERS
ENTRIES
■ BROWSER COMMAND INTERPRETER (BCI)
- Parent Dir
- Enter Dir
- Previous Entry
- Next Entry
- Get Record Infos
May 2001
1/45
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
STA016T
DESCRIPTION
The STA016 is a single chip MPEG 1, 2 and 2.5 Layer III audio decoder with embedded CDROM decoding ca-
pability. It can be easily connected to most existing CDDSP devices via a software configurable serial link. A
tipical application block diagram is show in Figure 1. Besides MPEG decoding the device can also perform AD-
PCM encoding/decoding from different audio sources and the encoded stream, for instance, can be stored on
an external flash memory.
A useful bypass mode allow using this device also as an audio processor for volume and tone controls.
Figure 1. Typical CD-Player application
CD
Mechanic
TUNERMODULE
OR
AUX.AUDIO
SOURCE
CDDSPI/F
L
R
I2S OUT
D/A
CDDSP
STA016
I2C
FLASHMEMORY
for
SDI
MCU
MP3files orADPCM
encoded messages
GPSO
(optional)
CDMODULE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
Power Supply
-0.3 to 3
DD
V
Voltage on Input pins
Voltage on output pins
Storage Temperature
Operative ambient temp
-0.3 to V
-0.3 to V
+0.3
+0.3
V
i
DD
DD
V
V
O
T
-40 to +150
-20 to +85
°C
°C
stg
T
op
THERMAL DATA
Symbol
Parameter
Value
Unit
R
Thermal resistance Junction to Ambient
85
°C/W
th j-amb
2/45
STA016T
1
OVERVIEW
The device can decode/process data coming from three possible sources, as showed in Figure 2:
■ CDDSP serial link: using this input interface, besides MP3 encoded data CD, it’s possible to playback
also standard Audio CD using the available volume and tone equalizer features of the device and
allowing the use of only one D/A converter with no external analog switch.
■ SDI input interface: through this input interface it’s possible to decode any MP3 bitstream coming, for
instance, from an external flash memory. This same interface is also used to decode ADPCM streams.
2
■ I S input interface: this interface can be used both to encode an external audio source (with variable
compression based on 4 different ADPCM algorithm) or to process an external audio source (tuner, for
instance) through the DSP based volume and tone controls:this BYPASS mode can avoid the use of
additional D/A converters or postprocessing units.
1.1 MP3 decoder engine
The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5
streams are supported.
Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding
2
the output I S interface. This results in no need for an external audio processor.
Table 1. MPEG Sampling Rates (KHz)
MPEG 1
48
MPEG 2
24
MPEG 2.5
12
11.025
8
44.1
32
22.05
16
1.2 ADPCM encoder/decoder engine
This device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates (from 8
KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits). During encoding process two different in-
terfaces can be used to feed data: the serial input interface (same interface used also to feed MP3 bitstream)
or the ADC input interface, which provides a seamless connection with an external A/D converter. The currently
used interface is selected via I2C bus.
Also to retrieve encoded data a specific interface is available: the fast GPSO output interface. GPSO interface
is able to output data with a bitrate up to 5 Mbit/s and its control pins (GPSO_SCKR, GPSO_DATA and
GPSO_REQ) can be configured in order to easily fit the target application.
3/45
STA016T
Figure 2. Block Diagram
CDROM DECODER (C3)
DESCRAM.
CD_BCK
CDDSP
I/F
SYNC
DETECT.
CD_SDI
ECC/EDC
CD_LRCK
SECTOR
BUFFER
BS_BCK
SDI
BS_SDI
I/F
INPUT SELECTOR
BS_LRCK
DREQ
BCKI
MMDSP
CORE
- ISO9660 + JOLIET
BCKO
SDO
2
I S IN
I/F
SDI
2
PCM OUTPUT
BUFFER
I S OUT
I/F
LRCKI
STB
-
BCI
LRCKO
- MP3 + ADPCM
RQST
GPSO_CK
SCL
SDA
2
I
C
GPSO_SDO
GPSO_REQ
2
I
C
GPSO
I/F
I/F
PLL
OSC
REG BANK
D00AU1221
OSCK
XTI
XTO
2
The basic functions of the device can be fully operated via the I C bus. Besides that the GPSO interface can be
used to move huge amount of data this fast and flexible interface can achieve transfer rates up to 5 Mbit/s.
The embedded DSP firmware implements all the layers required to decode a standard data CD, as shown in
the Figure 3:
Figure 3. Layers performed by embedded DSP firmware
FRAMES to SECTOR TRANSLATOR
SYNC DETECTOR
DESCRAMBLER
EDC/ECC (C3)
ISO9660 File System Decoding
(with Joliet support)
Browsing Command Interface
The whole CDROM and file-system decoding task is performed by embedded firmware. The application MCU,
basically, must manage CDDSP device according to STA016 requests. Three basic command flows exist:
■ MCU -> STA016: commands used to handle decoder operation and to ask for specific information like
2
filename, filelength, sector raw data, etc. This flow will use I C (GPSO for special operations) interface.
■ STA016 -> MCU: this channel is used to retrieve inquired information and to inform MCU that a CDDSP
4/45
STA016T
2
specific operation must be performed (like pick-up repositioning). This flow is based on I C link plus an
additional interrupt signal in order to avoid time consuming polling techniques.
■ MCU -> CDDSP: the CDDSP management is fully up to the application MCU. This architecture allows
maximum flexibility and easy migration from existing CDPlayers to MP3 CDPlayers.
PIN CONNECTION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
CD_LRCK
CD_BCK
CD_SDI
DREQ
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IODATA12
IODATA11
IODATA10
IODATA9
IODATA8
VSS_6
VDD_1
VSS_1
BS_LRCK
BS_BCK
BS_SDI
VDD_2
VSS_2
LRCK1
BCKI
VCC_2
PLL_GND
FILT0
PLL_VCC
FILT1
10
11
12
13
14
VSS_5
VDD_4
SDI
IODATA7
IODATA6
IODATA5
RESET
TESTEN
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D00AU1227
PIN DESCRIPTION
PIN
Pin Name
Type
Description
CDDSP interface
Sourde/Dest
1
3
2
CD_LRCK
I
I
I
DSP Interface left/right Clock
DSP interface serial data
DSP interface bit clock
SDI interface
From DSP
CD_SDI
From DSP
From DSP
CD_BCK
9
7
8
4
BS_SDI
BS_LRCK
BS_BCK
DREQ
I
I
I
Bitstream interface serial data
Bitstream interface left/right Clock
Bitstream interface clock
Bitstream data request
PCM IN interface
From MCU
From MCU
From MCU
To MCU
O
13
BCKI
I
ADC bit clock
From ADC
5/45
STA016T
PIN DESCRIPTION (continued)
PIN
14
Pin Name
SDI
Type
Description
Sourde/Dest
From ADC
I
I
ADC serial data
12
LRCKI
ADC left/right Clock
From ADC
PCM OUT interface
20
22
21
19
LRCKO
SDO
O
O
O
O
DAC Interface left/right Clock
DAC serial data
DAC bit clock
To DAC
To DAC
BCKO
OSCK
To DAC
DAC oversampling clock
GPSO interface
GPSO bit clock
GPSO serial data
GPSO request signal
GPIO interface
GPIODATA0
To DAC/ADC
55
54
56
GPSO_CK
GPSO_SDO
GPSO_REQ
I
From MCU
To MCU
O
O
To MCU
26
27
28
31
32
33
34
35
44
45
46
47
48
49
50
51
IODATA0
IODATA1
IODATA2
IODATA3
IODATA4
IODATA5
IODATA6
IODATA7
IODATA8
IODATA9
IODATA10
IODATA11
IODATA12
IODATA13
IODATA14
IODATA15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIODATA1
GPIODATA2
GPIODATA3
GPIODATA4
GPIODATA5
GPIODATA6
GPIODATA7
GPIODATA8
GPIODATA9
GPIODATA10
GPIODATA11
GPIODATA12
GPIODATA13
GPIODATA14
GPIODATA15
6/45
STA016T
PIN DESCRIPTION (continued)
PIN
Pin Name
Type
Description
Sourde/Dest
HANDSHAKE SIGNALS
60
59
STB
I
Strobe signal
From MCU
RQST
O
I2C data signal
To MCU
2
I C LINK
63
64
SCL
SDA
I
I2C clock signal
I2C data signal
From MCU
To MCU
I/O
MISCELLANEOUS
17
18
25
15
16
40
38
XTI
XTO
I
Oscillator input
O
O
I
Oscillator output
Buffered output clock
Reset
CLKOUT
-RESET
-TESTEN
FILT0
I
Reserved for test purpose
PLL external filter
PLL external filter
POWER SUPPLY
I
FILT1
39
41
5
PLL_VCC
PLL_GND
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VCC_1
VCC_2
VCC_3
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
Digital supply (2.5V Power Supply)
Digital supply (2.5V Power Supply)
Digital supply (2.5V Power Supply)
Digital supply (2.5V Power Supply)
Digital supply (2.5V Power Supply)
Digital supply (2.5V Power Supply)
Digital supply (3.3V Power Supply)
Digital supply (3.3V Power Supply)
Digital supply (3.3V Power Supply)
10
29
36
53
62
23
42
58
6
11
24
30
37
43
52
57
61
7/45
STA016T
ELECTRICAL CHARACTERISTCS
( V = 3.3V ±0.3V; T
= 0 to 70°C; R = 50Ω unless otherwise specified)
g
DD
amb
DC OPERATING CONDITIONS
Symbol
Parameter
Value
2.4
Unit
V
V
Power Supply Voltage
Operating Junction Temperature
DD
T
j
-20 to 125
°C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Condition
Min.
Typ.
Max.
Unit
Note
I
Low Level Input
CurrentWithout pull-up device
V = 0V
-10
10
µA
1
1
2
IL
i
I
High Level Input
CurrentWithout pull-up device
V = V
i DD
-10
10
µA
IH
V
esd
Electrostatic Protection
Leakage < 1µA
2000
V
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
Note
V
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
High Level Output Voltage
0.2*V
DD
IL
V
0.8*V
V
IH
DD
V
ol
I
ol
= Xma
0.4V
V
1, 2
1, 2
V
oh
0.85*V
V
DD
Note1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
Parameter
Pull-up current
Equivalent Pull-up Resistance
Test Condition
Min.
Typ.
-66
50
Max.
Unit
µA
Note
I
V = 0V; pin numbers 7, 24
-25
-125
1
pu
i
and 26
R
pu
kΩ
Note 1: Min. condition: VDD = 2.7V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max.
POWER DISSIPATION
Symbol
Parameter
Test Condition
Min.
Typ.
t.b.d.
t.b.d.
t.b.d.
Max.
Unit
mW
mW
mW
Note
P
Power Dissipation@ V = 2.4V Sampling_freq ≤24 kHz
D
DD
Sampling_freq ≤32 kHz
Sampling_freq ≤48 kHz
8/45
STA016T
2
HOST REGISTERS
The following table gives a description of STA016 register list.
2
The STA016 device includes 256 I C registers. In this document, only the user-oriented registers are described.
The undocumented registers are reserved or unused. These registers must never be accessed (in Read or in
Write mode). The Read-Only registers must never be written
We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read
or written :
■ DWT : During Whole Time (at any time during process).
■ DEC : During External Config (period between RUN=2 and RUN=1).
■ DBO : During Boot (period between RUN=0 and RUN=2).
■ ABO : After BOot (period after RUN=1).
■ AEC : After External Config (period after RUN=2).
■ EDF : Every Decoded Frame (each time a frame has been decoded).
■ EDB : Every Decoded Block (each time a block has been decoded).
SOFT_RESET = 1
CK_CMD = 0
block1
frame1
block2
frame1
block1
frame2
HR
RUN==0 RUN==2 RUN==1
time
DWT
DBO
DEC
ABO
AEC
D01AU1260
EDB
EDB
EDF
EDB
9/45
STA016T
REGISTER MAP BY FUNCTION
Register function
Hex
0x00
0x01
0xD3
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0x66
0x67
0x68
0x69
0x66
0x6A
0x5A
0x5B
0x5C
0x5D
Dec
0
Name
Type
RO
When
DWT
DWT
DWT
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
VERSION
VERSION
IDENT
1
RO
211
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
102
103
104
105
102
106
90
SOFT_VERSION
RO
PLL_AUDIO_CONFIGURATION
PLL_SYSTEM_CONFIGURATION
I2Sout_CONFIGURATION
PLL_AUDIO_PEL_192
PLL_AUDIO_PEH_192
PLL_AUDIO_NDIV_192
PLL_AUDIO_XDIV_192
PLL_AUDIO_MDIV_192
PLL_AUDIO_PEL_176
PLL_AUDIO_PEH_176
PLL_AUDIO_NDIV_176
PLL_AUDIO_XDIV_176
PLL_AUDIO_MDIV_176
PLL_SYSTEM_PEL_50
PLL_SYSTEM_PEH_50
PLL_SYSTEM_NDIV_50
PLL_SYSTEM_XDIV_50
PLL_SYSTEM_MDIV_50
PLL_SYSTEM_PEL_42_5
PLL_SYSTEM_PEH_42_5
PLL_SYSTEM_NDIV_42_5
PLL_SYSTEM_XDIV_42_5
PLL_SYSTEM_MDIV_42_5
OUTPUT_CONF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PCM_DIV
PCM_CONF
PCM_CROSS
GPSO_CONFIGURATION
I2Sin_CONFIGURATION
OUTPUT_CONF
GPSO_CONF
INPUT_CONF
91
I_AUDIO_CONFIG_1
I_AUDIO_CONFIG_2
I_AUDIO_CONFIG_3
92
93
10/45
STA016T
Register function
Hex
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x59
0x5A
0x5B
0x40
0x41
0x42
0x43
0x44
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
Dec
90
91
92
93
94
95
96
97
98
99
100
101
89
90
91
64
65
66
67
68
70
71
72
73
74
75
76
77
78
Name
INPUT_CONF
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
RW
RW
RW
RW
RO
When
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
AEC
ABO
ABO
ABO
ABO
AEC
AEC
AEC
AEC
AEC
AEC
ABO
ABO
ABO
CDBSA_CONFIGURATION
I_AUDIO_CONFIG_1
I_AUDIO_CONFIG_2
I_AUDIO_CONFIG_3
I_AUDIO_CONFIG_4
I_AUDIO_CONFIG_5
I_AUDIO_CONFIG_6
I_AUDIO_CONFIG_7
I_AUDIO_CONFIG_8
I_AUDIO_CONFIG_9
I_AUDIO_CONFIG_10
I_AUDIO_CONFIG_11
POL_REQ
BSB_CONFIGURATION
CD_CONFIGURATION
INPUT_CONF
I_AUDIO_CONFIG_1
BASIC_COMMAND
FAST_FUNCTION_VAL
REQUIRED_TRACK
REQUIRED_DIR
PLAY_MODE
TYPE _CD_EXT_REQ
MINUTE_REQ
RO
SECOND_REQ
RO
SECTOR_REQ
RO
MINUTE_SPENT
RO
SECOND_SPENT
SCANNING_TIME
PLAY_LIST_INDEX
PLAY_LIST_VALUE
RO
RW
RW
RW
11/45
STA016T
Register function
Hex
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
Dec
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
Name
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
When
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
CD_SONG_INFO_C1
CD_SONG_INFO_C2
CD_SONG_INFO_C3
CD_SONG_INFO_C4
CD_SONG_INFO_C5
CD_SONG_INFO_C6
CD_SONG_INFO_C7
CD_SONG_INFO_C8
CD_SONG_INFO_C9
CD_SONG_INFO_C10
CD_SONG_INFO_C11
CD_SONG_INFO_C12
CD_SONG_INFO_C13
CD_SONG_INFO_C14
CD_SONG_INFO_C15
CD_SONG_INFO_C16
CD_SONG_INFO_C17
CD_SONG_INFO_C18
CD_SONG_INFO_C19
CD_SONG_INFO_C20
CD_SONG_INFO_C21
CD_SONG_INFO_C22
CD_SONG_INFO_C23
CD_SONG_INFO_C24
CD_SONG_INFO_C25
CD_SONG_INFO_C26
CD_SONG_INFO_C27
CD_SONG_INFO_C28
CD_SONG_INFO_C29
CD_SONG_INFO_C30
CD_SONG_INFO_C31
CD_SONG_INFO_C32
CD_SONG_TYPE_INFO
12/45
STA016T
Register function
Hex
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBC
0x10
0x3A
0x55
0x56
0x52
0x53
0x57
0x58
Dec
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
188
16
Name
NB_OF_CUR_TRACK
NB_OF_CUR_DIR
CD_CUR_STATUS
CD_TRACK_FORMAT
CD_NB_OF_SUB_DIR
CD_NB_OF_SUB_FILE
DIRECTORY_LEVEL
DIR_IDENTIFIER_B1
DIR_IDENTIFIER_B2
DIR_IDENTIFIER_B3
DIR_IDENTIFIER_B4
VOL_IDENTIFIER_B1
VOL_IDENTIFIER_B2
VOL_IDENTIFIER_B3
VOL_IDENTIFIER_B4
EXTRACT_BYTE_IDX_B1
EXTRACT_BYTE_IDX_B2
EXTRACT_BYTE_IDX_B3
EXTRACT_BYTE_IDX_B4
EXTRACT_ADR_MODE
CONFIG_MODULE
SOFT_RESET
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
WO
WO
RW
RW
RW
RW
RW
RW
When
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
AEC
ABO
ABO
ABO
ABO
ABO
DEC
DWT
DBO
DEC
DEC
ABO
ABO
ABO
ABO
COMMAND
58
CK_CMD
85
DEC_SEL
86
RUN
82
CRC_IGNORE
83
MUTE
87
SKIP
88
PAUSE
13/45
STA016T
Register function
Hex
0xCC
0xCD
0xCE
0x6F
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0x70
0x71
0xCB
0x52
0x6B
0x6C
0x6D
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Dec
204
205
206
111
212
213
214
215
216
217
112
113
203
82
Name
STATUS_MODE
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
When
EDF
EDF
EDF
EDF
EDF
EDF
EDF
EDF
EDF
EDF
DEC
DEC
DEC
ABO
EDB
EDB
EDB
DEC
DEC
DEC
DEC
DEC
ABO
ABO
ABO
ABO
ABO
ABO
ABO
ABO
ABO
ABO
ABO
STATUS
STATUS_CHAN_NB
STATUS_SF
STATUS_FE
HEADER_1
HEADER_2
HEADER_3
HEADER_4
HEADER_5
HEADER_6
BYPASSA_CONFIGURATION
MP3_CONFIGURATION
CHAN_NB
SAMPLING_FREQ
PCMCLK_INPUT
CRC_IGNORE
ERR_DEC_LEVEL
ERR_DEC_NB_1
ERR_DEC_NB_2
CHAN_NB
107
108
109
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
ADPCM_CONFIGURATION
MIX_CONFIGURATION
TONE_CONFIGURATION
SAMPLING_FREQ
ENC_STATE_REPEAT
ENC_CODEC
ENC_FRAME_LEN
MIX_MODE
MIX_DLA
MIX_DLB
MIX_DRA
MIX_DRB
TONE_ON
TONE_FCUTH
TONE_FCUTL
TONE_GAINH
TONE_GAINL
TONE_GAIN_ATTEN
14/45
STA016T
3
REGISTER DESCRIPTION
3.2 PLL_AUDIO_CONFIGURATION registers
description
3.1 VERSION registers description
PLL_AUDIO_PEL_192 :
VERSION :
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xDC (220)
Type : RW - DEC
Address : 0x00 (0)
Type : RO - DWT
Software Reset : 58
Software Reset : 0x10
Hardware Reset : 0x10
Description :
This register must contain a PEL value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Description :
The VERSION register is Read-only and it is used to
identify the IC on the application board.
ofact is the oversampling factor needed by the DAC
(ofac==246 or ofac==384).
Default value at soft reset assume :
– ofact == 256
IDENT :
b7
b6
b5
b4
b3
b2
b1
b0
– external crystal provide a CRYCK running at
14.31818 MHz
1
0
1
0
1
1
0
0
Address : 0x01 (1)
Type : RO - DWT
PLL_AUDIO_PEH_192 :
b7
b6
b5
b4
b3
b2
b1
b0
Software Reset : 0xAC
Hardware Reset : 0xAC
Address : 0xDD (221)
Type : RW - DEC
Description :
Software Reset : 187
IDENT is a read-only register and it is used to identify
the IC on an application board. IDENT always has the
value 0xAC.
Description :
This register must contain a PEH value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
SOFT_VERSION :
Default value at soft reset assume :
– ofact == 256
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xD3 (211)
Type : RO - DWT
– external crystal provide a CRYCK running at
14.31818 MHz
Software Reset : X
PLL_AUDIO_NDIV_192 :
Description :
b7
b6
b5
b4
b3
b2
b1
b0
The SOFT_VERSION register is Read-only and it is
used to identify the software running on the IC.
Address : 0xDE (222)
Type : RW - DEC
Software Reset : 0
15/45
STA016T
Description :
Address : 0xE1 (225)
Type : RW - DEC
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Software Reset : 54
Default value at soft reset assume :
– ofact == 256
Description :
This register must contain a PEL value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
– external crystal provide a CRYCK running at
14.31818 MHz
Default value at soft reset assume :
– fact == 256
PLL_AUDIO_XDIV_192 :
– external crystal provide a CRYCK running at
14.31818 MHz
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xDF (223)
Type : RW - DEC
Software Reset : 3
PLL_AUDIO_PEH_176 :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
Address : 0xE2 (226)
Type : RW - DEC
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Software Reset : 118
Default value at soft reset assume :
– ofact == 256
Description :
This register must contain a PEH value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
– external crystal provide a CRYCK running at
14.31818 MHz
Default value at soft reset assume :
– ofact == 256
PLL_AUDIO_MDIV_192 :
– external crystal provide a CRYCK running at
14.31818 MHz
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xE0 (224)
Type : RW - DEC
PLL_AUDIO_NDIV_176 :
Software Reset : 12
b7
b6
b5
b4
b3
b2
b1
b0
Description :
Address : 0xE3 (227)
Type : RW - DEC
Software Reset : 0
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
– ofact == 256
Description :
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
– external crystal provide a CRYCK running at
14.31818 MHz
Default value at soft reset assume :
– ofact == 256
PLL_AUDIO_PEL_176 :
– external crystal provide a CRYCK running at
14.31818 MHz
b7
b6
b5
b4
b3
b2
b1
b0
16/45
STA016T
PLL_AUDIO_XDIV_176 :
b7 b6 b5 b4
Description :
This register must contain a PEL value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
b3
b2
b1
b0
Address : 0xE4 (228)
Type : RW - DEC
Software Reset : 2
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
Description :
PLL_SYSTEM_PEH_50 :
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xE7 (231)
Type : RW - DEC
Software Reset : 0
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
Description :
This register must contain a PEH value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
PLL_AUDIO_MDIV_176 :
b7
b6
b5
b4
b3
b2
b1
b0
Default value at soft reset assume :
Address : 0xE5 (229)
Type : RW - DEC
Software Reset : 8
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_NDIV_50 :
Description :
b7
b6
b5
b4
b3
b2
b1
b0
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1,2 & 3.
Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
Default value at soft reset assume :
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
Description :
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
PLL_SYSTEM_CONFIGURATION registers de-
scription
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEL_50 :
b7
b6
b5
b4
b3
b2
b1
b0
PLL_SYSTEM_XDIV_50 :
Address : 0xE6 (230)
Type : RW - DEC
Software Reset : 0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
17/45
STA016T
Description :
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 50 MHZ
for the SYSCK. See table 4.
This register must contain a PEH value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_MDIV_50 :
PLL_SYSTEM_NDIV_42_5 :
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xEA (234)
Type : RW - DEC
Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
Software Reset : 13
Description :
Description :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEL_42_5
PLL_SYSTEM_XDIV_42_5 :
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xE6 (230)
Type : RW - DEC
Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
Software Reset : 126
Description :
Description :
This register must contain a PEL value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
– external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEH_42_5 :
PLL_SYSTEM_MDIV_42_5 :
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xE7 (231)
Type : RW - DEC
Address : 0xEA (234)
Type : RW - DEC
Software Reset : 223
Software Reset : 10
18/45
STA016T
Description :
PCM_CONF :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
b7
b6
b5
b4
b3
b2
b1
b0
0
CO6 CO5 CO4 CO3 CO2 CO1 CO0
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
Address : 0x68 (104)
Type : RW - DEC
Software Reset : 0
3.3 I2Sout_CONFIGURATION registers
description
Description :
If OUTPUT_CONF == 1, configure the I2Sout inter-
face according following table.
OUTPUT_CONF :
b7
b6
b5
b4
b3
b2
b1
b0
Bit
Comment
fields
Address : 0x66 (102)
Type : RW - DEC
Software Reset : 0
CO[1:0 0 : 16 bits mode (16 slots transmitted).
]
1 : 18 bits mode (18 slots transmitted).
2 : 20 bits mode (20 slots transmitted).
3 : 24 bits mode (24 slots transmitted).
CO2
Polarity of BCKO :
0 : data are sent on the falling edge & stable
on the rising).
1 : (data are sent on the rising edge & stable
on the falling).
Description :
If set to 1 enable the configurability of the PCM-
BLOCK Output thanks to following registers, else dis-
able this configurability and take embedded default
configuration for PCM-BLOCK registers.
CO3
CO4
0 : I2S format is selected
1 : other format is selected
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
Polarity of LRCKO :
– PCM_DIV = 3;
0 : low->right, high->left).
1 : low->left, high->right so compliant to I2S
format ).
– PCM_CONF = 0;
– PCM_CROSS = 0;
CO5
CO6
0 : data are in the last BCKO cycles of
LRCKO (right aligned data).
1 : data are in the first BCKO cycles of
PCM_DIV :
LRCKO (left aligned data).
b7
b6
b5
b4
b3
b2
b1
b0
0 : the transmission is LS bit first.
1 : the transmission is MS bit first.
0
0
DV5 DV4 DV3 DV2 DV1 DV0
Address : 0x67 (103)
Type : RW - DEC
Software Reset : 0
PCM_CROSS :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
If OUTPUT_CONF == 1, configure the divider to gen-
erate the bit clock of the I2Sout interface, called
BCK0, from PCMCK. according the following relation
: BCKO = PCMCK / 2 * (PCM_DIV+1)
0
0
0
0
0
0
CR1 CR0
Address : 0x69 (105)
Type : RW - DEC
Software Reset : 0
19/45
STA016T
Description :
GPSO_CONF :
b7 b6 b5
If OUTPUT_CONF == 1, CR[1:0] is used to configure
the output crossbar according following table.
b4
b3
b2
b1
b0
CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
CR1 CR0
Comment
Address : 0x6A (106)
Type : RW - DEC
Software Reset : 0
0
0
Left channel is mapped on the left
output.
Right channel is mapped on the right
output.
0
1
1
1
0
1
Left channel is duplicated on both output
channels.
Description :
If OUTPUT_CONF == 1, this register configure the
GPSO interface.
Right channel is duplicated on both
output channels.
Bit
Right and left channels are toggled.
Comment
fields
CF0
Polarity of GPSO_CK :
0 : data provided on rising edge & stable
on falling edge
1 : data provided on falling edge & stable
on rising edge
3.4 GPSO_CONFIGURATION registers
description
OUTPUT_CONF :
CF1
Polarity of GPSO_REQ :
0 : data are valid when GPSO_REQ is high
1 : data are valid when GPSO_REQ is low
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
0C2 OC1 OC0
CF[7:2] Reserved : to be set to 0.
Address : 0x66 (102)
Type : RW - DEC
Software Reset : 0
3.5 I2Sin_CONFIGURATION registers
description
Description :
INPUT_CONF :
b7
b6
b5
b4
b3
b2
b1
b0
Bit fields
Comment
OC0
OC1
OC2
Configuration of gpso :
Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
0 : take embedded default configuration.
1 : configure gpso from register
GPSO_CONF.
Use of block PCM to generate clocks
(PCMCK, LRCK & BCK):
0 : no use.
Description :
1 : use it.
If set to 1 enable the configurability of the I2Sin Input
thanks to following registers, else disable this config-
urability and take embedded default configuration for
I2Sin registers.
Configuration of PCM block:
0 : take embedded default configuration.
1 : configure PCM block from PCM_DIV
& PCM_CONF registers.
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
Note that embedded default configuration for GPSO
can be retrieved by user thanks to following setting :
– I_AUDIO_CONFIG_1 = b00000110;
– I_AUDIO_CONFIG_2 = b11100000;
– I_AUDIO_CONFIG_3 = b00000001;
– GPSO_CONF = b00000011;
Note that embedded default configuration for PCM
block is described at previous chapter.
20/45
STA016T
I_AUDIO_CONFIG_1:
b7 b6 b5 b4
Address : 0x5C (92)
Type : RW - DEC
Software Reset : 0
b3
b2
b1
b0
CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
Description :
Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
See I_AUDIO_CONFIG_3 register description..
I_AUDIO_CONFIG_3 :
Description :
If INPUT_CONF == 1, this register configure the
I2Sin interface.
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
LR9 LR8
Bit
Comment
fields
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
CF0
CF1
CF2
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
Data reception configuration :
0 : LSB first
1 : MSB first
Description :
If INPUT_CONF == 1, this register is used to config-
ure the phase of the LRCK of the I2Sin.
Polarity of bit clock BCK :
0 : data provided on falling edge & stable
on rising edge.
Bit fields
Comment
1 : data provided on rising edge & stable
on falling edge
LR[4:0]
Position of the data within the LRCK
phase :
- if CF1 = 0 (LSB), value must be set to[31
- SL[9:5] - bit position of the first bit of data
within the LRCK phase].
- if CF1 = 1 (MSB), value must be set to bit
position of the first bit of data within the
LRCK phase.
CF3
CF4
Polarity of LR clock LRCK :
0 : negative
1 : positive
Start value of LRCK : combined with CF3,
this bit enable user to determine left/right
couple according to the following table.
Note that range of value for this bit position
is [0:31].
CF[7:5]
Reserved : to be set to 0.
LR[9:5]
Length-1 of the data.
Max value is 31.
CF3
CF4
0
Left/Right couples
LR[15:10] Reserved : to be set to 0
0
1
0
1
(data1/data2), (data3/data4),...
(data0/data1), (data2/data3),...
(data0/data1), (data2/data3),...
(data1/data2), (data3/data4),...
0
1
3.6 CDBSA_CONFIGURATION registers
description
1
INPUT_CONF :
b7
b6
b5
b4
b3
b2
b1
b0
I_AUDIO_CONFIG_2 :
b7 b6 b5 b4
LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
b3
b2
b1
b0
21/45
STA016T
Description :
Bit
Comment
Reserved : to be set to 0
Reserved : to be set to 1
If set to 1 enable the configurability of the CD & BS
input interfaces in audio mode thanks to following
registers, else disable this configurability and take
embedded default configuration.
CF0
CF1
CF2
Direction of bit clocks CD_BCK & BS_BCK:
0 : input
1 : output
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
CF3
Polarity of bit clocks CD_BCK & BS_BCK :
0 : data provided on falling edge & stable on
rising edge
1 : data provided on rising edge & stable on
falling edge
– I_AUDIO_CONFIG1 = b00010010;
// clocks in input
// & polarity negative
– I_AUDIO_CONFIG2 = b00110010;
// synchro with first data bit
CF4
CF5
Reserved : to be set to 1
// data unsigned, MSB first
Direction of LR clocks CD_LRCK &
– I_AUDIO_CONFIG3 = b11001111;
// LRCK phase length is 1
BS_LRCK :
0 : input
1 : output
– I_AUDIO_CONFIG4 = b00000011;
// LRCK phase length is 16
CF6
Polarity of LR clocks CD_LRCK &
BS_LRCK :
– I_AUDIO_CONFIG5 = 0xFF;
// received 16 bits
0 : left sample corresponds to the low level
phase of LRCK
1 : left sample corresponds to the high level
phase of LRCK
– I_AUDIO_CONFIG6 = 0xFF;
// received 16 bits
CF7
Reserved : to be set to 0
– I_AUDIO_CONFIG7 = 0x00;
// received 16 bits
– I_AUDIO_CONFIG8 = 0x00;
// received 16 bits
I_AUDIO_CONFIG_2 :
b7 b6 b5 b4
b3
b2
b1
b0
– I_AUDIO_CONFIG9 = 16;
// data size is 16
CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8
– I_AUDIO_CONFIG10 = 0x00;
// no use because clock in input
Address : 0x5C (92)
Type : RW - DEC
Software Reset : 0
– I_AUDIO_CONFIG11 = 0x00;
// no use because clock in input
Description :
If INPUT_CONF == 1, this register is used to config-
urate CD & BS input interfaces in audio mode.
_AUDIO_CONFIG_1 :
b7
b6
b5
b4
b3
b2
b1
b0
Bit
Comment
Relative synchro :
CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
CF8
0 : synchro with first data bit
1 : synchro one bit before first data bit
Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
CF9
Data reception configuration :
0 : LSB first
1 : MSB first
CF10
Arithmetic type of the reception :
0 : unsigned data
Description :
If INPUT_CONF == 1, this register is used to config-
urate CD & BS input interfaces in audio mode.
1 : signed data
22/45
STA016T
Bit
Comment
Bit fields
Comment
CF11
Bit to select the reference clock used to
generate BCK if clocks are in output
(CF2=1 & CF5=1). Otherwise this bit is
useless.
LR[11:6]
Length-1 of phase 2 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
LR[15:12]
Reserved : to be set to 0
0 : SYSCK
1 : PCMCK
CF12
CF13
CF14
CF15
Reserved : to be set to 1
Reserved : to be set to 1
Reserved : to be set to 0
Reserved : to be set to 0
I_AUDIO_CONFIG_5:
b7 b6 b5 b4
b3
b2
b1
b0
MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
Address : 0x5F (95)
Type : RW - DEC
Software Reset : 0
I_AUDIO_CONFIG_3 :
b7 b6 b5 b4
b3
b2
b1
b0
Description :
LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
See I_AUDIO_CONFIG_8 register description.
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
I_AUDIO_CONFIG_6 :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8
See I_AUDIO_CONFIG_4 register description..
Address : 0x60 (96)
Type : RW - DEC
Software Reset : 0
I_AUDIO_CONFIG_4 :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
LR15 LR14 LR13 LR12 LR11 LR10 LR9 LR8
See I_AUDIO_CONFIG_8 register description..
Address : 0x5E (94)
Type : RW - DEC
Software Reset : 0
I_AUDIO_CONFIG_7 :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
If INPUT_CONF == 1, this register is used to config-
urate LR clocks (CD_LRCK & BS_LRCK) of CD & BS
input interfaces in audio mode.
Address : 0x61 (97)
Type : RW - DEC
Software Reset : 0
Bit fields
Comment
LR[5:0]
Length-1 of phase 1 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
Description :
See I_AUDIO_CONFIG_8 register description..
23/45
STA016T
I_AUDIO_CONFIG_8 :
II_AUDIO_CONFIG_11 :
b7 b6 b5 b4
b7
b6
b5
b4
b3
b2
b1
b0
b3
b2
b1
b0
MA31 MA30 MA29 MA28 MA27 MA26 MA25 MA24
DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8
Address : 0x62 (98)
Type : RW - DEC
Software Reset : 0
Address : 0x65 (101)
Type : RW - DEC
Software Reset : 0
Description :
Description :
If INPUT_CONF == 1, those registers are used to
configure the MASK to be appllied to CD_LRCK &
BS_LRCK phase 1 & 2.
If INPUT_CONF == 1, those registers are used to
create BCK if configurated in output (so if CF2=1 &
CF5=1): then value of DV[15:0] is the divider factor to
be applied to the selected clock (CF11 select either
SYSCLK or PCMCLK) to create BCK.
– if MAi set to 0, then bit i of both phases is not
received.
Note : value 0 & 1 correspond to a bypass of the di-
viders.
– if MAi set to 1, then bit i of both phases is re-
ceived.
I_AUDIO_CONFIG_9 :
3.7 BSB_CONFIGURATION registers
description
b7
b6
b5
b4
b3
b2
b1
b0
POL_REQ :
DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x63 (99)
Type : RW - DEC
Software Reset : 0
Address : 0x59 (89)
Type : WO - DEC
Software Reset : 0
Description :
Description :
If INPUT_CONF == 1, this register is used to config-
urate the size of the data to be received by CD & BS
input interfaces in audio mode. Max is 32.
This register manage the polarity of the data REQ
signal DREQ of the BS input interface.
If set to 0, data are requested when REQ = 0.
If set to 1, data are requested when REQ = 1.
I_AUDIO_CONFIG_10 :
b7
b6
b5
b4
b3
b2
b1
b0
INPUT_CONF :
DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x64 (100)
Type : RW - DEC
Software Reset : 0
Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_11 register description.
Description :
24/45
STA016T
If set to 1 enable the configurability of the BSB input
interfaces in burst mode thanks to following register,
else disable this configurability and take embedded
default configuration.
Value
3
Command
fast forward
fast rewind
track up
4
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
5
6
track down
– I_AUDIO_CONFIG1 = b00000000;// polarity
choice
9
directory down
10
directory up
11
play specified track
set a play-list index
edit play list
I_AUDIO_CONFIG_1 :
12
13
b7
b6
b5
b4
b3
b2
b1
b0
14
play current dir
0
0
0
0
0
0
0
CF0
15
play cd from beginning
start playing music
112
113
124
125
126
127
128
Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
start searching bytes/mute navigation
ID3 name of song required
ID3 name of author required
ID3 name of album required
name of file required
Description :
If INPUT_CONF == 1, this register is used to config-
ure BSB bit clock.
name of directory required
Bit
Comment
CF0
Polarity of bit clock BS_BCK :
0 : data provided on falling edge & stable
on rising edge.
FAST_FUNCTIONAL_VAL :
b7 b6 b5 b4 b3
1 : data provided on rising edge & stable
on falling edge.
b2
b1
b0
Address : 0x41 (65)
Type : RW - ABO
Software Reset : 0
3.8 CD_CONFIGURATION registers
description
BASIC_COMMAND :
Description :
This register specifies the volume of fast function.
For the “fast forward function” it is a number between
1 and 20.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x40 (64)
Type : RW - AEC
Software Reset : 0
For the “fast rewind function” it is a number of second
REQUIRED_TRACK :
Description :
b7
b6
b5
b4
b3
b2
b1
b0
Used for giving to dsp basic cd-player commands.
Value
Command
stop playing music
pause
Address : 0x42 (66)
Type : RW - ABO
Software Reset : 0
1
2
25/45
STA016T
Description :
TYPE_CD_EXT_REQ:
b7 b6 b5 b4
This specifies the number of track to play.
b3
b2
b1
b0
Address : 0x46 (70)
Type : RO - AEC
Software Reset : 0
REQUIRED_DIR :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x43 (67)
Type : RW - ABO
Software Reset : 0
Description :
Description :
This register specifies the type of request sent to the
cd module.
Value
10
Signification
application is in pause after EOT or EOD
request for a sector
This register specifies the number of directory to
play.
18
20
begin of track reached
PLAY_MODE :
30
ready to receive a new command
dsp ready to run
b7
b6
b5
b4
b3
b2
b1
b0
35
40
cd application stopped.
time spent on track available
request for root
Address : 0x44 (68)
Type : RW - ABO
Software Reset : 0
66
112
120
song information available
Description :
This register specifies the playing mode.
Bit
Mode
MINUTE_REQ :
b7 b6 b5
[1:0]
end of directory:
0: play next directory
1: replay same directory
2: make pause.
b4
b3
b2
b1
b0
Address : 0x47 (71)
Type : RO - AEC
Software Reset : 0
other: reserved
[3:2]
end of track:
0: play next track.
1: replay same track.
2: make pause.
other: reserved
Description :
This register specifies to the CD module the minute
location requested.
4
5
6
next track choice:
0: linear mode.
1: random mode.
playing time for track:
0: until end of track.
1: scanning mode.
SECOND_REQ :
b7
b6
b5
b4
b3
b2
b1
b0
end of CD:
0: stop.
1: replay same CD..
Address : 0x48 (72)
Type : RO - AEC
26/45
STA016T
Software Reset : 0
Description :
SCANNING_TIME :
b7 b6 b5
b4
b3
b2
b1
b0
This register specifies to the CD module the second
location requested.
Address : 0x4C (76)
Type : RW - ABO
Software Reset : 0
SECTOR_REQ :
Description :
This register specifies in second (<60) the playing
time for each track in scanning mode.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x49 (73)
Type : RO - AEC
Software Reset : 0
Description :
PLAY_LIST_INDEX:
b7
b6
b5
b4
b3
b2
b1
b0
This register specifies to the CD module the sector lo-
cation requested.
Address : 0x4D (77)
Type : RW - ABO
Software Reset : 0
MINUTE_SPENT :
Description :
b7
b6
b5
b4
b3
b2
b1
b0
This register specifies the index in the play list of the
song to enter in the play list, it is also a value between
1 and the maximum number of track in the directory.
Address : 0x4A (74)
Type : RO - AEC
Software Reset : 0
PLAY_LIST_VALUE:
Description :
This register specifies the number of minute spent
from the beginning of the track. It is reset at the be-
ginning of a new track.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x4E (78)
Type : RW - ABO
Software Reset : 0
Description :
SECOND_SPENT :
This register specifies the song index in the directory
to enter in the play list, it is also a value between 1
and the maximum number of track in the directory.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x4B (75)
Type : RO - AEC
Software Reset : 0
CD_SONG_INFO_Cn :
Description :
b7
b6
b5
b4
b3
b2
b1
b0
This register specifies the number of second spent
from the beginning of the track. It is resected at the
beginning of a new track.
Address : 0x86 (134) to 0xA5 (165)
Type : RO - AEC
Software Reset : 0
27/45
STA016T
Description :
NB_OF_CUR_DIR :
b7 b6 b5
th
This register contains the n character of the song
info required (ASCII code).
b4
b3
b2
b1
b0
Address : 0xA8 (168)
Type : RO - AEC
CD_SONG_TYPE_INFO :
Software Reset : 0
b7
b6
b5
b4
b3
b2
b1
b0
Description :
Address : 0xA6 (166)
Type : RO - AEC
This register specifies the number of the current di-
rectory into the CD: from 1 to max number of directo-
ry. This number is negative if going backward to the
end of the CD with the command directory-down.
Software Reset : 0
Description :
This register specifies the kind of current information
contained in the
CD_CUR_STATUS :
b7
b6
b5
b4
b3
b2
b1
b0
Value
Signification
information not valid
0
1
2
3
4
5
6
7
Address : 0xA9 (169)
Type : RO - ABO
ID3 song name information
ID3 author name information
ID3 album name information
file name information
Software Reset : 0
Description :
This register gives the status of the CD application.
directory name information
bytes requested
Bit
Mode
0
0: unknown format.
1: recognized format
play list content
1
2
reserved.
When the track has changed the previous informa-
tion are declared “not valid”. New valid information
should be requested by user.
0: searching track.
1: track founded.
3
4
5
6
7
0: ID3 present.
1: ID3 missing.
NB_OF_CUR_TRACK :
0: no error detected.
1: error detected.
b7
b6
b5
b4
b3
b2
b1
b0
0: CD application in pause.
1: CD application not in pause.
Address : 0xA7 (167)
Type : RO - AEC
0: CD not playable.
1: CD playable.
Software Reset : 0
0: music mode.
1: searching bytes mode
Description :
This register specifies the number of the current track
into his directory (sub-directories included): from 1 to
max number of track/subdirectory.
28/45
STA016T
CD_TRACK_FORMAT :
b7 b6 b5 b4
Description :
This register specifies the number offile in the current
directory.
b3
b2
b1
b0
Address : 0xAA (170)
Type : RO - AEC
DIRECTORY_LEVEL :
Software Reset : 0
b7
b6
b5
b4
b3
b2
b1
b0
Description :
Address : 0xAD (173)
Type : RO - AEC
This register specifies the format of the played track
considering the extension name. Only 1 bit can be set
in the same time:
Software Reset : 0
Bit
FORMAT
0 : UNKNOWN
Description :
0
This register specifies the current directory level.
1 : MP3
1
2
3
4
1: RESERVED
MPEG1
DIR_IDENTIFIER_Bn :
MPEG2
b7
b6
b5
b4
b3
b2
b1
b0
MPG
Address : 0xAE (174) to 0xB1 (177)
Type : RO - AEC
Software Reset : 0
NB_OF_SUBDIR :
Description :
b7
b6
b5
b4
b3
b2
b1
b0
This register specifies the nth byte of the number of
byte of the current directory. Considering that two di-
rectories have very few chance to have exactly the
same number of byte, this number allows to identify
the directory. The first byte (174) is the MSB and the
last one (177) is the LSB.
Address : 0xAB (171)
Type : RO - AEC
Software Reset : 0
Description :
This register specifies the number of sub-directory in
the current directory.
VOL_IDENTIFIER_Bn:
Address : 0xB2 (178) to 0xB5 (181)
Type : RO - AEC
NB_OF_SUB_TRACK :
Software Reset : 0
b7
b6
b5
b4
b3
b2
b1
b0
Description :
This register specifies the nth byte of the number of
byte of the CD. Considering that two CD have very
few chance to have exactly the same number of byte,
this number allows to identify the CD. The first byte
(178) is the MSB and the last one (181) is the LSB.
Address : 0xAC (172)
Type : RO - AEC
Software Reset : 0
29/45
STA016T
EXTRACT_BYTE_IDX_Bn:
Bit
FORMAT
b7
b6
b5
b4
b3
b2
b1
b0
1
0: ID3 tag not checked
1: ID3 tag checked
Address : 0xB6 (182) to 0xB8 (185)
Type : RW - ABO
other
reference for counting sector in
minute.
Software Reset : 0
Description :
th
3.9 COMMAND registers description
This register specifies the n byte of the index of the
byte block to extract from the CD. This number
should be relative to the beginning of the track con-
taining these bytes.
SOFT_RESET :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x10 (16)
Type : WO - DWT
Software Reset : 0
EXTRACT_ADR_MODE :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
Address : 0xBA (186)
Type : RW - ABO
Software Reset : 0
When user write 1 in this register, a soft reset occurs.
The core command register and the interrupt register
are cleared. The decoder goes into idle mode.
Description :
This register specifies addressing mode type for byte
extraction: if set to 0, it is a relative (to the beginning
of the current file) addressing mode, if set to 1 it is an
absolute addressing mode (relative to the beginning
of the CD).
CK_CMD :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x3A (58)
Type : WO - DBO
Software Reset : 1
Hardware Reset : 1
CD_CONFIG_MODULE :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
Address : 0xBC (188)
Type : RO - ABO
After a soft reset, user must write 0 in CK_CMD to run
the core clock of the chip. This will begin the boot of
the chip, and so get it out of its idle state.
Software Reset : 0xA
Description :
DEC_SEL :
This register set some parameters describing the
way the module transmit the data to the DSP.
b7
b6
b5
b4
b3
b2
b1
b0
Bit
FORMAT
Address : 0x55 (85)
Type : RW - DEC
Software Reset : 0
0
0: valid data byte swapped.
1: valid data not byte swapped.
30/45
STA016T
Description :
Address : 0x52 (82)
Type : RW - ABO
Software Reset : 0
This register select the decoding data flux according
the mode written in following table.
Bit(7:0)
Mode
Description :
0
1
CD_MP3
For decoders having CRC abilities (see each decod-
er configuration), if set to 0 enable the check of CRC,
if set to 1 disable the check of the CRC.
CD_BYPASSA
2
RESERVED
3
BSB_MP3
4
BSB_ADPCM_DECODER
RESERVED
MUTE :
5
b7
b6
b5
b4
b3
b2
b1
b0
6
BSA_ADPCM_ENCODER
BSA_BYPASSA
7
Address : 0x53 (83)
Type : RW - ABO
Software Reset : 0
8
I2Sin_ADPCM_ENC
I2Sin_BYPASSA
9
10
SINE (test mode chip alive)
Description :
For decoders having MUTE abilities (see each de-
coder configuration), ifset to 0 disable the mute ofthe
decoder, if set to 1 enable the mute of the decoder.
Note that during a MUTE the input stream keeps on
entering.
RUN :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x56 (86)
Type : RW - DEC
Software Reset : 0
SKIP :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
Address : 0x57 (87)
Type : RW - ABO
Software Reset : 0
– When a software reset occurs, register RUN
is reset (value 0) by the dsp (see I).
– When boot routines are finished, the dsp
write inside RUN register the value 2 : this is
the start of the external configuration period
(start of DEC : see I).
Description :
For data flux using USSB Input, if SKIP == n>2, de-
coder skip (n-1) out of n frames. Note that maximum
value for n is 8, and if n==0 or n==1, no frames is
skipped.
– When the external device wants to end the
external configuration period, it must write the
value 1 inside the register RUN: this is the run
command that starts the decoding process
(see I).
PAUSE :
b7
b6
b5
b4
b3
b2
b1
b0
CRC_IGNORE :
Address : 0x58 (88)
Type : RW - ABO
b7
b6
b5
b4
b3
b2
b1
b0
31/45
STA016T
Software Reset : 0
STATUS_CHANS_NB :
b7 b6 b5 b4
b3
b2
b1
b0
Description :
For decoders having PAUSE abilities (see each de-
coder configuration), if set to 0 disable the pause of
the decoder, if set to 1 enable the pause of the de-
coder. Note that during a PAUSE the input stream is
stopped.
Address : 0xCD (205)
Type : RO - EDF
Software Reset : 0
Description :
This register gives the number of channel currently
decoded.
3.10STATUS registers description
STATUS_MODE :
b7
b6
b5
b4
b3
b2
b1
b0
STATUS_SF :
Address : 0xCC (204)
Type : RO - EDF
Software Reset : 0
Description :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xCE (206)
Type : RO - EDF
This register give the type of the currently decoded
bitstream according following table.
Software Reset : 0
Description :
Value
0
Mode
This register gives the index of the sampling frequen-
cy of the stream currently decoded. Note that sam-
pling frequency indexes are given by table 5
MP3
1
MP3_25
2
RESERVED
RESERVED
RESERVED
ADPCM
3
STATUS_FE :
4
5
b7
b6
b5
b4
b3
b2
b1
b0
6
RESERVED
BYPASS
Address : 0x6F (111)
Type : RO - AEC
7
8
RESERVED
RESERVED
RESERVED
MPG2
Software Reset : 0
9
10
11
12
13
14
15
16
17
18
Description :
This register give the status of the synchronization
process according following table.
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
UNKNOWN
Value
Level
0
1
2
3
Syncrho not started
Syncword found
Syncword search
Syncword hard to find
32/45
STA016T
HEADER _n:
b7 b6
Address : 0xCB (203)
Type : RW - DEC
b5
b4
b3
b2
b1
b0
Software Reset : 0
Address : 0xD4 (212) to 0xD9 (217)
Type : RO - EDF
Description :
Software Reset : 0
If set to 1, the PCMCLK pad is configure as input in
order to receive an external reference clock.
Description :
This register give the nth byte of the header of the
frame currently decoded
3.12MP3_CONFIGURATION registers
description
ERR_DEC_LEVEL :
3.11BYPASSA_CONFIGURATION registers
description
b7
b6
b5
b4
b3
b2
b1
b0
CHAN_NB :
Address : 0x6B (107)
Type : RO - EDF
b7
b6
b5
b4
b3
b2
b1
b0
Software Reset : 0
Address : 0x70 (112)
Type : RW - DEC
Software Reset : 0
Description :
This register give the status of the mp3 decoding pro-
cess according the error level written in following ta-
ble.
Description :
Value
Level
User must specify the number of channel for bypassa
decoder to decode.
0
1
2
3
No error
Warning while decoding
Error while decoding
SAMPLING_FREQ: :
Fatal error while decoding
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x71 (113)
Type : RW - DEC
Software Reset : 0
ERR_DEC_NB_1 :
b7
b6
b5
b4
b3
b2
b1
b0
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
Description :
User must specify the sampling frequency of the
stream to decode if clocks direction of the input inter-
face is input. Sampling frequency index is given by
table 4.
Address : 0x6C (108)
Type : RO - EDF
Software Reset : 0
Description :
See ERR_DEC_NB_2 register description.
PCMCLK_INPUT :
b7
b6
b5
b4
b3
b2
b1
b0
33/45
STA016T
ERR_DEC_NB_2 :
Description :
It allows the user to specify the number of channel of
the stream to encode.
b7
b6
b5
b4
b3
b2
b1
b0
ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8
Value
Codec
Address : 0x6D (109)
Type : RO - EDF
1
2
5
stream mono encoded as mono
stream stereo encoded as stereo
Software Reset : 0
stream stereo encoded as mono
with left channel.
Description :
9
stream stereo encoded as mono
with right channel.
This register give the status of the mp3 decoding pro-
cess according the error number written in following
table.
stream mono stands for only 1 channel is transmit-
ted, data are also not interleaved.
Event
Comment
crc_error
Encode a stereo stream as mono reduce from an half
the encoded data.
ER0 == 1
ER1 == 1
ER2 == 1
ER3 == 1
ER4 == 1
ER5 == 1
ER6 == 1
ER7 == 1
ER8 == 1
ER9 == 1
ER10 == 1
ER11 == 1
ER12 == 1
ER13 == 1
ER14 == 1
ER15 == 1
cutoff_error
big_value_error
hufftable_error
SAMPLING_FREQ. :
mod_buf_size_error
huffman_decode_error
dynpart_exchange_error
gr_length_error
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x71 (113)
Type : RW - DEC
Software Reset : 0
input_bit_available_error
ch_length_error
Description :
head_framelength_error
dynpart_length_error
block_type_error
It allows the user to specify the sampling frequency
of the stream to encode.See table 6 of sample fre-
quencies.
head_emphasis_error
head_samp_freq_error
head_layer_error
ENC_STATE_REPEAT :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x72 (114)
Type : RW - DEC
Software Reset : 0
Description :
3.13ADPCM_CONFIGURATION registers
description
CHAN_NB :
b7
b6
b5
b4
b3
b2
b1
b0
It allows the user to specify at which frequency the
state of the encoder should be repeated in the stream
:(1/HOST_ENC_STATE_REPEAT) frame.
Address : 0x70 (112)
Type : RW - DEC
Software Reset : 0
34/45
STA016T
ENC_CODEC :
b7 b6 b5
:
Value
Mode
b4
b3
b2
b1
b0
0
1
2
3
diseable mix/volume control
volume control
Address : 0x73 (115)
Type : RW - DEC
Software Reset : 0
mono to stereo (up-mix)
stereo to mono (down-mix)
Description :
It allows the user to specify the codec to use for the
encoding:
MIX_DLA:
b7 b6
Value
Codec
b5
b4
b3
b2
b1
b0
0
1
2
3
Intel/DVI
G723_24
G721
Address : 0x76 (118)
Type : RW - ABO
Software Reset : 0
G723_40
Description :
This register specifies the direct left attenuation (in
dB).
ENC_FRAME_LEN :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x74 (116)
Type : RW - DEC
Software Reset : 0
MIX_DLB:
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x77 (119)
Type : RW - ABO
Software Reset : 0
Description :
It allows the user to specify the number of words by
channel included in 1 frame: value from 1 to 15 (mul-
tiplied by 64 inside dsp).
Description :
This register specifies the left attenuation (in dB) on
rigth channel.
3.14MIX_CONFIGURATION registers
description
MIX_MODE:
MIX_DRA:
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x75 (117)
Type : RW - ABO
Software Reset : 2
Address : 0x78 (120)
Type : RW - ABO
Software Reset : 0
Description :
Description :
This register selectes the mode of mix/volume control
This register specifies the direct right attenuation (in
dB).
35/45
STA016T
MIX_DRB:
Software Reset : 10
Description :
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x79(121)
Type : RW - ABO
Software Reset : 0
This register specifies the low cut frequency: fcut(in
Hz) = (TONE_FCUTL+1)*10
TONE_GAINH :
Description :
This register specifies the rigth attenuation (in dB) on
left channel.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x7D(125)
Type : RW - ABO
3.15TONE_CONFIGURATION registers
description
Software Reset : 12
TONE_ON:
Description :
This register specifies the gain on high frequencies:
gain(in Db)=(TONE_GAINH-12)*1.5
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x7A(122)
Type : RW - ABO
Software Reset : 0
TONE_GAINL :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
This register enables/diseables (1/0) the tone control.
Address : 0x7E(126)
Type : RW - ABO
Software Reset : 12
TONE_FCUTH :
Description :
b7
b6
b5
b4
b3
b2
b1
b0
This register specifies the gain on high frequencies:
gain (in Db)=(TONE_GAINL-12)*1.5. Value of regis-
ter from 0 to 24.
Address : 0x7B(123)
Type : RW - ABO
Software Reset : 20
TONE_GAIN_ATTEN :
Description :
This register specifies the high cut frequency: fcut(in
Hz)=(TONE_FCUTH+1)*50.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x7F(127)
Type : RW - ABO
Software Reset : 0
TONE_FCUTL :
b7
b6
b5
b4
b3
b2
b1
b0
Description :
This register specifies the attenuation on global spec-
trum: gain (in dB)=-TONE_GAIN_ATTEN*1.5. Value
of register from 0 to 12.
Address : 0x7C(124)
Type : RW - ABO
36/45
STA016T
3.16TABLES
Table 2. values to configure audio PLL for ofact==256.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 256*SF.
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
Register
PLL_AUDIO_PEL_192
PLL_AUDIO_PEH_192
PLL_AUDIO_NDIV_192
PLL_AUDIO_XDIV_192
PLL_AUDIO_MDIV_192
PLL_AUDIO_PEL_176
PLL_AUDIO_PEH_176
PLL_AUDIO_NDIV_176
PLL_AUDIO_XDIV_176
PLL_AUDIO_MDIV_176
42
169
0
58
187
0
85
85
0
3
3
0
18
56
16
0
12
54
118
0
2
0
64
0
3
2
3
17
8
11
Table 3. values to configure audio PLL for ofact==384
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 384*SF.
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
Register
PLL_AUDIO_PEL_192
PLL_AUDIO_PEH_192
PLL_AUDIO_NDIV_192
PLL_AUDIO_XDIV_192
PLL_AUDIO_MDIV_192
PLL_AUDIO_PEL_176
PLL_AUDIO_PEH_176
PLL_AUDIO_NDIV_176
PLL_AUDIO_XDIV_176
PLL_AUDIO_MDIV_176
224
190
0
108
76
0
0
0
0
1
1
1
13
42
140
0
9
9
54
118
0
0
48
0
1
1
1
12
8
8
37/45
STA016T
Table 4. values to configure audio PLL for ofact==512.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 512*SF.
CRYCK in MHz
10
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
Register
PLL_AUDIO_PEL_192
PLL_AUDIO_PEH_192
PLL_AUDIO_NDIV_192
PLL_AUDIO_XDIV_192
PLL_AUDIO_MDIV_192
PLL_AUDIO_PEL_176
PLL_AUDIO_PEH_176
PLL_AUDIO_NDIV_176
PLL_AUDIO_XDIV_176
PLL_AUDIO_MDIV_176
42
169
0
58
187
0
85
85
0
1
0
1
18
56
16
0
5
12
0
157
157
0
64
0
1
1
1
17
11
11
Table 5. values to configure system PLL for SYSCK.
This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz.
or SYSCK == 42.5MHz.
CRYCK in MHz
14.31818
CRYCK in MHz
14.7456
Register
CRYCK in MHz 10
PLL_SYSTEM_PEL_50
PLL_SYSTEM_PEH_50
PLL_SYSTEM_NDIV_50
PLL_SYSTEM_XDIV_50
PLL_SYSTEM_MDIV_50
PLL_SYSTEM_PEL_42_5
PLL_SYSTEM_PEH_42_5
PLL_SYSTEM_NDIV_42_5
PLL_SYSTEM_XDIV_42_5
PLL_SYSTEM_MDIV_42_5
162
11
0
0
0
28
152
0
0
1
1
1
19
0
13
126
223
0
12
100
135
0
0
0
1
1
1
16
10
10
38/45
STA016T
Table 6. index of the Sampling Frequency.
Index
Frequency
48 kHz
0
1
44.1 kHz
32 kHz
2
4
96 kHz
5
88.2 kHz
64 kHz
6
8
24 kHz
9
22.05 kHz
16 kHz
10
12
12 kHz
13
11.025 kHz
8 kHz
14
16
192 kHz
176.4 kHz
128 kHz
illegal frequency
17
18
3, 7, 11, 15 or 19
3.17NOTATIONS
ABO
AEC
BCK
BSA
: After BOot (see I).
: After External Config (see I).
: Bit ClocK
: BitStream input interface in Audio mode.
: BitStream input interface in Burst mode.
: BitStream input interface.
: decoder BYPASS an Audio stream.
: input interface for CD.
BSB
BS
BYPASSA
CD
CK
: ClocK.
CRYCK
DBO
DEC
DWT
EDB
EDF
: CRYstal ClocK provided to the chip by an external crystal.
: During BOot (see I).
: During External Config (see I).
: During Whole Time (see I).
: Every Decoded Block (see I).
: Every Decoded Frame (see I).
LRCK
ofact
PCMCK
SF
: Left Right ClocK for an I2S interface.
: oversampling factor for PCMCK (PCMCK == ofact * SF).
: PCM ClocK (can be generated by the audio PLL).
: Sampling Frequency.
SYSCK
X
: SYStem ClocK (clock of the core, can be generated by the system PLL).
: don’t care.
39/45
STA016T
I/O CELL DESCRIPTION
1) TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control
Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59
EN
INPUT PIN
MAX LOAD
Z
A
Z
100pF
D98AU904
2) TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control
Pin numbers: 1, 2, 3, 7, 8, 9, 19
EN
IO
OUTPUT
PIN
MAX
LOAD
INPUT PIN CAPACITANCE
A
IO
TBD
IO
100pF
ZI
D98AU905
3) TTL Schmitt Trigger Inpud Pad Buffer, 3V capable / Pin numbers:17, 60, 63
A
Z
INPUT PIN
CAPACITANCE
A
TBD
D98AU906
4) TTL Inpud Pad Buffer, 3V capable with Pull-Up / Pin numbers:15, 16
INPUT PIN
CAPACITANCE
A
Z
A
TBD
D98AU907
5) TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable
Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64
EN
OUTPUT
MAX
LOAD
IO
INPUT PIN CAPACITANCE
PIN
A
IO
TBD
IO
100pF
ZI
D00AU1150
6) TTL Input Pad Buffer, 3V capable, with pull down / Pin numbers: 12, 13, 14, 55
A
Z
INPUT PIN
CAPACITANCE
A
TBD
D00AU1222
40/45
STA016T
4
COMMAND PROTOCOL CONFIGURATION
General Information About The Command Protocol
I2C protocol :
CD_module & mmdsp are using an I2C protocol to communicate : CD_module is master of the I2C protocol,
and can access (in read and write mode) host registers of the sta016 to write commands to the mmdsp and to
read request from the mmdsp. It must use following I2C syntax :
device_address, host_register_number, host_register_value
where :
for a writeacces, device_address is 0x86.
for a read acces, device_address is 0x87.
Writing a command to mmdsp :
CD_module write its command inside dedicated host registers (mainly H64 to H69), then it must signals the writ-
ing of this command to mmdsp by sending the interrupt IT_CMD to the core of mmdsp.
Note that IT_CMD is generated by cd_module threw a falling edge on the input line number 0 of the sta016 (the
INTLINE[0] pin).
Reading a request from mmdsp :
MMDSP write its request inside dedicated host registers (mainly H70 to H78 and H134 to H169), then it signals
to cd_module that it must read a request by sending the interrupt IT_REQ.
Note that IT_REQ interrupt is generated by mmdsp on the IRQB pin of sta016.
Note also that once it has finished to read the message, cd_module must always acknowledge it by reading
H10.
41/45
STA016T
Figure 4. Block diagram for running the CD application.
Hxx: host register
number xx
power on
cd
inserted ?
no
write 1 in SOFT_RESET
write 0 in CK_CMD
wait IT_REQ
with 35 in H70
start cd-rom application:
write 0 in H85, then 1 in H86
wait IT_REQ
with 112 in H70
send play_music command :
write 112 in H64
send IT_CMD
cd
ejected?
yes
run other
application?
yes
send pause command :
write 2 in H64
any
send IT_CMD
command?
no
run the other
application
send other command :
write in H64
send IT_CMD
return
to cd?
yes
no
42/45
STA016T
Figure 5. Block diagram for answer to a sector request from dsp.
Hxx: host register
number xx
power on
IT_REQ occured
H70==18
read minute in H71
read second in H72
read frame in H73
please check
with rest of
documentation
acknowledge
IT_REQ
acknowledge
IT_REQ
move the pick-up
according to m,s,f
43/45
STA016T
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
A2
B
1.60
0.063
0.006
0.05
1.35
0.18
0.12
0.15 0.002
1.40
0.23
1.45 0.053 0.055 0.057
0.28 0.007 0.009 0.011
C
0.16
0.20 0.0047 0.0063 0.0079
D
12.00
10.00
7.50
0.472
D1
D3
e
0.394
0.295
0.50
0.0197
E
12.00
10.00
7.50
0.472
0.394
E1
E3
L
0.295
0.40
0.60
0.75 0.0157 0.0236 0.0295
0.0393
L1
K
1.00
TQFP64
0°(min.), 7°(max.)
D
D1
D3
A
A2
A1
48
33
32
49
0.10mm
Seating Plane
17
16
64
1
C
e
K
TQFP64
44/45
STA016T
Note:1
2
STA016 is a device based on an integrated DSP core. Some of the I C registers default values are loaded after an internal DSP boot oper-
ation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
- Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
45/45
相关型号：
©2020 ICPDF网 联系我们和版权申明