STA500_06 [STMICROELECTRONICS]
30V 3.5A QUAD POWER HALF BRIDGE; 30V 3.5A四路电源半桥
| 型号： | STA500_06 |
| 厂家： | 
ST |
| 描述： | 30V 3.5A QUAD POWER HALF BRIDGE |
| 文件： | 总11页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA500
30V 3.5A QUAD POWER HALF BRIDGE
■ MINIMUM INPUT OUTPUT PULSE WIDTH
MULTIPOWER BCD TECHNOLOGY
DISTORTION
■ 200mΩ RdsON COMPLEMENTARY DMOS
OUTPUT STAGE
■ CMOS COMPATIBLE LOGIC INPUTS
■ THERMAL PROTECTION
■ THERMAL WARNING OUTPUT
PowerSO36
■ OVERVOLTAGE, UNDERVOLTAGE
ORDERING NUMBER: STA500
PROTECTION
current capability.
DESCRIPTION
The device is particulary designed to make the output
stage of a stereo All-Digital High Efficiency (DDX™)
amplifier capable to deliver 30 + 30W output power
STA500 is a monolithic quad half bridge stage in Mul-
tipower BCD Technology. The device can be used as
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current
capability, and as half bridge (Binary mode) with half
on 8
figuration or mono 60W on 4
have threshold proportional to Ibias pin voltage.
Ω
load and 60W on 8
Ω
load in bridge BTL con-
Ω
load. The input pins
AUDIO APPLICATION CIRCUIT (Dual BTL)
+VCC
VCC1A
15
17
16
C30
1µF
C55
1000µF
IN1A
29
M3
M2
M5
M4
IN1A
L18 22µH
C20
V
L
23
24
+3.3V
OUT1A
CONFIG
PWRDN
FAULT
100nF
OUT1A
GND1A
C52
330pF
PWRDN
25
C99
100nF
14
12
R98
6
PROTECTIONS
R57
10K
R59
10K
27
26
&
C23
470nF
8Ω
LOGIC
VCC1B
R63 R100
C101
100nF
TRI-STATE
20
6
C58
100nF
C31
1µF
11
10
C21
100nF
TH_WAR
IN1B
28
30
OUT1B
OUT1B
GND1B
TH_WAR
L19 22µH
IN1B
VDD
VDD
VSS
VSS
21
22
33
34
13
7
REGULATORS
VCC2A
C32
1µF
M17
M15
M16
M14
C58
100nF
C53
100nF
L113 22µH
VCCSIGN
8
9
35
OUT2A
C60
100nF
C110
100nF
V
CCSIGN
36
31
20
19
OUT2A
GND2A
C109
330pF
C107
100nF
6
4
R103
6
IN2A
IN2B
IN2A
C108
470nF
8Ω
GND-Reg
VCC2B
R104
20
R102
6
C106
100nF
GND-Clean
C33
1µF
3
2
C111
100nF
OUT2B
OUT2B
GND2B
IN2B
32
1
L112 22µH
GNDSUB
5
D00AU1148B
Rev. 7
1/11
January 2006
STA500
PIN FUNCTION
N°
1
Pin
Description
GND-SUB
Vcc Sign
Vcc1A
Vcc1B
Vcc2A
Vcc2B
GND1A
GND1B
GND2A
GND2B
OUT1A
OUT1B
OUT2A
OUT2B
IN1A
Substrate ground
35 ; 36
15
Signal Positive supply
Positive Supply
12
Positive Supply
7
Positive Supply
4
Positive Supply
14
Negative Supply
13
Negative Supply
6
Negative Supply
5
Negative Supply
16 ; 17
10 ; 11
8 ; 9
2 ; 3
29
Output half bridge 1A
Output half bridge 1B
Output half bridge 2A
Output half bridge 2B
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5V Regulator referred to ground
5V Regulator referred to +Vcc
Stand-by pin (Control input)
30
IN1B
31
IN2A
32
IN2B
21 ; 22
33 ; 34
25
Vdd
Vss
PWRDN
26
TRI-STATE Hi-Z pin (Control input)
27
FAULT
CONFIG
TH-WAR
Fault pin advisor (Open Collector Output)
24
Configuration setting pin
Thermal warning advisor (Open Collector Output)
28
19
GND-clean Logical ground
23
IBIAS
NC
High logical state setting voltage
18
Not connected
20
GND-Reg
Ground for Vdd regulator
2/11
STA500
FUNCTIONAL PIN STATUS
PIN NAME
Logical value
IC -STATUS
FAULT
0
Fault detected (Short circuit, or
Thermal ..)
FAULT (*)
TRI-STATE
TRI-STATE
PWRDN
1
Normal Operation
0
1
0
1
0
1
All powers in Hi-Z state
Normal operation
Low absorpion
PWRDN
Normal operation
THWAR
Temperature of the IC =130°C
Normal operation
THWAR(*)
CONFIG
0
1
Normal Operation
CONFIG(**)
OUT1A=OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**:) To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
PIN CONNECTION
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND-SUB
OUT2B
OUT2B
VCC2B
VCCSign
2
VCCSign
VSS
3
4
VSS
5
GND2B
GND2A
IN2B
6
IN2A
7
VCC2A
IN1B
8
OUT2A
OUT2A
OUT1B
OUT1B
IN1A
9
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
IBIAS
10
11
12
13
14
15
16
17
18
VCC1B
GND1B
GND1A
VCC1A
V
V
DD
OUT1A
OUT1A
N.C.
DD
GND-Reg
GND-Clean
D00AU1133
3/11
STA500
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
40
Unit
V
VCE
Vmax
Top
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins (23 to 32)
Operating Temperature Range
5.5
V
0 to 70
-40 to 150
°C
°C
Tstg, Tj
Storage and Junction Temperature
THERMAL DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
°C/W
°C
Tj-case Thermal Resistance Junction to Case (thermal pad)
2.5
TjSD
Twarn
thSD
Thermal shut-down junction temperature
Thermal warning temperature
150
130
25
°C
Thermal shut-down hysteresis
°C
ELECTRICAL CHARACTERISTCS
(Ibias = 3.3V; Vcc = 28V; T = 25°C unless otherwise specified)
amb
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
RdsON Power Pchannel/Nchannel
MOSFET RdsON
Id=1A;
200
270
mΩ
Idss
Power Pchannel/Nchannel
leakage Idss
Vcc=35V
Id=1A
50
µA
gN
Power Pchannel RdsON
Matching (*)
95
95
%
gP
Power Nchannel RdsON
Matching (*)
Id=1A
%
Dt_s
Dt_d
Low current Dead Time (static)
see test circuit no.1; see fig. 1
10
20
50
ns
ns
High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8Ω
Id = 3.5A; see fig. 3
td ON
td OFF
tr
Turn-on delay time
Turn-off delay time
Rise time
Resistive load
100
100
25
ns
ns
ns
ns
V
Resistive load
Resistive load; as fig. 1
Resistive load; as fig. 1
tf
Fall time
25
VCC
VIN-H
Supply voltage operating voltage
High level input voltage
9
VOV
Ibias/2
+300mV
V
VIN-L
Low level input voltage
Ibias/2
-300mV
V
IIN-H
IIN-L
Hi level Input current
Low level input current
Pin voltage=Ibias
Pin voltage = 0.3V
1
1
µA
µA
µA
V
I
Hi level PWRDN pin input current Ibias = 3.3V
35
PWRDN-H
VL
Low logical state voltage VL (pin
PWRDN, TRISTATE) (note 1)
Ibias = 3.3V
0.8
VH
High logical state voltage VH (pin Ibias = 3.3V
PWRDN, TRISTATE) (note 1)
1.7
V
4/11
STA500
ELECTRICAL CHARACTERISTCS (continued)
(Ibias = 3.3V; Vcc = 28V; T = 25°C unless otherwise specified)
amb
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IVCC-
PWRDN
Supply current from Vcc in Power PWRDN = 0
Down
3
mA
IFAULT
Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
Vpin = 3.3V
Tri-state=0
1
mA
mA
IVCC-hiz Supply current from Vcc in Tri-
state
22
IVCC
Supply current from Vcc in
operation
(both channel switching)
Input pulse width = 50% Duty;
Switching Frequency = 384Khz;
No LC filters;
80
6
mA
A
IOUT-SH Overcurrent Protection Threshold
(short circuit current limit) (note 2)
3.5
30
8
VOV
VUV
Overvoltage protection threshold
Undervoltage protection threshold
35
7
40
V
V
tpw_min Output minimum pulse width
No Load
70
150
ns
Notes: 1. The following table explains the VL, VH variation with Ibias
Ibias
2.7
3.3
5
VLmax
0.7
VHmin
1.5
Unit
V
0.8
1.7
V
0.85
1.85
V
Note 2: If used in single BTL configuration, the device may be not short circuit protected
LOGIC TRUTH TABLE (see fig. 2)
OUTPUT
MODE
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
Hi-Z
DUMP
ON
OFF
ON
NEGATIVE
POSITIVE
Not used
OFF
ON
OFF
OFF
ON
OFF
5/11
STA500
Figure 1. Test Circuit.
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
DTf
Duty cycle = 50%
M58
M57
OUTxY
R 8Ω
INxY
+
-
V67 =
vdc = Vcc/2
gnd
D03AU1458
Figure 2.
+VCC
Q1
Q2
OUTxA
OUTxB
INxA
INxB
Q3
Q4
GND
D00AU1134
Figure 3.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
M57
M64
M63
Q1
OUTxA
Iout=3.5A
Q2
Q4
DTin(A)
DTout(B)
DTin(B)
INxB
Rload=8Ω
OUTxB
INxA
L67 22µ
L68 22µ
Iout=3.5A
Q3
C69
470nF
C70
470nF
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure
D00AU1162
6/11
STA500
Figure 4. Typical Quad Half Bridge Configuration
+VCC
VCC1P
15
17
16
C21
2200µF
IN1A
29
M3
M2
M5
M4
R61
5K
IN1A
C31 820µF
L11 22µH
IBIAS
23
24
+3.3V
OUTPL
C71
100nF
CONFIG
R41
20
C91
1µF
OUTPL
PWRDN
PWRDN
FAULT
25
C81
100nF
14
12
PGND1P
R51
6
R62
5K
C41
330pF
PROTECTIONS
R57
10K
R59
10K
27
26
&
LOGIC
VCC1N
TRI-STATE
C58
100nF
C51
1µF
C61
100nF
11
10
R63
5K
TH_WAR
IN1B
28
30
OUTNL
OUTNL
PGND1N
C32 820µF
L12 22µH
TH_WAR
C72
100nF
R42
20
IN1B
C92
1µF
VDD
VDD
VSS
VSS
21
22
33
34
13
7
C82
100nF
R52
6
R64
5K
C42
330pF
REGULATORS
VCC2P
M17
M15
M16
M14
R65
5K
C58
100nF
C53
100nF
C33 820µF
L13 22µH
VCCSIGN
VCCSIGN
8
9
35
OUTPR
C60
100nF
C73
100nF
R43
20
C93
1µF
36
31
20
19
OUTPR
C83
100nF
6
4
PGND2P
R53
6
R66
5K
IN2A
IN2B
C43
330pF
IN2A
GND-Reg
VCC2N
GND-Clean
C52
1µF
C62
100nF
3
2
R67
5K
OUTNR
OUTNR
PGND2N
C34 820µF
L14 22µH
IN2B
32
1
C74
100nF
R44
20
GNDSUB
C94
1µF
5
C84
100nF
R54
6
R68
5K
C44
330pF
D03AU1474
Note:
The diagran showed below, have been obtained using the demonstration board described in the application
Note AN1456 (STA304 + STA500 Digital Audioprocessor evolution board evaluating manual - Jan 2002), refer
to the schematic shown in fig. 1).
For the Quad Half Bridge Configuration (fig. 4), refers to the application note AN1661 (STA308 Half Bridge
Board - March 2003)
7/11
STA500
Figure 5. Distortion vs Output Power
(STA304A+STA500)
Figure 7. Output Power vs Supply Voltage
(STA304A+STA500)
50
10
Pout (W)
45
5
40
Vcc=30V
STA500
4 ohm load
filter 22uH+ 0.47uF diff+
0.1uF common mode
Rl=80hm
f=1KHz
2
35
THD = 10%
1
30
0.5
25
%
20
0.2
THD = 1%
15
0.1
10
5
0.05
.
Eq
0.02
0.01
0
+12
+12.5
+13
+13.5
+14
+14.5
+15
Vdc
+15.5
+16
+16.5
+17
+17.5 +18
700m
1
2
3
4
5
6
7
8
9
10
20
30
40 50
Vsupply (V)
W
Figure 8. Output Power vs Supply Voltage
(STA304A+STA500)
Figure 6. Tolal Power Dissipation & Efficiency
vs Output Power
50
Pout (W)
90
80
70
60
50
40
30
20
7
6
5
4
3
2
1
0
45
40
Rload = 8 ohm
Pdiss
f = 1KHz
THD = 10%
35
30
25
STA304A+STA500
1channel
Vcc=25V
Rl=8ohm
F=1KHz
THD = 1%
20
Efficiency
15
10
0
5
10
15
20
25
30
5
+12 +13 +14 +15 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28
Pout (W)
Vcc (V)
8/11
STA500
mm
inch
DIM.
MIN.
TYP. MAX. MIN.
3.60
TYP. MAX.
0.1417
0.0118
0.1299
0.0039
0.0150
0.0126
0.6299
0.3858
0.5709
0.4370
0.1142
0.2441
0.0256
0.4350
0.0039
0.6260
0.0433
0.0433
OUTLINE AND
MECHANICAL DATA
A
a1
a2
a3
b
0.10
0.30 0.0039
3.30
0
0.10
0.22
0.23
15.80
9.40
13.90
10.90
0.38 0.0087
0.32 0.0091
16.00 0.6220
9.80 0.3701
14.5 0.5472
11.10 0.4291
2.90
c
D
D1
E
E1
E2
E3
e
5.80
6.20 0.2283
0.65
e3
G
11.05
0
0.10
H
15.50
15.90 0.6102
1.10
h
L
0.8
1.10 0.0315
10˚ (max)
8˚ (max)
N
s
PowerSO-36
Note: “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions are "a3", "E" and "G".
0096119 C
9/11
STA500
Table 1. Revision History
Date
Revision
Description of Changes
July 2003
6
7
First Issue
January 2006
Modified in the Electrical Characteristics table (page 4) the values of
IN-H, VIN-L, VL & VH parameters.
Modified the notes 1( page 5).
V
10/11
STA500
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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11/11
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